Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device capable of suitably reducing the area of a semiconductor chip and a method for manufacturing method the same.SOLUTION: According to one embodiment, a semiconductor device has a first substrate, a first transistor provided on a top surface of the first substrate, and a memory cell array provided above the first transistor. The device further comprises a second substrate provided above the memory cell array and a second transistor provided on a top surface of the second substrate.SELECTED DRAWING: Figure 1

Description

Technical Field

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[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] The area of a semiconductor chip of a 3D memory can be reduced, for example, by reducing the area of a memory cell array. However, unless the area of the CMOS circuit is also reduced along with the area of the memory cell array, the area of the semiconductor chip may be determined by the area of the CMOS circuit.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Provided are a semiconductor device and a method for manufacturing the same that can suitably reduce the area of a semiconductor chip.

Means for Solving the Problems

[0005] According to one embodiment, a semiconductor device includes a first substrate, a first transistor provided on an upper surface of the first substrate, and a memory cell array provided above the first transistor. The device further includes a second substrate provided above the memory cell array and a second transistor provided on an upper surface of the second substrate.

Brief Description of the Drawings

[0006] [Figure 1] It is a cross-sectional view showing the structure of a semiconductor device of the first embodiment. [Figure 2] It is a cross-sectional view showing the structure of a columnar portion of the first embodiment. [Figure 3] This is a cross-sectional view (1 / 2) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] This is a cross-sectional view (2 / 2) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] This is a block diagram showing the configuration of the semiconductor device according to the first embodiment. [Figure 6] This is a cross-sectional view (1 / 4) showing details of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 7] This is a cross-sectional view (2 / 4) showing details of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 8] This is a cross-sectional view (3 / 4) showing details of the manufacturing method for the semiconductor device according to the first embodiment. [Figure 9] This is a cross-sectional view (4 / 4) showing details of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 10] This is a cross-sectional view showing an example of the structure of a semiconductor device according to the first embodiment. [Figure 11] This is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment. [Figure 12] This is a cross-sectional view showing the structure of a semiconductor device of a comparative example of the second embodiment. [Figure 13] This is a cross-sectional view showing an example of the structure of a semiconductor device according to a second embodiment. [Figure 14] These are cross-sectional and plan views showing another example of the structure of the semiconductor device according to the second embodiment. [Figure 15] This is a cross-sectional view (1 / 3) showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 16] This is a cross-sectional view (2 / 3) showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 17] This is a cross-sectional view (3 / 3) showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 18] This is a cross-sectional view showing the structure of a semiconductor device of a modified example of the second embodiment. [Modes for carrying out the invention]

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In FIGS. 1 to 18, the same components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0008] (First Embodiment) FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to the first embodiment.

[0009] The semiconductor device of the present embodiment is, for example, a semiconductor chip including a three-dimensional memory. The semiconductor device of the present embodiment is manufactured by bonding a circuit wafer including a circuit chip 1 and an array wafer including an array chip 2 as will be described later. FIG. 1 shows the bonding surface S between the circuit chip 1 and the array chip 2.

[0010] In FIG. 1, the array chip 2 includes a memory cell array including a plurality of memory cells, and the circuit chip 1 includes a CMOS circuit for controlling the operation of the memory cell array. However, as will be described later, the CMOS circuit of the present embodiment is included not only in the circuit chip 1 but also in the array chip 2.

[0011] The circuit chip 1 includes a substrate 11, a plurality of transistors 12, an interlayer insulating film 13, a plurality of plugs 14a to 14f, a plurality of wiring layers 15a to 15e, and a plurality of metal pads 16. The substrate 11 is an example of a first substrate, and each transistor 12 is an example of a first transistor. Each transistor 12 includes a gate insulating film 12a, a gate electrode 12b, a diffusion layer 12c, and a diffusion layer 12d.

[0012] The array chip 2 includes an interlayer insulating film 21, a stacked film 22, a substrate 23, a plurality of transistors 24, an interlayer insulating film 25, a plurality of metal pads 26, a plurality of plugs 27a to 27j, a plurality of wiring layers 28a to 28e, and a columnar portion 29. The substrate 23 is an example of a second substrate, and each transistor 24 is an example of a second transistor. Each transistor 24 includes a gate insulating film 24a, a gate electrode 24b, a diffusion layer 24c, and a diffusion layer 24d. The stacked film 22 includes a plurality of electrode layers 31 and a plurality of insulating films 32. Each columnar portion 29 includes a memory insulating film 33, a channel semiconductor layer 34, a core insulating film 35, and a core semiconductor layer 36.

[0013] The substrate 11 is, for example, a semiconductor substrate such as a Si (silicon) substrate. FIG. 1 shows an X direction and a Y direction that are parallel to the surface of the substrate 11 and perpendicular to each other, and a Z direction that is perpendicular to the surface of the substrate 11. The X direction, the Y direction, and the Z direction intersect each other. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may coincide with the direction of gravity or may not coincide with the direction of gravity. FIG. 1 further shows the thickness D1 of the substrate 11.

[0014] Each transistor 12 includes a gate insulating film 12a and a gate electrode 12b formed in sequence on the substrate 11, and diffusion layers 12c and 12d formed in the substrate 11. One of the diffusion layers 12c and 12d functions as a source region, and the other of the diffusion layers 12c and 12d functions as a drain region. The circuit chip 1 includes a plurality of transistors 12 on the upper surface of the substrate 11, and these transistors 12 constitute, for example, the above-described CMOS circuit. These transistors 12 include, for example, one or both of an LV (low voltage) transistor having a thin film thickness of the gate insulating film 12a and a HV (high voltage) transistor having a thick film thickness of the gate insulating film 12a. In the present embodiment, it is desirable that these transistors 12 include LV transistors and HV transistors or include only LV transistors. The thin film thickness is an example of a first film thickness, and the thick film thickness is an example of a second film thickness.

[0015] Figure 1 includes regions R1, R2, and R3 within and on the substrate 11. Transistor 12 in region R1 constitutes, for example, a sense amplifier (S / A). Transistor 12 in region R2 functions, for example, as a word line switch (WLSW). Transistor 12 in region R3 is, for example, another transistor in the CMOS circuit described above.

[0016] The interlayer insulating film 13 is formed on the substrate 11 and covers these transistors 12. The interlayer insulating film 13 is, for example, a multilayer film including an SiO2 film (silicon oxide film) and other insulating films.

[0017] Plugs 14a to 14f and wiring layers 15a to 15e are formed on the substrate 11 or transistor 12 in the following order: plug 14a, wiring layer 15a, plug 14b, wiring layer 15b, plug 14c, wiring layer 15c, plug 14d, wiring layer 15d, plug 14e, wiring layer 15e, and plug 14f. Plug 14a corresponds to a contact plug, and plugs 14b to 14f correspond to via plugs. Each of the wiring layers 15a to 15e contains multiple wirings within a single wiring layer. Plugs 14a to 14f and wiring layers 15a to 15e are provided within the interlayer insulating film 13.

[0018] The multiple metal pads 16 described above are arranged on the plug 14f within the interlayer insulating film 13. These metal pads 16 and the interlayer insulating film 13 form the upper surface of the circuit chip 1 and are in contact with the lower surface of the array chip 2. Each metal pad 16 contains, for example, a Cu (copper) layer.

[0019] The interlayer insulating film 21 is formed on the interlayer insulating film 13. The interlayer insulating film 21 is, for example, a laminated film including an SiO2 film and other insulating films.

[0020] The laminated film 22 includes a plurality of electrode layers 31 and a plurality of insulating films 32 alternately arranged within the interlayer insulating film 21. These electrode layers 31 are spaced apart from each other in the Z direction. These electrode layers 31 include, for example, a plurality of word lines and a plurality of selection lines. Each electrode layer 31 is, for example, a metal layer including a W (tungsten) layer. Each insulating film 32 is, for example, an SiO2 film. The laminated film 22, together with columnar portions 29 and the like, constitutes a memory cell array.

[0021] The substrate 23 is placed on the interlayer insulating film 21 and is located above the laminated film 22. The substrate 23 is a semiconductor substrate, such as a Si substrate. Figure 1 further shows the thickness D2 of the substrate 23.

[0022] Each transistor 24 includes a gate insulating film 24a and a gate electrode 24b formed sequentially on the substrate 23, and diffusion layers 24c and 24d formed within the substrate 23. One of the diffusion layers 24c and 24d functions as a source region, and the other functions as a drain region. The array chip 2 has a plurality of transistors 24 on the upper surface of the substrate 23, and these transistors 24 constitute, for example, the CMOS circuit described above. These transistors 24 include, for example, one or both of LV transistors whose gate insulating film 24a has the thin film thickness described above, and HV transistors whose gate insulating film 24a has the thick film thickness described above. In this embodiment, it is desirable that these transistors 24 include only HV transistors. As described above, in this embodiment, the CMOS circuit described above is composed of transistors 12 and 24.

[0023] In Figure 1, the thickness D2 of the substrate 23 is set to be thinner than the thickness D1 of the substrate 11. This has the advantage of making it easier to form a plug that penetrates the substrate 23, for example. On the other hand, if transistor 12 includes only LV transistors and transistor 24 includes only HV transistors, the thickness D2 of the substrate 23 may be set to be thicker than the thickness D1 of the substrate 11. In this case, it is possible to make the thickness D1 of the substrate 11, which is provided only with LV transistors that do not easily cause depletion layer expansion, thinner, and the thickness D2 of the substrate 23, which is provided only with HV transistors that easily cause depletion layer expansion, thicker. This makes it possible to achieve both miniaturization of the semiconductor device by making the substrate 11 thinner and suitable handling of the depletion layer by making the substrate 23 thicker. When the thickness D2 of the substrate 23 is thicker than the thickness D1 of the substrate 11, the thickness D2 of the substrate 23 is, for example, 10 μm or more.

[0024] The interlayer insulating film 25 is formed on the substrate 24 and covers the transistor 23. The interlayer insulating film 25 is, for example, a multilayer film including an SiO2 film and other insulating films.

[0025] The multiple metal pads 26 described above are arranged on the metal pad 16 within the interlayer insulating film 21. These metal pads 26 and the interlayer insulating film 21 form the lower surface of the array chip 2 and are in contact with the upper surface of the circuit chip 1. Each metal pad 26 contains, for example, a Cu (copper) layer.

[0026] The plugs 27a to 27c and the wiring layers 28a to 28b are formed in the interlayer insulating film 21 on the metal pad 26 in the order of plug 27a, wiring layer 28a, plug 27b, wiring layer 28b, and plug 27c. Plugs 27a to 27c correspond to via plugs. Each of the wiring layers 28a to 28b contains multiple wirings within a single wiring layer. The wiring layers 28b in regions R1 and R2 contain multiple wirings extending in the Y direction, and these wirings correspond to bit lines.

[0027] Plugs 27d to 27f and the wiring layer 28c are also formed within the interlayer insulating film 21. Plug 27d is provided on plug 27c and below the core semiconductor layer 36 in the columnar portion 29. Plug 27e is provided on plug 27c and below the electrode layer 31 in the laminated film 22. Plug 27f is provided on plug 27c and below plug 27j. Plugs 27d to 27f correspond to contact plugs. In Figure 1, one wiring (source wire) in the wiring layer 28c is provided on the above-mentioned columnar portions 29.

[0028] Plugs 27g to 27h and wiring layer 28d are formed in the interlayer insulating film 25 on the substrate 23 or transistor 24 in the order of plug 27g, wiring layer 28d, and plug 27h. Wiring layer 28e is formed on the interlayer insulating film 25 and plug 27h. Plug 27g corresponds to a contact plug, and plug 27h corresponds to a via plug. Each of the wiring layers 28d and 28e contains multiple wirings within a single wiring layer. At least some of the wirings in wiring layer 28e function as bonding pads for electrically connecting the semiconductor device of this embodiment with other devices. Wiring layer 28e may be partially covered with a passivation insulating film (not shown).

[0029] Plugs 27i to 27j are formed within the interlayer insulating film 21, the substrate 23, and the interlayer insulating film 25, and penetrate the substrate 23. Plug 27i is provided on the wiring layer 28c and below the wiring layer 28e. In Figure 1, plug 27i is electrically connected to the channel semiconductor layer 34 in the columnar portion 29 via the wiring layer 28c. Plug 27j is provided on plug 27f and below the wiring layer 28e. In Figure 1, plug 27j is electrically connected to the diffusion layer 12c or 12d of the transistor 12 in region R3. Plug 27j may also be electrically connected to the gate electrode 12b of the transistor 12 in region R3. Plug 27i corresponds to a contact plug, and plug 27j corresponds to a via plug. Each of the plugs 27i to 27j in this embodiment is electrically insulated from the substrate 23 by an insulating film (not shown). Plugs 27i to 27j are examples of the second plug.

[0030] Each columnar portion 29 is formed within the laminated film 22 and has a columnar shape extending in the Z direction. Each columnar portion 29 includes a memory insulating film 33, a channel semiconductor layer 34, and a core insulating film 35, which are sequentially provided within the laminated film 22, and a core semiconductor layer 36 provided below the core insulating film 35. The channel semiconductor layer 34 is, for example, a polysilicon layer. The core insulating film 35 is, for example, an SiO2 film. The core semiconductor layer 36 is, for example, a polysilicon layer. The core semiconductor layer 36 is electrically connected to the channel semiconductor layer 34. The channel semiconductor layer 34 is also electrically connected to the wiring (source lines) in the wiring layer 28c, and the core semiconductor layer 36 is electrically connected to the wiring (bit lines) in the wiring layer 28b via plugs 27d and 27c.

[0031] The area of ​​the semiconductor device (semiconductor chip) in this embodiment can be reduced, for example, by reducing the area of ​​the memory cell array. The area of ​​the memory cell array is generally determined by the area of ​​the stacked film 22. However, if the area of ​​the CMOS circuit is not reduced along with the area of ​​the memory cell array, there is a risk that the area of ​​the semiconductor device in this embodiment will be determined by the area of ​​the CMOS circuit.

[0032] Therefore, the CMOS circuit of this embodiment is composed of transistors 12 on substrate 11 and transistors 24 on substrate 23. For example, if a CMOS circuit is configured with M+N transistors 12 on substrate 11, the area of ​​the CMOS circuit on substrate 11 will generally depend on the value of M+N. On the other hand, if a CMOS circuit is configured with M transistors 12 on substrate 11 and N transistors 24 on substrate 23, the area of ​​the CMOS circuit on substrate 11 will generally depend on the value of M, and the area of ​​the CMOS circuit on substrate 23 will generally depend on the value of N. In these cases, if the area of ​​the semiconductor device is determined by the area of ​​the CMOS circuit, then in the former case the area of ​​the semiconductor device will generally depend on the value of M+N, and in the latter case the area of ​​the semiconductor device will generally depend on the larger of the value of M and the value of N. When M=N, the area of ​​the semiconductor device in the former case will generally depend on the value of 2N, and the area of ​​the semiconductor device in the latter case will generally depend on the value of N, with the area of ​​the latter being half the area of ​​the former. Therefore, according to this embodiment, by configuring the CMOS circuit with transistors 12 and 24, it is possible to reduce the area of ​​the semiconductor device.

[0033] Furthermore, if the area of ​​the CMOS circuit on substrate 11 or the area of ​​the CMOS circuit on substrate 23 becomes small, the area of ​​the semiconductor device may again be determined by the area of ​​the memory cell array. Even in this case, the above effects can be obtained. For example, if the "area of ​​the CMOS circuit on substrate 11" in the former case is 2N, and the "area of ​​the CMOS circuit on substrate 11" and the "area of ​​the CMOS circuit on substrate 23" in the latter case are both N, and the area of ​​the memory cell array is 1.5N, then the "area of ​​the semiconductor device" in the former case will be 2N, and the "area of ​​the semiconductor device" in the latter case will be 1.5N.

[0034] In this embodiment, the semiconductor device comprises one circuit chip 1 and one array chip 2, but it may instead comprise one circuit chip 1 and two or more array chips 2. In this case, the transistors constituting the CMOS circuit may be arranged on three or more substrates.

[0035] Figure 2 is a cross-sectional view showing the structure of the columnar portion 29 of the first embodiment.

[0036] Figure 2 shows one of the multiple columnar portions 29 shown in Figure 1. The columnar portion 29 shown in Figure 2 includes a memory insulating film 33, a channel semiconductor layer 34, a core insulating film 35, and a core semiconductor layer 36 (not shown). The memory insulating film 33 includes a block insulating film 33a, a charge storage layer 33b, and a tunnel insulating film 33c arranged in order within the laminated film 22. The block insulating film 33a is, for example, an SiO2 film. The charge storage layer 33b is, for example, a SiN film (silicon nitride film). The tunnel insulating film 33c is, for example, an SiO2 film.

[0037] Figure 2 further shows multiple electrode layers 31 and multiple insulating films 32 contained within the laminated film 22, similar to Figure 1. In Figure 2, the laminated film 22 in region R2 includes multiple word lines WL, source-side selection lines SGS, and drain-side selection lines SGD as these electrode layers 31. These word lines WL, together with the memory insulating film 33 and the channel semiconductor layer 34, form multiple memory cells. The source-side selection lines SGS are positioned above these word lines WL, and the drain-side selection lines SGD are positioned below these word lines WL. Note that in Figure 2, two or more source-side selection lines SGS may be positioned above these word lines WL, or two or more drain-side selection lines SGD may be positioned below these word lines WL. The same applies to the laminated film 22 in region R1, etc.

[0038] Figures 3 and 4 are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment.

[0039] Figure 3 shows a circuit wafer W1 containing circuit chip 1 and an array wafer W2 containing array chip 2. Figure 3 further shows the top surface S1 of circuit wafer W1 and the top surface S2 of array wafer W2. The orientation of array wafer W2 shown in Figure 3 is the opposite of the orientation of array chip 2 shown in Figure 1. The semiconductor device of this embodiment is manufactured by bonding circuit wafer W1 and array wafer W2 together, as described above. Figure 3 shows array wafer W2 before its orientation is reversed for bonding, and Figure 4 shows array wafer W2 after its orientation has been reversed for bonding and bonded to circuit wafer W1.

[0040] The semiconductor device of this embodiment is manufactured, for example, as follows. First, a plurality of transistors 12, an interlayer insulating film 13, a plurality of plugs 14a to 14f, a plurality of wiring layers 15a to 15e, and a plurality of metal pads 16 are formed on a substrate 11 (Figure 3). Then, an interlayer insulating film 21, a laminated film 22, a plurality of metal pads 26, a plurality of plugs 27a to 27f, a plurality of wiring layers 28a to 28c, and a plurality of columnar portions 29 are formed on a substrate 23 (Figure 3).

[0041] Next, as shown in Figure 4, the circuit wafer W1 and the array wafer W2 are bonded together by mechanical pressure. This bonds the interlayer insulating film 13 and the interlayer insulating film 21. Next, the circuit wafer W1 and the array wafer W2 are annealed. This bonds the metal pad 16 and the metal pad 26.

[0042] Subsequently, substrates 11 and 23 are thinned by CMP (Chemical Mechanical Polishing) as needed. At this time, the thickness D2 of substrate 23 may be thinner than or thicker than the thickness D1 of substrate 11. Furthermore, multiple transistors 24, interlayer insulating film 25, multiple plugs 27g to 27j, and multiple wiring layers 28d to 28e are formed on substrate 23 (see Figure 1). Plugs 27i to 27j are formed to penetrate substrate 23. Then, the circuit wafer W1 and array wafer W2 are cut into multiple semiconductor chips. In this way, the semiconductor device shown in Figure 1 is manufactured.

[0043] Figure 1 shows the interface between the interlayer insulating film 13 and the interlayer insulating film 21, and the interface between the metal pad 16 and the metal pad 26. However, after the annealing described above, these interfaces are generally no longer visible. Nevertheless, the locations where these interfaces were located can be estimated by detecting the inclination of the side surface of the metal pad 16, the inclination of the side surface of the metal pad 26, and the positional displacement between the metal pad 16 and the metal pad 26.

[0044] Figure 5 is a block diagram showing the configuration of the semiconductor device according to the first embodiment.

[0045] In Figure 5, the semiconductor device of this embodiment includes a memory cell array 41, an I / O (Input / Output) control circuit 42, a logic control circuit 43, a status register 44, an address register 45, a command register 46, a control circuit 47, a ready / busy circuit 48, a voltage generator 49, a row decoder 51, a sense amplifier 52, a data register 53, and a column decoder 54.

[0046] The memory cell array 41 is formed by the aforementioned stacked film 22 and columnar portion 29, and contains multiple memory cells. The I / O control circuit 42 exchanges input and output signals with a controller (not shown) via data lines DQ0-0 to DQ7-0. The logic control circuit 43 receives the chip enable signal BCE-0, command latch enable signal CLE-0, address latch enable signal ALE-0, write enable signal BWE-0, read enable signals RE-0 and BRE-0, and controls the operation of the I / O control circuit 42 and control circuit 47 according to these signals.

[0047] The status register 44 stores the status of read, write, and erase operations and is used to notify the controller of the completion of these operations. The address register 45 is used to store address signals received by the I / O control circuit 42 from the controller. The command register 46 is used to store command signals received by the I / O control circuit 42 from the controller.

[0048] The control circuit 47 controls the status register 44, ready / busy circuit 48, voltage generator 49, row decoder 51, sense amplifier 52, data register 53, and column decoder 54 in response to command signals from the command register 46 to perform read operations, write operations, erase operations, etc.

[0049] The ready / busy circuit 48 sends a ready / busy signal RY / BBY-0 to the controller depending on the operating conditions of the control circuit 47. This allows the control circuit 47 to indicate whether it is ready to accept commands or not. The voltage generator 49 generates the voltages required for read, write, and erase operations.

[0050] The row decoder 51 applies a voltage to the word line WL of the memory cell array 41. The sense amplifier 52 detects the data read to the bit line BL of the memory cell array 41. The data register 53 is used to store data from the I / O control circuit 42 and the sense amplifier 52. The column decoder 54 decodes the column address and selects a latch circuit in the data register 53 based on the decoding result. The row decoder 51, sense amplifier 52, data register 53, and column decoder 54 function as interfaces for read, write, and erase operations to the memory cell array 41.

[0051] These blocks, with the exception of the memory cell array 41, are included within the CMOS circuit described above and are formed by transistors 12 and 24. For example, the sense amplifier 52, data register 53, and column decoder 54 are formed by transistors 12 on substrate 11, while the other blocks are formed by transistors 24 on substrate 23.

[0052] In this embodiment, the voltage generator 49 and the raw decoder 51 are formed from HV transistors, while the other blocks are formed from LV transistors. Therefore, the voltage generator 49 and the raw decoder 51 may be placed on the substrate 23, and the other blocks may be placed on the substrate 11. This makes it possible to place only LV transistors on the substrate 11, or only HV transistors on the substrate 23.

[0053] Furthermore, the sense amplifier 52 includes a transistor that functions as a switch for the bit line BL, for example. This transistor is, for example, an HV transistor. In this case, a portion of the sense amplifier 52 may be placed on the substrate 11, and the remaining portion of the sense amplifier 52 may be placed on the substrate 23, thereby placing the HV transistor on the substrate 23 as transistor 24.

[0054] Furthermore, the voltage generator 49 includes, for example, a capacitor. Therefore, the area of ​​the voltage generator 49 is often large. In this case, when deciding to move a portion of the block on the substrate 11 onto the substrate 23 during the design of the semiconductor device, it is desirable to move the large-area voltage generator 49 onto the substrate 23.

[0055] Figures 6 to 9 are cross-sectional views showing details of the manufacturing method of a semiconductor device according to the first embodiment. Specifically, Figures 6 to 9 show details of the process related to the array wafer W2.

[0056] Figure 6(a) shows the array wafer W2 before bonding. First, an interlayer insulating film 21 (more precisely, a part of the interlayer insulating film) is formed on the substrate 23, openings H1 and H2 are formed in the interlayer insulating film 21 and the substrate 23, and wiring material 28c1 for the wiring layer 28c is formed on the interlayer insulating film 21 and the substrate 23 (Figure 6(a)). As a result, the wiring material 28c1 is formed in the openings H1 and H2. Opening H1 is not completely filled with the wiring material 28c1, while opening H2 is completely filled with the wiring material 28c1. In Figure 6(a), region R4 is the alignment mark region including opening H1, region R5 is the ACP region including opening H2, and region R6 is the edge seal region.

[0057] Next, an insulating film 61 is formed on the wiring material 28c1, a portion of the insulating film 61 is removed by etching, and wiring material 28c2 for the wiring layer 28c is formed on the wiring material 28c1 and the insulating film 61 (Figure 6(b)). As a result, a wiring layer 28c containing wiring materials 28c1 and 28c2 that are electrically connected to each other is formed on the interlayer insulating film 21. The opening H1 is not completely filled with wiring materials 28c1 and 28c2.

[0058] Next, a laminated film 22 is formed on the wiring material 28c2, and multiple plugs 27f and multiple columnar portions 29 are formed within the laminated film 22 (Figure 6(b)). These plugs 27f are formed within the laminated film 22 via an insulating film 62. Also, a wiring layer 64 is formed within the laminated film 22 via an insulating film 63 (Figure 6(b)). The plugs 27f, columnar portions 29, and wiring layer 64 are formed to reach the wiring layer 28c. Note that the plugs 27f shown in Figure 6(b) differ from the plugs 27f shown in Figure 1 in that they are formed within the laminated film 22. Alternatively, the laminated film 22 may be formed by alternately stacking multiple sacrificial layers and multiple insulating films 32, and replacing these sacrificial layers with multiple electrode layers 31. A portion of the laminated film 22 is embedded in the opening H1.

[0059] Next, the array wafer W2 is bonded to a circuit wafer W1 (not shown) (Figure 7(a)). As a result, the orientation of the array wafer W2 shown in Figure 7(a) is opposite to the orientation of the array chip 2 shown in Figure 6(b). Next, the substrate 23 is thinned by CMP (Figure 7(b)). This thinning is performed so that the layers within the openings H1 and H2 are not exposed on the upper surface of the substrate 23.

[0060] Next, the transistor 24, the insulating film 25a for the interlayer insulating film 25, the plug 27g, and the wiring layer 28d are formed on the substrate 23 (Figure 8(a)). Next, the insulating film 25b for the interlayer insulating film 25 and the plug 27h are formed on the insulating film 25a and the wiring layer 28d (Figure 8(b)).

[0061] Next, a wiring layer 28e and an insulating film 25c for the interlayer insulating film 25 are formed on the insulating film 25b and plug 27h (Figure 9(a)). The wiring layer 28e shown in Figure 9(a) differs from the wiring layer 28e shown in Figure 1 in that it is formed within the interlayer insulating film 25.

[0062] Next, openings H3, H4, and H5 are formed by etching in the interlayer insulating film 25, substrate 23, interlayer insulating film 21, and wiring layer 28c (Figure 9(b)). The openings H3, H4, and H5 are formed in regions R3, R5, and R6, respectively.

[0063] Next, an insulating film 65 is formed on the interlayer insulating film 25, and a portion of the insulating film 65 is removed by etching (Figure 9(b)). As a result, the plug 27f is exposed at the bottom of opening H3, the wiring layer 28c is exposed at the bottom of opening H4, and the wiring layer 64 is exposed at the bottom of opening H5.

[0064] Next, a wiring layer 66 is formed on the insulating film 65, and a portion of the wiring layer 66 is removed by etching (Figure 9(b)). As a result, wirings 66a to 66d are formed from the wiring layer 66. Wiring 66a is formed on the insulating film 65 within region R4. Wiring 66b is formed on the side and bottom surfaces of the opening H3 within region R3 and is placed on the plug 27f. Wiring 66c is formed on the side and bottom surfaces of the opening H4 within region R5 and is placed on the wiring layer 28c. Wiring 66d is formed on the side and bottom surfaces of the opening H5 within region R6 and is placed on the wiring layer 64. The wiring layer 66 is, for example, a metal layer containing an Al (aluminum) layer. In Figure 9(b), unlike in Figure 1, at least a portion of the wiring in the wiring layer 66 functions as a bonding pad.

[0065] In this way, the semiconductor device of this embodiment is manufactured. The steps that were omitted from the description in Figures 6(a) to 9(b) can be carried out in the same way as the steps described with reference to Figures 3 and 4.

[0066] Figure 10 is a cross-sectional view showing an example of the structure of a semiconductor device according to the first embodiment.

[0067] In the example shown in Figure 10(a), the substrate 23 includes a semiconductor layer 23a, wells 23b to 23c, and diffusion layers 23d to 23f, and the transistor 24 further includes diffusion layers 24e to 24f. Figure 10(a) also shows the element isolation insulating film 71.

[0068] Well 23b is an N-type well located on the upper side of the semiconductor layer 23a. Well 23c is a P-type well located on the upper side of well 23b. The substrate 23 shown in Figure 10(a) has a triple-well structure including the semiconductor layer 23a, well 23b, and well 23c.

[0069] The diffusion layers 23d, 23e, and 23f are formed near the top surface of the substrate 23, within the semiconductor layer 23a, well 23b, and well 23c, respectively, and are in contact with the plug 27g. The plugs 27g on the diffusion layers 23d, 23e, and 23f are used to control the potentials of the semiconductor layer 23a, well 23b, and well 23c to predetermined values. The predetermined potentials of the semiconductor layer 23a, well 23b, and well 23c are, for example, 0V, 0~2V, and -2V, respectively. Each of the diffusion layers 23d, 23e, and 23f is sandwiched between the element isolation insulating film 71. Similarly, the diffusion layers 24c~24f of the transistor 24 are also sandwiched between the element isolation insulating film 71. In the example shown in Figure 10(a), the diffusion layers 23d, 23e, and 23f are p+ type layer, n+ type layer, and p+ type layer, respectively.

[0070] The diffusion layer 24e is located within the diffusion layer 24c and is in contact with the plug 27g. The diffusion layer 24f is located within the diffusion layer 24d and is in contact with the plug 27g. In the example shown in Figure 10(a), the diffusion layers 24c and 24d are n-type layers, and the diffusion layers 24e and 24f are n+-type layers. The transistor 24 shown in Figure 10(a) is formed on the well 23c.

[0071] Figure 10(b) shows a structure similar to that shown in Figure 10(a). However, in the example shown in Figure 10(b), the substrate 23 includes wells 23b to 23c and diffusion layers 23e' to 23f', and some of the plugs 27g are replaced with plugs 27g'. In this case, well 23c is an example of the first well, and plug 27g' is an example of the first plug.

[0072] In the example shown in Figure 10(b), well 23b is an N-type well extending from the top to the bottom of the substrate 23, and well 23c is a P-type well extending from the top to the bottom of the substrate 23. The diffusion layers 23e' and 23f' are formed within wells 23b and 23c near the bottom of the substrate 23, respectively, and are in contact with the plugs 27g'. Therefore, these plugs 27g' are in contact with the bottom of the substrate 23 and are located below wells 23b and 23c, respectively. The plugs 27g' below the diffusion layers 23e' and 23f' are used to control the potential of wells 23b and 23c to the predetermined values ​​mentioned above. In the example shown in Figure 10(b), the diffusion layers 23e' and 23f' are an n+ type layer and a p+ type layer, respectively.

[0073] In this example, by replacing some of the plugs 27g with plugs 27g', it is possible to reduce the area required to arrange the plugs 27g (and 27g'). Furthermore, in this example, it is possible to eliminate the need for the semiconductor layer 23a.

[0074] Figure 10(c) shows a structure similar to that shown in Figure 10(b). However, in the example shown in Figure 10(c), the substrate 23 includes a well 23c and a diffusion layer 23f', and the element isolation insulating film 71 penetrates the substrate 23. In this case, well 23c is an example of a first well, and plug 27g' is an example of a first plug.

[0075] In the example shown in Figure 10(c), the well 23c is a P-type well extending from the top to the bottom surface of the substrate 23, and is sandwiched between element isolation insulating films 71 that penetrate the substrate 23. The diffusion layer 23f' is formed in the well 23c near the bottom surface of the substrate 23 and is in contact with the plug 27g'. Therefore, this plug 27g' is in contact with the bottom surface of the substrate 23 and is located below the well 23c. The plug 27g' below the diffusion layer 23f' is used to control the potential of the well 23c to the predetermined value mentioned above. In the example shown in Figure 10(c), the diffusion layer 23f' is a p+ type layer.

[0076] In this example, similar to the example shown in Figure 10(b), it is possible to reduce the area required to arrange plugs 27g (and 27g') by replacing some of the plugs 27g with plugs 27g'. Furthermore, in this example, it is possible to eliminate the semiconductor layer 23a and well 23b.

[0077] As described above, the semiconductor device of this embodiment includes a transistor 12 on a substrate 11 for the circuit chip 1 and a transistor 24 on a substrate 23 for the array chip 2. Therefore, according to this embodiment, it is possible to suitably reduce the area of ​​the semiconductor device (semiconductor chip).

[0078] (Second Embodiment) Figure 11 is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment.

[0079] The semiconductor device of this embodiment (Figure 11) has the same structure as the semiconductor device of the first embodiment (Figure 1). However, the structure of the semiconductor device of this embodiment differs from the structure of the semiconductor device of the first embodiment in several respects, as will be explained below. Note that Figure 11 shows the array chip 2, but the circuit chip 1 is not shown.

[0080] The arrangement of plugs 27e and 27f shown in Figure 11 differs from the arrangement of plugs 27e and 27f shown in Figure 1. Plug 27e shown in Figure 11 is electrically connected to the electrode layer 31, similar to plug 27e shown in Figure 1, but is located on the upper side of the laminated film 22 instead of the lower side. Plug 27f shown in Figure 11 has a length in the Z direction that is longer than the thickness of the laminated film 22 in the Z direction, similar to plug 27f shown in Figure 1, but is located inside the laminated film 22 instead of outside it. Plugs 27e to 27f shown in Figure 11 are examples of second plugs. The semiconductor device of this embodiment further comprises a plurality of plugs 27b', a wiring layer 28b', a plurality of plugs 27b'', and a wiring layer 28b''.

[0081] The following describes the details of the plug 27e shown in Figure 11.

[0082] Figure 11 illustrates three plugs 27e. Each of these plugs 27e is formed within the laminated film 22 and substrate 23 via an insulating film 81 and is electrically connected to one electrode layer 31 and one plug 27g. Specifically, the left plug 27e penetrates the first and second electrode layers 31 (second electrode layer) from the top and is electrically connected to the third electrode layer 31 (first electrode layer) from the top. The right plug 27e penetrates the first electrode layer 31 (second electrode layer) from the top and is electrically connected to the second electrode layer 31 (first electrode layer) from the top. The center plug 27e penetrates the first to fourth electrode layers 31 (second electrode layers) from the top and is electrically connected to the fifth electrode layer 31 (first electrode layer) from the top. According to this embodiment, by arranging the plugs 27e on the upper side of the laminated film 22, it is possible to easily electrically connect the electrode layers 31 (e.g., word lines) and the transistors 24 (e.g., word line switches). The word line switch is, for example, an HV transistor located within the low decoder 81 (Figure 5).

[0083] Next, we will explain the details of plug 27f shown in Figure 11.

[0084] Plug 27f is formed within the laminated film 22 and substrate 23 via an insulating film 82 and is electrically connected to one plug 28b'' and one plug 27g. Specifically, plug 27f is electrically connected to the metal pad 26 via plug 27a, wiring layer 28a, plug 27b, wiring layer 28b, plug 27b', wiring layer 28b', plug 27b'', and wiring layer 28b''. This metal pad 26 is electrically connected, for example, to a transistor 12 (not shown). Plug 27f is also electrically connected to the bonding pad 84 via plug 27g, wiring layer 28d, plug 27h, wiring layer 28e, and plug 83. The bonding pad 84 is formed on the interlayer insulating film 25.

[0085] Figure 12 is a cross-sectional view showing the structure of a semiconductor device of a comparative example of the second embodiment.

[0086] The semiconductor device of this comparative example (Figure 12) has the same structure as the semiconductor device of the second embodiment (Figure 11). However, the arrangement of plugs 27e and 27f in this comparative example differs from the arrangement of plugs 27e and 27f in the second embodiment.

[0087] In this comparative example, the plug 27e is located on the underside of the laminated film 22 having a stepped structure. Therefore, each plug 27e in this comparative example is electrically connected to the plug 27g via the wiring layer 28b'', the plug 27e', and the wiring layer 86. In Figure 12, each wiring within the wiring layer 86 is formed in the substrate 23 via the insulating film 85. Thus, each plug 27e in this comparative example is electrically connected to the plug 27g via a complex wiring structure. On the other hand, according to this embodiment, each plug 27e can be electrically connected to the plug 27g via a simple wiring structure.

[0088] In this comparative example, plug 27f is located on the outside of the laminated film 22 having a stepped structure. Also, plug 27f in this comparative example is electrically connected to plug 27g via the wiring layer 86, similar to plug 27e in this comparative example. On the other hand, according to this embodiment, plug 27f can be directly electrically connected to plug 27g.

[0089] Figure 13 is a cross-sectional view showing an example of the structure of a semiconductor device according to a second embodiment.

[0090] Figure 13(a) is an enlarged cross-sectional view showing the transistor 24 and plug 27e in Figure 11. In the example shown in Figure 13(a), the plug 27e is electrically connected to the diffusion layer 24d of the transistor 24 via the right plug 27g, the wiring layer 28e, and the central plug 27g.

[0091] Figure 13(b) shows one transistor 24 and two plugs 27e. In the example shown in Figure 13(b), the left plug 27e is electrically connected to the diffusion layer 24c of the transistor 24 via a metal layer 87, and the right plug 27e is electrically connected to the diffusion layer 24d of the transistor 24 via a metal layer 87. Each metal layer 87 is provided in a ring shape on the side of the plug 27e and is in contact with the plug 27e and the diffusion layer 27c (or 27d). Each metal layer 87 is, for example, a multilayer film including a Ti (titanium) layer and a TiN (titanium nitride) film. According to this example, each plug 27e can be electrically connected to the transistor 24 via a simple wiring structure.

[0092] Figure 14 shows a cross-sectional view and a plan view illustrating another example of the structure of the semiconductor device according to the second embodiment.

[0093] Figure 14(c) is a plan view showing an example of the structure of transistor 24. Figures 14(a) and 14(b) show the A-A' and B-B' cross-sections shown in Figure 14(c), respectively. Figures 14(a) and 14(b) each show a single plug 27e formed within the multilayer film 22 and the substrate 23.

[0094] Hereafter, the symbol 24b shown in Figure 14(c) will be referred to as "wiring 24b". Wiring 24b on the A-A' line functions as the gate electrode of transistor 24. On the other hand, wiring 24b on the B-B' line functions as a routing wire that supplies a signal to the gate electrode of transistor 24. The black circle on the B-B' line shown in Figure 14(c) indicates the position of plug 27e shown in Figure 14(b).

[0095] Figure 14(b) shows an element isolation insulating film 88 provided within the substrate 23. The plug 27e shown in Figure 14(b) is provided within the substrate 23 via the element isolation insulating film 88 and is in contact with the lower surface of the wiring 24b. In this example, it is possible to electrically connect this plug 27 to the transistor 24 via a simple wiring structure.

[0096] Figures 15 to 17 are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the second embodiment. Specifically, Figures 15 to 17 show the process of forming the transistor 24 and plug 27e shown in Figure 13(b).

[0097] First, after bonding the circuit wafer W1 (not shown) and the array wafer W2, multiple contact holes are formed in the substrate 23 and the laminated film 22, and multiple plugs 27e are formed in these contact holes via an insulating film 81 (Figure 15(a)).

[0098] Next, the insulating film 81 in the substrate 23 is removed by etching (Figure 15(b)). As a result, multiple ring-shaped openings H are formed between the substrate 23 and the plug 27e. This etching is performed, for example, by wet etching using a dilute hydrofluoric acid aqueous solution.

[0099] Next, a metal layer 87 is formed over the entire surface of the substrate 23 (Figure 16(a)). As a result, the metal layer 87 is formed inside the opening H and on the upper surface of the substrate 23.

[0100] Next, the substrate 23 and the metal layer 87 are annealed (Figure 16(b)). This annealing is performed at, for example, 550°C. As a result, the substrate 23 near the metal layer 87 changes from, for example, silicon to a metal silicide (e.g., titanium silicide).

[0101] Next, the metal layer 87 inside the opening H is removed (Figure 17(a)). As a result, the upper surface of the substrate 23 is exposed again.

[0102] Next, a gate insulating film 24a and a gate electrode 24b are formed sequentially on the substrate 23, and diffusion layers 24c and 24d are formed within the substrate 23 (Figure 17(b)). As a result, the transistor 24 is formed on the upper surface of the substrate 23. The diffusion layers 24c and 24 are formed so as to sandwich the gate electrode 24b and are also formed so as to be in contact with the metal layer 87.

[0103] Figure 18 is a cross-sectional view showing the structure of a semiconductor device of a modified example of the second embodiment.

[0104] The semiconductor device of this modified example (Figure 18) has the same structure as the semiconductor device of the second embodiment (Figure 11). However, the shape of the laminated film 22 in this modified example is different from the shape of the laminated film 22 in the second embodiment.

[0105] The laminated film 22 of this modified example has a structure that combines a stepped structure and a non-stepped structure, as shown in Figure 18. Specifically, the first to sixth electrode layers 31 from the top have a non-stepped shape, while the seventh to eighth electrode layers 31 from the top have a stepped shape. The first to sixth electrode layers 31 from the top include, for example, a word line WL and a source-side selection line SGS (see Figure 2). The seventh to eighth electrode layers 31 from the top include, for example, a drain-side selection line SGD (see Figure 2).

[0106] In Figure 18, some of the plugs 27e are positioned on the upper side of the laminated film 22, similar to Figure 11, while the remaining plugs 27e are positioned on the lower side of the laminated film 22, similar to Figure 12. Each of the former plugs 27e is electrically connected to one of the first to sixth electrode layers 31 from the top, and each of the latter plugs 27e is electrically connected to one of the seventh to eighth electrode layers 31 from the top. Figure 18 further shows plugs 27e', an insulating film 85, and a wiring layer 86, similar to Figure 12. However, the plugs 27e' shown in Figure 18 are provided within the laminated film 22 via an insulating film 89.

[0107] When the plug 27e is placed on the upper side of the laminated film 22, it may not be possible to correctly position the plug 27e on the electrode layer 31 near the lower surface of the laminated film 22. This is because the contact hole for such a plug 27e becomes deeper. For example, a plug 27e that should be placed on the 7th electrode layer 31 from the top may end up being placed on the 8th electrode layer 31 from the top.

[0108] Therefore, in this modified example, the plugs 27e for the electrode layers 31 located near the bottom surface of the laminated film 22 are placed on the bottom side of the laminated film 22, rather than the top side. For example, the plugs 27e for the 7th to 8th electrode layers 31 from the top are placed on the bottom side of the laminated film 22. This makes it easy to correctly position these plugs 27e.

[0109] As described above, the semiconductor device of this embodiment includes a transistor 12 on a substrate 11 for the circuit chip 1 and a transistor 24 on a substrate 23 for the array chip 2. Therefore, according to this embodiment, it is possible to suitably reduce the area of ​​the semiconductor device (semiconductor chip). Furthermore, according to this embodiment, by arranging at least some of the plugs 27e on the upper side of the laminated film 22, it is possible to easily electrically connect the electrode layer 31 and the transistor 24.

[0110] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel apparatus and methods described herein can be implemented in a variety of other forms. Furthermore, various omissions, substitutions, and modifications can be made to the embodiments of the apparatus and methods described herein, without departing from the spirit of the invention. The appended claims and equivalents are intended to include such forms and modifications that are included in the scope and spirit of the invention. [Explanation of Symbols]

[0111] 1: Circuit chip, 2: Array chip, 11: substrate, 12: transistor, 12a: gate insulating film, 12b: Electrode gate, 12c~12d: Diffusion layer, 13: Interlayer insulating film, 14a~14f: Plug, 15a~15e: Wiring layer, 16: Metal pad, 21: Interlayer insulating film, 22: Multilayer film, 23: Substrate, 23a: Semiconductor layer, 23b~23c: wells, 23d~23f: diffusion layer, 23e': diffusion layer, 23f': diffusion layer, 24: transistor, 24a: gate insulating film, 24b: Electrode gate, 24c~24f: Diffusion layer, 25: Interlayer insulating film, 25a~25c: Insulating film, 26: Metal pad, 27a~27j: Plug 27b': plug, 27b”: plug, 27e': plug, 27g': plug 28a~28e: wiring layer, 28b': wiring layer, 28b": wiring layer, 28c1~28c2: Wiring material, 29: Columnar part, 31: Electrode layer, 32: Insulating film, 33: Memory insulating film, 33a: Block insulating film, 33b: Charge storage layer, 33c: Tunnel insulating film, 34: Channel semiconductor layer, 35: Core insulating film, 36: Core semiconductor layer, 41: Memory cell array, 42: I / O control circuit 71, 43: Logic control circuit, 44: Status register, 45: Address register, 46: Command register, 47: Control circuit, 48: Ready / busy circuit, 49: Voltage generator, 51: Raw decoder, 52: Sense amplifier, 53: Data register, 54: Column decoder, 61: insulating film, 62: insulating film, 63: insulating film, 64: wiring layer, 65: insulating film, 66: Wiring layer, 66a~66d: Wiring, 71: Element isolation insulating film, 81: Insulating film, 82: Insulating film, 83: Plug, 84: Bonding pad, 85: Insulating film, 86: Wiring layer, 87: Metal layer, 88: Element isolation insulating film, 89: Insulating film

Claims

1. First circuit board and A first transistor provided on the upper surface of the first substrate, A memory cell array provided above the first transistor, A second substrate provided above the memory cell array, A second transistor provided on the upper surface of the second substrate, The second plug that penetrates the second substrate, Equipped with, The memory cell array includes a plurality of electrode layers spaced apart from each other. The second plug is electrically connected to the first electrode layer among the plurality of electrode layers, The second plug penetrates the second electrode layer among the plurality of electrode layers. Semiconductor equipment.

2. First circuit board and A first transistor provided on the upper surface of the first substrate, A first bonding pad provided above the first transistor, A second adhesive pad directly bonded to the first adhesive pad, A bit line provided above the second adhesive pad, A memory cell array provided above the bit line, A source line provided above the memory cell array, A second substrate is provided above the source line, A second transistor provided on the upper surface of the second substrate, Equipped with, The thickness of the second substrate is greater than the thickness of the first substrate. The gate insulating film of the first transistor has a first film thickness, The gate insulating film of the second transistor has a second film thickness that is greater than the first film thickness. The first transistor comprises only transistors in which the gate insulating film has the first film thickness. Semiconductor equipment.

3. The gate insulating film of the first transistor has a first film thickness, or a second film thickness greater than the first film thickness. The semiconductor device according to claim 1, wherein the gate insulating film of the second transistor has the second film thickness.

4. The circuit further comprises a circuit for controlling the memory cell array, The semiconductor device according to claim 1 or 2, wherein the circuit includes the first transistor and the second transistor.

5. The second substrate includes a first well that extends from the top surface to the bottom surface of the second substrate. The semiconductor device according to claim 1 or 2, wherein the second transistor is provided on the first well.

6. The semiconductor device according to claim 5, further comprising a first plug in contact with the lower surface of the second substrate and located below the first well.

7. The semiconductor device according to claim 1 or 2, further comprising an element isolation insulating film provided in the second substrate and penetrating the second substrate.

8. The semiconductor device according to claim 1, wherein the second plug is electrically connected to a semiconductor layer that penetrates the plurality of electrode layers.

9. The semiconductor device according to claim 1, wherein the second plug is electrically connected to the first transistor.

10. The semiconductor device according to claim 1, wherein the second plug is electrically connected to a bonding pad provided above the second substrate.

11. Further comprising a second plug that penetrates the second substrate, The memory cell array includes a plurality of electrode layers spaced apart from each other. The semiconductor device according to claim 2, wherein the second plug is electrically connected to the first electrode layer among the plurality of electrode layers.

12. The second plug penetrates the second electrode layer among the plurality of electrode layers, The second electrode layer is located between the second substrate and the first electrode layer. The semiconductor device according to claim 11.

13. The semiconductor device according to claim 1 or 11, further comprising a metal layer in contact with the side surface of the second plug and the side surface of the diffusion layer for the second transistor.

14. The semiconductor device according to claim 1 or 11, wherein the second plug is in contact with the underside of the wiring including the gate electrode of the second transistor at a position other than the gate electrode.

15. The semiconductor device according to claim 1 or 11, wherein the plurality of electrode layers include portions having a stepped shape.

16. A first transistor is formed on the first substrate. A memory cell array is formed above the first transistor. The second substrate is bonded to the first substrate via the first transistor and the memory cell array. After the bonding, a second transistor is formed on the second substrate. A second plug is formed that penetrates the second substrate. This includes, The memory cell array includes a plurality of electrode layers spaced apart from each other. The second plug is electrically connected to the first electrode layer among the plurality of electrode layers, The second plug penetrates the second electrode layer among the plurality of electrode layers, A method for manufacturing a semiconductor device.

17. A first transistor is formed on the first substrate. A first bonding pad is formed above the first transistor. A source line is formed above the second substrate. A memory cell array is formed above the source line. A bit line is formed above the memory cell array. A second bonding pad is formed above the bit line. The first substrate and the second substrate are bonded together so that the first bonding pad and the second bonding pad are directly joined. A second transistor is formed on the side of the second substrate opposite to the side of the memory cell array. This includes, The thickness of the second substrate is greater than the thickness of the first substrate. The gate insulating film of the first transistor has a first film thickness, The gate insulating film of the second transistor has a second film thickness that is greater than the first film thickness. A semiconductor device is manufactured that comprises only transistors having the gate insulating film having the first thickness as the first transistor. A method for manufacturing a semiconductor device.

18. The method for manufacturing a semiconductor device according to claim 16 or 17, wherein the first transistor and the second transistor are included in a circuit for controlling the memory cell array.

19. After the bonding, a second plug is formed that penetrates the second substrate. Within the second substrate, a metal layer is formed on the side surface of the second plug. This includes, The method for manufacturing a semiconductor device according to claim 17, wherein the diffusion layer for the second transistor is formed in the second substrate so as to be in contact with the metal layer.

20. Within the second substrate, a metal layer is formed on the side surface of the second plug. This includes, The method for manufacturing a semiconductor device according to claim 16, wherein the diffusion layer for the second transistor is formed in the second substrate so as to be in contact with the metal layer.

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