Method for manufacturing silicon carbide-based semiconductor structures and intermediate composite structures

Abstract

The present invention relates to a method for producing a semiconductor structure, the method comprising the steps of: a) forming a semiconductor structure having a grain size between 4 microns and 35 microns, a porosity between 6% and 17%, and a thermal expansion coefficient of 4×10 -6 / ℃~5×10 -6 / ° C., b) depositing a carrier layer made of polycrystalline silicon carbide with a thickness between 10 microns and 200 microns on the front side of the temporary substrate, c) transferring, directly or via an intermediate layer, a working layer made of monocrystalline silicon carbide to the carrier layer to form a composite structure, the transfer being carried out by bonding by molecular adhesion, d) forming an active layer on the working layer, and e) removing the temporary substrate to form a semiconductor structure comprising the active layer, the working layer and the carrier layer. The invention also relates to a composite structure obtained in an intermediate step of this manufacturing method.

Description

[Technical Field]

[0001] The present invention relates to the field of semiconductor materials for ultra-miniature electronic components. In particular, the present invention relates to a method for producing a semiconductor structure comprising an active layer made of high-quality single-crystal silicon carbide, which is intended to include or house electronic components, wherein the active layer is arranged on a carrier layer made of polycrystalline silicon carbide. The present invention further relates to an intermediate composite structure obtained by the above method. [Background technology]

[0002] Silicon carbide (SiC) semiconductor materials have seen a significant increase in interest in recent years due to their ability to enhance energy processing capabilities. SiC is increasingly being used to manufacture innovative power devices to meet the demands of growing areas of electronic technology, particularly electric vehicles.

[0003] Power devices and integrated power supply systems based on single-crystal silicon carbide can achieve much higher power densities compared to similar conventional devices made from silicon, and this can be accomplished with a relatively small active region. To further reduce the dimensions of power devices in SiC, it is advantageous to manufacture components in a vertical orientation instead of a lateral orientation. For this to work, vertical electrical conduction between electrodes positioned on the front and back of the component assembly must be permitted by the assembly.

[0004] However, bulk substrates made from single-crystal SiC for the microelectronics industry remain expensive, and sourcing large sizes is difficult. Furthermore, when manufactured on bulk substrates, assemblies of electronic components often need to have a back surface of the substrate thinned to approximately 100 microns to reduce vertical electrical resistivity and / or to meet space and miniaturization requirements.

[0005] Therefore, to manufacture composite structures that typically include a thin layer made of single-crystal SiC on a relatively low-cost carrier substrate, and where this thin layer is used to form electronic components, it is advantageous to use a thin-layer transfer solution. One well-known solution for thin-layer transfer is the Smart Cut™ method, which is based on implanting light ions and bonding them by direct bonding. Such a method makes it possible to manufacture composite structures that include a thin layer made of c-SiC, obtained from a donor substrate made of single-crystal SiC (c-SiC), enabling perpendicular electrical conduction, by directly contacting a carrier substrate made of polycrystalline SiC (p-SiC), for example. The carrier substrate must be thick enough to be compatible with the formation of components and is ultimately thinned to obtain an assembly of electronic components ready for integration. Even if the carrier substrate is of relatively low quality, the thinning step and material loss are still preferable cost factors to eliminate.

[0006] U.S. Patent No. 8,436,363 is also known, which describes a method for manufacturing a composite structure including a thin layer made of c-Si placed on a metal carrier substrate, the coefficient of thermal expansion of which matches the coefficient of thermal expansion of the thin layer. This manufacturing method involves the following steps: The steps include forming an embedded brittle surface on a donor substrate made of c-SiC, and defining a thin layer between the embedded brittle surface and the front surface of the donor substrate, For example, a metal layer made of tungsten or molybdenum is deposited on the front surface of a donor substrate to form a carrier substrate having sufficient thickness to serve as a reinforcing material. The process involves separating along the embedded weakened surface to form a composite structure on one side, which includes a metal carrier substrate and a thin layer made of c-SiC, and on the other side, which forms the remaining portion of the donor substrate made of c-SiC. Includes.

[0007] A drawback of this method is that the metal carrier substrate may not always be suitable for the production line of electronic components. Depending on the application, the carrier substrate may need to be thinner. [Overview of the project] [Problems that the invention aims to solve]

[0008] The present invention relates to alternative solutions to prior art solutions and aims to improve all or part of the aforementioned shortcomings. In particular, the present invention relates to a method for manufacturing semiconductor structures for electronic components, preferably vertical components, which are manufactured on and / or within an active layer made of high-quality single-crystal silicon carbide, arranged in a carrier layer made of polycrystalline silicon carbide. The present invention also relates to composite structures obtained in an intermediate step of the said manufacturing method. [Means for solving the problem]

[0009] The present invention is a method for manufacturing a semiconductor structure, a) The particle size is between 4 microns and 35 microns, the porosity is between 6% and 17%, and the coefficient of thermal expansion is 4 × 10⁻⁶ -6 / ℃~5×10 -6 The steps include preparing a temporary substrate made from graphite at a temperature between / ℃, b) A step of directly depositing a carrier layer made of polycrystalline silicon carbide, with a thickness of 10 to 200 microns, onto the front surface of a temporary substrate, c) A step of transferring a processed layer made from single-crystal silicon carbide to a carrier layer, either directly or via an intermediate layer, to form a composite structure, wherein the transfer involves bonding by molecular adhesion. d) A step of forming an active layer on the processed layer, e) A step of removing a temporary substrate and forming a semiconductor structure, wherein the structure includes an active layer, a processed layer, and a carrier layer. Regarding methods including

[0010] Other advantageous and non-limiting features of the present invention, individually or in any technically feasible combination, are as follows:

[0011] The deposition in step b) is also performed on the back surface of the temporary substrate and / or on the peripheral edges of the substrate to form a second carrier layer.

[0012] The transcription step c) is, This involves injecting lightweight species into a donor substrate made from single-crystal silicon carbide to define a processed layer together with the front surface of the donor substrate, thereby forming an embedded brittle surface. The front surface of the donor substrate is bonded to the carrier layer by molecular adhesion, either directly or via an intermediate layer. Separating along the embedded weakening surface and transferring the processed layer to the carrier layer Includes.

[0013] The intermediate layer is formed from tungsten, silicon, silicon carbide, or other conductive or semiconductor materials.

[0014] The separation occurs during heat treatment at temperatures between 800°C and 1200°C.

[0015] Step d) includes epitaxially growing at least one additional layer made from doped single-crystal silicon carbide onto the processed layer, wherein the additional layer forms all or part of the active layer.

[0016] This manufacturing method includes step d') for manufacturing all or part of the electronic components on and / or within the active layer, which is inserted between step d) and step e).

[0017] Step e) involves mechanically delaminating the temporary substrate by propagating a crack that penetrates the temporary substrate after applying mechanical stress, the crack extending substantially parallel to the plane of the interface between the temporary substrate and the carrier layer.

[0018] Step e) includes chemically peeling between the carrier layer and the temporary substrate by lateral chemical etching.

[0019] Step e) includes chemically etching all or part of the temporary substrate.

[0020] Step e) includes peeling by causing thermal damage to the graphite of the temporary substrate.

[0021] Step c) includes transferring a second processed layer made of single-crystalline silicon carbide to the second carrier layer directly or through a second intermediate layer, and the transfer performs bonding by molecular adhesion.

[0022] Step d) includes forming a second active layer on the second processed layer.

[0023] By step e), a second semiconductor structure can be formed, the structure includes a second active layer, a second processed layer, and a second carrier layer, and the temporary substrate provided in step a) is in the form of a circular wafer and has a diameter 5% - 10% larger than the target diameter in the semiconductor structure.

[0024] The temporary substrate provided in step a) is in the form of a circular wafer and has a diameter slightly smaller than the target diameter in the semiconductor structure, so the deposition in step b) is also performed on the peripheral edge of the temporary substrate and can reach the target diameter.

[0025] The present invention also A temporary substrate made of graphite having a particle size between 4 microns and 35 microns, a porosity between 6% and 17%, and a coefficient of thermal expansion between 4×10 -6 / °C and 5×10 -6 / °C, and - At least a carrier layer made of polycrystalline silicon carbide, having a thickness between 10 microns and 200 microns, disposed on the front surface of this temporary substrate and in contact with the front surface of this temporary substrate, - A processed layer made from single-crystal silicon carbide placed in this carrier layer and This relates to a composite structure comprising the following features.

[0026] Other advantageous and non-limiting features of the present invention, individually or in any technically feasible combination, are as follows:

[0027] The thickness of the processed layer is between 100 nm and 1500 nm.

[0028] The thickness of the temporary substrate is between 100 microns and 2000 microns.

[0029] The thermal conductivity of the temporary substrate is between 70 W / mK and 130 W / mK.

[0030] The combined thickness of the temporary substrate and carrier layer is between 110 microns and 500 microns, typically 350 microns ± 25 microns.

[0031] Other features and advantages of the present invention will become apparent from the following detailed description of the invention, which is given with reference to the accompanying drawings. [Brief explanation of the drawing]

[0032] [Figure 1] This figure shows a semiconductor structure manufactured according to the manufacturing method of the present invention. [Figure 2a] This figure shows the steps of the manufacturing method according to the present invention. [Figure 2b] This figure shows the steps of the manufacturing method according to the present invention. [Figure 2c] This figure shows the steps of the manufacturing method according to the present invention. [Figure 2d] This figure shows the steps of the manufacturing method according to the present invention. [Figure 2d-1] This figure shows the steps of the manufacturing method according to the present invention. [Figure 2e] This figure shows the steps of the manufacturing method according to the present invention. [Figure 3a]This figure shows the steps of a specific embodiment of the manufacturing method according to the present invention. [Figure 3b] This figure shows the steps of a specific embodiment of the manufacturing method according to the present invention. [Figure 4a] This figure shows the transfer step c) of the manufacturing method according to the present invention. [Figure 4b] This figure shows the transfer step c) of the manufacturing method according to the present invention. [Figure 4c] This figure shows the transfer step c) of the manufacturing method according to the present invention. [Modes for carrying out the invention]

[0033] In each figure, the same reference number may be used for elements of the same type.

[0034] Each diagram is a schematic representation and is not proportional to the actual size for ease of reading. In particular, the thickness of each layer along the z-axis is not proportional to the lateral dimensions along the x-axis and y-axis, and the relative thickness of each layer relative to each other is not necessarily considered in each diagram.

[0035] The present invention relates to a method for manufacturing a semiconductor structure 100 (Figure 1). The semiconductor structure 100 is understood to mean a stack of layers 4, 3, 2 intended to house at least a plurality of micro-electronic components, which also means a stack of layers 4, 3, 2 having the electronic components 40, resulting from wafer-scale manufacturing on and / or within the active layer 4 held in wafer form by a carrier layer 2, and ready to undergo a unification step before being packaged.

[0036] This manufacturing method is advantageous because it can be applied to vertically miniature electronic components that require vertical electrical conduction via a carrier layer 2 that forms mechanical carriers in the component 40.

[0037] This manufacturing method includes, firstly, step a) providing a temporary substrate 1 made of graphite having a front surface 1a, a back surface 1b, and a peripheral edge 1c (Figure 2a). The substrate 1 made of graphite may be manufactured, for example, by plasma deposition, ion sputtering, cathode arc deposition, laser evaporation of graphite, carbonization of resin, etc.

[0038] The graphite of temporary substrate 1 has an average particle size between 4 microns and 35 microns, a porosity between 6% and 17%, and a coefficient of thermal expansion of 4 × 10⁻⁶. -6 / ℃~5×10 -6 The temperature range is between / °C (ambient temperature ~1000°C). These characteristics are selected to provide excellent species for depositing a layer made of polycrystalline silicon carbide (p-SiC), which will be referred to below as carrier layer 2 and will be described with reference to step b) of this method.

[0039] It should be noted that the average particle size corresponds to the arithmetic mean of particle sizes larger than 100 nm. These particle sizes may be measured, for example, by scanning electron microscopy (SEM) or electron backscatter diffraction (EBSD).

[0040] In particular, the average particle size range is specified so that it is of the same order as the average particle size expected in carrier layer 2 in the planes of surfaces 1a and 1b. Since the particle size of carrier layer 2 will not become too small, the thermal conductivity of this carrier layer 2 is thus ensured, and even if the particle size increases during the deposition of carrier layer 2, the specified range of average particle size for graphite keeps it within a controlled particle size range, limiting the roughness of the free surface of the deposited carrier layer 2. The porosity range is also limited to control the surface roughness of carrier layer 2 after subsequent deposition (step b). Typically, the surface roughness is limited to less than 1 micron RMS, or even less than 10 nm RMS, to reduce the smoothing treatment after the deposition of carrier layer 2. Finally, the coefficient of thermal expansion is specified to match the coefficient of thermal expansion of silicon carbide to limit mechanical stress in the structure during high-temperature processing (described later in this method).

[0041] The temporary substrate 1 can withstand temperatures that can reach up to 1400°C when the atmosphere is controlled, i.e., in the absence of oxygen, because when exposed to air, graphite begins to burn in a lower temperature range, typically between 400°C and 600°C. The temporary substrate 1, made from graphite, is protected by a protective layer that completely encapsulates it, allowing it to withstand extremely high temperatures exceeding 1400°C.

[0042] This manufacturing method then includes step b) of directly depositing a carrier layer 2 made from polycrystalline silicon carbide (p-SiC) onto the front surface 1a of the temporary substrate 1 (Figure 2b).

[0043] This deposition may be carried out at a temperature of approximately 1100°C to 1400°C using any known technique, particularly chemical vapor deposition (CVD). For example, thermal CVD techniques such as atmospheric pressure CVD (APCVD) or low-pressure CVD (LPCVD) may be used, and the precursor can be selected from methylsilane, dimethyldichlorosilane, or dichlorosilane + i-butane. For example, plasma-enhanced CVD (PECVD) techniques may be used with silicon tetrachloride and methane as precursors, and the frequency of the source used to generate the plasma discharge is approximately 3.3 MHz, and more generally, preferably between 10 kHz and 100 GHz.

[0044] Prior to deposition, a conventional cleaning sequence may be applied to the temporary substrate 1 to remove all or part of any potentially present particulate matter, metal, or organic contaminants on the free surfaces 1a and 1b of the temporary substrate 1.

[0045] The thickness of the carrier layer 2, made from p-SiC, is between 10 and 200 microns. This thickness is selected according to the expected thickness specification of the semiconductor structure 100. The combined thickness of the temporary substrate 1 and the carrier substrate 2 is between 110 and 500 microns, and is typically favorably 350 ± 25 microns. Specific examples include a 250-micron temporary substrate 1 and a 100-micron carrier layer 2, or a 300-micron temporary substrate 1 and a 50-micron carrier layer 2.

[0046] In the semiconductor structure 100, the carrier layer 2 functions as a mechanical substrate, and in some cases, it is necessary to ensure electrical conduction in the vertical direction. To guarantee the aforementioned electrical conductivity characteristics (low resistivity), it is advantageous for the carrier layer 2 to be n-doped or p-doped as required.

[0047] According to one advantageous embodiment, the deposition in step b) is also performed on the back surface 1b of the temporary substrate 1 and / or on the peripheral edge 1c of the substrate 1 to form a second carrier layer 2'.

[0048] The role of the second carrier layer 2' (and the p-SiC deposited on the peripheral edge 1c) is essentially to protect the temporary substrate 1 made of graphite during the very high-temperature heat treatment that will subsequently occur in this method. Subsequently, the thickness of the second carrier layer 2' and the p-SiC deposited on the peripheral edge 1c (these will also be referred to as the protective layer below) will be limited to approximately 1 micron or a few microns.

[0049] Alternatively, the second carrier layer 2' may be deposited on the back surface 1b of the temporary substrate 1, with the intention of performing the next step of this method on both surfaces 1a, 1b of the substrate 1 (Figure 3a). The second carrier layer 2' is then located on the front surface 1a of the temporary substrate 1 and has the same order of thickness as the first carrier layer 2.

[0050] Generally, after the deposition of carrier layer 2 (and possibly a second carrier layer 2'), surface treatment is performed with the intention of transferring the processed layer 3 in the next step, to improve the surface roughness of carrier layer 2 and / or the quality of the structural edges.

[0051] Conventional chemical etching (wet or dry), and / or mechanical grinding and / or chemical mechanical polishing techniques may be used to achieve a surface roughness of approximately 0.5 nm RMS, preferably less than 0.3 nm RMS, of the p-SiC (for example, roughness measurement using atomic force microscopy (AFM) with a 20 micron × 20 micron scan). Nevertheless, the aforementioned characteristics of the graphite forming the temporary substrate 1 make it possible to limit the surface treatments that can be applied.

[0052] According to the first variant, the temporary substrate 1 provided in step a) is typically in the shape of a circular wafer, with a diameter 5% to 10% larger than the target diameter of the final semiconductor structure 100. This suppresses edge problems during deposition in step b) and makes it possible to maximize the area occupied by the subsequent components 40 in the semiconductor structure 100.

[0053] According to the second variant, the temporary substrate 1 provided in step a) has a diameter slightly smaller than the target diameter of the final semiconductor structure 100 (typically less than 5% smaller), and therefore, in this case, the target diameter can be reached by deposition in step b) performed on the peripheral edge of the temporary substrate 1.

[0054] Next, the manufacturing method according to the present invention includes step c) transferring a processed layer 3 made from single-crystal silicon carbide (c-SiC) to a carrier layer 2, either directly or via an intermediate layer, to form a composite structure 10 (Figure 2c). This transfer carries out bonding by molecular adhesion, resulting in the formation of a bonding interface 5. An intermediate layer may be formed on the side of the processed layer 3 and / or on the side of the carrier layer 2 to facilitate the bonding.

[0055] Conveniently, and as is known in relation to the Smart Cut (trademark) Act, transcription step c) is, Lightweight species are injected into a donor substrate 30 made from single-crystal silicon carbide to form an embedded weakened surface 31 that defines the processed layer 3 together with the front surface 30a of the donor substrate 30 (Figure 4a), The front surface 30a of the donor substrate 30 is bonded to the carrier layer 2 along the bonding interface 5 by bonding through molecular adhesion, either directly or via an intermediate layer (Figure 4b). The process involves separating along the embedded weakened surface 31 and transferring the processed layer 3 to the carrier layer 2 (Figure 4c). It contains consecutive occurrences.

[0056] The lightweight material is preferably hydrogen, helium, or a combination of both, and is injected into the donor substrate 30 to a determined depth that matches the thickness of the target processed layer 3 (Figure 4a). These lightweight materials form microcavities dispersed as a thin layer parallel to the free surface 30a of the donor substrate 30, parallel to the (x,y) plane in each figure, at the determined depth. For simplicity, this thin layer is referred to as the embedded weakening surface 31.

[0057] The injection energy of the lightweight species is selected to reach the determined depth. For example, hydrogen ions are injected at energies between 10 keV and 250 keV, at a rate of 5 e16 / cm². 2 ~1E17 / cm 2 The ion implantation is performed at irradiation doses between these values ​​to define a processed layer 3 with a thickness of approximately 100 nm to 1500 nm. Note that an additional layer may be deposited on the front surface 30a of the donor substrate 30 before the ion implantation step. This additional layer may be composed of a material such as silicon oxide or silicon nitride. This additional layer may be retained for the next step (and may also form all or part of the aforementioned intermediate layer), or it may be removed.

[0058] The donor substrate 30 is bonded to the carrier layer 2 at each of its front surfaces, forming a bonded assembly along the bonding interface 5 (Figure 4b). As is well known, bonding by molecular adhesion does not require adhesives because bonding occurs at the atomic level between each bonding surface. There are several types of bonding by molecular adhesion, with differences particularly in temperature, pressure, atmospheric conditions, or pre-contact treatment of the surfaces. Examples include bonding at ambient temperature with or without prior plasma activation of the surfaces to be bonded, atomic diffusion bonding (ADB), and surface activation bonding (SAB).

[0059] The bonding step may include conventional cleaning, surface activation, or other surface treatment sequences that tend to enhance the quality of the bonding interface 5 (low defect rate, good adhesion energy) before bringing the surfaces to be bonded into contact.

[0060] As already mentioned, the front surface 30a of the donor substrate 30 and / or the free surface of the carrier layer 2 may optionally include an intermediate layer, such as a metal layer (such as tungsten) or a doped semiconductor layer (such as silicon) to promote perpendicular electrical conduction, or an insulating layer (such as silicon oxide or silicon nitride) for applications that do not require perpendicular electrical conduction. The intermediate layer tends to promote bonding by molecular adhesion, in particular, by eliminating residual roughness or surface defects present on the surface to be bonded. This intermediate layer may be planarized or smoothed to achieve a roughness of less than 1 nm RMS, or even less than 0.5 nm RMS, which is favorable for bonding.

[0061] Separation along the embedded weakened surface 31 is typically achieved by heat treatment at temperatures of 800°C to 1200°C (Figure 4c). Such heat treatment creates cavities and microcracks in the embedded weakened surface 31, which are then pressurized by lightweight species present in gaseous form, after which fracture propagates along the weakened surface 31. Alternatively, or in conjunction with, mechanical stress may be applied to the bonded assembly, particularly the embedded weakened surface 31, to transmit or facilitate the mechanical propagation of fracture leading to separation. Once this separation is complete, a composite structure 10 is obtained, on the one hand, comprising a temporary substrate 1 made of graphite, a carrier layer 2 made of p-SiC, and a transferred processed layer 3 made of c-SiC, and on the other hand, the remaining 30' of the donor substrate is obtained. The thickness of the processed layer 3 is typically between 100 nm and 1500 nm. The level and type of doping of the processed layer 3 may be determined by the selection of each property of the donor substrate 30, or may be adjusted later by known techniques for doping semiconductor layers.

[0062] The free surface of the processed layer 3 is typically rough after separation, for example, with a roughness of 5 nm to 100 nm RMS (AFM, scanned at 20 microns × 20 microns). A cleaning step and / or a smoothing step may be added to restore a good surface finish (typically less than a few angstroms RMS roughness in a 20 micron × 20 micron AFM scan).

[0063] Alternatively, the free surface of the processed layer 3 may remain rough, as separated, if the following steps of this method allow for this roughness.

[0064] If the edges 1c and back surface 1b of the temporary substrate 1 are not covered by a protective layer, the separation heat treatment is performed in a controlled atmosphere without oxygen.

[0065] Prior to this heat treatment, it is advantageous to deposit a protective layer to mitigate the atmospheric conditions during the heat treatment. This protective layer may be formed from p-SiC as previously described with reference to a specific embodiment including a second carrier layer 2', or it may be made from amorphous SiC.

[0066] In a particular embodiment for implementing the second carrier layer 2', step c) may also include transferring a second processed layer 3' made of c-SiC to the second carrier layer 2', either directly or via a second intermediate layer with a second bonding interface 5' (Figure 3b).

[0067] Next, the manufacturing method according to the present invention includes step d) forming an active layer 4 on the processed layer 3 (Figure 2d).

[0068] This active layer 4 is advantageously manufactured by epitaxially growing at least one additional layer made from doped single-crystal silicon carbide onto the processed layer 3. This epitaxial growth occurs within the conventional temperature range, i.e., between 1500°C and 1900°C, forming a layer with a thickness of approximately 1 micron to several tens of microns, depending on the target electronic component.

[0069] In the composite structure 10, a protective layer is required on the edges 1c and back surface 1b of the temporary substrate 1 made of graphite in order to prevent damage to the graphite due to the aforementioned processing at very high temperatures. As mentioned above, this protective layer may consist of, for example, a layer made of polycrystalline silicon carbide (second carrier layer 2') or an amorphous layer.

[0070] The manufacturing method according to the present invention may further include step d') manufacturing all or part of the electronic components 40 on and / or within the active layer 4 (Figure 2d-1). The electronic components 40 may consist of, for example, a transistor or other high-voltage and / or high-frequency components.

[0071] Conventional steps such as washing, deposition, lithography, injection, etching, planarization, and heat treatment are performed to produce these on and / or within the active layer 4. In particular, some of the aforementioned heat treatments are aimed at activating the dopants locally injected into the active layer 4 (or the processed layer 3), and are usually performed at temperatures of 1600°C or higher.

[0072] In a particular embodiment in which a second carrier layer 2' is mounted on the back surface of the temporary substrate 1, step d) may also include forming a second active layer on the second processed layer 3', and it should be noted that step d') may also include fabricating all or some of the second electronic components on and / or in the second active layer.

[0073] Finally, the manufacturing method according to the present invention includes step e) removing the temporary substrate 1 to form a semiconductor structure 100, the structure comprising an active layer 4, a processed layer 3, and a carrier layer 2 (Figure 2e(i)), and optionally comprising an electronic component 40 if step d' is performed (Figure 2e(ii)).

[0074] Several variations may be implemented for this step, namely, some variations (the first and second variations described below) may involve peeling off the temporary substrate 1, and therefore may include, in some cases, reusing it for a new application, while some variations (the third and fourth variations) may require the removal of part or all of the temporary substrate 1.

[0075] According to the first modification, step e) includes mechanically delaminating the temporary substrate 1 by propagating a crack that penetrates the temporary substrate 1 after applying mechanical stress, the crack extending substantially parallel to the plane of the interface between the temporary substrate 1 and the carrier layers 2, 2'. For example, by inserting a chamfering tool on the opposite side of the interface or in close proximity to it, an opening can be created and propagated at this interface or within the graphite of the temporary substrate 1 until complete separation exists between the semiconductor structure 100 and the temporary substrate 1. It is advantageous that the protective layer present on the edge 1c of the temporary substrate 1 is removed to facilitate crack formation in the graphite.

[0076] According to the second variant, step e) includes chemically removing the carrier layers 2, 2' and the temporary substrate 1 by lateral chemical etching. The protective layer located at the edge 1c of the temporary substrate 1 in the composite structure 10 must be removed chemically or mechanically to allow access to the graphite. Lateral chemical etching may be carried out in particular with a solution based on nitric acid and / or sulfuric acid, such as a solution of concentrated sulfuric acid and potassium dichromate, or a solution of sulfuric acid, nitric acid, and potassium chlorate. Chemical etching carried out with an alkaline solution (such as potassium hydroxide (KOH) or sodium hydroxide (NaOH)) may be added.

[0077] Of course, great care will be taken to protect the free surfaces and edges of the active layer 4, as well as the electronic components 40 if present, and / or limit the contact time with the etching solution, so as not to damage them during this chemical removal.

[0078] According to the third variant, step e) includes chemical etching all or part of the temporary substrate 1. As previously stated, the protective layer on the edges 1c and back surface 1b (second carrier layer 2') of the temporary substrate 1 of the composite structure 10 must be removed to allow access to the graphite. Mechanical removal can usually be performed, for example, by grinding each edge and grinding the back surface, or chemical removal can be performed depending on the properties of the protective layer. Chemical etching of the temporary substrate 1 can also be performed, for example, by carrying out one of the solutions described above for the second variant, taking care to protect the active layer 4 and possibly the components 40.

[0079] According to the fourth modification, step e) includes delaminating the graphite forming the temporary substrate 1 by thermal damage. Here again, the protective layer present at least on the edges of the temporary substrate 1 must be removed. If the second processed layer 3' is not present on the back of the composite structure 10, the protective layer can also be removed from this side.

[0080] Delamination due to thermal damage can occur at temperatures of 600°C to 1000°C in the presence of oxygen, after which the graphite of the temporary substrate 1 burns and crumbles into pieces, leaving only the semiconductor structure 100 intact.

[0081] Of course, if the electronic component 40 is manufactured in step d', this delamination deformation may only be applied if the component 40 is suitable for the applied temperature.

[0082] It should be noted that the aforementioned modified forms may be combined with each other in any way that is technically feasible, and can be chosen at will.

[0083] Regardless of the deformation method performed, the removal of the temporary substrate 1 may leave residue on the back surface 2b of the carrier layer 2. These residues are then removed by mechanical grinding, chemical mechanical polishing, chemical etching, and / or thermal damage. If necessary, chemical mechanical polishing or chemical etching techniques may also be used to reduce the roughness of the back surface 2b of the carrier layer 2.

[0084] In the particular embodiment described above, in which a second carrier layer 2', a second processing layer 3', and a second active layer are arranged on the back surface 1b of the temporary substrate 1, a second semiconductor structure can also be formed by step e) removing the temporary substrate 1, which comprises a second active layer (and, optionally, electronic components), a second processing layer 3', and a second carrier layer 2'.

[0085] During and after the removal of the temporary substrate 1, the semiconductor structure 100 must be processed. If the total thickness of the semiconductor structure is insufficient to mechanically hold it during this processing, a removable handle can be considered. This handle, for example, is placed on the active layer 4 and temporarily fixed therein to perform the processing up to the unification step.

[0086] When the manufacturing method according to the present invention is completed, the semiconductor structure 100 obtained may, in some cases, include an active layer 4 completed with the electronic component 40, which is disposed on the carrier layer 2 with a thickness suitable for this application. Mechanical thinning with significant material loss is not required. The carrier layer 2 is made of high-quality p-SiC (since it is deposited at a relatively high temperature), but is low-cost compared to a bulk substrate of single-crystalline or polycrystalline SiC, and should have been significantly thinned before component integration. The temporary substrate 1 made of graphite is advantageously recovered for reuse. Therefore, since graphite is a low-cost material, even if this temporary substrate is not reused, the manufacturing method according to the present invention remains economically advantageous compared to the solution using a bulk substrate made of SiC. By selecting the physical characteristics (grain size, porosity, coefficient of thermal expansion) of the temporary substrate 1 made of graphite, the formation of the carrier layer 2 is ensured, and a robust and high-quality composite structure 10 can be obtained, enabling a highly reliable and high-performance semiconductor structure 100. The performance of the component 40 results, in particular, from the fact that the composite structure 10 allows processing at very high temperatures to form the active layer 4.

[0087] The present invention also relates to a composite structure 10 (Figs. 2c, 2d, 3b) as described above with reference to the manufacturing method and corresponding to the intermediate structure obtained in the manufacturing method.

[0088] The composite structure 10 comprises a temporary substrate 1 made of graphite with a grain size between 4 microns and 35 microns, a porosity between 6% and 17%, and a coefficient of thermal expansion between 4×10 -6 / °C and 5×10 -6 / °C, and at least a carrier layer 2 made of polycrystalline silicon carbide, with a thickness between 10 microns and 200 microns, disposed on the front surface 1a of this temporary substrate 1 and in contact with the front surface of this temporary substrate, and a processing layer 3 made of single-crystalline silicon carbide, disposed directly on this carrier layer 2 or via an intermediate layer and comprises.

[0089] The thickness of the processed layer 3 is preferably between 100 nm and 1500 nm. The thickness of the temporary substrate 1 is between 100 microns and 2000 microns.

[0090] For vertical, ultra-miniature electronic component applications, carrier layer 2 has good conductivity, i.e., 0.015-0.03 ohms / cm, high thermal conductivity, i.e., 200 W / mK or higher, and a thermal expansion coefficient similar to that of processed layer 3, i.e., typically 3.8 × 10⁻¹⁰ at ambient temperature. -6 / ℃~4.2×10 -6 It is advantageous to indicate the temperature in degrees Celsius.

[0091] It may be advantageous for the temporary substrate 1 to have a thermal conductivity between 70 W / mK and 130 W / mK in order to achieve a uniform temperature on the temporary substrate 1 during the very high-temperature heat treatment step of the manufacturing method. In particular, this improves the uniformity of the deposited layer and the reproducibility of the physical characteristics of the manufactured layer and components.

[0092] Finally, as described with reference to the manufacturing method according to the present invention, the composite structure 10 may be "double-sided," that is, A second carrier layer 2' made of polycrystalline silicon carbide, with a thickness of 10 to 200 microns, is placed on the temporary substrate 1, A second processed layer 3' made from single-crystal silicon carbide is placed in this second carrier layer 2' and It may also be equipped with (Figure 3b).

[0093] With such a composite structure 10, two active layers 4 can be formed in the first processed layer 3 and the second processed layer 3', respectively, and when the manufacturing method according to the present invention is completed, two semiconductor structures 100 can be obtained from a single temporary substrate 1.

[0094] Of course, the present invention is not limited to the embodiments and examples described, and modifications may be made to them without departing from the scope of the invention as defined by the claims.

Claims

1. A method for manufacturing a semiconductor structure (100), a) The particle size is between 4 microns and 35 microns, the porosity is between 6% and 17%, and the coefficient of thermal expansion is 4 × 10⁻⁶ －６ / ℃~5×10 －６ The steps include preparing a temporary substrate (1) made from graphite in the range of / ℃, b) A step of directly depositing a carrier layer (2) made of polycrystalline silicon carbide with a thickness of 10 to 200 microns onto the front surface (1a) of the temporary substrate (1), c) A step of transferring a processed layer (3) made from single-crystal silicon carbide to the carrier layer (2) directly or via an intermediate layer to form a composite structure (10), wherein the transfer is performed by bonding through molecular adhesion. d) The step of forming an active layer (4) on the processed layer (3), e) A step of removing the temporary substrate (1) to form the semiconductor structure (100), wherein the semiconductor structure (100) includes the active layer (4), the processed layer (3), and the carrier layer (2), A manufacturing method that includes this.

2. The deposition in step b) To form the second carrier layer (2'), the back surface (1b) of the temporary substrate (1), and / or The manufacturing method according to claim 1, further applied to the peripheral edge (1c) of the temporary substrate (1).

3. The transcription step c) is, A lightweight species is injected into a donor substrate (30) made from single-crystal silicon carbide to form an embedded weakening surface (31) that defines the processed layer (3) together with the front surface (30a) of the donor substrate (30), The front surface (30a) of the donor substrate (30) is bonded to the carrier layer (2) by bonding through molecular adhesion, either directly or via an intermediate layer. The process involves separating the processed layer (3) along the embedded weakened surface (31) and transferring it to the carrier layer (2), A manufacturing method according to claim 1 or 2, including

4. The manufacturing method according to claim 3, wherein the intermediate layer is formed from tungsten, silicon, silicon carbide, or other conductive or semiconductor material.

5. The manufacturing method according to any one of claims 1 to 4, wherein step d) includes epitaxially growing at least one additional layer made of doped single-crystal silicon carbide on the processed layer (3), the additional layer forming all or part of the active layer (4).

6. A manufacturing method according to any one of claims 1 to 5, comprising step d') of manufacturing all or part of the electronic components (40) on and / or within the active layer (4), wherein step d') is inserted between step d) and step e).

7. Step e) includes mechanically delaminating the temporary substrate (1) by propagating a crack that penetrates it after applying mechanical stress, wherein the crack extends substantially parallel to the plane of the interface between the temporary substrate (1) and the carrier layer (2), and / or Step e) includes chemically delaminating the carrier layer (2) and the temporary substrate (1) by lateral chemical etching, and / or Step e) includes chemical etching all or part of the temporary substrate (1), and / or The manufacturing method according to any one of claims 1 to 6, wherein step e) includes peeling off the graphite of the temporary substrate (1) by inflicting thermal damage.

8. The deposition in step b) is further carried out on the back surface (1b) of the temporary substrate (1) to form a second carrier layer (2'), Step c) includes transferring a second processed layer (3') made from single-crystal silicon carbide to the second carrier layer (2') either directly or via a second intermediate layer, wherein the transfer carries out bonding by molecular adhesion. Step d) includes forming a second active layer on the second processed layer (3'), The manufacturing method according to claim 1, wherein step e) enables the formation of a second semiconductor structure (100), the second semiconductor structure comprising the second active layer, the second processed layer (3'), and the second carrier layer (2').

9. The manufacturing method according to any one of claims 1 to 8, wherein the temporary substrate (1) provided in step a) takes the shape of a circular wafer and has a diameter 5% to 10% larger than the target diameter of the semiconductor structure (100).

10. The manufacturing method according to any one of claims 1 to 8, wherein the temporary substrate (1) provided in step a) takes the shape of a circular wafer and has a diameter slightly smaller than the target diameter of the semiconductor structure (100), and therefore the deposition in step b) can be further performed on the peripheral edge (1c) of the temporary substrate (1) to reach the target diameter.

11. The particle size ranges from 4 microns to 35 microns, the porosity is between 6% and 17%, and the coefficient of thermal expansion is 4 × 10⁻⁶. －６ / ℃~5×10 －６ A temporary substrate (1) made from graphite between / ℃, At a minimum, a carrier layer (2) made of polycrystalline silicon carbide, having a thickness of 10 to 200 microns, is placed on the front surface of the temporary substrate (1) and is in contact with the front surface of the temporary substrate (1), A processed layer (3) made of single-crystal silicon carbide is placed on the carrier layer (2), A composite structure (10) comprising the above.

12. The composite structure according to claim 11, wherein the thickness of the processed layer (3) is between 100 nm and 1500 nm.

13. The composite structure according to claim 11 or 12, wherein the thickness of the temporary substrate (1) is between 100 microns and 2000 microns.

14. The composite structure according to any one of claims 11 to 13, wherein the thermal conductivity of the temporary substrate (1) is between 70 W / mK and 130 W / mK.

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