A system and method for regulating persistent cash flushing.

Abstract

The techniques described herein provide a handshake mechanism and protocol for informing the operating system of system hardware support for persistent cache flushing. The system firmware may determine whether the hardware can support a full flush of the processor cache and volatile memory buffers in the event of a power outage or asynchronous reset. If the hardware support is possible, persistent cache flushing may be selectively enabled and the operating system may be notified. Once persistent cache flushing is enabled, the operating system and applications may treat data stored in the volatile processor cache as persistent data. If persistent cache flushing is disabled or not supported by the system hardware, the platform need not inform the operating system of persistent cache flushing support.

Description

[Technical Field]

[0001] This disclosure relates to cache management technology. More specifically, this disclosure relates to technology for flushing volatile cache states in the event of a power loss. [Background technology]

[0002] background Modern server designs typically incorporate persistent memory (PMEM), such as data center persistent memory modules (DCPMMs) or non-volatile dual in-line memory modules (NVDIMMs), into their memory architecture. Persistent memory offers several advantages over block-based persistent media, including low-latency random access times, and provides the ability to directly perform remote direct memory access (RDMA) operations within the persistent memory itself.

[0003] Because directly storing data in persistent memory devices is costly, servers with persistent memory typically support the ability to treat several volatile on-chip states as persistent to limit the number of times explicit software-based storage operations are required. A program can treat any data stored in a volatile buffer as persistent if the system can guarantee that the state of the volatile buffer is flushed to persistent memory during any reset or power transition where the contents of the volatile buffer may be lost. One such technique for flushing volatile buffers is called asynchronous dynamic random access memory refresh (ADR), which places the memory controller's volatile buffer in the persistent domain. With this technique, the system reserves enough energy to flush the volatile memory controller's buffer to a persistent memory device for a sufficient amount of time after a power loss to power the system.

[0004] Another technique, sometimes called Extended ADR (eADR) or Persistent Cache Flash (PCF), extends the volatile state that can be treated as persistent to include all processor caches and on-chip buffers. Generally, processor caches are orders of magnitude larger than the volatile memory buffers of the memory controller. Therefore, the system requires a considerable amount of energy to complete the flash operation. Servers that support persistent cache flash need to include some form of auxiliary energy storage to power the system while persistent cache flash is in operation. Some servers include a battery backup unit (BBU) to provide enough energy to complete the flash of data from the processor cache to persistent memory after a power loss. While BBUs can store a considerable amount of energy, they have many challenges, including a large footprint, limited ability to supply the large currents required by the server system, thermal constraints, and additional costs.

[0005] Asynchronous hardware reset events further complicate the implementation of persistent cache flushing mechanisms. Asynchronous hardware resets are typically performed by directly asserting the reset request pin and may be undetectable to the processor or chipset power sequencing logic. If the system allows an externally triggered reset event to initiate a hardware reset without calling the persistent flush handler prior to the reset, persistent memory states may not be properly flushed. When platform hardware support is insufficient, applications relying on persistent cache flushing may result in the loss or corruption of application data during power outage events.

[0006] The methods described in this section are methods that can be pursued, but they are not necessarily methods that have been previously conceived or pursued. Therefore, unless otherwise indicated, none of the methods described in this section should be assumed to be prior art simply because they are included in this section.

[0007] Embodiments are shown in the accompanying drawings as examples, not as limitations. It should be noted that references to “an” or “one” embodiment in this disclosure do not necessarily refer to the same embodiment, but rather mean “at least one” embodiment. [Brief explanation of the drawing]

[0008] [Figure 1] This figure shows a system for performing a persistent cache flush operation according to several embodiments. [Figure 2] This figure shows a set of examples of operations for performing persistent cache flush operations to maintain a persistent memory state, according to several embodiments. [Figure 3] This figure shows a set of illustrative operations for managing persistent cache flush operations in a system with multiple power sources, according to several embodiments. [Figure 4] This figure shows an exemplary system for managing multiple power sources according to several embodiments. [Figure 5] This is an illustrative timing diagram showing time-delay warning signals from separate power supply units according to several embodiments. [Figure 6] This figure shows a set of examples of behaviors for handling an externally triggered asynchronous reset event, according to several embodiments. [Figure 7] This figure shows an exemplary system for intercepting and processing an externally triggered asynchronous reset event, according to several embodiments. [Figure 8]A diagram showing an exemplary set of operations for adjusting a persistent memory operation mode according to some embodiments. [Figure 9] A block diagram showing a computer system according to some embodiments. **Modes for Carrying Out the Invention**

[0009] Detailed Description In the following description, for the sake of explanation, numerous specific details are set forth in order to provide a thorough understanding. One or more embodiments may be practiced without these specific details. Features described in one embodiment may be combined with features described in another embodiment. In some instances, well-known structures and devices are described in block diagram form in order not to obscure the present invention needlessly.

[0010] 1. General Overview This specification describes techniques for using a system power supply unit (PSU) to supply auxiliary energy for flashing volatile system memory to persistent memory after a loss of alternating current (AC) power. In some embodiments, these techniques include implementing a sufficiently long extended hold-up window for fully flashing the processor cache and memory controller buffer using the available energy of the PSU bulk capacitor after a power supply interruption event. These techniques may enable flashing the volatile system cache without requiring a backup battery unit (BBU), even when the amount of available energy in the PSU is relatively small compared to most BBUs.

[0011] Many PSUs include large-capacity capacitors, allowing the system to cope with a temporary 10-millisecond (ms) loss of AC power. The exemplary PSU implementation assumes a worst-case output load and includes a 10-millisecond timer that turns off the supplied output when the timer expires. This implementation limits the longest hold-up window that the PSU can perform to 10 milliseconds, regardless of the system's power consumption, which may not be enough time to flush all system caches.

[0012] In some embodiments, the PSU is implemented to extend the hold-up window for an indefinite-time window determined by the system's power consumption, rather than a fixed-time window. The voltage of a large-capacity capacitor inside one or more PSUs may be monitored, and a notification may be triggered when a programmable threshold voltage for a power shortage warning is detected in the large-capacity capacitor. The system may configure a voltage threshold in the PSU to indicate that a certain minimum amount of energy is available to successfully complete a cache flush operation. The PSU may further implement a second voltage threshold related to the minimum amount of energy required to safely sequentially devoltage the system's power rails. Since both notifications are based on the amount of energy available in the PSU's large-capacity capacitor, the system may implement a configurable hold-up window where the window period is determined by the power consumption, rather than a fixed period of the system. As a result, the system may define an operating point for minimizing energy consumption without being constrained by a fixed-period timer.

[0013] In some embodiments, system logic may implement an energy counter to estimate the total amount of energy available across all installed PSUs, and generate an interrupt signal to invoke a persistent flush handler when the estimated total system energy reaches a threshold related to the minimum energy required to successfully complete a cache flush operation. System logic may implement an energy counter for each PSU installed in the system. After a PSU generates a low power warning signal to system logic, system logic may begin decrementing the energy counter associated with that PSU at a rate and in a mode of operation of the system proportional to the number of active power sources in the system. System logic may estimate the total available energy by summing the PSU counters for each of them. When the total estimated energy falls below a critical threshold, system logic may invoke a persistent cache flush handler and generate an interrupt signal.

[0014] In some embodiments, the system is configured to reduce power consumption during the flash process in order to minimize the amount of energy required to complete the flash. The processor, persistent memory device, and support circuitry may remain powered. Other system components not involved in the flash process, such as fans, input / output (I / O) devices, and hard disk drives, may have their power disabled. The system's power control loop may further include hooks to reduce the power consumption of the central processing unit (CPU), such as by lowering the processor frequency.

[0015] To ensure that volatile system resources containing states considered persistent are properly flushed to a persistent medium prior to a system reset or power transition, in some embodiments, a persistent flush handler is executed prior to all resets or power transitions to write all volatile states to the persistent medium. The system may trap access to registers used to initiate a reset or power transition to initiate a persistent cache flush before allowing the completion of the trapped write. By trapping access to registers, the system can activate the cache flush handler before performing the requested reset or power transition action. Similar mechanisms may be implemented to handle resets and power transitions requested by platform entities outside the host subsystem.

[0016] System resets and power transitions can occur not only due to power outages, but also in response to events initiated by external agents. For example, certain system errors may trigger a hardware-initiated system reset. Another example is when a user initiates a warm reset or forced voltage drop by pressing a button or flipping a switch. If the system allows an externally initiated reset or power transition event to trigger a hardware reset without calling a flash handler beforehand, data in the volatile processor cache or memory buffer may be lost. To ensure that externally initiated system resets or power transitions properly call persistent flash handlers, the system may proxy these asynchronous events with system logic to generate interrupts that call a special persistent flash interrupt handler to perform a persistent cache flush before calling the requested hardware operation. In addition, or instead, the system may include hardware backup mechanisms to ensure that all resets and power transitions requested by the hardware are completed within a bounded window of time, regardless of the success or failure of the persistent cache flush handler.

[0017] The techniques described herein further provide handshake mechanisms and protocols for informing the operating system whether the system hardware supports persistent cache flushing. The system can determine whether the hardware can support a complete flush of the processor cache and volatile memory buffers in the event of a power outage or asynchronous reset. If hardware support is available, persistent cache flushing may be selectively enabled, and this may be communicated to the operating system. Once persistent cache flushing is enabled, the operating system can treat data stored in the volatile processor cache as persistent data. If persistent cache flushing is disabled or not supported by the system hardware, such data may be lost due to power outage or reset events, and the platform does not need to inform the operating system of persistent cache flushing support.

[0018] This general overview section may not include one or more embodiments described herein and / or enumerated in the claims.

[0019] 2. System Architecture In some embodiments, the techniques described herein are implemented in one or more computer devices that include persistent memory in their memory layout, such as server equipment or other network hosts. While illustrative computer architectures are provided herein, these techniques are applicable to a wide variety of computer architectures depending on the specific implementation. These techniques may be used to (a) determine whether a particular combination of system components can support persistent cache flushing, (b) configure the system components to enable persistent cache flushing if supported, and / or (c) execute a persistent cache flush handler prior to a power transition or reset if persistent cache flushing is enabled.

[0020] Figure 1 shows a system for performing persistent cache flush operations according to several embodiments. As shown, Figure 1 includes a PSU 102a, a PSU 102b, a power management subsystem 104, a persistent cache flush handler 106, a memory subsystem 108, a CPU 116, a system management module 118, system firmware 120, peripheral components 124, and an operating system 122. In other embodiments, the components that may be included in system 100 may be more or less than those shown in Figure 1. In some cases, the components shown in Figure 1 may be local or remote to each other.

[0021] PSUs 102a and 102b convert power into a form that enables the proper operation of the components of system 100. In some embodiments, PSUs 102a and 102b convert AC power into direct current (DC) energy used to power the components of system 100. In addition, or instead, PSUs 102a and 102b may include DC-DC power conversion, such as a converter that steps up or steps down the input voltage. PSUs 102a and 102b may be electrically coupled to other components of system 100 by one or more power rails, such as +3 volts (V), +5V, and / or +12V rails. Although two PSUs are shown, the system may have only one PSU or additional PSUs, depending on the particular implementation.

[0022] The power management subsystem 104 controls the delivery of power to the components of system 100 by the system PSU. In some embodiments, the power management subsystem 104 selectively powers off components during reset or power outage events to gracefully shut down system 100. In addition, or instead, the power management subsystem 104 may monitor the voltage levels of the large-capacity capacitors of PSUs 102a and 102b. If the voltage level drops below a programmable threshold, the power management subsystem 104 may assert or deassert signals to notify other components of system 100.

[0023] The memory subsystem 108 includes volatile and non-volatile storage areas. In some embodiments, the volatile storage area includes a processor cache 110 and a memory buffer 112. The processor cache 110 may include caches such as a Level 3 (L3) cache and a Level 4 (L4) cache, which are located inside the CPU 116 and can be used by the CPU 116 to reduce data access time to main memory. The memory buffer 112 may include registers and / or a memory controller of the CPU 116, which provide intermediate storage for data being transferred between separate areas. For example, a memory controller buffer may provide temporary storage for data being transferred between the processor cache 110 and main memory.

[0024] The persistent memory 114 includes one or more non-volatile memory devices, such as a data center persistent memory module (DCPMM) and a non-volatile dual in-line memory module (NVDIMM). In some embodiments, the persistent memory 114 is byte-addressable and resides on the memory bus, providing speed and latency similar to volatile DRAM, which is generally much faster than peripheral non-volatile storage devices such as hard disks and flash drives that are not on the memory bus. Furthermore, the persistent memory 114, like volatile DRAM, can be paged and mapped by the operating system 122, which is not common in other forms of persistent storage devices. The persistent memory 114 can function as the main memory within the system 100. In other cases, the main memory may include one or more volatile memory modules, such as DRAM.

[0025] When a persistent cache flush handler is installed and the platform signaling mechanism is enabled, data stored within the volatile memory area, including the processor cache 110 and memory buffer 112, can be treated as part of the persistent memory state even in the event of a power outage or other power transition event. To maintain the persistent state, the cache flush handler 106 performs and manages cache flush operations in response to the detection of trigger events. If the persistent cache flush operation is not enabled, a full cache flush may not be performed during a power transition event, and some or all of the data within the volatile memory area may be lost. Without a persistent cache flush handler, data may be flushed from the memory buffer 112 but not from the processor cache 110, potentially reducing the time required to perform the flush operation.

[0026] The system management module 118 comprises software and / or hardware for managing system-level operations. In some embodiments, the system management module 118 includes a service processor (SP) and a CPU chipset. The system management module 118 may interface with one or more sensors to monitor hardware components. In addition, or instead, the system management module 118 may perform other functions, including writing traps to system registers, generating system management interrupts (SMIs), and monitoring the system's startup status.

[0027] The system firmware 120 includes software that provides low-level control over the system hardware. In some embodiments, the system firmware 120 includes software such as basic input / output system (BIOS) firmware that manages startup processes, such as when the system is powered on or reset. The system firmware 120 may further provide runtime services for the operating system 122, such as persistent cache flushing operations and management of peripheral components 124.

[0028] The operating system 122 includes software that supports operations including executing scheduling instructions on the CPU 116, providing services to software applications, and controlling access to peripheral components 124. In some embodiments, the system firmware 120 may, if supported by the system 100, indicate the ability to include cache content in the persistence domain. The operating system 122 may then selectively enable or disable persistent cache flushing. When persistent cache flushing is enabled, the operating system 122 may treat data stored in volatile memory, including the processor cache 110 and memory buffer 112, as persistent.

[0029] The peripheral components 124 include auxiliary hardware devices such as hard disks, input devices, display devices, and / or other output devices that can be electrically coupled to other components of the system 100. The power consumption of the system 100 may vary in part depending on which peripheral components 124 are connected and active. The worst-case scenario for maximum power load can be calculated by assuming that all hardware components, including the peripheral components 124, are operating at full capacity.

[0030] 3. Sustained Cash Flush 3.1 Managing Cache Flush Operations During Power Outage Events When AC power is interrupted, power can be restored quickly, so it may not be desirable to immediately initiate a cache flush operation. However, if too much time passes without power being restored, there is a risk that the internal hold-up energy of PSU 102a and PSU 102b will become insufficient to perform a full cache flush. In such a case, if persistent cache flush is enabled, the persistent memory state may be corrupted. To maintain the persistent memory state, the power management subsystem 104 may generate a warning signal when the residual energy inside the large-capacity capacitors of PSU 102a and PSU 102b falls below a threshold level.

[0031] Figure 2 shows a set of illustrative operations for performing cache flush operations to maintain a persistent memory state, according to several embodiments. All of the operations shown in Figure 2 are modifiable, rearrangeable, or omitted. Therefore, the specific order of the operations shown in Figure 2 should not be interpreted as limiting the scope of one or more embodiments.

[0032] Referring to Figure 2, process 200 includes the step (operation 202) of estimating the total amount of ride-through time and hold-up time based on the system load. Ride-through time is the estimated time during which the system 100 can operate without AC power while leaving enough energy to perform a cache flush and sequential voltage drop on the power rails. Hold-up time is the time required to perform a full cache flush and sequential voltage drop on the power rails, given the system load. The estimation may be calculated based on the total system load or a reduced system load with an upper limit, as further described herein.

[0033] In some embodiments, process 200 programs one or more energy thresholds based on estimated ride-through and hold-up times (operation 204). For example, process 200 may estimate a voltage level on a large capacitance capacitor in the PSU that will ensure a predetermined amount of hold-up time for the system 100 to complete the cache flush and sequential power rail shutdown operations under a bounded system load. This voltage level may then be programmed as a threshold. In other implementations, the time may be set based on the estimated ride-through time rather than a voltage / energy-based threshold.

[0034] In some embodiments, operations 202 and 204 are performed as separate processes from the remaining operations described herein. For example, operations 202 and 204 may be performed during the startup sequence of system 100, and for each operating point, the required amount of energy and associated voltage thresholds may be calculated. The calculation may be performed in part on the system components detected by the startup sequence and the estimated power required to operate the components during normal operation and / or reduced-power operating modes. The startup sequence may then set programmable voltage thresholds for system 100. In other embodiments, programmable thresholds may be set or modified by user input. For example, a system administrator may set programmable voltage thresholds for each operating point, allowing the system administrator to introduce domain knowledge regarding the system's power requirements.

[0035] Referring again to Figure 2, process 200 includes the step of monitoring for loss of AC power (operation 206). In some embodiments, the system 100 may incorporate sensors and / or circuits in the PSU 102a and / or PSU 102b that detect when input AC power is interrupted. In other embodiments, external circuits and / or sensors may signal the system 100 when AC power is lost.

[0036] Process 200 may detect a loss of AC power based on the monitoring circuit (operation 208). Accordingly, process 200 triggers a notification (operation 210). In some embodiments, the notification is triggered by deasserting the acok signal. Deasserting the acok signal warns that the power is no longer unstable and that the energy reserves inside the PSU's large-capacity capacitors have dropped to a critical point where a system shutdown must be initiated to maintain the data persistence state, and writes the start of an estimated hold-up time. In other words, the notification warns the power management subsystem 104 to store enough energy in the system PSU to hold up the power rails for a sufficient amount of time to perform a full cache flush of the processor cache 110 and memory buffer 112.

[0037] In some implementations, an early warning mechanism is associated with a certain period prior to shutdown, allowing the power management subsystem 104 to assume that system 100 is operating at maximum load and to ensure the shortest possible time to complete the cache flush and sequentially devoltage the power rails under maximum load. However, this approach may lead to a return to traditional implementations where system shutdown begins earlier than planned, particularly during persistent cache flushes, where the maximum PSU load is considerably greater than the actual system load. In comparison, a programmable early warning threshold allows the system to trade off energy consumption before asserting a warning signal for ride-through versus energy consumption after asserting a warning signal for hold-up.

[0038] After the notification is triggered, process 200 continues to power the system components in a first operating mode (operation 212). While operating in the first operating mode, the system components may be powered using the energy of the PSU's large-capacity capacitors. In some embodiments, power may be supplied as if the AC power were not interrupted. In other embodiments, power saving adjustments may be made within the system 100. For example, the processor frequency or the brightness of the display may be reduced, and / or other power saving actions may be employed. In addition, or instead, data may be successively written to and updated in the processor cache 110 and the memory buffer 112.

[0039] Process 200 further monitors the internal energy levels of one or more system PSUs based on programmed thresholds (operation 214). In some embodiments, system 100 includes a sensor for monitoring the voltage of a large-capacity capacitor in the PSU. Since the capacitance value of the large-capacity capacitor is fixed, the voltage of the large-capacity capacitor can be used as a proxy for the PSU energy level when AC power is interrupted. In other embodiments, the energy level can be calculated as a function of the capacitance value of the large-capacity capacitor and the measured voltage.

[0040] Process 200 further determines whether the energy level of one or more PSUs meets a threshold (operation 216). For example, process 200 may determine whether the threshold is met if the measured voltage of one or more large-capacity capacitors drops below the voltage threshold programmed in operation 204. If the threshold is not met, process 200 may continue to monitor the PSU energy level until power is restored or the voltage of the PSU large-capacity capacitors drops below a programmable threshold. Once the threshold is met, an alert signal may be asserted to trigger a cache flush and voltage drop sequence.

[0041] In some embodiments, process 200 enters a second operating mode (operation 218) by reducing the system load to minimize power consumption. During this phase, the power management subsystem 104 may reduce the voltage of components not involved in the cache flush operation. For example, peripheral components 124 whose voltage may be reduced by the power management subsystem 104 may include hard disk drives, fans, displays, peripheral component interconnect express (PCIe) devices, and / or other peripheral hardware. In addition, or instead, the power management subsystem 104 may reduce the clock speed or the frequency of the CPU 116 to minimize power consumption.

[0042] Process 200 then performs a cache flush (operation 220). During the cache flush operation, the CPU 116 may write data stored in the processor cache 110 and memory buffer 112 to persistent memory 114 in order to maintain the data persistence state. In some embodiments, process 200 may continue to monitor the PSU energy level during this operation. If the PSU energy level drops below a second voltage threshold, process 200 may initiate a voltage drop sequence even if the cache flush is not complete, in order to prevent all power rails from failing simultaneously. The second voltage threshold may be programmed to be much lower than the first threshold, which leaves enough energy to sequentially voltage drop the power rails.

[0043] Once the cache flush is complete, process 200 devoltages the remaining system components (operation 224). Process 200 can then sequentially devoltage the power rails to properly shut down system 100. The power rail devoltage sequence may differ from system to system.

[0044] The process shown in Figure 2 can maintain a persistent memory state without requiring the installation of a BBU or relying on energy from a BBU. Instead, the power management subsystem 104 can manage the energy inside the large-capacity capacitors of one or more PSUs to ensure persistence. Furthermore, by the power management subsystem 104 sensing the runtime power load, variable ride-through and hold-up times enable more efficient and effective use of the stored energy.

[0045] 3.2 Managing Multiple Power Supply Units If a system has multiple power supplies (PSUs) and one or more AC power is lost from one of the PSUs, the energy from a single PSU may be insufficient to complete a cache flush operation. However, the combined energy from multiple PSUs may be sufficient to complete a cache flush to maintain data persistence. When there are multiple PSUs, the power management subsystem 104 may monitor the total energy available across all power supplies. When the total voltage level crosses a threshold for triggering a cache flush operation, the power management system 104 may issue a power shortage warning.

[0046] In some embodiments, the power management subsystem 104 detects the following events with respect to each PSU it manages:

[0047] - Loss of AC power that can be detected by deassertion of the ACOK signal. When the power management subsystem 104 receives this signal from one or more PSUs, it enters a first operating mode and, if AC power is recovered, reduces the power during the ride-through window.

[0048] - An indication that the energy or voltage level of the PSU has crossed a first threshold, which can be detected by asserting the vwarn signal. The power management subsystem 104 combines voltage warning information from all PSUs to determine when to enter a second operating mode, thereby causing the persistent cache flush handler 106 to initiate a cache flush operation. During the second operating mode, the power management system 104 may further reduce power as previously described.

[0049] - An indication that the PSU's energy or voltage level has crossed a second threshold, which can be detected by the assertion of the pwrok signal. The power management subsystem 104 may combine the information from the pwrok signal to determine whether the system voltage should be immediately reduced. If the PSU energy level drops further and there is not enough energy remaining to safely and sequentially reduce the voltage of the power rails, a shutdown may be triggered.

[0050] In some embodiments, in the event of AC power loss, the power management subsystem 104 maintains a set of per-PSU counters in each PSU to track the estimated energy level. The initial values ​​of the per-PSU counters may be hardcoded or programmable to correspond to the amount of energy available in the PSU when vwarn is asserted. When the power management subsystem 104 detects that a PSU has asserted vwarn, it may begin decrementing the energy counter of the relevant PSU at a rate proportional to the number of active power supplies in the system and the maximum load per power supply. For example, if there is one active PSU with a maximum load of 1200 watts (W), the counter may be decremented at 1.2 joules (J) / millisecond. If there are two active power supplies with a load of 600 watts (W) per power supply, the energy counter may be decremented at 600 mJ / millisecond. If there are four active power supplies, the energy counter may be decremented at 300 mJ / millisecond. As another example, if the worst-case system load drops to 1000W, the counter's decrement rate may be changed to 1J / millisecond for one power supply, 500mJ / millisecond for two power supplies, and 250mJ / millisecond for four power supplies. The counter may be adjusted to provide the maximum ride-through time while maintaining sufficient energy to maintain persistent cache flushing during extended blackout periods.

[0051] Figure 3 shows an illustrative set of operations for managing persistent cache flush operations in a system with multiple power supplies, according to several embodiments. All of the operations shown in Figure 3 are modifiable, rearrangeable, or omitted. Therefore, the specific order of operations shown in Figure 3 should not be interpreted as limiting the scope of one or more embodiments.

[0052] Referring to Figure 3, process 300 detects assertions of one or more vwarn signals from one or more PSUs (operation 302). As previously mentioned, each PSU may be configured to assert a vwarn signal when AC power is lost and the energy in the PSU's large capacitance capacitor falls below a programmable threshold.

[0053] In response to detecting the vwarn signal, process 300 starts one or more associated countdown timers (operation 304). In some embodiments, the countdown timers track the estimated energy level for each PSU that asserted the vwarn signal. Process 300 may decrement the counter at a rate proportional to the number of PSUs in the system and the maximum load per power supply. In other embodiments, other mechanisms may be used to track the internal energy level of the PSUs. For example, instead of decrementing the counter, process 300 may increment the counter until a threshold is reached, or use other tracking logic.

[0054] In addition, or instead, the process 300 may cause the system 100 to enter a reduced-power mode in response to the detection of one or more vwarn signals. The reduced-power mode may be activated by one signal or a threshold number of signals, depending on the particular implementation. In other embodiments, the process 300 may gradually reduce power using each newly detected signal. For example, the process 300 may gradually reduce the CPU frequency for each new vwarn signal and / or initiate or enhance other power-saving actions as previously described.

[0055] Process 300 further monitors (a) the combined energy level of the PSUs based on a countdown timer (or other tracking logic), (b) assertions of further vwarn signals from other PSUs, and (c) assertions of pwrok signals from PSUs (operation 306). When further vwarn signals are detected, process 300 starts the countdown timer associated with the PSU that asserted the signal (operation 304).

[0056] If the total energy level meets a first threshold, process 300 performs a cache flush operation (operation 308). For example, process 300 may determine whether the total energy level of all PSUs has fallen below a minimum threshold. During the cache flush operation, the CPU 116 may write data stored in the processor cache 110 and memory buffer 112 to persistent memory 114 in order to maintain the data persistence state. In some embodiments, process 300 may continue to monitor the PSU energy levels during this operation.

[0057] Once the cache flush operation is complete, or the voltage drops below a second voltage threshold number that triggers one or more pwrok signals in the PSU, process 300 sequentially lowers the voltages of the power rails (operation 310). When a pwrok signal is detected, process 300 may initiate a voltage drop sequence to prevent all power rails from dropping simultaneously, even if the cache flush is not complete. The second voltage threshold may be programmed to be much lower than the first threshold that leaves enough energy to sequentially lower the voltages of the power rails.

[0058] Figure 4 shows an exemplary system 400 for managing multiple power sources according to several embodiments. System 400 includes PSUs 402 and 404. However, the number of PSUs may vary depending on the specific implementation. One or more large-capacity capacitors, such as capacitor 406, which may be included in each PSU, store electrostatic energy obtained from the connected AC power network. Capacitor-based storage allows PSUs to be implemented in a smaller footprint than BBUs and results in faster charge and discharge rates. PSUs 402 and 404 may be connected to the same AC power network or separate AC power networks, depending on the specific implementation. If connected to separate AC power networks, if one PSU loses AC power, the other PSU continues to be powered by the other AC network. In this scenario, each PSU may supply a separate acok signal (not shown) to the power management subsystem 408. These signals may be individually deasserted by the individual PSU to indicate which PSU has lost power when AC power is lost. In other cases, a deassertion of the ACok signal may indicate that a group or all of the PSUs have lost AC power.

[0059] In some embodiments, each PSU asserts a vwarn signal when the energy of a large-capacity capacitor (e.g., large-capacity capacitor 406) reaches a threshold. The vwarn signal then notifies the power management subsystem 408 that the available energy of the associated PSU has reached a first threshold level. The power management subsystem 408 maintains a separate energy counter for each PSU, which is activated when the associated PSU asserts the vwarn signal. For example, when PSU 402 asserts the vwarn signal, the power management subsystem 408 may then decrement energy counter 410 at a rate proportional to the number of PSUs in the system and the maximum load per power supply. Energy counter 412 is managed independently of energy counter 410 (the vwarn signal from a PSU does not activate counters for other unrelated PSUs) and is decremented in response to PSU 404 asserting the vwarn signal. An adder 414 included in the power management subsystem 408 sums up the estimated energy counts of each PSU to calculate a total energy counter 416.

[0060] In some embodiments, the system threshold may be programmable and vary depending on the specific implementation, and the power management subsystem monitors the total energy counter 416 to determine whether the total energy of all PSUs has fallen below the system threshold. When the threshold is reached, the power management subsystem 408 asserts the SMI signal and stops the current task being performed by the CPU / chipset 422 in preparation for persistent cache flush and reset. The persistent cache flush handler 424 may, in response to the SMI, initiate the aforementioned persistent cache flush operation.

[0061] FIG. 5 shows an exemplary timing diagram 500 showing time difference warning signals from various power units according to some embodiments. The upper half of FIG. 500 represents the timing of power shortage, and the lower half represents possible power reduction that system 100 may implement in response to an impending power shortage. FIG. 500 assumes the worst-case behavior where the system operates at maximum load until the power shortage cache flush is triggered. When the power shortage cache flush is triggered, the power consumption of the system is reduced to minimize the load when the flush operation is completed.

[0062] The variables in FIG. 500 can be defined as follows. ·t max - The time when the first PSU asserts v1warn ·t psu1_v1warn - The time when the second PSU asserts v1warn ·t flush_start - The time when the power management subsystem 104 starts the power shortage flush operation ·t psu1_pwrok - The time when the second PSU de-asserts pwrok and system 100 starts the voltage drop sequence ·T v1warn_delay - The time delay between t psu0_v1warn and t psu1_v1warn ·T v1warn_debounce - The time delay from t psu1_v1warn to t flush_start ·T v1warn - The time to consume all the energy E of the power supply under maximum load v1warn ·P max - The maximum system load ·P throttle - The system load after the first PSU asserts v1warn ·P debounce - The system load after all PSUs assert v1warn ·P flush - The system load after the power shortage flush operation is triggered ·E v1warn ​​​- After the v1warn assertion and before the pwrok deassertion, available energy in the PSU ·E pwrok - After a PWROK deassertion, the available energy in the PSU before the primary power rail is lost. ·E psu0_reserve - The second PSU is psu1_v1warn After asserting v1warn, the available energy remaining in the first PSU to assert v1warn ·E reserve - The total available energy remaining in all PSUs after all PSUs have asserted v1warn and before the deassertion of pwrok in the last PSU. ·E v1warn_delay - System 100 is t v1warn_delay Energy consumed inside ·E flush - Energy required to successfully complete a power-under flash operation. • N - Number of active PSUs supplying power to the system Referring to Figure 5, the first PSU is t psu0_v1warn When v1warn is asserted in this case, it takes time for the power supply to shut off the associated power rail and stop supplying power to the system, (E v1warn +E pwrok The energy of ) is available. There are N active PSUs, and the system load is distributed among all active PSUs in the system. The second PSU is delayed by several points in time. psu1_v1warn Assert v1warn in this case. psu0_v1warn and t psu1_v1warn The amount of energy consumed between is E v1warn_delay It is expressed as follows.

[0063] System 100 obtains energy from all N active PSUs from the time the first power supply asserts v1warn until the second power supply asserts v1warn. The first PSU, after asserting v1warn, (E v1warn +E pwrokThe maximum energy of the first PSU is consumed when the second CPU asserts v1warn. The remaining energy in the first PSU is E psu0reserve It is expressed as follows.

[0064] T v1warn_delay If the value is small, the second PSU will deassert pwrok before the system consumes all the energy from the first power supply. In the worst case, when both power supplies assert v1warn simultaneously, both power supplies will also deassert pwrok simultaneously. Under these circumstances, when all power supplies deassert pwrok and the system shuts down, the first power supply's energy will be depleted. pwrok It may become impossible to use energy. To accommodate this possibility, system 100 uses the first power supply E pwrok It can be constructed with the assumption that energy is unavailable.

[0065] To utilize the full energy of both power supplies, system 100 may be configured such that a low-voltage flash does not immediately begin when the second PSU asserts v1warn. Instead, system 100 may delay the flash activation until the amount of energy stored in all active PSUs equals the amount required to complete the flash. System 100 stores enough energy to complete the cache flash operation. reserve ≧E flush It can be further configured to guarantee this.

[0066] If both PSUs assert v1warn simultaneously, T v1warn_delay =0, and T v1warn_debounce =T v1warn This is the case. If both PSUs assert a v1warn at different times, T v1warn_debounce =0, and a power shortage flash can be triggered immediately when the second PSU asserts v1warn. The power management subsystem 104 can program the energy threshold / voltage threshold accordingly.

[0067] 4. Managing externally initiated asynchronous reset events System shutdowns or resets are not always caused by power outage events. In some cases, system errors or user actions can trigger a system shutdown or reset. For these externally initiated asynchronous events, monitoring power loss may be insufficient to maintain a persistent memory state, as A / C power can be relatively constant. Asynchronous hardware resets are typically performed by directly asserting the reset request pin, initiating a reset in hardware and not giving the ability to invoke a software cache flush handler before the reset. In some embodiments, to prevent data loss, the board logic is configured to generate an SMI signal that initiates a cache flush when an externally initiated reset request is detected.

[0068] Figure 6 shows an illustrative set of actions for handling an externally triggered asynchronous reset event, according to several embodiments. All of the actions shown in Figure 6 are modifiable, rearrangeable, or omitted. Therefore, the specific order of the actions shown in Figure 6 should not be interpreted as limiting the scope of one or more embodiments.

[0069] Referring to Figure 6, process 600 intercepts the assertion of the HW reset request signal (operation 602). In some embodiments, platform-initiated reset requests, including reset requests initiated by the system management module 118, are proxied through the power management subsystem 104. This allows system 100 to activate the persistence cache flush handler 106 before performing the requested reset or power transition action.

[0070] In some embodiments, process 600 determines whether persistent cache flushing is enabled (operation 604). As will be further described below, system firmware (or other system logic) may selectively enable or disable persistent cache flushing to configure whether data in the processor cache 110 is included in the persistent memory state.

[0071] If persistent cache flushing is not enabled, then process 600 routes the request to the reset pin (operation 606). In some embodiments, the power management subsystem 104 routes the request to the system chipset. The chipset may initiate a hardware reset sequence.

[0072] When persistent cache flushing is enabled, process 600 routes the request to the system management module 118 (operation 608). In this case, the reset pin is not asserted immediately in response to a platform or user-initiated reset in order to allow time to invoke the software-based cache flush handler.

[0073] In some embodiments, process 600 generates an SMI signal (operation 610) to transition system 100 into system management mode. The SMI signal may be asserted by a system management module 118 using special signal lines directly coupled to the CPU 116. The SMI signal may cause system firmware 120 (e.g., BIOS) to halt tasks currently being performed by the CPU 116 in preparation for cache flushing and resetting.

[0074] In some embodiments, once persistent cache flush is enabled, the system firmware 120 (e.g., the BIOS) then configures a general-purpose input / output (GPIO) pin inside the system management module 118 as a trigger for SMI. The GPIO pin may be used to notify the system firmware 120 when a cache flush following a warm reset is to be performed. This GPIO may differ from the GPIO used to notify the chipset of an impending power shortage in order to signal that the persistent cache flush handler should terminate with the requested warm reset rather than a power off.

[0075] Process 600 then performs a cache flush operation (operation 612). In response to the SMI signal, the system firmware 120 may call the cache flush handler 106 to manage the cache flush operation, as previously described. Thus, data is transferred from volatile memory such as the processor cache 110 and memory buffer 112 to persistent memory 114, thereby maintaining the persistent state.

[0076] Process 600 further determines whether the flash is complete (operation 614). The persistent cache flash handler 106 may assert or notify a signal when data from the processor cache 110 and memory buffer 112 has been written to persistent memory 114.

[0077] Once the cache flush is complete, process 600 generates a reset request (operation 622). For example, the persistent cache flush handler 106 may initiate a system reset by writing a specific value to a register of a particular IO port / PCH (for example, writing 0x06 to port CF9), or by instructing the system logic to assert a hardware reset request signal to the chipset.

[0078] If the flush is not complete, process 600 may determine whether a timeout has been reached (operation 616). For example, process 600 may allow one second or another threshold period configurable by system 100 until the flush operation is complete. In some cases, system conditions associated with a reset event may prevent the flush from completing. By enforcing a timeout, system 100 may be prevented from becoming unable to perform a warm reset.

[0079] When the timeout is reached, process 600 directly generates a reset request signal to the chipset (operation 618). The reset request in operation 622 may be a direct reset request to the chipset or a software-based request. Therefore, the mechanism for resetting the system may differ depending on whether the flashing was successful or not.

[0080] In response to the reset signal, the system 100 is then reset (operation 420). This reset may cause the system 100 to shut down or restart.

[0081] Figure 7 shows an exemplary system 700 for intercepting and processing an externally triggered asynchronous reset event, according to several embodiments. The system management module 702 included in system 700 may be implemented by programmable hardware such as a field-programmable gate array (FPGA), or by other hardware components (or a combination of hardware and software) as further described below. The system management module 702 acts as a proxy and intercepts assertions of hardware request signals that may be triggered by a user pressing a reset button or by a reset request asserted by a board management controller (BMC) or debug header.

[0082] The system management module 702 includes a logic gate 704 that routes an asserted reset request signal to the demultiplexer 706. A selection wire coupled to the demultiplexer 706 can be set based on whether persistent cache flushing is enabled or disabled. A value of "0," or a low-voltage state, represents a memory operation mode in which persistent cache flushing is disabled, where data in the processor cache 110 and memory buffer 112 are not managed as part of the persistence domain. A value of "1," or a high-voltage state, represents a persistent cache operation mode in which persistent cache flushing is enabled, where data in the processor cache 110 and memory buffer 112 are part of the persistence domain. However, the value on the selection wire can be swapped depending on the specific implementation.

[0083] When persistent cache flushing is disabled, the system management module 702 then asserts a request reset interrupt signal to a pin electrically coupled to the CPU / chipset 712. In response, the reset control logic 714 of the CPU / chipset 712 stops the currently running task and initiates a hardware reset, which may include sending a signal to reset the finite state machine (FSM) 710. Resetting the FSM 710 may devoltage the power rails in a specific order to avoid damaging hardware components. As mentioned above, the order in which the power rails are devoltaged may vary depending on the system architecture.

[0084] When persistent cache flush is enabled, the system management module 702 asserts SMI using a special signal line directly coupled to another pin on the CPU / chipset 712. This signal line is different from the line previously described that is used to perform a hardware reset when persistent cache flush is disabled. In response to the detection of SMI, the CPU / chipset 712 sends a software-based request to the underpower flash handler 716 to initiate persistent cache flush.

[0085] The persistent cache flush handler 716 initiates a persistent cache flush operation in response to the request, transferring data from the processor cache and memory buffers to the persistent storage medium. If the cache flush is successful, the underpower flush handler 716 sends a software reset request to the reset control logic 714, which may trigger a voltage drop sequence as previously described.

[0086] When persistent cache flushing is enabled, the system management module 702 further initializes timer 708. Timer 708 may decrement or increment until it is canceled or reaches a timeout value. The count may be canceled in response to detecting a signal assertion to the input pin that resets the FSM 710. This signal indicates that the underpower flash handler 716 has successfully flushed the processor cache and memory buffers to the persistent storage medium, and the reset sequence begins. If the timeout value is reached before the timer is canceled, the system management module 702 then directly asserts the rst_req_in pin of the CPU / chipset 712 to trigger a hardware reset.

[0087] 5. Adjusting the persistent cache flush state between system components The system boot firmware may expose persistent cache flush support through a user-configurable option. However, the boot firmware may be deployed across a wide variety of hardware platforms, and the presentation of this option does not necessarily mean that a particular platform hardware can support persistent cache flush. Whether a platform can support persistent cache flush may depend on the hardware configuration, the presence and / or health of the energy storage module, and the capabilities of the underlying hardware components. In some embodiments, components of system 100 perform a handshake to (a) determine whether the hardware is sufficiently capable to support persistent cache flush, (b) selectively enable / disable persistent cache flush, (c) configure the system components to support persistent cache flush when persistent cache flush is enabled, and (d) communicate to the operating system whether persistent cache flush has been successfully enabled.

[0088] Figure 8 shows an illustrative set of operations for adjusting the persistent memory operation mode according to several embodiments. All of the operations shown in Figure 8 are modifiable, rearrangeable, or omitted. Therefore, the specific order of the operations shown in Figure 8 should not be interpreted as limiting the scope of one or more embodiments.

[0089] Referring to Figure 8, process 800 initiates the boot sequence (operation 802). In some embodiments, the boot sequence loads system firmware 120, which may include BIOS firmware. System firmware 120 may be configured to expose user-configurable options regarding persistent cache flushing. For example, system firmware 120 may prompt the user to confirm whether to enable persistent cache flushing, or the user may interact with a user interface, such as a BIOS setup utility screen.

[0090] In some embodiments, the user interface exposes multiple settings for “persistence domain” setup options to configure whether the platform operates in ADR mode or persistent cache flush mode. For example, the user interface may expose an option to select either a “memory controller” setting or a “CPU cache hierarchy” setting. In the “memory controller” setting, ADR is enabled but persistent cache flush is disabled. When this setting is selected, the memory buffer 112 is flushed during a power outage event, but the flush operation does not apply to the processor cache 110. In some embodiments, the system hardware may be configured to this setting by default.

[0091] The "CPU Cache Hierarchy" setting enables persistent cache flushing. Therefore, when this option is selected, if the platform hardware supports persistent cache flushing, the data in memory buffer 112 and processor cache 110 will be flushed in the event of a power outage.

[0092] In addition, or instead, other settings may be supported. For example, a “standard domain” setting may be selected in which cache data is not flushed during power shortage events. As previously described, the user may select a preferred setting via the user interface. If the user has not selected a setting, the system firmware 120 may select a default setting that varies depending on the specific implementation.

[0093] In some embodiments, the system firmware 120 checks to determine whether the persistent cache mode has been selected by the user or is the default (operation 804). Even if the option is selected, the platform hardware may not support persistent cache flush operation in some cases. Furthermore, the system hardware may change gradually as components are added, removed, age, and / or fail.

[0094] If persistent cache mode is not selected, the system firmware 120 continues the boot sequence without indicating support for persistent cache mode (operation 822). The boot sequence may include steps to initialize hardware components, load the operating system, and / or process any outstanding system boot files. The boot sequence may continue without performing the hardware capability checks described further below.

[0095] If persistent cache mode is selected, the system firmware 120 sends a request to the system management module 118 to determine whether the system 100 can support persistent cache flush operation (operation 806).

[0096] The system management module 118 evaluates the hardware capabilities of the system 100 in response to a request (operation 808). In some embodiments, the system management module 118 handshakes with one or more hardware components to determine settings, configurations, and other information indicating whether persistent cache flushing is supported. For example, firmware that may include hardware components connected during the boot sequence supplies the system firmware with a list of features that the components support. The system management module 118 scans the supplied list of features and / or other information to determine whether there is a feature that corresponds to persistent cache flushing.

[0097] In some embodiments, the step of evaluating the hardware capabilities of system 100 includes determining whether PSU 102a and / or PSU 102b support the generation of pre-warning signals and the configuration of programmable vwarn thresholds. For example, the system management module 118 may determine whether PSU 402 includes pins for asserting vwarn signals. If the PSU does not have these capabilities, the system management module 118 may determine that the platform hardware does not support persistent cache flush operation.

[0098] In addition, or instead, the system management module 118 may determine whether the power management subsystem 104 includes logic for detecting vwarn signals, monitoring the total energy level of multiple PSUs, and / or triggering interrupts when the overall system energy level falls below a threshold. If the power management subsystem 104 lacks these capabilities, the system management module 118 may determine that the platform hardware does not support persistent cache flush operation.

[0099] In addition, or instead, the system management module 118 may evaluate other hardware capabilities. For example, the system management module 118 may evaluate system 100 to determine whether system 100 supports the ability to intercept reset signals and configure GPIO pins to handle asynchronous reset events. As another example, the system management module 118 may evaluate CPU 116 to determine whether CPU 116 includes special signal lines for calling a persistent cache flush handler.

[0100] In addition, or instead, the system management module 118 may determine whether any BBU that supports persistent cache flush operation is installed. If a BBU is installed, the system management module 118 may determine that persistent cache flush is supported even if the PSU architecture does not support it. On the other hand, if a BBU is not installed and the PSU and / or power management subsystem does not support persistent cache flush operation, the system management module 118 may determine that persistent cache flush is not supported.

[0101] In addition, or alternatively, the system management module 118 may evaluate other hardware capabilities. For example, the system management module 118 may evaluate the capacity of auxiliary energy storage devices such as BBUs installed on the platform to determine whether these devices can supply enough energy to power active system components during flash processing. In addition, or alternatively, the system management module 118 may evaluate the health of the battery, such as by measuring battery impedance, to determine whether the platform hardware supports persistent cache flashing.

[0102] Based on its evaluation, the system management module 118 returns a response to the system firmware 120 indicating whether the platform can support persistent cache flushing (operation 810). This response may authorize the system firmware 120 to enable persistent cache flushing (if supported). Otherwise, the system management module 118 does not authorize the system firmware 120 to enable persistent cache flushing.

[0103] When the system firmware 120 receives a response, it determines whether the system 100 supports persistent cache flushing (operation 812).

[0104] If the platform hardware does not support persistent cache flushing, the system firmware 120 continues the boot sequence without informing the operating system 122 of the support for persistent cache flushing (operation 822). When persistent cache flushing is not known and is not enabled, the operating system 122 may prevent applications from attempting to treat the processor cache as persistent in system 100.

[0105] If persistent cache flushing is supported, the system firmware 120 and / or the system management module 118 configure the system components to support persistent cache flushing operations (operation 814). For example, the system firmware 120 may establish GPIO pins, initialize per-PSU timers, configure the PSU, and otherwise configure the system hardware / software to perform cache flushing operations, as previously described.

[0106] Next, the system firmware 120 and / or the system management module 118 inform the operating system 122 of the support for persistent cache flushing (operation 816). In some embodiments, the system firmware 120 may supply the operating system 122 with a list of supported features and / or configuration settings. The list may include entries indicating that persistent cache flushing is supported and enabled. However, the manner in which the support is communicated may vary depending on the specific implementation.

[0107] The operating system 122 detects, based on the notification, that the persistent cache mode is supported (operation 818). For example, during the boot sequence, the operating system 122 scans the list of supported features to determine whether the system firmware or system management module 118 has notified it of persistent cache flush support.

[0108] If the platform hardware enables and supports persistent cache mode, the operating system 122 informs one or more applications of the persistent cache mode (operation 820). In some embodiments, an application queries the operating system 122 to determine whether persistent cache mode is available and supported. The operating system 122 may provide a response indicating whether the application may rely on the persistent cache. Depending on whether the persistent cache is enabled and supported, the application may perform different logic. For example, if enabled, a database application may simplify the application code and make read and write operations more efficient by treating reads and writes as committed without performing complex software-based checks.

[0109] When a system component changes, process 800 may be repeated to determine whether support for persistent cache mode has changed. A hardware change, such as the installation of a BBU or an upgrade of a PSU, may cause system 100 to notify of support for persistent cache flushing if it was not previously supported. In other cases, the notification may be cleared if a component, such as a BBU, is removed or fails.

[0110] 6. Hardware Implementation Form According to one embodiment, the technology described herein is implemented by one or more dedicated computer devices. The dedicated computer device may be wired to perform the technology and may include one or more digital electronic devices such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or network processing units (NPUs) permanently programmed to perform the technology, or may include one or more general-purpose hardware processors programmed to perform the technology according to firmware, memory, other storage devices, or a combination of programmed instructions. Such a dedicated computer device may also combine custom wired logic, ASICs, FPGAs, or NPUs with custom programs to achieve the technology. The dedicated computer device may be a desktop computer system, a portable computer system, a handheld device, a networking device, or other device incorporating wired logic and / or programmed logic for performing the technology.

[0111] For example, Figure 9 is a block diagram showing a computer system 900 in which one embodiment of the present invention may be implemented. The computer system 900 includes a bus 902 or other communication mechanism for communicating information and a hardware processor 904 coupled to the bus 902 for processing information. The hardware processor 904 may be, for example, a general-purpose microprocessor.

[0112] The computer system 900 also includes main memory 906, such as random access memory (RAM) or other dynamic memory device coupled to bus 902, for storing information and instructions executed by processor 904. Main memory 906 may also be used to store temporary variables or other intermediate information while processor 904 is executing instructions. When such instructions are stored in a non-temporary storage medium accessible from processor 904, the computer system 900 becomes a dedicated machine individually tuned to perform the operations specified by those instructions.

[0113] The computer system 900 further includes a read-only memory (ROM) 908 or other static storage device coupled to a bus 902 for storing static information and instructions for the processor 904. A storage device 910, such as a magnetic disk or optical disk, is provided and coupled to the bus 902 for storing information and instructions.

[0114] The computer system 900 may be coupled via bus 902 to a display 912, such as a cathode ray tube (CRT) or light-emitting diode (LED) monitor, for displaying information to the computer user. An input device 914, which may include alphanumeric characters and other keys, is coupled to bus 902 for communicating information and command selections to the processor 904. Another type of user input device is a cursor control 916, such as a mouse, trackball, touchscreen, or cursor directional keys, for communicating directional information and command selections to the processor 904 and for controlling the movement of a cursor on the display 912. The input device 914 typically has two degrees of freedom on two axes, a first axis (e.g., x) and a second axis (e.g., y), and can specify a position in a plane.

[0115] The computer system 900, combined with individually coordinated wiring logic, one or more ASICs or FPGAs, firmware and / or program logic, can become a dedicated machine, or be programmed into a dedicated machine, to implement the technology described herein. According to one embodiment, the technology described herein is executed by the computer system 900 in response to the execution of one or more sequences of one or more instructions contained in the main memory 906 by the processor 904. Such instructions may be read into the main memory 906 from another storage medium, such as a storage device 910. The processor 904 executes the processing steps described herein by executing the sequence of instructions contained in the main memory 906. In alternative embodiments, wired circuits may be used instead of, or in combination with, software instructions.

[0116] As used herein, the term “storage medium” refers to any non-temporary medium that stores data and / or instructions that cause a machine to operate in a particular way. Such storage mediums may comprise non-volatile and / or volatile media. Non-volatile media include, for example, optical or magnetic disks such as storage device 910. Volatile media include dynamic memory such as main memory 906. Common forms of storage media include, for example, floppy disks, flexible disks, hard disks, semiconductor drives, magnetic tapes or other magnetic data storage media, CD-ROMs, other optical data storage media, any physical media with a pattern of holes, RAM, PROMs, and EPROMs, FLASH-EPROMs, NVRAMs, other memory chips or cartridges, Content Addressable Memory (CAM), and ternary Content Addressable Memory (TCAM).

[0117] A storage medium is distinct from a transmission medium, but can be used in conjunction with a transmission medium. A transmission medium participates in the transfer of information between storage mediums. For example, transmission media include coaxial cables, copper wires, and optical fibers, and include the wires that make up bus 902. Transmission media can also take the form of sound waves or light waves, such as those generated during data communication using radio waves or infrared light.

[0118] Various forms of media may be used to transport one or more sequences of one or more instructions to the processor 904 for execution. For example, the instructions may initially be carried on a magnetic disk or semiconductor drive of a remote computer. The remote computer may load the instructions into its dynamic memory and send them using a modem over a network line such as a telephone line, fiber optic cable, or coaxial cable. A modem local to the computer system 900 may receive the data on the network line and convert the data into an infrared signal using an infrared transmitter. An infrared detector may receive the data transported by the infrared signal, and appropriate circuitry may output the data to the bus 902. The bus 902 transports the data to the main memory 906, and the processor 904 retrieves and executes the instructions. The instructions received by the main memory 906 may optionally be stored in the storage device 910 before or after execution by the processor 904.

[0119] The computer system 900 also includes a communication interface 918 coupled to the bus 902. The communication interface 918 provides bidirectional data communication coupling to a network link 920 connected to a local network 922. For example, the communication interface 918 may be an Integrated Digital Communications Service (ISDN) card, a cable modem, a satellite modem, or a modem that provides data communication connectivity to a corresponding type of telephone line. As another example, the communication interface 918 may be a local area network (LAN) card that provides data communication connectivity to a compatible LAN. Wireless links may also be implemented. In any such implementation, the communication interface 918 transmits and receives electrical, electromagnetic, or optical signals that carry digital data streams representing various types of information.

[0120] Network link 920 typically provides data communication to other data devices through one or more networks. For example, network link 920 may provide connectivity to data devices operated by a host computer 924 or an Internet service provider (ISP) 926 through a local network 922. ISP 926 may also provide data communication services through a global packet data communication network 928, now commonly referred to as the "Internet." Both the local network 922 and the Internet 928 use electrical, electromagnetic, or optical signals to carry digital data streams. Signals traversing various networks, and signals on network link 920 passing through the communication interface 918, are illustrative forms of transmission media that carry digital data to and from the computer system 900.

[0121] The computer system 900 can send messages and receive data, including program code, through the network, network link 920, and communication interface 918. In the case of the internet, server 930 can transmit requested code for an application program through the internet 928, ISP 926, local network 922, and communication interface 918.

[0122] The code may be executed by processor 904 when received and / or stored in memory device 910 or other non-volatile memory for later execution.

[0123] 7. Other extensions The embodiments relate to a system having one or more devices including a hardware processor, which is configured to perform any of the operations described herein and / or any of the operations enumerated in any of the following claims.

[0124] In one embodiment, when an instruction contained in a non-temporary computer-readable storage medium is executed by one or more hardware processors, any of the operations described herein and / or any of the operations enumerated in any of the claims are performed.

[0125] Any combination of the features and functionalities described herein may be used in one or more embodiments. The embodiments described herein refer to many specific details that may vary depending on the implementation. Therefore, the specification and drawings should be considered illustrative rather than restrictive. The sole and exclusive indicator of the scope of the invention, and what the applicant intends to be the scope of the invention, is the literal scope equivalent to the set of claims in the specific form of the claims issued in this application, including any subsequent amendments.

Claims

1. A computer system determines that a configuration option of the computer system has been selected to enable a first operating mode in which data stored in a volatile processor cache is part of a persistent memory state, The computer system includes the step of determining whether the hardware components of the computer system can support persistent cache flushing, In response to the determination that the first operating mode is valid and that the hardware components can support persistent cache flushing, the computer system configures one or more components of the computer system to perform a persistent cache flush operation when a power interruption event or a power transition request is detected. A method comprising the steps of: the computer system notifying the operating system that the persistent cache flush is supported in response to a determination that the hardware component supports a persistent cache flush.

2. The computer system determines that a configuration option of the computer system has been selected in order to enable a first operating mode in which data stored in a volatile processor cache is part of a persistent memory state, The computer system includes the step of determining whether the hardware components of the computer system can support persistent cache flushing, The steps include: in response to a determination that the first operating mode is valid and that the hardware components can support persistent cache flushing, the computer system configures one or more components of the computer system to perform a persistent cache flush operation when a power interruption event or a power transition request is detected; A method wherein, even if the configuration option for enabling the first operating mode is selected, if the hardware component cannot support persistent cache flushing, the firmware running on the computer system is configured not to inform the operating system of support for the first operating mode.

3. The method according to claim 1 or 2, wherein the step of determining whether the computer system supports persistent cache flushing of the hardware components includes the step of determining whether the power supply unit of the computer system supports a programmable threshold associated with the energy stored in the power supply unit.

4. The method according to claim 1 or 2, wherein the step of determining whether the computer system supports persistent cache flushing includes the step of determining whether the battery backup unit has sufficient energy capacity to support persistent cache flushing operation.

5. The method according to any one of claims 1 to 4, wherein the step of configuring the computer system to perform a persistent cache flush includes the step of programming a voltage threshold based on the energy required to complete the cache flush operation.

6. The method according to any one of claims 1 to 4, wherein the step of configuring the computer system to perform a persistent cache flush includes configuring a GPIO pin so that an interrupt triggers a cache flush operation of data stored in a volatile processor cache.

7. The method of claim 2, further comprising the step of the computer system notifying the operating system in response to a determination that the hardware component supports persistent cache flushing.

8. The method according to any one of claims 1 to 7, wherein the system firmware further presents a second option of selecting a second operating mode in which the data stored in the volatile processor cache is not part of the persistent memory state.

9. The method according to any one of claims 1 to 8, wherein one or more of the components are initially in a default configuration that does not enable persistent cache flushing when a power outage event is detected.

10. The method according to any one of claims 1 to 9, wherein the first operating mode is enabled in response to a user selecting a configuration option to enable persistent cache flushing.

11. A computer-readable program that stores instructions, wherein when the instructions are executed by one or more hardware processors, the operation described in any one of claims 1 to 10 is performed.

12. A system comprising means for performing the operation described in any one of claims 1 to 10.

13. A system comprising a hardware processor and configured to perform the operations described in any one of claims 1 to 10.

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