How to set the initial erase voltage

Abstract

This invention provides a method for setting the initial erase voltage to shorten the erase time by setting different initial erase voltages for the memory die. [Solution] A method for setting an initial erase voltage includes: performing a preprogramming operation on a first target memory cell; setting an erase voltage and performing an erase operation on the first target memory cell using the erase voltage; performing an erase verification operation on the first target memory cell using a plurality of verification voltages; and determining whether to set the erase voltage as the initial erase voltage based on the erase verification result.

Description

Technical Field

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[0005]

[0001] The present invention relates to a voltage setting method, and particularly to a method for setting an initial erase voltage.

Background Art

[0002] The erase time of a flash memory is an important factor related to test cost and product applications. In the case of a NOR-type flash memory product having a tunnel oxide structure, charge trapping occurs in the tunnel oxide, resulting in a longer erase time during cycle operations.

[0003] In the prior art, in order to shorten the erase time, during the erase operation, first an erase pulse is issued, and then an erase verification is performed to determine whether the target memory cell passes the verification. If the target memory cell fails the erase verification, an erase pulse is continuously issued. This is repeated, and after several erase pulses, the erase voltage is increased to increase the erase speed.

[0004] In the above erase operation, it is necessary to set an initial erase voltage. Generally, the initial erase voltage of one wafer or one batch of samples is set to be the same. However, there are differences between dies in the wafer process, and the erase time becomes longer with cycle operations. Therefore, the same initial erase voltage may not be suitable for all wafers or samples.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present invention provides a method for setting an initial erase voltage that sets different initial erase voltages for memory dies to shorten the erase time.

Means for Solving the Problems

[0006] One embodiment of the present invention provides a method for setting an initial erase voltage. The setting method includes performing a preprogramming operation on a first target memory cell, setting an erase voltage and performing an erase operation on the first target memory cell using the erase voltage, performing an erase verification operation on the first target memory cell using a plurality of verification voltages, and determining whether to set the erase voltage as the initial erase voltage based on the erase verification result. [Effects of the Invention]

[0007] This invention provides a method for setting the initial erase voltage, which can shorten the erase time. [Brief explanation of the drawing]

[0008] [Figure 1] A block diagram showing a memory storage device according to one embodiment of the present invention. [Figure 2] This is a schematic diagram showing the threshold voltage distribution of a memory cell according to one embodiment of the present invention. [Figure 3] This is a step flowchart showing a method for setting the initial erase voltage according to one embodiment of the present invention. [Figure 4] This is a step flowchart showing a method for setting the initial erase voltage according to another embodiment of the present invention. [Figure 5] This is a block diagram showing a memory storage device according to another embodiment of the present invention. [Figure 6] This is a step flowchart showing a method for setting the initial erase voltage according to another embodiment of the present invention. [Figure 7] This is a step flowchart showing a method for setting the initial erase voltage according to another embodiment of the present invention. [Modes for carrying out the invention]

[0009] Referring to Figure 1, the memory storage device 100 includes a memory array 110, a sense amplifier circuit 120, a voltage generation circuit 130, a counter circuit 140, and a control circuit 150. The memory array 110 includes a plurality of memory cells. The memory storage device 100 is, for example, a NOR flash memory, but the type of memory storage device 100 is not limited in this invention.

[0010] The control circuit 150 is used to perform pre-programming, erase, or erase verification operations on the memory array 110. For example, the control circuit 150 can be used to set the initial erase voltage for an erase operation and the verification voltage for an erase verification operation. The control circuit 150 is used to perform block or sector erase operations on the memory array 110 according to an erase command. Before performing an erase operation, the control circuit 150 first performs a pre-programming operation on the selected block or sector, sets the initial erase voltage for the erase operation, and then performs the erase operation on the selected block or sector.

[0011] In one embodiment, the control circuit 150 may be a digital logic circuit, for example, a hardware circuit designed by a Hardware Description Language (HDL) or any other digital circuit design method familiar to those skilled in the art, and implemented by a Field Programmable Gate Array (FPGA), a Complex Programmable Logic Device (CPLD), or an Application-Specific Integrated Circuit (ASIC). Alternatively, the control circuit 150 may be a processor or controller with arithmetic capabilities.

[0012] Furthermore, the hardware structures of the memory array 110, sense amplifier circuit 120, voltage generation circuit 130, and counter circuit 140 can be adequately taught, suggested, and described for implementation from general knowledge in the relevant technical field.

[0013] The following explains how the control circuit 150 sets the initial erase voltage for the erase operation, referring to Figures 1 to 3. In Figure 2, the horizontal axis represents the threshold voltage of the memory cell, the vertical axis represents the number of memory cells, PPV is the verification voltage used for preprogramming verification, and EV, EV1, and EV2 are the verification voltages used for erase verification. Of these, verification voltage EV2 (second verification voltage) is greater than verification voltage EV1 (first verification voltage), and verification voltage EV1 is greater than verification voltage EV.

[0014] In this embodiment, the control circuit 150 can set the initial erase voltage for each sector, for example, using the method flow shown in Figure 3. The initial erase voltage settings for each sector may be the same or different. Generally, in a block erase command, the initial erase voltage for all sectors is the same. The algorithm of the embodiment of the present invention finds the adjusted erase voltage and applies it simultaneously to all sectors of the block to be erased. If the erase command is a sector erase command, the algorithm of the embodiment of the present invention finds the adjusted erase voltage and applies it to this sector. In Figure 2, the distribution curve 200 is the threshold voltage distribution of memory cells across the entire target sector after a preprogramming operation has been performed on the selected sector (hereinafter referred to as the target sector).

[0015] In step S100, the control circuit 150 selects a first target memory cell from the target sector and performs a preprogramming operation. In one embodiment, the number of first target memory cells may be, for example, 32, 64, 128, or any other suitable number, and the present invention does not limit the number of first target memory cells. In step S100, the control circuit 150 may also perform a preprogramming operation on the entire target sector.

[0016] In the sense amplifier circuit 120, a corresponding number of sense amplifiers 122 perform sensing operations on the first target memory cell and complete the erase verification operation. The voltage generation circuit 130 can provide verification voltages EV, EV1, and EV2 to the sense amplifiers 122 via the same signal line L1.

[0017] In step S110, the control circuit 150 sets a first erase voltage and uses the set first erase voltage to perform an erase operation on the first target memory cell. In step S120, the control circuit 150 uses a verification voltage EV1 to perform an erase verification operation on the first target memory cell. Next, in step S130, the control circuit 150 uses a verification voltage EV2 to perform an erase verification operation on the first target memory cell. In other words, in this embodiment, the control circuit 150 sequentially performs erase verification operations on the first target memory cell using verification voltages EV1 and EV2.

[0018] In step S140, the control circuit 150 determines whether the number of first target memory cells that did not pass the verification at verification voltage EV1 but passed the verification at verification voltage EV2 is greater than the reference amount.

[0019] If the number of first target memory cells that failed verification with verification voltage EV1 but passed verification with verification voltage EV2 is greater than the reference amount, it means that the first erase voltage set by the control circuit 150 in step S110 is appropriate as the initial erase voltage. Therefore, in step S150, the control circuit 150 sets the first erase voltage as the initial erase voltage for the target sector. In this embodiment, the reference amount may be set in advance, or the reference amount may be a reference ratio.

[0020] On the one hand, when the number of the first target memory cells that passed the verification of the verification voltage EV1 is greater than or equal to the reference amount (the distribution curve 210 in FIG. 2), it means that the first erasure voltage is too high. The control circuit 150 returns to step S100 and executes the pre-programming operation on the first target memory cells again. In step S110, the control circuit 150 lowers the first erasure voltage to the second erasure voltage and executes the erasure operation on the target memory cells using the second erasure voltage. Next, in steps S120 and S130, the control circuit 150 sequentially executes the erasure verification operation on the first target memory cells using the verification voltages EV1 and EV2. In step S140, when the number of the first target memory cells for which the second erasure voltage fails to pass the verification of the verification voltage EV1 but can be made greater than the reference amount for passing the verification of the verification voltage EV2, in step S150, the control circuit 150 sets the second erasure voltage as the initial erasure voltage of the target sector.

[0021] Alternatively, when the number of the first target memory cells that failed to pass the verification of the verification voltage EV2 is greater than or equal to the reference amount (for example, the distribution curve 220 in FIG. 2), it means that the first erasure voltage is too low. The control circuit 150 returns to step S100 and executes the pre-programming operation on the first target memory cells again. In step S110, the control circuit 150 raises the first erasure voltage to the third erasure voltage and executes the erasure operation on the target memory cells using the third erasure voltage. Next, in steps S120 and S130, the control circuit 150 sequentially executes the erasure verification operation on the first target memory cells using the verification voltages EV1 and EV2. In step S140, when the number of the first target memory cells for which the third erasure voltage fails to pass the verification of the verification voltage EV1 but can be made greater than the reference amount for passing the verification of the verification voltage EV2, in step S150, the control circuit 150 sets the third erasure voltage as the initial erasure voltage of the target sector.

[0022] In the embodiment of FIG. 1, the counter circuit 140 includes a first counter circuit 142 and a second counter circuit 144. The first counter circuit 142 counts the number of first target memory cells that have passed the verification of the verification voltage EV1 and is used to provide the count result to the control circuit 150. The second counter circuit 144 counts the number of first target memory cells that have failed the verification of the verification voltage EV2 and is used to provide the count result to the control circuit 150.

[0023] In the embodiment of FIG. 3, the control circuit 150 repeatedly executes steps S100 to S140 until the determination in step S140 becomes "YES", and then executes step S150, but the present invention is not limited thereto. In another embodiment, as long as the erasure operation is performed on the first target memory cells a predetermined number of times (for example, twice), the control circuit 150 can execute step S150 and set the adjusted erasure voltage as the initial erasure voltage of the target sector.

[0024] Specifically, referring to FIG. 4, in the embodiment of FIG. 4, the control circuit 150 repeatedly executes steps S200 to S240, and after performing the erasure operation on the first target memory cells a predetermined number of times, executes step S250. That is, in step S260, the control circuit 150 determines whether the erasure operation performed on the first target memory cells has exceeded a predetermined number of times. If the number of erasure times exceeds the predetermined number of times, the control circuit 150 can execute step S250 after adjusting the erasure voltage in step S270 and set the adjusted erasure voltage as the initial erasure voltage of the target sector. In this embodiment, the predetermined number of times is, for example, two times, but the present invention is not limited thereto.

[0025] Therefore, by using the method of FIG. 3 or FIG. 4, the initial erasure voltage required for the erasure operation of each sector can be set. Also, by the method of FIG. 3 or FIG. 4, the same or different initial erasure voltages can be set for each block.

[0026] Referring to Figures 1 and 5, in the embodiment of Figure 1, the control circuit 150 uses verification voltages EV1 and EV2 in sequence to perform an erase verification operation on the first target memory cell. Furthermore, the voltage generation circuit 130 provides the verification voltages EV, EV1, and EV2 to the sense amplifier 124 via the same signal line L1. However, the present invention is not limited thereto.

[0027] In the embodiment shown in Figure 5, the control circuit 150 can perform an erase verification operation on the first target memory cell using verification voltage EV1 and simultaneously perform an erase verification operation on the second target memory cell using verification voltage EV2, thereby shortening the erase verification time. The first and second target memory cells are target memory cells of different groups within the same block or sector. The number of second target memory cells is the same as that of the first target memory cells. Therefore, in this embodiment, the control circuit 150 performs erase verification operations on the first and second target memory cells, respectively, using verification voltages EV1 and EV2, and sets the initial erase voltage based on the verification results of both.

[0028] The voltage generation circuit 130 provides a verification voltage EV, EV1 to the sense amplifier 122 corresponding to the first target memory cell via the signal line L1. The voltage generation circuit 130 also provides a verification voltage EV2 to the sense amplifier 124 corresponding to the second target memory cell via the signal line L2.

[0029] Referring to Figure 6, in this embodiment, in step S320, the control circuit 150 performs an erase verification operation on the first target memory cell using verification voltage EV1, and simultaneously performs an erase verification operation on the second target memory cell using verification voltage EV2. Next, in step S330, the control circuit 150 determines whether the number of first target memory cells that did not pass the verification with verification voltage EV1 and the number of second target memory cells that passed the verification with verification voltage EV2 are greater than a reference amount. Therefore, in step S340, the control circuit 150 can set the set or adjusted erase voltage as the initial erase voltage for the target sector.

[0030] Therefore, in the embodiment shown in Figure 6, the erase verification operation is performed on the first target memory cell and the second target memory cell, respectively, using verification voltages EV1 and EV2, and the initial erase voltage is set based on the two verification results.

[0031] In the embodiment shown in Figure 6, the control circuit 150 may repeatedly execute steps S300 to S330, and after performing a predetermined number of erase operations on the first target memory cell and the second target memory cell, it may execute step S340. In other words, if the number of erase operations exceeds the predetermined number, the control circuit 150 adjusts the erase voltage and then executes step S340, and the adjusted erase voltage can be set as the initial erase voltage for the target sector.

[0032] Referring to Figures 1 and 7, the method for setting the initial erase voltage in this embodiment is applicable to the memory storage device 100 in Figure 1, but the present invention is not limited thereto. Taking the memory storage device 100 in Figure 1 as an example, in step S400, the control circuit 150 performs a preprogramming operation on the first target memory cell. In step S410, the control circuit 150 sets the erase voltage and performs an erase operation on the first target memory cell using the erase voltage. In step S420, the control circuit 150 performs an erase verification operation on the first target memory cell using a plurality of verification voltages EV1, EV2. In step S430, the control circuit 150 decides whether to set the erase voltage as the initial erase voltage based on the result of the erase verification.

[0033] The method for setting the initial erase voltage in this embodiment can be sufficiently taught, suggested, and explained from the descriptions of the embodiments in Figures 1 to 6, so a detailed explanation is omitted.

[0034] In summary, in the embodiments of the present invention, an initial erase voltage suitable for a block or sector can be determined by performing multiple erase verification operations on one or more target memory cells in the same block or sector using multiple verifications. Therefore, the method for setting the initial erase voltage in the embodiments of the present invention allows for setting different initial erase voltages for the memory die, thereby reducing the erase time. Furthermore, before each cycle operation begins, the control circuit may reset the initial erase voltage for that erase operation.

[0035] Although the present invention has been disclosed through embodiments as described above, this does not limit the invention. Those with ordinary skill in the art can make some changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application. [Industrial applicability]

[0036] The method for setting the initial erase voltage of the present invention can also be applied to memory storage devices. [Explanation of Symbols]

[0037] 100: Memory storage device 110: Memory Array 120: Sense amplifier circuit 122, 124: SenseAmp 130: Voltage generation circuit 140: Counter circuit 142, 144: Counter 150: Control circuit EV, EV1, EV2, PPV: Verification Voltage L1, L2: Signal line S100, S110, S120, S130, S140, S150, S200, S210, S220, S230, S240, S250, S260, S270, S300, S310, S320, S330, S340, S400, S410, S420, S430: Method Steps

Claims

1. Perform a preprogramming operation on the first target memory cell. Set an erase voltage and perform an erase operation on the first target memory cell using the erase voltage. Performing an erase verification operation on the first target memory cell using a plurality of verification voltages, wherein the plurality of verification voltages include a first verification voltage and a second verification voltage, and the second verification voltage is greater than the first verification voltage, and performing the erase verification operation on the first target memory cell using the plurality of verification voltages includes performing the erase verification operation on the first target memory cell using the first verification voltage and the second verification voltage in sequence, and The process involves determining whether to set the erase voltage as the initial erase voltage based on the erase verification results, and determining whether to set the erase voltage as the initial erase voltage based on the erase verification results. A method for setting an initial erase voltage, which includes setting the erase voltage as the initial erase voltage if the number of first target memory cells that failed to pass the verification of the first verification voltage but passed the verification of the second verification voltage is greater than a reference amount.

2. Performing the preprogramming operation on the first target memory cell means A method for setting an initial erase voltage according to claim 1, comprising performing the preprogramming operation on a block or sector in which the first target memory cell is located.

3. Based on the erase verification results, it is determined whether to set the erase voltage as the initial erase voltage. A method for setting an initial erase voltage according to claim 1, comprising adjusting the erase voltage if the number of first target memory cells that passed the verification of the first verification voltage is equal to or greater than a standard amount, or if the number of first target memory cells that did not pass the verification of the second verification voltage is equal to or greater than a standard amount.

4. The process further includes performing the erase operation on the first target memory cell using the adjusted erase voltage, Based on the erase verification results, it is determined whether to set the erase voltage as the initial erase voltage. A method for setting an initial erase voltage according to claim 3, comprising setting the adjusted erase voltage as the initial erase voltage based on the erase verification result.

5. Based on the erase verification results, it is determined whether to set the erase voltage as the initial erase voltage. A method for setting an initial erase voltage according to claim 3, comprising lowering the erase voltage and setting the erase voltage after the reduction as the initial erase voltage if the number of first target memory cells that have passed the verification of the first verification voltage is equal to or greater than a standard amount.

6. Based on the erase verification results, it is determined whether to set the erase voltage as the initial erase voltage. A method for setting an initial erase voltage according to claim 3, comprising raising the erase voltage and setting the erase voltage after raising it as the initial erase voltage if the number of first target memory cells that did not pass the verification of the second verification voltage is equal to or greater than a standard amount.

7. Performing a preprogramming operation on the second target memory cell, Using the erase voltage, perform an erase operation on the second target memory cell, and This includes performing the erase verification operation on the second target memory cell using the plurality of verification voltages, The method for setting the initial erase voltage according to claim 1, wherein the first target memory cell and the second target memory cell are target memory cells of different groups within the same block or sector.

8. The method for setting an initial erase voltage according to claim 7, wherein the erase verification operations of the first target memory cell and the second target memory cell are performed simultaneously.

9. The plurality of verification voltages include a first verification voltage and a second verification voltage, and the second verification voltage is greater than the first verification voltage. Performing the erase verification operation on the first target memory cell using the plurality of verification voltages includes performing the erase verification operation on the first target memory cell using the first verification voltage, The method for setting an initial erase voltage according to claim 7, wherein performing the erase verification operation on the second target memory cell using the plurality of verification voltages includes performing the erase verification operation on the second target memory cell using the second verification voltage.

10. The method for setting an initial erase voltage according to claim 7, wherein the number of erase operations performed on the first target memory cell or the second target memory cell is less than or equal to a predetermined number of times.

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