DC / DC converter

Abstract

A switching modulation circuit (11) generates a first control signal with a specific duty ratio. A delay circuit (16) delays the first control signal to generate a second control signal. A zero cross detector (12) detects whether the output current of the DC / DC converter (1) falls below a threshold value in a rectification section, and generates a third control signal. A monitoring circuit detects the possibility of the output current flowing in reverse, and generates a fourth control signal. The delay time of the delay circuit is set to be shorter than the delay time of the zero cross detector (12). A driver circuit turns off both of first and second switching elements (Q1, Q2) when there is no possibility of the output current flowing in reverse and the third control signal transitions to indicate that the output current has fallen below the threshold value. The driver circuit turns off both of the first and second switching elements (Q1, Q2) when there is a possibility of the output current flowing in reverse and the second control signal transitions from an on state to an off state.

Description

Technical Field

[0001] The present disclosure relates to a DC / DC converter and its control circuit.

Background Art

[0002] In recent years, with the high functionality and miniaturization of portable devices, as a power supply circuit, a switching power supply with hysteresis control that operates at high frequency and can be made highly efficient and miniaturized has been widely used. For example, Patent Document 1 discloses a switching regulator that operates in a synchronous mode in which two power transistors are complementarily turned on and an asynchronous mode in which the high-side power transistor is turned on / off while the low-side power transistor remains off.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When a DC / DC converter is synchronously rectified under a light load, a reverse current can occur at the output terminal, significantly reducing its efficiency. To prevent this reverse current, a current detection circuit may be used to monitor the output current of the DC / DC converter. However, current detection circuits generally have an inherent delay time, so even if they detect a precursor to reverse current, such as the output current falling below a predetermined threshold, they cannot immediately turn off the switching element. As a result, a reverse current occurs while the switching element is on, reducing efficiency. Also, if the peak output current is small, it may be assumed that there is a risk of reverse current occurring, and the switching element may be turned off. However, when the switching element is turned off, the energy of the inductor is released, causing current to flow through the body diode of the switching element, resulting in reduced efficiency. Therefore, it is necessary to operate the DC / DC converter with higher efficiency than conventional designs while preventing or at least reducing reverse current.

[0005] The object of this disclosure is to provide a control circuit for a DC / DC converter that can operate the DC / DC converter with higher efficiency than conventional methods while preventing or at least reducing reverse current. Furthermore, the object of this disclosure is to provide a DC / DC converter equipped with such a control circuit. [Means for solving the problem]

[0006] According to a control circuit for a DC / DC converter in one aspect of this disclosure, In a control circuit for controlling a DC / DC converter comprising an inductor and first and second switching elements for storing and releasing energy relative to the inductor, The aforementioned control circuit is A switching modulation circuit that generates a first control signal having a predetermined duty cycle including an on state and an off state, A delay circuit that delays the first control signal over a first delay time to generate a second control signal, A zero-crossing detector that detects whether the output current of the DC / DC converter has fallen below a first threshold while the inductor is releasing its energy, and generates a third control signal indicating whether the output current has fallen below the first threshold, A monitoring circuit that detects whether or not there is a possibility of reverse current flow occurring in the output current, and generates a fourth control signal indicating whether or not the possibility of reverse current flow exists, The system includes a driver circuit that generates drive signals to turn the first and second switching elements on and off based on the first to fourth control signals, The zero-crossing detector has a second delay time inherent to the zero-crossing detector between detecting that the output current has become smaller than the first threshold and transitioning the state of the third control signal. The first delay time is set to be shorter than the second delay time. The aforementioned driver circuit is When the fourth control signal indicates that there is no possibility of reverse current, and the inductor is releasing its energy, and the third control signal transitions to indicate that the output current has become smaller than the first threshold, both the first and second switching elements are turned off. When the fourth control signal is in a state indicating the possibility of reverse current, and the inductor is releasing its energy, and the second control signal transitions from the ON state to the OFF state, both the first and second switching elements are turned off. [Effects of the Invention]

[0007] According to one aspect of this disclosure, a DC / DC converter can be operated with higher efficiency than conventional methods while preventing or at least reducing reverse current. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram showing the configuration of the DC / DC converter 1 according to the first embodiment. [Figure 2] It is a timing chart showing the first operation example of the DC / DC converter 1 in FIG. 1. [Figure 3] It is a timing chart showing the second operation example of the DC / DC converter 1 in FIG. 1. [Figure 4] It is a timing chart showing the third operation example of the DC / DC converter 1 in FIG. 1. [Figure 5] It is a circuit diagram showing the configuration of the delay circuit 16 in FIG. 1. [Figure 6] It is a circuit diagram showing the configuration of the delay circuit 16A according to the first modification example. [Figure 7] It is a circuit diagram showing the configuration of the delay circuit 16B according to the second modification example. [Figure 8] It is a circuit diagram showing the configuration of the delay circuit 16C according to the third modification example. [Figure 9] It is a circuit diagram showing the configuration of the delay circuit 16D according to the fourth modification example. [Figure 10] It is a block diagram showing the configuration of the DC / DC converter 1A according to the second embodiment. [Figure 11] It is a timing chart showing the first operation example of the DC / DC converter 1A in FIG. 10. [Figure 12] It is a timing chart showing the second operation example of the DC / DC converter 1A in FIG. 10. [Figure 13] It is a circuit diagram showing the configuration of the delay circuit 16E according to the fifth modification example. [Figure 14] It is a block diagram showing the configuration of the DC / DC converter 1B according to the third embodiment. [Figure 15] It is a block diagram showing the configuration of the DC / DC converter 1C according to the first comparative example. [Figure 16] It is a timing chart showing the first operation example of the DC / DC converter 1C in FIG. 15. [Figure 17] It is a timing chart showing the second operation example of the DC / DC converter 1C in FIG. 15. [Figure 18]It is a block diagram showing the configuration of the DC / DC converter 1D according to the second comparative example. [Figure 19] It is a timing chart showing the first operation example of the DC / DC converter 1D in FIG. 18. [Figure 20] It is a timing chart showing the second operation example of the DC / DC converter 1D in FIG. 18. [Figure 21] It is a timing chart showing the third operation example of the DC / DC converter 1D in FIG. 18.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Throughout the drawings, the same components are denoted by the same reference numerals.

[0010] [[ID=2l]]Before explaining the embodiments of the present disclosure in detail, the configuration and operation of the DC / DC converter according to the comparative example will be described.

[0011] [First Comparative Example] FIG. 15 is a block diagram showing the configuration of the DC / DC converter 1C according to the first comparative example. The DC / DC converter 1C receives the supply of the input voltage Vin from the input voltage source Vdd, generates the output voltage Vout at its output terminal Nout, and supplies the output voltage Vout to the load device 2. The DC / DC converter 1C is an example of a step-down converter that generates an output voltage Vout lower than the input voltage Vin.

[0012] The DC / DC converter 1C includes switching elements Q1, Q2, an inductor L1, a capacitor C1, a control circuit 10C, and a current sensor 21.

[0013] Switching elements Q1 and Q2 are connected in series with each other between the input voltage source Vdd and ground. Switching elements Q1 and Q2 are provided on the high side and low side, respectively. Switching element Q1 is, for example, a P-channel field-effect transistor, and switching element Q2 is, for example, an N-channel field-effect transistor.

[0014] Inductor L1 is connected between the node between switching elements Q1 and Q2 and the output terminal Nout of DC / DC converter 1C. Capacitor C1 is connected between the output terminal Nout of DC / DC converter 1C and ground.

[0015] The current sensor 21 detects the value of the output current Iout of the DC / DC converter 1C. In the first comparison example, the zero-crossing detector 12 (described later) of the control circuit 10C uses the value of the output current Iout that flows when the energy of the inductor L1 is released. Therefore, the current sensor 21 may be configured to detect the value of the output current Iout by, for example, monitoring the voltage across the switching element Q2.

[0016] The control circuit 10C generates drive signals S1 and S2 to control the on / off state of each switching element Q1 and Q2 based on the values ​​of the output voltage Vout and output current Iout, and applies the drive signals S1 and S2 to the control electrodes (gates) of each switching element Q1 and Q2. In this way, the control circuit 10C controls the switching elements Q1 and Q2 to store and release energy with respect to the inductor L1.

[0017] The control circuit 10C includes a switching modulation circuit 11, a zero-crossing detector 12, an inverter 61, and a negative OR (NOR) circuit 62.

[0018] The switching modulation circuit 11 generates a signal S0 having a predetermined duty cycle, including on and off states, based on the value of the output voltage Vout. The switching modulation circuit 11 changes the duty cycle of the signal S0 so that the output voltage Vout matches the desired voltage of the load device 2.

[0019] The zero-crossing detector 12 detects when the output current Iout of the DC / DC converter 1 becomes less than the threshold Ith1 while the inductor L1 is releasing energy, and generates a signal Szc indicating whether the output current Iout is less than or equal to the threshold Ith1. When the output current Iout is greater than or equal to the threshold Ith1 while the inductor L1 is releasing energy, the signal Szc becomes low level, and when the output current Iout becomes less than the threshold Ith1 while the inductor L1 is releasing energy, the signal Szc becomes high level. The zero-crossing detector 12 has an inherent delay time d1 between detecting that the output current Iout has become less than the threshold Ith1 and transitioning the state of the signal Szc.

[0020] The inverter 61 inverts signal S0 to generate signal S1. The NOR gate 62 performs a negation OR operation on signals S0 and Szc to generate signal S2.

[0021] Figure 16 is a timing chart showing a first operating example of the DC / DC converter 1C in Figure 15. Figure 17 is a timing chart showing a second operating example of the DC / DC converter 1C in Figure 15. Figures 16 and 17 show the output current Iout, signal Szc, and signals S0 to S1 in Figure 15. The switching operation of switching elements Q1 and Q2 includes an on-interval, a rectification interval, and an off-interval during one cycle. The "on-interval" is the time interval during which energy is stored in the inductor; in the example in Figure 15, it is the time interval during which switching element Q1 is turned on and switching element Q2 is turned off. The "rectification interval" is the time interval during which energy is released from the inductor; in the example in Figure 15, it is the time interval during which switching element Q1 is turned off and switching element Q2 is turned on. The "off-interval" is the time interval during which both switching elements Q1 and Q2 are turned off.

[0022] Figure 16 shows the case where the peak of the output current Iout is sufficiently large. In this case, the zero-crossing detector 12 transitions the signal Szc from a low level (L) to a high level (H) after a delay time d1 has elapsed following the output current Iout becoming less than the threshold Ith1 in the rectification section. This turns off both switching elements Q1 and Q2. The threshold Ith1 is set considering the delay time d1 of the zero-crossing detector 12 so that the output current Iout becomes zero at the moment the signal Szc rises. As shown in Figure 16, when the peak of the output current Iout is sufficiently large, the signal Szc transitions from a low level to a high level before a reverse current occurs, even though the zero-crossing detector 12 has a delay time d1. Therefore, the zero-crossing detector 12 can be used to prevent or at least reduce the reverse current. The zero-crossing detector 12 also resets the signal Szc to a low level at the end of the cycle based on the signal S0.

[0023] On the other hand, Figure 17 shows the case where the peak of the output current Iout is smaller than the threshold Ith1. In this case, the zero-crossing detector 12 detects that the output current Iout is smaller than the threshold Ith1 when it enters the rectification section. However, due to its delay time d1, the zero-crossing detector 12 cannot immediately transition the signal Szc from a low level to a high level. Therefore, the switching element Q2 is not turned off when the output current Iout decreases to zero, and a reverse current is generated.

[0024] According to the DC / DC converter 1C in Figure 15, even with the zero-crossing detector 12, it may not be possible to prevent the generation of reverse current when the peak of the output current Iout is small. Therefore, it is necessary to more reliably prevent or at least reduce reverse current.

[0025] [Second Comparative Example] Figure 18 is a block diagram showing the configuration of the DC / DC converter 1D according to the second comparative example. The DC / DC converter 1D includes a control circuit 10D instead of the control circuit 10C in Figure 15.

[0026] The control circuit 10D includes a switching modulation circuit 11, a zero-crossing detector 12, a peak current detector 13, an inverter 71, an inverter 72, and a negative OR (NOR) circuit 73.

[0027] The switching modulation circuit 11 and zero-crossing detector 12 in Figure 18 are configured and operate similarly to the corresponding components in Figure 15.

[0028] The peak current detector 13 detects the possibility of reverse current flow occurring in the output current Iout and generates a signal Spc indicating whether or not reverse current possibility exists. The peak current detector 13 detects reverse current possibility when the output current Iout does not exceed the threshold Ith2 while energy is being stored in the inductor L1. When the output current Iout is less than or equal to the threshold Ith2 while energy is being stored in the inductor L1, the signal Spc becomes low level, and when the output current Iout becomes greater than the threshold Ith2 while energy is being stored in the inductor L1, the signal Spc becomes high level. Reverse current possibility is, for example, a precursor to the occurrence of reverse current. The peak current detector 13 has an inherent delay time d2 between detecting that the output current Iout has become greater than the threshold Ith2 and transitioning the state of the signal Spc.

[0029] Inverter 71 inverts signal Spc. Inverter 72 inverts signal S0 to generate signal S1. NOR gate 73 performs a negative OR operation on signal S0, the inverted signal of signal Spc, and signal Szc to generate signal S2.

[0030] In the second comparative example, the zero-crossing detector 12 of the control circuit 10D uses the value of the output current Iout that flows when the inductor L1 releases energy. Therefore, the current sensor 21 may be configured to detect the value of the output current Iout for the zero-crossing detector 12, for example, by monitoring the voltage across the switching element Q2. Also in the second comparative example, the peak current detector 13 (described later) of the control circuit 10D uses the value of the output current Iout that flows when the inductor L1 stores energy. Therefore, the current sensor 21 may be configured to detect the value of the output current Iout for the peak current detector 13, for example, by monitoring the voltage across the switching element Q1.

[0031] Figure 19 is a timing chart showing the first operating example of the DC / DC converter 1D in Figure 18. Figure 20 is a timing chart showing the second operating example of the DC / DC converter 1D in Figure 18. Figure 21 is a timing chart showing the third operating example of the DC / DC converter 1D in Figure 18. Figures 19 to 21 show the signal Spc in addition to the signals shown in Figures 16 to 17.

[0032] Figure 19 shows the case where the peak of the output current Iout is sufficiently large, for example, greater than the threshold Ith2. The threshold Ith2 is set such that the peak of the output current Iout is sufficiently large so that the signal Szc transitions from a low level to a high level before a reverse current occurs, as explained with reference to Figure 16. The threshold Ith2 may also be set to be greater than the threshold Ith1, as shown in Figure 19. In this case, the peak current detector 13 transitions the signal Spc from a low level to a high level after a delay time d2 has elapsed since the output current Iout became greater than the threshold Ith2 during the ON section. Then, the zero-crossing detector 12 transitions the signal Szc from a low level to a high level after a delay time d1 has elapsed since the output current Iout became less than the threshold Ith1 during the rectification section. This turns off both switching elements Q1 and Q2. Based on the signal S0, the peak current detector 13 resets the signal Spc to a low level at the end of the cycle.

[0033] Figure 20 shows the case where the peak of the output current Iout is greater than threshold Ith1 and less than threshold Ith2. In this case, the signal Spc remains at a low level, and even when the ON section ends, the switching element Q2 does not turn on and transitions directly to the OFF section. Since the switching element Q2 is not turned on, no reverse current is generated. However, the energy of the inductor L1 is released by flowing through the body diode of the switching element Q2.

[0034] Figure 21 shows the case where the peak of the output current Iout is less than the threshold Ith1. In this case as well, as in Figure 20, the signal Spc remains at a low level, and the switching element Q2 does not turn on even after the ON section ends, and transitions directly to the OFF section. The energy of the inductor L1 is released by flowing through the body diode of the switching element Q2.

[0035] According to the DC / DC converter 1D in Figure 18, the inclusion of a peak current detector 13 prevents the generation of reverse current. However, current flows through the body diode of the switching element Q2 during the off-period, resulting in lower efficiency compared to when the switching element Q2 is on. Therefore, it is necessary to operate the DC / DC converter more efficiently while preventing or at least reducing reverse current.

[0036] The following describes a DC / DC converter according to an embodiment that can operate with higher efficiency than conventional converters while preventing or at least reducing reverse current.

[0037] [First Embodiment] A DC / DC converter according to the first embodiment will be described with reference to Figures 1 to 9.

[0038] [Configuration of the first embodiment] Figure 1 is a block diagram showing the configuration of a DC / DC converter 1 according to the first embodiment. The DC / DC converter 1 includes switching elements Q1, Q2, an inductor L1, a capacitor C1, a control circuit 10, and a current sensor 21.

[0039] The switching elements Q1, Q2, inductor L1, capacitor C1, and current sensor 21 in Figure 1 are configured and operate similarly to the corresponding components in Figures 15 and 18.

[0040] The control circuit 10 includes a switching modulation circuit 11, a zero-crossing detector 12, a peak current detector 13, a negative AND (NAND) circuit 14, an inverter 15, a delay circuit 16, a negative OR (NOR) circuit 17, an inverter 18, and a negative OR (NOR) circuit 19. The control circuit 10 may be configured as an integrated circuit having terminals N0 to N4.

[0041] The switching modulation circuit 11, zero-crossing detector 12, and peak current detector 13 in Figure 1 are configured and operate similarly to the corresponding components in Figure 18.

[0042] The NAND gate 14 performs a logical AND operation on the signals Szc and Spc. The inverter 15 inverts the output signal of the NAND gate 14.

[0043] The delay circuit 16 generates signal S0d by delaying signal S0 over a predetermined delay time d10. The length of the delay time d10 is set to be shorter than the delay time d1 of the zero-crossing detector 12. The length of the delay time d10 may be a fixed value, or it may change according to the peak of the output current Iout, or according to the difference between the input voltage Vin and the output voltage Vout.

[0044] The NOR gate 17 performs the negative OR operation of signals S0, S0d, and Spc. The inverter 18 inverts signal S0 to generate signal S1. The NOR gate 19 performs the negative OR operation of signal S0, the output signal of the inverter 15, and the output signal of the NOR gate 17 to generate signal S2.

[0045] The peak current detector 13 is an example of a monitoring circuit that detects the possibility of reverse current in the output current Iout and generates a control signal indicating whether or not reverse current is possible. The NAND gate 14, inverter 15, NOR gate 17, inverter 18, and NOR gate 19 are examples of driver circuits that generate drive signals S1 and S2 to turn switching elements Q1 and Q2 on and off based on signals S0, S0d, Szc, and Spc.

[0046] [Operation of the first embodiment] Figure 2 is a timing chart showing the first operating example of DC / DC converter 1 in Figure 1. Figure 3 is a timing chart showing the second operating example of DC / DC converter 1 in Figure 1. Figure 4 is a timing chart showing the third operating example of DC / DC converter 1 in Figure 1. Figures 2 to 4 show the signal S0d in addition to the signals shown in Figures 19 to 21.

[0047] Figure 2 shows the case where the peak of the output current Iout is sufficiently large, i.e., greater than the threshold Ith2. In this case, the peak current detector 13 transitions the signal Spc from a low level to a high level after a delay time d2 has elapsed following the output current Iout becoming greater than the threshold Ith2 during the ON section. Subsequently, the zero-crossing detector 12 transitions the signal Szc from a low level to a high level after a delay time d1 has elapsed following the output current Iout becoming less than the threshold Ith1 during the rectification section. As a result, both switching elements Q1 and Q2 are turned off.

[0048] Figure 3 shows the case where the peak of the output current Iout is greater than threshold Ith1 and less than threshold Ith2. In this case, after the ON section, it transitions to the rectification section. After that, the signal S0d When the signal transitions from a high level to a low level, both switching elements Q1 and Q2 are turned off. If the output current Iout does not decrease to zero during the rectification section, the energy of inductor L1 is released during the off section by flowing through the body diode of switching element Q2. However, since the switching operation in Figure 3 includes a rectification section, the time during which current flows through the body diode of switching element Q2 is shorter than in the case of Figure 20, resulting in improved efficiency.

[0049] Figure 4 shows the case where the peak of the output current Iout is less than the threshold Ith1. In this case as well, similar to Figure 3, after the ON section, it transitions to the rectified section. After that, the signal S0d When the signal transitions from a high level to a low level, both switching elements Q1 and Q2 are turned off. Since the operation in Figure 4 includes a rectification section, the time during which current flows through the body diode of switching element Q2 is shorter than in the case of Figure 21, resulting in improved efficiency.

[0050] As shown in Figures 2 to 4, reverse current can be prevented or at least reduced by turning off both switching elements Q1 and Q2 in response to the signal Szc or signal S0d. In particular, by setting the length of the delay time d10 to be shorter than the delay time d1 of the zero-crossing detector 12, as shown in Figure 4, when the output current Iout is small, the switching element Q2 can be turned off before reverse current occurs, thereby preventing or at least reducing reverse current. Furthermore, as shown in Figures 3 to 4, even when the output current Iout is smaller than the threshold Ith2, the switching operation includes a rectification section, which shortens the time that current flows through the body diode of the switching element Q2 and improves efficiency. Thus, the DC / DC converter 1 in Figure 1 can operate with higher efficiency than conventional converters while preventing or at least reducing reverse current.

[0051] [Configuration of the delay circuit] Figure 5 is a circuit diagram showing the configuration of the delay circuit 16 in Figure 1. The delay circuit 16 may include an even number of inverters 31 connected in series. The delay time d10 of the delay circuit 16 is the sum of the delay times of each inverter 31.

[0052] Figure 6 is a circuit diagram showing the configuration of the delay circuit 16A according to the first modified example. The delay circuit 16A comprises inverters 31-1 to 31-3, switching elements Q31 to Q32, a resistor E31, and a capacitor C31. The delay time d10 of the delay circuit 16A is determined according to the time constants of the resistor R31 and the capacitor C31.

[0053] Figure 7 is a circuit diagram showing the configuration of a delay circuit 16B according to a second modified example. The delay circuit 16B includes a constant current source 32 instead of the resistor R31 in Figure 6. The delay time d10 of the delay circuit 16B is determined according to the current supplied by the constant current source 32 and the capacitance of the capacitor C31.

[0054] Figure 8 is a circuit diagram showing the configuration of a delay circuit 16C according to a third modification. The delay circuit 16C includes a variable current source 33 instead of the resistor R31 in Figure 6. The variable current source 33 may include a resistor to which the voltage across the switching element Q1 is applied. In this case, as the current flowing through the switching element Q1 increases, the voltage across the switching element Q1 also increases, and consequently, the current flowing through the resistor also increases. By folding back the current through the resistor with a current mirror, a variable current source that changes according to the value of the output current Iout can be obtained. The delay time d10 of the delay circuit 16C changes according to the magnitude of the peak Ipeak of the output current Iout. By changing the delay time d10, the time during which current flows through the body diode of the switching element Q2 can be shortened.

[0055] Figure 9 is a circuit diagram showing the configuration of the delay circuit 16D according to the fourth modification. The delay circuit 16D includes switching elements Q33~Q36, resistors R32~R33, and a constant current source 34 instead of the resistor R31 in Figure 6. The circuit in Figure 9 is a combination of a current mirror circuit that operates as a variable current source that changes according to the input voltage Vin and a current mirror circuit that operates as a variable current source that changes according to the output voltage Vout. The delay time d10 of the delay circuit 16D changes according to the difference between the input voltage Vin and the output voltage Vout of the DC / DC converter 1. The lower the input voltage Vin and / or the higher the output voltage Vout, the shorter the delay time d10 becomes. By changing the delay time d10, the time during which current flows through the body diode of the switching element Q2 can be shortened.

[0056] The examples shown in Figures 5 to 9 are not the only ones; any other delay circuit can be used.

[0057] [Summary of the first embodiment] As described above, the DC / DC converter 1 according to the first embodiment can operate with higher efficiency than conventional converters while preventing or at least reducing reverse current.

[0058] [Second Embodiment] A DC / DC converter according to the second embodiment will be described with reference to Figures 10 to 13.

[0059] [Configuration of the second embodiment] Figure 10 is a block diagram showing the configuration of the DC / DC converter 1A according to the second embodiment. The DC / DC converter 1A includes a control circuit 10A instead of the control circuit 10 in Figure 1.

[0060] The control circuit 10A includes an on-time detector 41 instead of the peak current detector 13 in Figure 1. The on-time detector 41 detects the possibility of reverse current, where a reverse current of the output current Iout occurs, and generates a signal Sont indicating whether or not a reverse current possibility exists. The on-time detector 41 detects the possibility of reverse current when the length of time for storing energy in the inductor L1 does not exceed a threshold Tth. If the time for storing energy in the inductor L1 is less than or equal to the threshold Tth, the signal Sont becomes low level, and if the time for storing energy in the inductor L1 is longer than the threshold Tth, the signal Sont becomes high level. If the time for storing energy in the inductor L1 is short, the peak of the output current Iout is also expected to be small, and as a result, there is a risk of reverse current occurring, as explained with reference to Figure 17. The signal Sont is input to the NAND circuit 14 and the NOR circuit 17 instead of the signal Spc in Figure 1.

[0061] The on-time detector 41 is an example of a monitoring circuit that detects the possibility of reverse current flow in the output current Iout and generates a control signal indicating whether or not reverse current flow is possible.

[0062] [Operation of the second embodiment] Figure 11 is a timing chart showing a first operating example of the DC / DC converter 1A in Figure 10. Figure 12 is a timing chart showing a second operating example of the DC / DC converter 1A in Figure 10. Figures 11 and 12 show the signal Sont instead of the signal Spc shown in Figures 2 to 4. The on-time detector 41 has an inherent delay time d3 from the time it detects that the length of time for storing energy in the inductor L1 is longer than the threshold Tth until it transitions the state of the signal Sont.

[0063] Figure 11 shows the case where the ON interval is sufficiently long, i.e., longer than the threshold Tth, that it is estimated that no reverse current will occur. In this case, the ON-time detector 41 transitions the signal Sont from a low level to a high level after a delay time d3 has elapsed since the length of time for storing energy in the inductor L1 in the ON interval exceeds the threshold Tth. Subsequently, the zero-crossing detector 12 transitions the signal Szc from a low level to a high level after a delay time d1 has elapsed since the output current Iout became less than the threshold Ith1 in the rectification interval. As a result, both switching elements Q1 and Q2 are turned off.

[0064] Figure 12 shows the case where the ON time is shorter than the threshold Tth. In this case, the signal Sont remains at a low level. After the ON period, it transitions to the rectification period. Then the signal S0d When the signal transitions from a high level to a low level, both switching elements Q1 and Q2 are turned off.

[0065] As shown in Figures 11 and 12, reverse current can be prevented or at least reduced by turning off both switching elements Q1 and Q2 in response to the signal Szc or signal S0d. In particular, by setting the length of the delay time d10 to be shorter than the delay time d1 of the zero-crossing detector 12, reverse current can be prevented or at least reduced when the ON interval is short, as shown in Figure 12. Furthermore, since the switching operation includes a rectification interval, the time during which current flows through the body diode of switching element Q2 can be shortened, improving efficiency. Thus, the DC / DC converter 1A in Figure 10 can operate with higher efficiency than conventional converters while preventing or at least reducing reverse current.

[0066] [Configuration of the delay circuit] The delay circuit 16 in Figure 10 may have any configuration from the delay circuit 16 in Figure 5 and the delay circuits 16A to 16D in Figures 6 to 9.

[0067] Figure 13 is a circuit diagram showing the configuration of a delay circuit 16E according to a fifth modification. The control circuit 10A in Figure 10 may include the delay circuit 16E in Figure 13 instead of the delay circuit 16 in Figure 5. The delay circuit 16E includes an inverter 35, a constant current source 36, switches SW31 and SW32, and a capacitor C32 instead of the resistor R33 in Figure 9. The delay time d10 of the delay circuit 16E changes according to the length of time that energy is stored in the inductor L1 (i.e., the length of time that the signal S1 is at a high level). By changing the delay time d10, the time that current flows through the body diode of the switching element Q2 can be shortened.

[0068] The examples in Figures 5-9 and Figure 13 are not the only ones; any other delay circuit can be used.

[0069] [Summary of the second embodiment] As described above, the DC / DC converter 1A according to the second embodiment can operate with higher efficiency than conventional converters while preventing or at least reducing reverse current.

[0070] [Third Embodiment] Referring to Figure 14, a DC / DC converter according to a third embodiment will be described.

[0071] Figure 14 is a block diagram showing the configuration of the DC / DC converter 1B according to the third embodiment. The DC / DC converter 1B includes a control circuit 10B instead of the control circuit 10 in Figure 1.

[0072] Control circuit 10B includes, in addition to the components of control circuit 10 in Figure 1, an on-time detector 41, a negative AND (NAND) circuit 51, and an inverter 52. In other words, control circuit 10B has a configuration that combines control circuit 10 in Figure 1 and control circuit 10A in Figure 10.

[0073] The DC / DC converter 1B according to the third embodiment has a configuration that combines the first and second embodiments, thereby more reliably preventing or at least reducing reverse current than the first and second embodiments, and enabling more efficient operation.

[0074] [Other variations] In the example shown in Figure 2, the case where both the rising and falling edges of signal S0 are delayed to generate signal S0d was described. However, in the embodiment described, only the portion of signal S0 indicating the end of the ON period (the falling edge in the example shown in Figure 2) needs to be delayed for a predetermined delay time d10. The portion of signal S0 indicating the start of the ON period (the rising edge in the example shown in Figure 2) does not need to be delayed, and may be delayed for a delay time different from the delay time d10.

[0075] In the example shown in Figure 1, the switching elements Q1 and Q2 are located outside the integrated circuit having terminals N0 to N4, but the switching elements Q1 and Q2 may also be integrated inside the control circuit 10.

[0076] Figures 1, 10, and 14 show examples of DC / DC converters that are step-down converters. On the other hand, the control of the DC / DC converter according to the embodiment is also applicable to step-up converters or step-up / step-down converters.

[0077] [Summary of Embodiments] DC / DC converter 1 relating to the first aspect of this disclosure ,1A,1B Control circuit 10 ,10A,10B A DC / DC converter 1 comprises an inductor L1 and first and second switching elements Q1 and Q2 that store and release energy relative to the inductor L1. ,1A,1B Controls the control circuit 10. ,10A,10B The DC / DC converter 1 includes a switching modulation circuit 11, a delay circuit 16, a zero-crossing detector 12, a monitoring circuit, and a driver circuit. The switching modulation circuit 11 generates a first control signal having a predetermined duty cycle, including an on state and an off state. The delay circuit 16 delays the first control signal over a first delay time to generate a second control signal. The zero-crossing detector 12 detects when the energy of the inductor L1 is being released. ,1A,1BThe zero-crossing detector 12 detects whether the output current has fallen below a first threshold and generates a third control signal indicating whether the output current has fallen below the first threshold. The monitoring circuit detects the possibility of reverse current flow and generates a fourth control signal indicating whether the possibility of reverse current flow exists. The driver circuit generates drive signals to turn the first and second switching elements Q1 and Q2 on and off based on the first to fourth control signals. The zero-crossing detector 12 has a second delay time specific to the zero-crossing detector 12 from the time it detects that the output current has fallen below the first threshold until it transitions the state of the third control signal. The first delay time is set to be shorter than the second delay time. When the fourth control signal indicates that the possibility of reverse current flow does not exist, the driver circuit releases the energy of the inductor L1, and when the third control signal transitions to indicate that the output current has fallen below the first threshold, it turns off both the first and second switching elements Q1 and Q2. The driver circuit turns off both the first and second switching elements Q1 and Q2 when the fourth control signal indicates that reverse current is possible, when the inductor L1 is releasing energy, and when the second control signal transitions from the ON state to the OFF state.

[0078] According to the control circuit 10 of the DC / DC converter 1 in the second aspect of this disclosure, the control circuit in the first aspect may be configured as follows: The monitoring circuit detects, as a possibility of reverse current, that the output current did not exceed a second threshold when energy was being stored in the inductor L1.

[0079] According to the control circuit 10 of the DC / DC converter 1 in the third aspect of this disclosure, the control circuit in the second aspect may be configured as follows: The delay circuit 16C changes the length of the first delay time according to the magnitude of the peak of the output current.

[0080] According to the control circuit 10 of the DC / DC converter 1 in the fourth aspect of this disclosure, the control circuit in the second aspect may be configured as follows: The delay circuit 16D changes the length of the first delay time according to the difference between the input voltage and output voltage of the DC / DC converter 1.

[0081] According to the control circuit 10A of the DC / DC converter 1A in the fifth aspect of this disclosure, the control circuit in the first aspect may be configured as follows: The monitoring circuit detects that the length of time for storing energy in the inductor L1 does not exceed a third threshold, as a possibility of reverse current.

[0082] According to the control circuit 10A of the DC / DC converter 1A according to the sixth aspect of this disclosure, the control circuit according to the fifth aspect may be configured as follows: The delay circuit 16C changes the length of the first delay time according to the magnitude of the peak of the output current.

[0083] According to the control circuit 10A of the DC / DC converter 1A in the seventh aspect of this disclosure, the control circuit in the fifth aspect may be configured as follows: The delay circuit 16D changes the length of the first delay time according to the difference between the input voltage and output voltage of the DC / DC converter 1A.

[0084] According to the control circuit 10A of the DC / DC converter 1A according to the eighth aspect of this disclosure, the control circuit according to the fifth aspect may be configured as follows: The delay circuit 16E changes the length of the first delay time according to the length of time for storing energy in the inductor L1.

[0085] DC / DC converter 1 according to the ninth aspect of this disclosure ,1A,1B This includes an inductor L1, first and second switching elements Q1 and Q2 that store and release energy relative to the inductor L1, and DC / DC converters 1, 1A, and 1B according to one of the first to eighth embodiments. Control circuits 10, 10A, 10B It is equipped with the following. [Explanation of Symbols]

[0086] 1.1A~1D DC / DC converter 2 Load device 10, 10A~10D Control Circuit 11 Switching Modulation Circuit 12 Zero-crossing detectors 13. Peak current detector 14. Negative AND (NAND) Circuit 15 Inverter 16 Delay Circuit 17. Negative OR (NOR) Circuit 18 Inverter 19. Negative OR (NOR) Circuit 21 Current Sensor 31, 31-1~31-3 Inverter 32 Constant current source 33 Variable current source 34 Constant current source 35 Inverter 36 Constant current source 41 On-time detector 51 Negated AND (NAND) Circuit 52 Inverter 61 Inverter 62 Negative OR (NOR) Circuit 71 Inverter 72 Inverter 73 Negative OR (NOR) Circuit C1, C31, C32 Capacitors L1 Inductor Q1, Q2, Q31~Q36 Switching elements R31~R33 Resistor SW31, SW32 switches

Claims

1. In a control circuit for controlling a DC / DC converter comprising an inductor and first and second switching elements for storing and releasing energy relative to the inductor, The aforementioned control circuit is A switching modulation circuit that generates a first control signal having a predetermined duty cycle including an on state and an off state, A delay circuit that delays the first control signal over a first delay time to generate a second control signal, A zero-crossing detector that detects whether the output current of the DC / DC converter has fallen below a first threshold while the inductor is releasing its energy, and generates a third control signal indicating whether the output current has fallen below the first threshold, A monitoring circuit that detects whether or not there is a possibility of reverse current flow occurring in the output current, and generates a fourth control signal indicating whether or not the possibility of reverse current flow exists, The system includes a driver circuit that generates drive signals to turn the first and second switching elements on and off based on the first to fourth control signals, The zero-crossing detector has a second delay time inherent to the zero-crossing detector between detecting that the output current has become smaller than the first threshold and transitioning the state of the third control signal. The first delay time is set to be shorter than the second delay time. The aforementioned driver circuit is When the fourth control signal indicates that there is no possibility of reverse current, and the inductor is releasing its energy, and the third control signal transitions to indicate that the output current has become smaller than the first threshold, both the first and second switching elements are turned off. When the fourth control signal is in a state indicating the possibility of reverse current, and the inductor is releasing its energy, and the second control signal transitions from the ON state to the OFF state, both the first and second switching elements are turned off. Control circuit for a DC / DC converter.

2. The monitoring circuit detects, as the possibility of reverse current, that the output current did not exceed a second threshold while energy was being stored in the inductor. Control circuit for a DC / DC converter according to claim 1.

3. The delay circuit changes the length of the first delay time according to the magnitude of the peak of the output current. Control circuit for a DC / DC converter according to claim 2.

4. The delay circuit changes the length of the first delay time according to the difference between the input voltage and output voltage of the DC / DC converter. Control circuit for a DC / DC converter according to claim 2.

5. The monitoring circuit detects, as the possibility of reverse current, that the length of time for storing energy in the inductor did not exceed a third threshold. Control circuit for a DC / DC converter according to claim 1.

6. The delay circuit changes the length of the first delay time according to the magnitude of the peak of the output current. Control circuit for a DC / DC converter according to claim 5.

7. The delay circuit changes the length of the first delay time according to the difference between the input voltage and output voltage of the DC / DC converter. Control circuit for a DC / DC converter according to claim 5.

8. The delay circuit changes the length of the first delay time according to the length of time for storing energy in the inductor. Control circuit for a DC / DC converter according to claim 5.

9. Inductor and First and second switching elements that store and release energy in relation to the inductor, A control circuit according to one of claims 1 to 8, DC / DC converter.

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