Semiconductor device and method for manufacturing a semiconductor device

Abstract

This semiconductor device comprises a first conductive layer that is on an insulating surface, a first insulating layer that is on the first conductive layer, an oxide semiconductor layer that is on the first insulating layer, a second conductive layer that is on the oxide semiconductor layer, and a third conductive layer that is on the oxide semiconductor layer. The oxide semiconductor layer comprises: a first region; a second region that is in contact with the second conductive layer; a third region that is in contact with the third conductive layer; a first impurity region that is in contact with the second conductive layer, while being positioned between the first region and the second region; and a second impurity region that is in contact with the third conductive layer, while being positioned between the first region and the third region. The electrical conductivities of the first impurity region and the second impurity region are higher than the electrical conductivities of the second region and the third region.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device including a transistor. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] In recent years, oxide semiconductors have attracted attention as semiconductors that make up organic light-emitting diode (OLED) displays. Transistors that use oxide semiconductors as semiconductor layers (transistors with oxide semiconductor layers) have low off-leak current and can be driven at low frequencies, thus enabling low-power display devices. In particular, applying transistors with oxide semiconductor layers to self-emissive OLED displays has an even greater effect in reducing power consumption.

[0003] Because oxide semiconductors have high insulating properties, it is preferable to reduce the resistance of the regions in contact with the source and drain electrodes within the oxide semiconductor layer. For example, Patent Document 1 discloses a top-gate transistor in which impurity elements are added to the oxide semiconductor layer using the gate electrode as a mask, thereby forming a low-resistance region within the oxide semiconductor layer. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-27942 [Overview of the project] [Problems that the invention aims to solve]

[0005] Even if a low-resistance region cannot be provided in the oxide semiconductor layer, the transistor will still function. However, in that case, the negative bias temperature instability of the transistor is significant, and problems such as a large shift in the threshold value in the positive direction occurred. Therefore, as mentioned above, it is preferable to provide a low-resistance region in the oxide semiconductor layer in top-gate transistors. On the other hand, in bottom-gate transistors, since the gate electrode is located below the oxide semiconductor layer, it is not possible to add impurities to the oxide semiconductor layer using the gate electrode as a mask. To form a low-resistance region in the oxide semiconductor layer of a bottom-gate transistor, separate mask patterning is required, which increases the cost and cycle time in the fabrication of semiconductor devices including transistors.

[0006] One embodiment of the present invention aims to provide a semiconductor device and a method for manufacturing the same that reduces cost and cycle time and improves reliability, in view of the above problems. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment of the present invention includes a first conductive layer on an insulating surface, a first insulating layer on the first conductive layer, an oxide semiconductor layer on the first insulating layer, a second conductive layer on the oxide semiconductor layer, and a third conductive layer on the oxide semiconductor layer, wherein the oxide semiconductor layer includes a first region, a second region in contact with the second conductive layer, a third region in contact with the third conductive layer, a first impurity region in contact with the second conductive layer and between the first and second regions, and a second impurity region in contact with the third conductive layer and between the first and third regions, wherein the electrical conductivity of the first impurity region and the second impurity region is greater than the electrical conductivity of the second and third regions, respectively.

[0008] Furthermore, a semiconductor device according to one embodiment of the present invention includes a first conductive layer on an insulating surface, a first insulating layer on the first conductive layer, an oxide semiconductor layer on the first insulating layer, a second insulating layer on the oxide semiconductor layer, a second conductive layer on the second insulating layer, and a third conductive layer on the second insulating layer, wherein the oxide semiconductor layer includes a first region in contact with the second insulating layer, a second region in contact with the second insulating layer and superimposed on the second conductive layer, a third region in contact with the second insulating layer and superimposed on the third conductive layer, a first impurity region in contact with the second conductive layer and between the first and second regions, and a second impurity region in contact with the third conductive layer and between the first and third regions, wherein the electrical conductivity of each of the first and second impurity regions is greater than the electrical conductivity of each of the second and third regions.

[0009] Furthermore, a method for manufacturing a semiconductor device according to one embodiment of the present invention involves forming a first conductive layer and a first connecting electrode on an insulating surface, forming a first insulating layer on the first conductive layer and the first connecting electrode, forming an oxide semiconductor layer on the first insulating layer superimposed on the first conductive layer, forming a resist layer including a first opening and a second opening superimposed on the oxide semiconductor layer, adding an impurity element to the oxide semiconductor layer using the resist layer as a mask to form a first impurity region corresponding to the first opening and a second impurity region corresponding to the second opening in the oxide semiconductor layer, forming a second conductive layer in contact with the first impurity region, and forming a third conductive layer in contact with the second impurity region.

[0010] Furthermore, a method for manufacturing a semiconductor device according to one embodiment of the present invention involves forming a first conductive layer and a first connecting electrode on an insulating surface, forming a first insulating layer on the first conductive layer and the first connecting electrode, forming an oxide semiconductor layer on the first insulating layer superimposed on the first conductive layer, forming a second insulating layer on the oxide semiconductor layer and the first insulating layer, forming a resist layer including a first opening and a second opening superimposed on the oxide semiconductor layer, and using the resist layer as a mask, adding an impurity element to the oxide semiconductor layer to form a first impurity region corresponding to the first opening and a second impurity region corresponding to the second opening in the oxide semiconductor layer.

Brief Description of the Drawings

[0011] [Figure 1] It is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. [Figure 2A] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 2B] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 2C] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 2D] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 3A] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 3B] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 3C] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 4] It is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. [Figure 5A] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 5B] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 5C] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 5D] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6A] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6B]This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6C] This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7A] This is a schematic cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 7B] This is a schematic plan view of a semiconductor device according to one embodiment of the present invention. [Figure 8] This is a schematic enlarged cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 9] This is a schematic plan view of a semiconductor device according to one embodiment of the present invention. [Figure 10A] This is a schematic cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 10B] This is a schematic plan view of a semiconductor device according to one embodiment of the present invention. [Figure 11] This is a schematic diagram showing the configuration of a display device relating to one embodiment of the present invention. [Figure 12] This is a circuit diagram (pixel circuit) of a pixel of a display device according to one embodiment of the present invention. [Figure 13] This is a cross-sectional view of a pixel of a display device according to one embodiment of the present invention. [Modes for carrying out the invention]

[0012] The embodiments of the present invention will be described below with reference to the drawings. Note that each embodiment is merely an example, and any embodiment that a person skilled in the art could easily conceive by modifying it appropriately while maintaining the spirit of the invention is naturally included within the scope of the present invention. Furthermore, in order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc., of each part compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention.

[0013] In this specification, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A, B, and C, unless otherwise explicitly stated. Furthermore, these expressions do not exclude cases where α includes other elements.

[0014] In this specification, for the sake of explanation, the terms "up" or "above" or "down" or "below" will be used. However, as a general rule, the substrate on which the structure is formed is used as the reference point, and the direction from the substrate toward the structure is defined as "up" or "above." Conversely, the direction from the structure toward the substrate is defined as "down" or "below." Therefore, in the expression "structure on a substrate," the side of the structure facing the substrate is the bottom surface, and the opposite side is the top surface. Furthermore, the expression "structure on a substrate" merely describes the hierarchical relationship between the substrate and the structure, and other components may be placed between the substrate and the structure. Moreover, the terms "up" or "above" or "down" or "below" refer to the stacking order in a structure with multiple layers, and do not necessarily mean that the layers are in a superimposed positional relationship in a plan view.

[0015] In one embodiment of the present invention, when a single film is processed to form multiple films, these multiple films may have different functions and roles. However, these multiple films originate from a film formed as the same layer in the same process and have the same structure or the same material. Therefore, these multiple films are defined as existing in the same layer.

[0016] <First Embodiment> A semiconductor device 10 according to one embodiment of the present invention will be described with reference to Figures 1 to 2D.

[0017] [1. Configuration of semiconductor device 10] Referring to Figure 1, the configuration of the semiconductor device 10 according to one embodiment of the present invention will be described.

[0018] Figure 1 is a schematic cross-sectional view of a semiconductor device 10 according to one embodiment of the present invention. As shown in Figure 1, the semiconductor device 10 includes a transistor 100 and a connector 200. The transistor 100 has, for example, a switching function. The connector 200 electrically connects, for example, wiring provided on different layers.

[0019] The transistor 100 includes a substrate 110, a first conductive layer 120, a first insulating layer 130, an oxide semiconductor layer 140, a second conductive layer 160, and a third conductive layer 170. The first conductive layer 120 is provided on the substrate 110. The first insulating layer 130 is provided on the first conductive layer 120 so as to cover the first conductive layer 120. The oxide semiconductor layer 140 is provided on the first insulating layer 130. The second conductive layer 160 and the third conductive layer 170 are each provided on the first insulating layer 130 and the oxide semiconductor layer 140. The second conductive layer 160 and the third conductive layer 170 are each electrically connected to the oxide semiconductor layer 140.

[0020] The substrate 110 has an insulating surface and can support each layer provided on the substrate 110. For example, a translucent rigid substrate such as a glass substrate, quartz substrate, or sapphire substrate can be used as the substrate 110. Alternatively, a non-translucent rigid substrate such as a silicon substrate can be used as the substrate 110. Furthermore, a translucent flexible substrate such as a polyimide resin substrate, acrylic resin substrate, siloxane resin substrate, or fluororesin substrate can also be used as the substrate 110. To improve the heat resistance of the substrate 110, impurities may be introduced into the resin substrate. A substrate on which a silicon oxide film or silicon nitride film is deposited can also be used as the substrate 110.

[0021] The first conductive layer 120 can function as a gate electrode. As the material of the first conductive layer 120, for example, metals such as aluminum (Al), titanium (Ti), molybdenum (Mo), copper (Cu), or tungsten (W), or alloys thereof can be used. Also, as the material of the first conductive layer 120, for example, transparent conductive oxides such as indium tin oxide (ITO) or zinc oxide (ZnO) can be used. The first conductive layer 120 may be a single layer or a laminate.

[0022] The first insulating layer 130 can function as a gate insulating layer. As the material of the first insulating layer 130, for example, silicon oxide (SiO y ,

[0023] , y , x , x , ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon nitride oxide (SiN x O y ), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ), aluminum nitride oxide (AlN x O y ), or aluminum nitride (AlN x ) etc. can be used. The first insulating layer 130 may be a single layer or a laminate. Here, silicon oxynitride (SiO x N y ) and aluminum oxynitride (AlO x N y ) are silicon compounds and aluminum compounds containing less nitrogen (N) than oxygen (O). On the other hand, silicon nitride oxide (SiN x O y ) and aluminum nitride oxide (AlN x O y ) are silicon compounds and aluminum compounds containing less oxygen than nitrogen. When the first insulating layer 130 is a laminate, the first insulating layer 130 is a laminate of an oxide layer and a nitride layer, and it is preferable that the oxide layer is in contact with the oxide semiconductor layer 140.

[0023] The oxide semiconductor layer 140 can function as a channel-forming region. Examples of materials that can be used for the oxide semiconductor layer 140 include indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium aluminum zinc oxide (IAZO), or zinc oxide (ZnO). Furthermore, the oxide semiconductor layer 140 may be a single layer or a stacked layer.

[0024] The oxide semiconductor layer 140 includes a first region 141, a second region 142, a third region 143, a first impurity region 151, and a second impurity region 152. The first impurity region 151 is located between the first region 141 and the second region 142. The second impurity region 152 is located between the first region 141 and the third region 143. The first region 141 can function as a channel-forming region. Each of the second region 142 and the third region 143 includes the edge of the oxide semiconductor layer 140. Each of the first impurity region 151 and the second impurity region 152 can function as a low-resistance region (high-concentration impurity region). Here, a low-resistance region is a region having a resistance lower than the resistance of the channel-forming region. In other words, the electrical conductivity of the low-resistance region is greater than the electrical conductivity of the channel-forming region.

[0025] Each of the first impurity region 151 and the second impurity region 152 contains impurity elements other than the material of the oxide semiconductor layer 140. Examples of impurity elements include boron (B), phosphorus (P), argon (Ar), hydrogen (H), or nitrogen (N). Trace amounts of aluminum (Al) may also be present. The electrical conductivity of each of the first impurity region 151 and the second impurity region 152 is greater than the electrical conductivity of each of the first region 141, the second region 142, and the third region 143. That is, the presence of impurity elements in each of the first impurity region 151 and the second impurity region 152 results in a higher electrical conductivity than each of the first region 141, the second region 142, and the third region 143. The impurity elements contained in the first impurity region 151 and the second impurity region 152 do not necessarily have to generate carriers for the material of the oxide semiconductor layer 140. The impurity elements may be those that create oxygen vacancies in the material of the oxide semiconductor layer 140. In the first impurity region 151 and the second impurity region 152, the concentration of the impurity elements is 1 × 10⁻⁶. 15 atoms / cm 3 The above is preferable to 1 × 10 16 atoms / cm 3 That's all.

[0026] The second conductive layer 160 and the third conductive layer 170 can function as a source electrode and a drain electrode, respectively. As the material for the second conductive layer 160 and the third conductive layer 170, for example, metals such as aluminum (Al), titanium (Ti), molybdenum (Mo), copper (Cu), or tungsten (W), or alloys thereof, can be used. Alternatively, transparent conductive oxides such as indium tin oxide (ITO) or zinc oxide (ZnO) can be used as the material for the second conductive layer 160 and the third conductive layer 170. Each of the second conductive layer 160 and the third conductive layer 170 may be a single layer or a laminate. In this specification, even when referred to as a source electrode and a drain electrode, the functions of the source electrode and the drain electrode may be interchangeable.

[0027] The second conductive layer 160 is electrically connected to the second region 142 and the first impurity region 151. Similarly, the third conductive layer 170 is electrically connected to the third region 143 and the second impurity region 152. Since each of the first impurity region 151 and the second impurity region 152 can function as a low-resistance region, the connections between the second conductive layer 160 and the first impurity region 151, and between the third conductive layer 170 and the second impurity region 152, are ohmic contacts.

[0028] The connection portion 200 includes a substrate 110, a first connection electrode 210, a first insulating layer 130, and a second connection electrode 220. The first connection electrode 210 is provided on the substrate 110. The first insulating layer 130 is provided on the first connection electrode 210 so as to cover it. The second connection electrode 220 is provided on the first insulating layer 130. The second connection electrode 220 is electrically connected to the first connection electrode 210 through an opening provided in the first insulating layer 130.

[0029] As the material for the first connecting electrode 210 and the second connecting electrode 220, for example, metals such as aluminum (Al), titanium (Ti), molybdenum (Mo), copper (Cu), or tungsten (W), or alloys thereof, can be used. Furthermore, the first connecting electrode 210 and the second connecting electrode 220 may be single layers or laminated. The first connecting electrode 210 may be the same layer as the first conductive layer 120. That is, the first connecting electrode 210 may be the same material or have the same structure as the first conductive layer 120. The second connecting electrode 220 may be the same layer as the second conductive layer 160 and the third conductive layer 170. That is, the second connecting electrode 220 may be the same material or have the same structure as the second conductive layer 160 and the third conductive layer 170.

[0030] The first connecting electrode 210 includes a third impurity region 213. The third impurity region 213 includes impurity elements other than the material of the first connecting electrode 210. Examples of impurity elements include boron (B), phosphorus (P), argon (Ar), hydrogen (H), or nitrogen (N). It may also contain trace amounts of aluminum (Al). The impurity elements included in the third impurity region 213 may be the same as the impurity elements included in the first impurity region 151 and the second impurity region 152. The concentration of impurity elements in the third impurity region 213 is not particularly limited. For example, the concentration of impurity elements in the third impurity region 213 may be 1 × 10⁻⁶. 15 atoms / cm 3 The above is preferable to 1 × 10 16 atoms / cm 3 That concludes the explanation. It should also be said that the second connecting electrode 220 is in contact with the third impurity region 213 and is electrically connected to the third impurity region 213.

[0031] In the semiconductor device 10 according to this embodiment, a first impurity region 151 and a second impurity region 152 having high electrical conductivity are provided in the oxide semiconductor layer 140 of the transistor 100. Furthermore, a second conductive layer 4160 and a third conductive layer 170 corresponding to the source electrode and drain electrode are electrically connected to the first impurity region 151 and the second impurity region 152, respectively. As a result, the connection between the second conductive layer 160 and the first impurity region 151 and the connection between the third conductive layer 170 and the second impurity region 152 become ohmic contacts, stabilizing the interface between the oxide semiconductor layer 140 and the second conductive layer 160 and the interface between the oxide semiconductor layer 140 and the third conductive layer 170. Consequently, the reliability of the transistor 100 is improved. In particular, the negative bias temperature instability of the transistor 100 is improved.

[0032] [2. Method for fabricating the semiconductor device 10] A method for manufacturing a semiconductor device 10 according to one embodiment of the present invention will be described with reference to Figures 2A to 2D.

[0033] Figures 2A to 2D are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device 10 according to one embodiment of the present invention. In the following, explanations of steps that are normally performed in the manufacturing method of a semiconductor device may be omitted.

[0034] A first conductive layer 120, a first insulating layer 130, and an oxide semiconductor layer 140 are sequentially formed on the substrate 110 (see Figure 2A). Each of the first conductive layer 120, the first insulating layer 130, and the oxide semiconductor layer 140 can be deposited using sputtering or CVD. The patterns of the first conductive layer 120 and the oxide semiconductor layer 140 can be formed using photolithography.

[0035] Next, a resist layer 800 is formed on the first insulating layer 130 and the oxide semiconductor layer 140, including a first opening 810 and a second opening 820 that overlap with the first conductive layer 120, and a third opening 830 that overlaps with the first connecting electrode 210 (see Figure 2B). The first opening 810, the second opening 820, and the third opening 830 can be formed by a photolithography patterning process.

[0036] Next, the first insulating layer 130 is etched using the resist layer 800 as a mask (see Figure 2C). The etching of the first insulating layer 130 can be performed by wet etching or dry etching, but it is preferable to perform dry etching, which allows for a high selectivity ratio for etching between the first insulating layer 130 and the oxide semiconductor layer 140. For example, a fluorine-based gas can be used as the dry etching gas. Specifically, sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), or trifluoromethane (CHF3) can be used as the dry etching gas. By using an etching gas with a high selectivity ratio for etching between the first insulating layer 130 and the oxide semiconductor layer 140, the first insulating layer 130 exposed by the third opening 830 is etched (i.e., an opening is formed in the first insulating layer 130), while the oxide semiconductor layer 140 exposed by the first opening 810 and the second opening 820 is hardly etched.

[0037] Next, using the resist layer 800 as a mask, impurity elements are added to the oxide semiconductor layer 140 (see Figure 2D). The addition of impurity elements can be performed using methods such as ion implantation. Through the first opening 810 and the second opening, the impurity elements are added to the oxide semiconductor layer 140, forming a first impurity region 151 and a second impurity region 152 in the oxide semiconductor layer 140. In addition, impurity elements are added to the first connecting electrode 210 through the third opening 830, forming a third impurity region 213 in the first connecting electrode 210.

[0038] Next, after peeling off the resist layer 800, a second conductive layer 160, a third conductive layer 170, and a second connecting electrode 220 can be formed to fabricate the semiconductor device 10 shown in Figure 1.

[0039] In the method for manufacturing the semiconductor device 10 according to this embodiment, impurity elements can be added to the oxide semiconductor layer 140 using a mask used in forming the opening of the first insulating layer 130 at the connection portion 200. Therefore, there is no need to pattern the mask for adding impurity elements, and the cost and cycle time in manufacturing the semiconductor device 10 can be reduced. Consequently, the semiconductor device 10 can be manufactured at a low cost.

[0040] <Example 1> Referring to Figures 3A to 3C, a modified example of semiconductor device 10 according to one embodiment of the present invention, semiconductor device 10A, will be described. In the description of semiconductor device 10A, the same configuration as that of semiconductor device 10 may be omitted. Note that the modifications of semiconductor device 10 are not limited to semiconductor device 10A.

[0041] Figures 3A to 3C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device 10A according to one embodiment of the present invention. In the following, explanations of steps that are normally performed in the manufacturing method of a semiconductor device may be omitted.

[0042] After the resist layer 800 shown in Figure 2B is formed, impurity elements are added to the oxide semiconductor layer 140 using the resist layer 800 as a mask (see Figure 3A). The impurity elements are added to the oxide semiconductor layer 140 through the first opening 810 and the second opening 820, forming the first impurity region 151 and the second impurity region 152 in the oxide semiconductor layer 140. In addition, impurity elements are added to the first insulating layer 130 through the third opening 830, forming the third impurity region 233 in the first insulating layer 130.

[0043] Next, the first insulating layer 130 is etched using the resist layer 800 as a mask (see Figure 3B). Dry etching is performed using an etching gas with a high selectivity ratio for etching the first insulating layer 130 and the oxide semiconductor layer 140. However, this step may also be performed by wet etching. As the first insulating layer 130 is etched, the third impurity region 233 is also etched. Therefore, the first insulating layer 130 is etched without the third impurity region 233 acting as an etch stopper (i.e., an opening is formed in the first insulating layer 130), and a part of the first connecting electrode 210 is exposed.

[0044] Next, after peeling off the resist layer 800, the semiconductor device 10A is fabricated by forming a second conductive layer 160 and a third conductive layer 170 (see Figure 3C). The semiconductor device 10A includes a transistor 100 and a connector 200A. In the semiconductor device 10A, the third impurity region 233 is formed in the first insulating layer 130 and etched away, so the connector 200A does not contain the third impurity region. That is, in the connector 200A, the third impurity region is not formed in the first connector electrode 210.

[0045] In addition, at the connection portion 200A of the semiconductor device 10A, a region in which impurity elements are added to the side surface of the opening of the first insulating layer 130 may be provided without completely etching the third impurity region 233.

[0046] In the method for manufacturing the semiconductor device 10A according to this embodiment, impurity elements can be added to the oxide semiconductor layer 140 using a mask used in forming the opening of the first insulating layer 130 in the connection portion 200A. Therefore, there is no need to pattern the mask for adding impurity elements, and the cost and cycle time in manufacturing the semiconductor device 10A can be reduced. Consequently, the semiconductor device 10A can be manufactured at a low cost.

[0047] <Second Embodiment> Referring to Figures 4 to 5D, a semiconductor device 30 according to one embodiment of the present invention will be described.

[0048] [1. Configuration of the semiconductor device 30] Referring to Figure 4, the configuration of a semiconductor device 30 according to one embodiment of the present invention will be described. Note that in the description of the semiconductor device 30, the description of a configuration similar to that of the semiconductor device 10 may be omitted.

[0049] Figure 4 is a schematic cross-sectional view of a semiconductor device 30 according to one embodiment of the present invention. As shown in Figure 4, the semiconductor device 10 includes a transistor 300 and a connection portion 400.

[0050] The transistor 300 includes a substrate 310, a first conductive layer 320, a first insulating layer 330, an oxide semiconductor layer 340, a second insulating layer 360, a second conductive layer 370, and a third conductive layer 380. The first conductive layer 320 is provided on the substrate 310. The first insulating layer 330 is provided on the first conductive layer 320 so as to cover the first conductive layer 320. The oxide semiconductor layer 340 is provided on the first insulating layer 330. The second insulating layer 360 is provided on the oxide semiconductor layer 340 so as to cover the edges and central part of the oxide semiconductor layer 340. That is, the second insulating layer 360 is provided so as to expose a portion of the oxide semiconductor layer 340. The second conductive layer 370 and the third conductive layer 380 are provided on the second insulating layer 360 and the oxide semiconductor layer 340, respectively. Each of the second conductive layer 370 and the third conductive layer 380 is electrically connected to the oxide semiconductor layer 340.

[0051] The oxide semiconductor layer 340 includes a first region 341, a second region 342, a third region 343, a first impurity region 351, and a second impurity region 352. The first impurity region 351 is located between the first region 341 and the second region 342. The second impurity region 352 is located between the first region 341 and the third region 343. The first region 341 overlaps with the second insulating layer 360 and can function as a channel-forming region. The second region 342 and the third region 343 also overlap with the second insulating layer 360. The second insulating layer 360 can protect the channel-forming region of the first region 341, as well as the edges of the second region 342 and the third region 343. That is, the second insulating layer 360 can function as a so-called channel protection layer.

[0052] For example, silicon oxide (SiO2) can be used as the material for the second insulating layer 360. x ), silicon oxide nitride (SiO x N y ), silicon nitride (SiN x ), silicon nitride (SiN x O y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y ), or aluminum nitride (AlN x ) and the like can be used. The second insulating layer 360 may be a single layer or a laminate. When the second insulating layer 360 is a laminate, it is preferable that the second insulating layer 360 is a laminate of an oxide layer and a nitride layer, and that the oxide layer is in contact with the oxide semiconductor layer 340.

[0053] The second conductive layer 370 is electrically connected to the first impurity region 351. Similarly, the third conductive layer 380 is electrically connected to the second impurity region 352. Since each of the first impurity region 351 and the second impurity region 352 can function as a low-resistance region, the connections between the second conductive layer 370 and the first impurity region 351, and between the third conductive layer 380 and the second impurity region 352, are ohmic contacts.

[0054] The connection portion 400 includes a substrate 310, a first connection electrode 410, a first insulating layer 330, a second insulating layer 360, and a second connection electrode 420. The first insulating layer 330 is provided on the first connection electrode 410 so as to cover the first connection electrode 410. The second connection electrode 220 is provided on the second insulating layer 360. The second connection electrode 420 is electrically connected to the first connection electrode 410 through openings provided in the first insulating layer 330 and the second insulating layer 360. The first connection electrode 410 also includes a third impurity region 413. The second connection electrode 420 is in contact with the third impurity region 413 and is electrically connected to the third impurity region 413.

[0055] In the semiconductor device 30 according to this embodiment, a first impurity region 351 and a second impurity region 352 having high electrical conductivity are provided in the oxide semiconductor layer 340 of the transistor 300. Furthermore, a second conductive layer 370 and a third conductive layer 380 corresponding to the source electrode and drain electrode are electrically connected to the first impurity region 351 and the second impurity region 352, respectively. As a result, the connection between the second conductive layer 370 and the first impurity region 351 and the connection between the third conductive layer 380 and the second impurity region 352 becomes an ohmic contact, stabilizing the interface between the oxide semiconductor layer 340 and the second conductive layer 370 and the interface between the oxide semiconductor layer 340 and the third conductive layer 380. In addition, the channel formation region and edges of the oxide semiconductor layer 340 are protected by the second insulating layer 360. Therefore, the reliability of the transistor 300 is improved. In particular, the negative bias temperature instability of the transistor 300 is improved.

[0056] [2. Method for fabricating the semiconductor device 30] A method for manufacturing a semiconductor device 30 according to one embodiment of the present invention will be described with reference to Figures 5A to 5D.

[0057] Figures 5A to 5D are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device 30 according to one embodiment of the present invention. In the following, explanations of steps that are normally performed in the manufacturing method of a semiconductor device may be omitted.

[0058] A first conductive layer 320, a first insulating layer 330, an oxide semiconductor layer 340, and a second insulating layer 360 are formed sequentially on the substrate 310 (see Figure 5A). Each of the first conductive layer 320, the first insulating layer 330, the oxide semiconductor layer 340, and the second insulating layer 360 can be deposited using sputtering or CVD. Furthermore, the patterns of the first conductive layer 320 and the oxide semiconductor layer 340 can be formed using photolithography.

[0059] Next, a resist layer 800 is formed on the second insulating layer 360, including a first opening 810 and a second opening 820 that overlap with the first conductive layer 320, and a third opening 830 that overlaps with the first connecting electrode 410 (see Figure 5B). The first opening 810, the second opening 820, and the third opening 830 can be formed by a photolithography patterning process.

[0060] Next, the second insulating layer 360 and the first insulating layer 330 are etched using the resist layer 800 as a mask (see Figure 5C). The etching of the second insulating layer 360 and the first insulating layer 330 is preferably performed using dry etching with an etching gas that can increase the selectivity ratio of etching between the first insulating layer 330 and the oxide semiconductor layer 140. First, the second insulating layer 360 exposed by the first opening 810, the second opening 820, and the third opening 830 are etched. Subsequently, the first insulating layer 330 exposed by the third opening 830 is etched (i.e., openings are formed in the first insulating layer 330 and the second insulating layer 360), and a part of the first connecting electrode 410 is exposed. Because the selectivity ratio of etching between the first insulating layer 330 and the oxide semiconductor layer 340 is high, the oxide semiconductor layer 340 exposed by the first opening 810 and the second opening 820 is hardly etched.

[0061] Next, using the resist layer 800 as a mask, impurity elements are added to the oxide semiconductor layer 340 (see Figure 5D). The impurity elements are added to the oxide semiconductor layer 340 through the first opening 810 and the second opening 820, forming a first impurity region 351 and a second impurity region 352 in the oxide semiconductor layer 340. In addition, impurity elements are added to the first connecting electrode 410 through the third opening 830, forming a third impurity region 413 in the first connecting electrode 410.

[0062] Next, after peeling off the resist layer 800, a second conductive layer 370, a third conductive layer 380, and a second connecting electrode 420 can be formed to fabricate the semiconductor device 30 shown in Figure 4.

[0063] In the method for manufacturing the semiconductor device 30 according to this embodiment, impurity elements can be added to the oxide semiconductor layer 340 using a mask used in forming the openings of the first insulating layer 330 and the second insulating layer 360 at the connection portion 400. Therefore, there is no need to pattern the mask for adding impurity elements, and the cost and cycle time in manufacturing the semiconductor device 30 can be reduced. Consequently, the semiconductor device 30 can be manufactured at a low cost.

[0064] <Modification 2> Referring to Figures 6A to 6C, a modified example of semiconductor device 30 according to one embodiment of the present invention, semiconductor device 30A, will be described. In the description of semiconductor device 30A, the same configuration as that of semiconductor device 30 may be omitted. Note that the modifications of semiconductor device 30 are not limited to semiconductor device 30A.

[0065] Figures 6A to 6C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device 30A according to one embodiment of the present invention. In the following, explanations of steps that are normally performed in the manufacturing method of a semiconductor device may be omitted.

[0066] After the resist layer 800 shown in Figure 5B is formed, impurity elements are added to the oxide semiconductor layer 340 through the second insulating layer 360, using the resist layer 800 as a mask (see Figure 6A). The impurity elements are added to the oxide semiconductor layer 340 through the first opening 810 and the second opening 820, forming the first impurity region 351 and the second impurity region 352 in the oxide semiconductor layer 340. In addition, impurity elements are added to the first insulating layer 330 through the third opening 830, forming the third impurity region 433 in the first insulating layer 330.

[0067] Next, the second insulating layer 360 and the first insulating layer 330 are etched using the resist layer 800 as a mask (see Figure 6B). The etching of the second insulating layer 360 and the first insulating layer 330 is preferably performed using dry etching with an etching gas that can increase the selectivity ratio of etching between the first insulating layer 330 and the oxide semiconductor layer 140. First, the second insulating layer 360 exposed by the first opening 810, the second opening 820, and the third opening 830 are etched. Subsequently, the first insulating layer 330 exposed by the third opening 830 is etched (i.e., openings are formed in the first insulating layer 330 and the second insulating layer 360), and a part of the first connecting electrode 410 is exposed. Because the selectivity ratio of etching between the first insulating layer 330 and the oxide semiconductor layer 340 is high, the oxide semiconductor layer 340 exposed by the first opening 810 and the second opening 820 is hardly etched.

[0068] Next, after peeling off the resist layer 800, the semiconductor device 30A is fabricated by forming a second conductive layer 370 and a third conductive layer 380 (see Figure 6C). The semiconductor device 30A includes a transistor 300 and a connector 400A. In the semiconductor device 30A, the third impurity region 433 is formed in the second insulating layer 360 and etched away, so the connector 400A does not contain the third impurity region. That is, in the connector 400A, the third impurity region is not formed in the first connector electrode 410.

[0069] In addition, at the connection portion 400A of the semiconductor device 30A, a region in which impurity elements are added may be provided on the side surface of the opening of the first insulating layer 330 without completely etching the third impurity region 433.

[0070] In the method for manufacturing the semiconductor device 30A according to this embodiment, impurity elements can be added to the oxide semiconductor layer 340 using a mask used in forming the openings of the first insulating layer 330 and the second insulating layer 360 in the connection portion 400A. Therefore, there is no need to pattern the mask for adding impurity elements, and the cost and cycle time in manufacturing the semiconductor device 30A can be reduced. Consequently, the semiconductor device 30A can be manufactured at a low cost.

[0071] <Third Embodiment> Referring to Figures 7A to 8, a semiconductor device 50 according to one embodiment of the present invention will be described. Note that in the description of the semiconductor device 50, the same configuration as that of the semiconductor device 10 may be omitted.

[0072] Figures 7A and 7B are schematic cross-sectional and plan views, respectively, of a semiconductor device 50 according to one embodiment of the present invention. As shown in Figures 7A and 7B, the semiconductor device 50 includes a substrate 510, a first conductive layer 520, a first insulating layer 530, an oxide semiconductor layer 540, a first oxygen absorption layer 550, a second oxygen absorption layer 560, a second conductive layer 570, and a third conductive layer 580. The first conductive layer 520 is provided on the substrate 510. The first insulating layer 530 is provided on the first conductive layer 520 so as to cover the first conductive layer 520. The oxide semiconductor layer 540 is provided on the first insulating layer 530. The first oxygen absorption layer 550 and the second oxygen absorption layer 560 are provided on the first insulating layer 530 and the oxide semiconductor layer 540, respectively. The second conductive layer 570 is provided on the first insulating layer 530, the oxide semiconductor layer 540, and the first oxygen absorption layer 550, covering the first oxygen absorption layer 550. The third conductive layer 580 is provided on the first insulating layer 530, the oxide semiconductor layer 540, and the second oxygen absorption layer 560, covering the second oxygen absorption layer 560. Each of the second conductive layer 570 and the third conductive layer 580 is electrically connected to the oxide semiconductor layer 540.

[0073] The first oxygen absorption layer 550 covers at least a portion of one end of the oxide semiconductor layer 540 and is in contact with at least a portion of one end of the oxide semiconductor layer 540. In a plan view, the second conductive layer 570 is provided so as to cover the entire surface of the first oxygen absorption layer 550. Similarly, the second oxygen absorption layer 560 covers at least a portion of the other end of the oxide semiconductor layer 540 and is in contact with at least a portion of the other end of the oxide semiconductor layer 540. Also in a plan view, the third conductive layer 580 is provided so as to cover the entire surface of the second oxygen absorption layer 560.

[0074] In a plan view, the shapes of the first oxygen absorption layer 550 and the second oxygen absorption layer 560 are not limited to rectangles. The shapes of the first oxygen absorption layer 550 and the second oxygen absorption layer 560 may include not only straight lines but also curves.

[0075] Figure 8 is a schematic enlarged cross-sectional view of a semiconductor device 50 according to one embodiment of the present invention. Specifically, Figure 8 is an enlarged cross-sectional view of region A shown in Figure 7A. The oxide semiconductor layer 540 is more prone to oxygen vacancies than the first insulating layer 530. Therefore, when the first oxygen absorption layer 550 comes into contact with the oxide semiconductor layer 540, the first oxygen absorption layer 550 absorbs oxygen in the oxide semiconductor layer 540. As a result, a region in which oxygen vacancies are generated is formed in the oxide semiconductor layer 540. That is, as shown in Figure 8, a first oxygen vacancy region 541 is formed in the oxide semiconductor layer 540 in contact with the first oxygen absorption layer 550. Not only the oxygen in the portion directly in contact with the first oxygen absorption layer 550, but also the oxygen in the vicinity of the portion in direct contact is absorbed, so the first oxygen vacancy region 541 has a certain extent. That is, the surface area of ​​the first oxygen vacancy region 541 is larger than the surface area of ​​the portion of the oxide semiconductor layer 540 that is in direct contact with the first oxygen absorption layer 550.

[0076] Because the first oxygen-deficient region 541 has many oxygen vacancies, it has a high carrier density. That is, the electrical conductivity of the first oxygen-deficient region 541 is greater than the electrical conductivity of the region in the oxide semiconductor layer 540 where the first oxygen-deficient region 541 is not formed. Since the first oxygen-deficient region 541 extends to the vicinity of the portion that is in direct contact with the first oxygen absorption layer 550, the second conductive layer 570 covering the first oxygen absorption layer 550 is in contact with the first oxygen-deficient region 541. That is, the connection between the second conductive layer 570 and the first oxygen-deficient region 541 is an ohmic contact. Similarly, the electrical conductivity of the second oxygen-deficient region 542 is greater than the electrical conductivity of the region in the oxide semiconductor layer 540 where the second oxygen-deficient region 542 is not formed. Also, the connection between the third conductive layer 580 and the second oxygen-deficient region 542 is an ohmic contact.

[0077] As the material for the first oxygen absorption layer 550 and the second oxygen absorption layer 560, for example, metals such as calcium (Ca) or its compounds, aluminum (Al), silver (Ag), or magnesium (Mg), or alloys thereof can be used. Alternatively, as the material for the first oxygen absorption layer and the second oxygen absorption layer 560, a material containing the above-mentioned metal or alloy in a resin such as polyolefin resin, polyester resin, polyamide resin, or polyvinyl alcohol resin can also be used.

[0078] In the semiconductor device 50, the second conductive layer 570 and the third conductive layer 580 can function as a source electrode and a drain electrode, respectively. The first oxygen-absorbing layer 550 and the second oxygen-absorbing layer 560, which have absorbed oxygen, may be conductive or insulating.

[0079] The first oxygen absorption layer 550 may be covered by the second conductive layer 570 only in the region that overlaps with the oxide semiconductor layer 540. That is, the region of the first oxygen absorption layer 550 that does not overlap with the oxide semiconductor layer 540 does not need to be covered by the second conductive layer 570. In this case, the first oxygen absorption layer 550 can be used as a wiring layer different from the second conductive layer 570. Similarly, the second oxygen absorption layer 560 can be used as a wiring layer different from the third conductive layer 580.

[0080] In the semiconductor device 50 according to this embodiment, the first oxygen absorption layer 550 and the second oxygen absorption layer 560 are in contact with the oxide semiconductor layer 540, thereby forming a first oxygen vacancy region 541 and a second oxygen vacancy region 542 having high electrical conductivity within the oxide semiconductor layer 540. Furthermore, the second conductive layer 570 and the third conductive layer 580, corresponding to the source and drain electrodes of the transistor, are electrically connected to the first oxygen vacancy region 541 and the second oxygen vacancy region 542, respectively. As a result, the connection between the second conductive layer 570 and the first oxygen vacancy region 541, and the connection between the third conductive layer 580 and the second oxygen vacancy region 542, are ohmic contacts, stabilizing the interfaces between the oxide semiconductor layer 540 and the second conductive layer 570, and between the oxide semiconductor layer 540 and the third conductive layer 580. Consequently, the reliability of the semiconductor device 50 is improved. In particular, the negative bias temperature instability of the semiconductor device 50 is improved.

[0081] <Variation 3> Referring to Figure 9, a modified example of semiconductor device 50A, which is a modified example of semiconductor device 50 according to one embodiment of the present invention, will be described. In the description of semiconductor device 50A, the description of components similar to those of semiconductor device 50 may be omitted. Note that the modifications of semiconductor device 50 are not limited to semiconductor device 50A.

[0082] Figure 9 is a schematic plan view of a semiconductor device 50A according to one embodiment of the present invention. As shown in Figure 9, the semiconductor device 50A includes an oxide semiconductor layer 540, a first oxygen absorption layer 550A, a second oxygen absorption layer 560A, a second conductive layer 570A, and a third conductive layer 580A.

[0083] The first oxygen absorption layer 550A covers at least a portion of one end of the oxide semiconductor layer 540 and is in contact with at least a portion of one end of the oxide semiconductor layer 540. In a plan view, the second conductive layer 570A covers the entire surface of one end of the oxide semiconductor layer 540. Similarly, the second oxygen absorption layer 560A covers at least a portion of the other end of the oxide semiconductor layer 540 and is in contact with at least a portion of the other end of the oxide semiconductor layer 540. In a plan view, the third conductive layer 580A covers the entire surface of the other end of the oxide semiconductor layer 540.

[0084] In the semiconductor device 50A, the first oxygen absorption layer 550A and the second oxygen absorption layer 560A are in contact with the oxide semiconductor layer 540 and absorb oxygen from the oxide semiconductor layer 540. As a result, an oxygen vacancy region is formed in the oxide semiconductor layer 540. The second conductive layer 570A and the third conductive layer 580A, which correspond to the source electrode and drain electrode of the transistor, are electrically connected to the oxygen vacancy region by ohmic contact. Therefore, the interface between the oxide semiconductor layer 540 and the second conductive layer 570A, and the interface between the oxide semiconductor layer 540 and the third conductive layer 580A are stabilized. Consequently, the reliability of the semiconductor device 50A is improved. In particular, the negative bias temperature instability of the semiconductor device 50A is improved.

[0085] <Fourth Embodiment> Referring to Figures 10A and 10B, a semiconductor device 60 according to one embodiment of the present invention will be described. Note that in the description of the semiconductor device 60, the same configuration as that of the semiconductor device 50 may be omitted.

[0086] Figures 10A and 10B are schematic cross-sectional and plan views, respectively, of a semiconductor device 60 according to one embodiment of the present invention. As shown in Figures 10A and 10B, the semiconductor device 60 includes a substrate 610, a first conductive layer 620, a first insulating layer 630, an oxide semiconductor layer 640, a second conductive layer 650, and a third conductive layer 660.

[0087] The second conductive layer 650 includes a first non-oxygen absorption layer 651, a first oxygen absorption layer 652, and a second non-oxygen absorption layer 653. The third conductive layer 660 includes a third non-oxygen absorption layer 661, a second oxygen absorption layer 662, and a fourth non-oxygen absorption layer 663. Each of the first oxygen absorption layer 652 and the second oxygen absorption layer 662 can absorb oxygen from the oxide semiconductor layer 640. On the other hand, each of the first non-oxygen absorption layer 651, the second non-oxygen absorption layer 653, the third non-oxygen absorption layer 661, and the fourth non-oxygen absorption layer 663 is a layer that absorbs less oxygen from the oxide semiconductor layer 640 than each of the first oxygen absorption layer 652 and the second oxygen absorption layer 662.

[0088] The materials for the first non-oxygen absorption layer 651, the second non-oxygen absorption layer 653, the third non-oxygen absorption layer 661, and the fourth non-oxygen absorption layer 663 can be, for example, metals such as titanium (Ti), molybdenum (Mo), tantalum (Ta), or tungsten (W), or alloys thereof. The third non-oxygen absorption layer 661 and the fourth non-oxygen absorption layer 663 can protect the first oxygen absorption layer 652 and the second oxygen absorption layer 662 from external influences, respectively. Therefore, if the first oxygen absorption layer 652 and the second oxygen absorption layer 662 are sufficiently stable, the third non-oxygen absorption layer 661 and the fourth non-oxygen absorption layer 663 may not be necessary.

[0089] As shown in Figure 10B, in a plan view, the second conductive layer 650 includes region B on its interior, and the third conductive layer 660 includes region C on its interior. Figure 10A can also be seen as a cross-sectional view taken through regions B and C. The first non-oxygen absorbing layer 651 is not provided within region B. The first non-oxygen absorbing layer 651 is provided around region B. That is, within region B, the first oxygen absorbing layer 652 and the second non-oxygen absorbing layer 653 are stacked in order, while around region B, the first non-oxygen absorbing layer 651, the first oxygen absorbing layer 652, and the second non-oxygen absorbing layer 653 are stacked in order. Similarly, the third non-oxygen absorbing layer 661 is not provided within region C. The third non-oxygen absorbing layer 661 is provided around region C. Specifically, within region C, the second oxygen-absorbing layer 662 and the fourth non-oxygen-absorbing layer 663 are stacked in order, while around region C, the third non-oxygen-absorbing layer 661, the second oxygen-absorbing layer 662, and the fourth non-oxygen-absorbing layer 663 are stacked in order.

[0090] The first oxygen absorption layer 652 covers at least a portion of one end of the oxide semiconductor layer 640 and is in contact with at least a portion of one end of the oxide semiconductor layer 640. As a result, oxygen from the oxide semiconductor layer 640 is absorbed by the first oxygen absorption layer 652, and a first oxygen vacancy region 641 is formed in the oxide semiconductor layer 640. Similarly, the second oxygen absorption layer 662 covers at least a portion of the other end of the oxide semiconductor layer 640 and is in contact with at least a portion of the other end of the oxide semiconductor layer 640. As a result, oxygen from the oxide semiconductor layer 640 is absorbed by the second oxygen absorption layer 662, and a second oxygen vacancy region 642 is formed in the oxide semiconductor layer 640.

[0091] The surface area of ​​the first oxygen-depleted region 641 is larger than the surface area of ​​the portion of the oxide semiconductor layer 640 that is in direct contact with the first oxygen-absorbing layer 652. Therefore, the first non-oxygen-absorbing layer 651 is electrically connected to the oxide semiconductor layer 640 (specifically, the first oxygen-depleted region 641) by ohmic contact. Similarly, the surface area of ​​the second oxygen-depleted region 642 is larger than the surface area of ​​the portion of the oxide semiconductor layer 640 that is in direct contact with the second oxygen-absorbing layer 662. Therefore, the third non-oxygen-absorbing layer 661 is electrically connected to the oxide semiconductor layer 640 (specifically, the second oxygen-depleted region 642) by ohmic contact.

[0092] In the semiconductor device 60, one layer of the stacked second conductive layer 650 is used as the first oxygen absorption layer 652, forming a first oxygen vacancy region 641 in the oxide semiconductor layer 640. Similarly, one layer of the stacked third conductive layer 660 is used as the second oxygen absorption layer 662, forming a second oxygen vacancy region 642 in the oxide semiconductor layer 640. The second conductive layer 650 and the third conductive layer 660, corresponding to the source and drain electrodes of the transistor, are electrically connected to the oxygen vacancy region in the oxide semiconductor layer 640 by ohmic contact. As a result, the interface between the oxide semiconductor layer 640 and the second conductive layer 650 (more specifically, the first non-oxygen absorption layer 651) and the interface between the oxide semiconductor layer 540 and the third conductive layer 660 (more specifically, the third non-oxygen absorption layer 661) are stabilized. Consequently, the reliability of the semiconductor device 60 is improved. In particular, the negative bias temperature instability of the semiconductor device 60 is improved.

[0093] <Fifth Embodiment> The semiconductor devices according to the first to fourth embodiments can be applied to display devices such as liquid crystal displays, organic light-emitting diode (OLED) displays, or micro-LED displays. Here, with reference to Figures 11 to 13, a display device 1000 to which the semiconductor device 10 is applied will be described. The display device 1000 is an OLED display device, but the display devices to which the semiconductor device 10 is applied are not limited to this.

[0094] Figure 11 is a schematic diagram showing the configuration of a display device according to one embodiment of the present invention. The display device 1000 has a display unit 1020, a drive circuit unit 1030, and a terminal unit 1040 provided on a substrate 1010. The drive circuit unit 1030 is provided around the display unit 1020 and can control the display unit 1020. The drive circuit unit 1030 includes, for example, a scanning drive circuit. The terminal unit 1040 is provided at the end of the substrate 1010 and can supply signals or power to the display device 1000. The terminal unit 1040 includes, for example, a terminal 1041. The terminal 1041 is connected to a flexible printed circuit board 1050. A driver IC 1060 may be provided on the flexible printed circuit board 1050.

[0095] The substrate 1010 may include a bend portion 1011. The substrate 1010 can be bent at the position of the bend portion 1011. The bend portion 1011 can be provided, for example, between the display portion 1020 and the terminal portion 1040. By bending the terminal portion 1040 at the bend portion 1011 so that it overlaps with the back surface of the display portion 1020, the bezel of the display device 1000 can be narrowed.

[0096] The display unit 1020 can display an image or video and includes a plurality of pixels 1021 arranged in a matrix. However, the arrangement of the plurality of pixels 1021 is not limited to a matrix. The plurality of pixels 1021 can also be arranged, for example, in a staggered pattern.

[0097] Figure 12 is a circuit diagram (pixel circuit) of a pixel 1021 of a display device 1000 according to one embodiment of the present invention. The pixel circuit includes a first transistor 100-1, a second transistor 100-2, a capacitive element 1230, and a light-emitting element 1240.

[0098] The first transistor 100-1 can function as a selection transistor; that is, the conduction state of the first transistor 100-1 is controlled by the scan line 1110. In the first transistor 100-1, the gate, source, and drain are electrically connected to the scan line 1110, the signal line 1120, and the gate of the second transistor 100-2, respectively.

[0099] The second transistor 100-2 can function as a drive transistor. That is, the second transistor 100-2 controls the luminescence brightness of the light-emitting element 1240. In the second transistor 100-2, the gate, source, and drain are electrically connected to the source of the first transistor 100-1, the drive power line 1140, and the anode of the light-emitting element 1240, respectively.

[0100] One of the capacitive electrodes of the capacitive element 1230 is electrically connected to the gate of the second transistor 100-2 and the drain of the first transistor 100-1. The other of the capacitive electrode is electrically connected to the anode of the light-emitting element 1240 and the drain of the second transistor 100-2.

[0101] The anode of the light-emitting element 1240 is connected to the drain of the second transistor 100-2. The cathode of the light-emitting element 1240 is connected to the reference power line 1160.

[0102] Figure 13 is a cross-sectional view of a pixel 1021 of a display device 1000 according to one embodiment of the present invention. Specifically, Figure 13 is a cross-sectional view of the display device 1000 shown in Figure 11, cut along the line A1-A2. As shown in Figure 13, the transistor 100 and connection portion 200 of the semiconductor device 10 are provided on the substrate 1010.

[0103] A planarization layer 1250 is provided on the semiconductor device 10. For example, an organic material such as photosensitive acrylic or polyimide can be used as the material for the planarization layer 1250. By providing the planarization layer 1250, the steps between the transistor 100 and the connection portion 200 can be flattened.

[0104] An anode 1241 is provided on the planarization layer 1250. The anode 1241 is electrically connected to the transistor 100 through an opening provided in the planarization layer. The anode 1241 may be a transparent conductive film or a metal film. Alternatively, the anode 1241 may be a laminate of a transparent conductive film and a metal film.

[0105] An anode 1241 is provided for each light-emitting element 1240. That is, an anode 1241 is provided for each of the red light-emitting element 1240R, the green light-emitting element 1240G, and the blue light-emitting element 1240B.

[0106] A partition wall 1260 is provided on the anode 1241. The partition wall 1260 covers the end of the anode 1241 and has an opening so that a portion of the surface of the anode 1241 is exposed. In other words, the anodes 1241 of each light-emitting element 1240 are separated by the partition wall 1260. It is preferable that the side surface of the opening of the partition wall 1260 has a gentle tapered shape. If the side surface of the opening of the partition wall 1260 has a steep shape, poor coverage of the organic layer 1242 formed on the anode 1241 will occur. The partition wall 1260 may also be called a bank or rib.

[0107] An organic layer 1242 is provided on the anode 1241 of each light-emitting element 1240, which includes at least a hole transport layer, an emissive layer, and an electron transport layer. The emissive layer of the organic layer 1242 may use different organic materials for each of the red light-emitting element 1240R, green light-emitting element 1240G, and blue light-emitting element 1240B. That is, each of the red light-emitting element 1240R, green light-emitting element 1240G, and blue light-emitting element 1240B may be provided with an organic layer 1242R containing a red emissive material, an organic layer 1242G containing a green emissive material, and an organic layer 1242B containing a blue emissive material. The hole transport layer and electron transport layer of the organic layer 1242 may be provided so as to cover the entire light-emitting element 1240.

[0108] A cathode 1243 is provided on the organic layer 1242. The cathode 1243 may be provided so as to cover the total light-emitting element 1240. The cathode 1243 may be a transparent conductive film or a metal film. The anode 1241 may be a laminate of a transparent conductive film and a metal film.

[0109] A sealing layer 1270 is provided on the cathode 1243. The sealing layer 1270 can be, for example, a laminated structure of a first inorganic insulating layer 1271, an organic insulating layer 1272, and a second inorganic insulating layer 1273.

[0110] As materials for the first inorganic insulating layer 1271 and the second inorganic insulating layer 1273, for example, silicon oxide, aluminum oxide, silicon nitride, aluminum nitride, silicon oxynitride, or aluminum oxynitride can be used. The film thickness of the first inorganic insulating layer 1271 and the second inorganic insulating layer 1273 is, for example, 750 nm or more and 1250 nm or less. The first inorganic insulating layer 1271 or the second inorganic insulating layer 1273 may be a single layer or a laminate. One of the functions of the sealing layer 1270 is to prevent moisture from the outside from entering the organic layer 1242, and the sealing layer 1270 is required to have high gas barrier properties. For this reason, it is preferable that the first inorganic insulating layer 1271 and the second inorganic insulating layer 1273 contain nitrides such as silicon nitride or aluminum nitride. The nitrides should include nitrides containing oxygen.

[0111] For example, acrylic resin, epoxy resin, polyimide resin, silicone resin, fluororesin, or siloxane resin can be used as the material for the organic insulating layer 1272. The film thickness of the organic insulating layer 1272 is, for example, 5 μm to 15 μm.

[0112] A cover glass 1290 is provided on the sealing layer 1270 via an adhesive layer 1280. The display device 1000 may be provided with a polarizing plate or a touch sensor, if necessary.

[0113] In the display device 1000 according to this embodiment, the reliability of the semiconductor device 10 is improved, and as a result, the reliability of the display device 1000 is improved.

[0114] In the above example, the semiconductor device 10 was applied to the light-emitting element 1240, but the semiconductor device 10 can also be applied to the scanning drive circuit.

[0115] The embodiments described above as embodiments of the present invention can be combined and implemented as appropriate, insofar as they do not contradict each other. Furthermore, any additions, deletions, or design changes to components, or additions, omissions, or changes to processes based on these embodiments, made by those skilled in the art, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0116] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0117] 10, 10A, 30, 30A, 50, 50A, 60: Semiconductor device, 100, 300: Transistor, 100-1: First transistor, 100-2: Second transistor, 200, 200A, 400, 400A: Connection part, 110: Substrate, 120: First conductive layer, 130: First insulating layer, 140: Oxide semiconductor layer, 141: First region, 142: Second region, 143: Third region, 151: First impurity region, 152: Second impurity region, 160: Second conductive layer, 170: Third conductive layer, 210: First connecting electrode, 213: Third impurity region, 220: Second connecting electrode, 223: Third impurity region, 310: Substrate, 320: First conductive layer, 330: First insulating layer, 340: Oxide semiconductor layer, 341: First region, 342: Second region, 343: Third region, 351: First impurity region, 352: Second impurity region, 360: Second insulating layer, 370: Second conductive layer, 380: Third conductive layer, 410: First connecting electrode, 413: Third impurity region, 420: Second connecting electrode, 433: Third impurity region, 510: Substrate, 520: First conductive layer, 530: First insulating layer, 540: Oxide semiconductor layer, 541: First oxygen vacancy region, 542: Second oxygen vacancy region, 550, 550A: First oxygen absorption layer, 560, 560A: Second oxygen absorption layer, 570, 570A: Second conductive layer, 580, 580A: Third conductive layer, 610: Substrate, 620: First conductive layer, 630: First insulating layer, 640: Oxide semiconductor layer, 641: First oxygen vacancy region, 642: Second oxygen vacancy region, 650: Second conductive layer, 651: First non-oxygen absorption layer, 652: First oxygen absorption layer, 653: Second non-oxygen absorption layer, 660: Third conductive layer, 661: Third non-oxygen absorption layer, 662: Second oxygen absorption layer, 663: Fourth non-oxygen absorption layer, 800: Resist layer, 810: First opening, 820: Second opening, 830: Third opening, 1000: Display device, 1010: Substrate, 1011: Bent section, 1020: Display section, 1021: Pixel, 1030: Drive circuit section, 1040: Terminal section, 1041: Terminal, 1050: Flexible printed circuit board, 1110: Scan line, 1120: Signal line, 1140: Drive power line,1160: Reference power line, 1230: Capacitive element, 1240: Light-emitting element, 1240B: Blue light-emitting element, 1240G: Green light-emitting element, 1240R: Red light-emitting element, 1241: Anode, 1242, 1242R, 1242G, 1242B: Organic layer, 1243: Cathode, 1250: Planarization layer, 1260: Partition, 1270: Sealing layer, 1271: First inorganic insulating layer, 1272: Organic insulating layer, 1273: Second inorganic insulating layer, 1280: Adhesive layer, 1290: Cover glass

Claims

1. A first conductive layer on the insulating surface, The first insulating layer on the first conductive layer, The oxide semiconductor layer on the first insulating layer, A second conductive layer on the oxide semiconductor layer, The oxide semiconductor layer includes a third conductive layer, The aforementioned oxide semiconductor layer is The first area and, The second region in contact with the second conductive layer, The third region in contact with the third conductive layer, A first impurity region between the first region and the second region that is in contact with the second conductive layer, A second impurity region between the first region and the third region, which is in contact with the third conductive layer, A semiconductor device wherein the electrical conductivity of the first impurity region and the second impurity region is greater than the electrical conductivity of the second region and the third region.

2. A first conductive layer on the insulating surface, The first insulating layer on the first conductive layer, The oxide semiconductor layer on the first insulating layer, The second insulating layer on the oxide semiconductor layer, The second conductive layer on the second insulating layer, The present invention includes a third conductive layer on the second insulating layer, The aforementioned oxide semiconductor layer is The first region in contact with the second insulating layer, A second region that is in contact with the second insulating layer and superimposed on the second conductive layer, A third region that is in contact with the second insulating layer and superimposed on the third conductive layer, A first impurity region between the first region and the second region that is in contact with the second conductive layer, A second impurity region between the first region and the third region, which is in contact with the third conductive layer, A semiconductor device wherein the electrical conductivity of the first impurity region and the second impurity region is greater than the electrical conductivity of the second region and the third region.

3. The semiconductor device according to claim 1 or claim 2, wherein the impurity element contained in each of the first impurity region and the second impurity region is selected from boron, phosphorus, argon, and nitrogen.

4. moreover, A first connecting electrode including a third impurity region on the insulating surface, A semiconductor device according to claim 1 or 2, comprising a second connecting electrode on the first connecting electrode that is in contact with the third impurity region.

5. The semiconductor device according to claim 4, wherein the impurity element contained in each of the first impurity region, the second impurity region, and the third impurity region is one selected from boron, phosphorus, argon, and nitrogen.

6. The concentration of the impurity element in at least one of the first impurity region, the second impurity region, and the third impurity region is 1.0 × 10⁻⁶ １６ atoms / cm ３ The semiconductor device according to claim 5.

7. The semiconductor device according to any one of claims 4 to 6, wherein the first connecting electrode is the same layer as the first conductive layer.

8. The semiconductor device according to any one of claims 4 to 7, wherein the second connecting electrode is the same layer as the second conductive layer and the third conductive layer.

9. A first conductive layer and a first connecting electrode are formed on the insulating surface. A first insulating layer is formed on the first conductive layer and the first connecting electrode. An oxide semiconductor layer is formed on the first insulating layer in superimposition with the first conductive layer. A resist layer is formed that includes a first opening and a second opening superimposed on the oxide semiconductor layer, and a third opening superimposed on the first connecting electrode. Using the resist layer as a mask, impurity elements are added to the oxide semiconductor layer to form a first impurity region corresponding to the first opening and a second impurity region corresponding to the second opening in the oxide semiconductor layer. By etching the first insulating layer using the resist layer as a mask, an opening is formed in the first insulating layer. A second connecting electrode is formed through the opening, which contacts the first connecting electrode. A second conductive layer is formed in contact with the first impurity region. A method for manufacturing a semiconductor device, comprising forming a third conductive layer in contact with the second impurity region.

10. The method for manufacturing a semiconductor device according to claim 9, wherein the addition of the impurity element to the oxide semiconductor layer is performed before etching the first insulating layer.

11. The method for manufacturing a semiconductor device according to claim 9, wherein the addition of the impurity element to the oxide semiconductor layer is performed after etching the first insulating layer.

12. A first conductive layer and a first connecting electrode are formed on the insulating surface. A first insulating layer is formed on the first conductive layer and the first connecting electrode. An oxide semiconductor layer is formed on the first insulating layer in superimposition with the first conductive layer. A second insulating layer is formed on the oxide semiconductor layer and the first insulating layer. A resist layer is formed that includes a first opening and a second opening superimposed on the oxide semiconductor layer, and a third opening superimposed on the first connecting electrode. Using the resist layer as a mask, impurity elements are added to the oxide semiconductor layer to form a first impurity region corresponding to the first opening and a second impurity region corresponding to the second opening in the oxide semiconductor layer. A method for manufacturing a semiconductor device, comprising etching the first insulating layer and the second insulating layer using the resist layer as a mask to form an opening in the first insulating layer and the second insulating layer.

13. The method for manufacturing a semiconductor device according to claim 12, wherein the addition of the impurity element to the oxide semiconductor layer is performed before etching the first insulating layer and the second insulating layer.

14. The method for manufacturing a semiconductor device according to claim 12, wherein the addition of the impurity element to the oxide semiconductor layer is performed after etching the first insulating layer and the second insulating layer.

15. The method for manufacturing a semiconductor device according to claim 9 or claim 12, wherein the impurity element contained in each of the first impurity region and the second impurity region is selected from boron, phosphorus, argon, and nitrogen.

16. A method for manufacturing a semiconductor device according to claim 11 or claim 14, wherein a third impurity region in which the impurity element is added is formed in the first connecting electrode.

17. The method for manufacturing a semiconductor device according to claim 16, wherein the impurity element contained in each of the first impurity region, the second impurity region, and the third impurity region is one selected from boron, phosphorus, argon, and nitrogen.

18. The concentration of the impurity element in at least one of the first impurity region, the second impurity region, and the third impurity region is 1.0 × 10⁻⁶ １６ atoms / cm ３ The above is the method for manufacturing a semiconductor device according to claim 17.

Images