Power conversion device and degradation determination method

Abstract

To detect separation of a bonding part of a bonding wire.SOLUTION: A power conversion device includes a semiconductor element including a first main electrode and a second main electrode, a first terminal electrically connected to the first main electrode, a wire bonded to the second main electrode, a second terminal electrically connected to the second main electrode through the wire, a voltage detection unit that detects an on voltage, which is a voltage in an on state between the first terminal and the second terminal, and an output unit that outputs a predetermined signal when the on voltage detected by the voltage detection unit changes at a predetermined change rate or more by the separation of the wire from the second main electrode.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a power conversion device and a degradation determination method.

Background Art

[0002] In recent years, power conversion devices have been extended to applications that require high reliability (such as power systems, or moving bodies such as trains or automobiles), and along with this, the demand for high reliability of power conversion devices has been increasing. In response to this demand, expectations for realizing predictive maintenance that predicts failures and takes countermeasures in advance have been increasing.

[0003] On the other hand, one of the main failure factors of a power conversion device is a power semiconductor module. It is known that the main failure of a power semiconductor module occurs when the thermal stress stress repeatedly generated by current conduction or switching operation deteriorates the bonding wire and solder. As the deterioration of the bonding wire and solder progresses, the conduction resistance between the main terminals when the power semiconductor module is in the on state (conducting state) increases, so the voltage Von between the main terminals when the power semiconductor module is in the conducting state rises. Therefore, it is said that the deterioration of the power semiconductor module can be detected by detecting the rise in the voltage Von (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the above-mentioned conventional technology, it may be difficult to detect the peeling of the bonding part of the bonding wire.

[0006] This disclosure aims to detect delamination at the joint of a bonding wire. [Means for solving the problem]

[0007] In one aspect of this disclosure, A semiconductor device having a first main electrode and a second main electrode, A first terminal electrically connected to the first main electrode, The wire joined to the second main electrode, A second terminal electrically connected to the second main electrode via the wire, A voltage detection unit that detects the on-voltage, which is the voltage between the first terminal and the second terminal when they are both on, A power conversion device is provided, which includes an output unit that outputs a predetermined signal when the ON voltage detected by the voltage detection unit changes at a rate exceeding a predetermined change rate due to the peeling of the wire from the second main electrode.

[0008] In one aspect of this disclosure, A semiconductor device having a first main electrode and a second main electrode, A first terminal electrically connected to the first main electrode, The wire joined to the second main electrode, A second terminal electrically connected to the second main electrode via the wire, A voltage detection unit that detects the on-voltage, which is the voltage between the first terminal and the second terminal when they are both on, A current detection unit for detecting the current passing through the first terminal and the second terminal, A temperature detection unit for detecting the temperature of the semiconductor element, A power conversion device is provided, comprising: an output unit that outputs a predetermined signal when the difference voltage between the ON voltage detected by the voltage detection unit and a reference voltage corresponding to the current and temperature changes at a predetermined rate or higher due to the peeling of the wire from the second main electrode. [Effects of the Invention]

[0009] According to one aspect of the present disclosure, deterioration of a semiconductor device can be detected.

Brief Description of the Drawings

[0010] [Figure 1] It is a diagram illustrating the relationship between the voltage Von between the main terminals when the power semiconductor module is in the conducting state and the operating time of the power semiconductor module. [Figure 2] It is a diagram showing the result of differentiating the voltage Von shown in FIG. 1. [Figure 3] It is a diagram showing an example of the overall configuration of the power conversion device according to the present embodiment. [Figure 4] It is a diagram showing the configuration of the semiconductor device according to the present embodiment in a top view with respect to the reference line AA in FIG. 5. [Figure 5] It is a diagram showing the cross-sectional configuration of the semiconductor device according to the present embodiment in a side view with respect to the reference line BB in FIG. 4. [Figure 6] It is a diagram showing the configuration of the semiconductor device according to the present embodiment in a top view. [Figure 7] It is a diagram illustrating waveforms of respective parts accompanying the detection operation of the voltage Vce_on1. [Figure 8] It is a diagram showing a first configuration example of a functional block for detecting aluminum wire lift-off. [Figure 9] It is a diagram showing a second configuration example of a functional block for detecting aluminum wire lift-off. [Figure 10] It is a diagram showing a third configuration example of a functional block for detecting aluminum wire lift-off. [Figure 11] It is a diagram showing a fourth configuration example of a functional block for detecting aluminum wire lift-off and other deterioration.

Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments will be described.

[0012] FIG. 1 is a diagram illustrating the relationship between the voltage Von between the main terminals when the power semiconductor module is in the conduction state and the operating time of the power semiconductor module. The power semiconductor module includes a power semiconductor chip (hereinafter referred to as a chip), an aluminum wire portion and a solder portion for connecting the chip to the outside. As a main degradation mode of the power semiconductor module, it is known that thermal stress occurs in the chip, the aluminum wire portion and the solder portion due to repeated conduction / cutoff operations of the chip, and the aluminum wire portion and the solder portion deteriorate.

[0013] The behavior during degradation will be described. First, cracks in the solder portion gradually increase, and the thermal resistance of the solder portion gradually increases. As the thermal resistance gradually increases, the chip temperature gradually rises. As a result, the voltage Von between the main terminals in the conduction state of the power semiconductor module gradually increases due to the influence of the chip temperature characteristics (see FIG. 1). Due to the increase in the chip temperature, the degradation of the aluminum wire portion is further accelerated. When the degradation of the aluminum wire has progressed to a certain extent, peeling of the ultrasonic bonding portion between the chip and the aluminum wire (aluminum wire lift-off) occurs, and the voltage Von increases steeply with a minute increase amount (see FIG. 1). Thus, the change over time of the voltage Von includes a gradual voltage increase due to solder degradation or the like and a minute and steep voltage increase associated with aluminum wire lift-off. Therefore, by detecting a minute and steep change in the voltage Von, it becomes possible to detect aluminum wire lift-off. The steep increase in the voltage Von (two voltage increases) associated with aluminum lift-off shown in FIG. 1 shows the case where two of the plurality of aluminum wires are lifted off in sequence.

[0014] FIG. 2 is a diagram showing the result of differentiating the voltage Von shown in FIG. 1. By differentiating the voltage Von, the steep voltage increase associated with aluminum wire lift-off is emphasized. Therefore, even if the change amount of the voltage Von associated with aluminum lift-off is minute, a predetermined detection means can detect aluminum wire lift-off with high accuracy by comparing the differential value of the voltage Von with a predetermined threshold value.

[0015] Next, we will describe more specific embodiments.

[0016] Figure 3 is a diagram showing an example of the overall configuration of the power conversion device according to this embodiment. The power conversion device 101 shown in Figure 3 comprises a main circuit unit 10 that converts DC power supplied from a DC power supply unit 33 into AC power supplied to a load 4, and a control unit 20 that controls the power conversion operation of the main circuit unit 10. Figure 3 illustrates a configuration in which the main circuit unit 10 converts DC power into three-phase AC power.

[0017] In the example shown in Figure 1, the main circuit section 10 includes a plurality of power semiconductor modules 111 to 116, a plurality of gate drive units 121 to 126, and a current detection unit 30. The power semiconductor modules 111 to 116 are examples of semiconductor devices.

[0018] Figure 3 illustrates an IGBT module in a 1-in-1 package, which incorporates an IGBT chip for one arm of an inverter and a diode chip (FWD chip) connected in antiparallel to it, as an example of a power semiconductor module. IGBT is an abbreviation for Insulated Gate Bipolar Transistor, an IGBT chip is an example of a power semiconductor element, and an FWD chip is an example of a rectifier element. However, the package configuration of the power semiconductor module may be other types of package configurations such as 6-in-1, and the power semiconductor elements configured in the power semiconductor module may be other types of power semiconductor elements such as MOSFETs. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. Furthermore, the multiple power semiconductor modules 111 to 116 each have the same configuration, and the multiple gate drive units 121 to 126 each have the same configuration. Therefore, for convenience, the upper arm of the u-phase will be used as an example in the following explanation.

[0019] In the example shown in Figure 3, the power semiconductor module 111 of the u-phase upper arm has an IGBT chip Q1 and an FWD chip D1. The power semiconductor module 111 also has a first main terminal C1, a second main terminal E1, a gate terminal SG1, and an emitter terminal SE1. The first main terminal C1 is an example of a first terminal, the second main terminal E1 is an example of a second terminal, and the gate terminal SG1 is an example of a control terminal.

[0020] The IGBT chip Q1 is an example of a switching element (semiconductor element) having a collector electrode 111c, an emitter electrode 111e, and a gate electrode 111g. The collector electrode 111c is an example of a first main electrode, the emitter electrode 111e is an example of a second main electrode, and the gate electrode 111g is an example of a control electrode.

[0021] The FWD chip D1 is an example of a rectifier element (semiconductor element) having an anode electrode 111a and a cathode electrode 111k.

[0022] The first main terminal C1 is electrically connected to the collector electrode 111c and the cathode electrode 111k via at least one connecting member (e.g., bonding wire, solder, etc.). The second main terminal E1 is electrically connected to the emitter electrode 111e and the anode electrode 111a via at least one connecting member. The gate terminal SG1 is electrically connected to the gate electrode 111g via at least one connecting member. The emitter terminal SE1 is electrically connected to the emitter electrode 111e and the anode electrode 111a via at least one connecting member.

[0023] The gate drive unit 121 is a drive circuit that includes a pre-driver PD1 and a voltage detection circuit Vce1.

[0024] The pre-driver PD1 is a circuit that drives the gate electrode 111g of the IGBT chip Q1 in response to an on or off switching command S1 supplied from the control unit 20.

[0025] The voltage detection circuit Vce1 detects the voltage Vce_on1 between the main terminals when the IGBT chip Q1 or FWD chip D1 of the power semiconductor module 111 is ON, and transmits it to the control unit 20. The main terminals refer to the space between the first main terminal C1 and the second main terminal C2.

[0026] The current detection unit 30 is a current sensor that detects the three-phase alternating currents iu, iv, and iw flowing between the power semiconductor modules 111 to 116 and the load 4 and transmits them to the control unit 20.

[0027] The control unit 20 is a control device that includes, for example, a processor such as a CPU (Central Processing Unit) and memory. The functions of the control unit 20 are realized by the processor operating according to a program stored in memory. The functions of the control unit 20 may also be realized by an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

[0028] The main circuit unit 10 may also include a heat sink temperature detection unit 80. The heat sink temperature detection unit 80 is a temperature sensor that detects the temperature of a heat sink (e.g., fins, etc.) for cooling the power semiconductor modules 111 to 116 and transmits the detected heat sink temperature Th to the control unit 20.

[0029] Figures 4 and 5 show the configuration of the semiconductor device 100 according to this embodiment. The semiconductor device 100 is an example of a power semiconductor module 111.

[0030] Figure 4 shows the configuration in a top view with respect to reference line AA in Figure 5, and Figure 5 shows the cross-sectional configuration in a side view with respect to reference line BB in Figure 4. The semiconductor device 100 protects the joint between the electrodes and wires of the semiconductor elements mounted thereon using a resin layer. This ensures the reliability of the semiconductor device 100. The semiconductor device 100 also protects the guard ring of the semiconductor elements using a resin layer. This improves the voltage resistance of the semiconductor device 100. The semiconductor device 100 comprises a case 1, a cover 2, an insulating substrate 3, terminals 5, 6 and 7, semiconductor elements 11 and 12, wires 15, 16 and 17, resin layers 21 and 22, and a gel filler 23.

[0031] Case 1 is a housing that accommodates the components of the semiconductor device 100, and its bottom portion is a base substrate 1a. The base substrate 1a supports the components of the semiconductor device 100 on it. The base substrate 1a can be made of a copper (Cu) substrate, an aluminum silicon carbide (Al-SiC) substrate, or the like, which have high heat dissipation properties. Alternatively, the base substrate 1a that constitutes the bottom portion of Case 1 and the frame that constitutes the sides may be formed separately, and Case 1 may be formed by erecting the frame on the periphery of the base substrate 1a.

[0032] The cover 2 is a flat lid that rests on the side of the case 1 and encloses the components of the semiconductor device 100 within the case 1. The cover 2 has multiple openings 2a formed therein to allow the upper ends of terminals 5, 6 and 7 to protrude outside the case 1.

[0033] The insulating substrate 3 is a substrate on which semiconductor elements 11 and 12 are mounted, and can be, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Blazing) substrate. The insulating substrate 3 includes an insulating board 3a, a metal layer 3b, and a wiring layer 3c. The insulating board 3a is a plate-shaped member made of insulating ceramics such as aluminum nitride, silicon nitride, or aluminum oxide, with a thickness of, for example, 0.2 to 1 mm. The metal layer 3b is made of a conductive metal such as copper or aluminum, and is provided on the lower surface of the insulating board 3a with a film thickness of, for example, 0.1 to 1 mm. For purposes such as rust prevention, the surface of the metal layer 3b may be plated with nickel or the like. The wiring layer 3c is made of a conductive metal such as copper or aluminum, similar to the metal layer 3b, and is provided on the upper surface of the insulating board 3a. The insulating substrate 3 is fixed onto the base substrate 1a via a bonding material such as solder (not shown).

[0034] The wiring layer 3c of the insulating substrate 3 has three wiring patterns 3c1, 3c2, and 3c3. Wiring pattern 3c1 is rectangular and is arranged in the area of ​​approximately two-thirds of the left side of the insulating board 3a as shown in the drawing. Semiconductor elements 11 and 12, which will be described later, are arranged side by side on wiring pattern 3c1. Wiring patterns 3c2 and 3c3 are rectangular and are arranged side by side in the area of ​​approximately one-third of the right side of the insulating board 3a as shown in the drawing.

[0035] Terminals 5, 6, and 7 are input / output terminals for inputting external signals to the semiconductor element 11 or inputting / outputting current from the semiconductor element 11 to the outside. Terminals 5, 6, and 7 are formed into cylindrical or flat shapes using a conductive metal such as copper or aluminum. Two terminals 5 are erected near the left end of the wiring pattern 3c1 of the wiring layer 3c. Terminals 5 are electrically connected to the collector electrode of the semiconductor element 11 and the cathode electrode of the semiconductor element 12, which will be described later, via the wiring pattern 3c1. Two terminals 6 are erected on the wiring pattern 3c2 of the wiring layer 3c. Terminals 6 are electrically connected to the emitter electrode 11a of the semiconductor element 11 and the anode electrode 12a of the semiconductor element 12 via the wiring pattern 3c2 and wires 15 and 16. One terminal 7 is erected on the wiring pattern 3c3 of the wiring layer 3c. Terminal 7 is electrically connected to the gate electrode 11b of the semiconductor element 11 via the wiring pattern 3c3 and wire 17. Terminals 5, 6, and 7 are erected on the wiring pattern using a bonding material such as solder (not shown), with their respective tips protruding outside the case 1 through the opening 2a of the cover 2. Terminals 5, 6, and 7 may also be pre-insert molded into the case 1 or cover 2.

[0036] The semiconductor element 11 is a Si semiconductor element or SiC semiconductor element incorporated into the semiconductor device 100 of this embodiment. For example, a vertical power metal oxide semiconductor field-effect transistor (power MOSFET) or an insulated gate bipolar transistor (IGBT) having electrodes on both the front and back surfaces can be used. Note that the semiconductor element 11 is not limited to a vertical element, but may also be a horizontal element with electrodes provided only on the front surface. In the case of an IGBT (or power MOSFET), the semiconductor element 11 has an emitter electrode (or source electrode) 11a and a gate electrode 11b on the front surface, as well as a guard ring 11c around these electrodes or on the edge of the front surface, and a collector electrode (or drain electrode (not shown)) on the back surface. The semiconductor element 11 is fixed on the insulating substrate 3 on its back surface by connecting the collector electrode (or drain electrode) to the wiring pattern 3c1 of the wiring layer 3c with a bonding material (not shown) such as solder.

[0037] The semiconductor element 12 is a Si semiconductor diode or a SiC semiconductor diode incorporated into the semiconductor device 100 of this embodiment. As an example, a PN junction diode or a Schottky barrier diode (SBD) connected in antiparallel to the semiconductor element 11 can be used. The semiconductor element 12 has an anode electrode 12a on its surface and a guard ring 12b around it or on the edge of the surface, and a cathode electrode (not shown) on its back surface. The semiconductor element 12 is fixed on the insulating substrate 3 on its back surface by connecting the cathode electrode to the wiring pattern 3c1 of the wiring layer 3c with a bonding material (not shown) such as solder. The cathode electrode of the semiconductor element 12 is connected to the collector electrode of the semiconductor element 11 by the wiring pattern 3c1 of the wiring layer 3c.

[0038] Wires 15, 16, and 17 are wire-shaped members that connect the surface electrodes of semiconductor elements 11 and 12, or connect their surface electrodes to wiring patterns 3c1 and 3c2. Wires 15, 16, and 17 are formed with a diameter of 300 to 500 μm using conductive metals such as copper and aluminum, or conductive alloys such as iron-aluminum alloy. Wire 15 includes a plurality of wires (four in this embodiment as an example), and both ends are connected to the surface electrode of semiconductor element 11, i.e., the emitter electrode 11a, and the surface electrode of semiconductor element 12, i.e., the anode electrode 12a. Wire 16 includes a plurality of wires (four in this embodiment as an example), and connects the surface electrode of semiconductor element 11, i.e., the emitter electrode 11a, to wiring pattern 3c2. Wire 17 includes one wire (may include multiple wires), and connects the surface electrode of semiconductor element 11, i.e., the gate electrode 11b, to wiring pattern 3c3. Wires 15 and 16 are integrally formed by stitch bonding at the electrodes of the semiconductor element 11, and the wiring pattern 3c3 may be wired from the surface electrodes of the semiconductor element 12 using continuous wires.

[0039] The resin layers 21 and 22 are components that cover the surfaces of the semiconductor elements 11 and 12, respectively, to protect the joints of the wires 15, 16, and 17, as well as the guard rings 11c and 12b. The resin layers 21 and 22 contain polyimides such as polyimide resin (glass transition temperature Tg of 324°C) and polyamide-imide resin (glass transition temperature Tg of 275°C).

[0040] The resin layer 21 integrally includes the first and second resin layers 21a and 21b. The first resin layer 21a is provided on the periphery of the surface of the semiconductor element 11 and covers the guard ring 11c of the semiconductor element 11. The second resin layer 21b is provided in the center of the surface of the semiconductor element 11 and covers the joints of wires 15 and 16 with the emitter electrode 11a and the joint of wire 17 with the gate electrode 11b. Note that the resin layer 21 may also include the first and second resin layers 21a and 21b as separate components.

[0041] The resin layer 22 integrally includes the first and second resin layers 22a and 22b. The first resin layer 22a is provided on the periphery of the surface of the semiconductor element 12 and covers the guard ring 12b of the semiconductor element 12. The second resin layer 22b is provided in the center of the surface of the semiconductor element 12 and covers the junction of the wire 15 with the anode electrode 12a. The resin layer 22 may also include the first and second resin layers 22a and 22b as separate components.

[0042] Furthermore, the resin layers 21 and 22 may be integrally provided on both surfaces of the semiconductor elements 11 and 12, including at least a portion of the surface of the wiring pattern 3c1. This can also mitigate the electric field strength generated on the sides of the semiconductor elements 11 and 12. Here, the entire wire 15 may be covered by the resin layers 21 and 22. Alternatively, resin layers may be provided at the joints of the wire 16 with the wiring pattern 3c2 and the wire 17 with the wiring pattern 3c3 of the wiring layer 3c, thereby covering the wiring patterns 3c2 and 3c3. In this case, the resin layers 21 and 22 may be integrally provided on both surfaces of the semiconductor elements 11 and 12, including at least a portion of the surfaces of the wiring patterns 3c1, 3c2, and 3c3. Here, the entire wires 15, 16, and 17 may be covered by the resin layers 21 and 22. By covering the entire wire, deformation of the wire due to vibration, etc., can be prevented, the load generated at the wire joints can be reduced, and reliability can be further improved.

[0043] The gel filler 23 is a component for sealing each component of the semiconductor device 100, and as an example, silicone gel can be used. The gel filler 23 is filled on top of the insulating substrate 3, semiconductor elements 11 and 12, terminals 5, 6 and 7, wires 15, 16 and 17, and resin layers 21 and 22, which are arranged inside the case 1 (on the base substrate 1a). Furthermore, by placing the cover 2 on the side of the case 1, each component is sealed inside the case 1. Note that the remaining portions of the wires 15, 16 and 17, excluding the joints covered by the resin layers 21 and 22, are exposed in the gel filler 23.

[0044] Figure 6 is a top view diagram showing the configuration of the semiconductor device 102 according to this embodiment. The semiconductor device 102 has a configuration that combines a u-phase upper arm power semiconductor module 111 and a u-phase lower arm power semiconductor module 112.

[0045] The IGBT chip Q1 is an example of a switching element (semiconductor element) having a collector electrode 111c formed on its back surface and an emitter electrode 111e and a gate electrode (not shown) formed on its front surface. The collector electrode 111c is electrically connected to the wiring layer 141 via a bonding material 131 such as solder. The wiring layer 141 is conductively connected to the first main terminal C1. Each of the multiple wires 151 has one end connected to the emitter electrode 111e and the other end connected to the wiring layer 142. The wiring layer 142 is conductively connected to the second main terminal E1.

[0046] The FWD chip D1 is an example of a rectifier element (semiconductor element) having an anode electrode 111a formed on its surface and a cathode electrode 111k formed on its back surface. The cathode electrode 111k is electrically connected to the wiring layer 141 via a bonding material 132 such as solder. Each of the multiple wires 152 has one end connected to the anode electrode 111a and the other end connected to the wiring layer 142.

[0047] The IGBT chip Q2 is an example of a switching element (semiconductor element) having a collector electrode 112c formed on its back surface and an emitter electrode 112e and a gate electrode (not shown) formed on its front surface. The collector electrode 112c is electrically connected to the wiring layer 142 via a bonding material 133 such as solder. The wiring layer 142 is conductively connected to the first main terminal C2, which is shared with the second main terminal E1. Each of the multiple wires 153 has one end connected to the emitter electrode 112e and the other end connected to the wiring layer 143. The wiring layer 143 is conductively connected to the second main terminal E2.

[0048] The FWD chip D2 is an example of a rectifier element (semiconductor element) having a cathode electrode 112k formed on its surface and an anode electrode 112a formed on its back surface. The cathode electrode 112k is electrically connected to the wiring layer 142 via a bonding material 134 such as solder. Each of the multiple wires 154 has one end connected to the anode electrode 112a and the other end connected to the wiring layer 143.

[0049] Next, we will describe an example of a method for detecting the voltage Vce_on1 between the main terminals when the IGBT chip or the FWD chip connected in antiparallel to it is ON.

[0050] Figure 7 illustrates the waveforms of each part during the detection operation of voltage Vce_on1. In the example shown, iu is a sinusoidal current, and the U-phase voltage command is a sinusoidal voltage. The on and off states of the upper and lower arms of the U-phase are determined by the relative magnitudes of the U-phase voltage command and the carrier wave. In the example shown, the control unit 20 outputs a switching command S1 that turns Q1 on and turns Q2 off during periods when the U-phase voltage command is greater than the carrier wave. On the other hand, the control unit 20 outputs a switching command S1 that turns Q1 off and turns Q2 on during periods when the U-phase voltage command is less than the carrier wave.

[0051] When Q1 is on and iu is positive, the same current as iu flows through Q1. When Q2 is off and iu is negative, the same current as iu flows through D1. The voltage Vce1_on when Q1 or D1 is conducting is determined depending on these currents and the respective chip temperatures of Q1 or D1. The voltage Vce1_on is transmitted as a discrete value from the voltage detection circuit Vce1 to the control unit 20. In the example shown in the figure, the sampling timing for Vce1_on is at each bottom of the carrier wave. The control unit 20 samples the detected value of the current iu detected by the current detection unit 30 at each bottom of the carrier wave and obtains it from the current detection unit 30.

[0052] However, the method for detecting the voltage Vce_on1 between the main terminals when the IGBT chip or the FWD chip connected in antiparallel to it is ON is not limited to this.

[0053] Figure 8 shows a first example configuration of a functional block for detecting aluminum wire lift-off. The functional block for detecting aluminum wire lift-off on the IGBT side and the functional block for detecting aluminum wire lift-off on the FWD side may have the same configuration, although various setting constants such as the judgment threshold differ. These functional blocks are implemented, for example, by the control unit 20.

[0054] The sample timing generation unit 41 generates a timing for sampling the detected value of the voltage Vce_on1 according to the timing at which the current iu detected by the current detection unit 30 passes through a predetermined current value Ith. The current value Ith may be the current value that minimizes the temperature dependence of the voltage Vce1_on between the main terminals of the power semiconductor module's conduction state. Alternatively, since the change in Vce1_on due to temperature changes is slower than the change in Vce1_on due to current or aluminum wire lift-off, and its derivative is relatively small, the current value Ith may be any other current value. The current value Ith may be set to different values ​​on the IGBT chip side and the FWD chip side.

[0055] Vce1_on is sampled and held by the sample-and-hold unit 42 at the timing generated by the sample timing generation unit 41. The sample-and-hold value Vce1_on_s obtained by the sample-and-hold unit 42 is differentiated by the differentiator 43. The fault prediction determination unit 44 compares the differentiated value Vce1_on_s' obtained by the differentiator 43 with a determination threshold and outputs a lift-off detection signal according to the relationship between the differentiated value Vce1_on_s' and the determination threshold. The differentiated value Vce1_on_s' is an example of the amount of change in on-voltage per unit time and represents the rate of change of on-voltage. The determination threshold is an example of a predetermined rate of change.

[0056] For example, IGBT lift-off (for example, one end of the wire and Emitter When delamination occurs at the junction with the electrode, the differential value Vce1_on_s' becomes a positive value. Therefore, when "Vce1_on_s'">"the IGBT side judgment threshold (positive value)" is reached, a lift-off detection signal indicating that lift-off on the IGBT side has been detected is output from the fault prediction unit 44.

[0057] On the other hand, if lift-off occurs on the FWD chip side (for example, separation of the junction between one end of the wire and the anode electrode), the differential value Vce1_on_s' becomes a negative value. Therefore, when "Vce1_on_s'" < "FWD side judgment threshold (negative value)", a lift-off detection signal indicating that lift-off on the FWD side has been detected is output from the fault prediction unit 44.

[0058] These judgment thresholds may be set individually for each module type, as they differ depending on the number of parallel aluminum wires, etc.

[0059] The lift-off detection signal is input to the latch circuit 45. The latch circuit 45, triggered by the input of the lift-off detection signal, outputs a determination value indicating that there is a precursor to a failure due to lift-off in the semiconductor module.

[0060] When the control unit 20 receives a determination value from the latch circuit 45 indicating that there is a fault indication, it notifies external devices and users of the power converter 101 that there is a fault indication due to lift-off of the IGBT chip Q1 or the FWD chip D1 which is inversely parallel to it. The control unit 20 may notify that there is a fault indication of the power semiconductor module 111 on which the IGBT chip Q1 is mounted, or of the main circuit section 10 on which the power semiconductor module 111 is mounted, or of the power converter 101 on which the main circuit section 10 is mounted. Notification of a fault indication makes it possible to take maintenance measures before a failure occurs on the IGBT chip Q1 side or the FWD chip D1 side.

[0061] Thus, the power converter 101 includes a voltage detection circuit Vce1 and a control unit 20 (a circuit unit that performs the detection operation shown in Figure 7) as an example of a voltage detection unit that detects the on-voltage, which is the voltage between the first and second terminals when they are in the ON state. The power converter 101 also includes a control unit 20 as an example of an output unit that outputs a predetermined signal when the on-voltage detected by the voltage detection unit changes at a predetermined rate of change or higher. Therefore, the control unit 20 can detect (determine) the occurrence of delamination (lift-off) of the bonding wire joint on the IGBT chip side or the FWD chip side which is in antiparallel to it, by executing the degradation determination method described above.

[0062] Figure 9 shows a second example configuration of a functional block for detecting aluminum wire lift-off. The functional block for detecting aluminum wire lift-off on the IGBT side and the functional block for detecting aluminum wire lift-off on the FWD side may have the same configuration, although various setting constants such as the judgment threshold differ. These functional blocks are implemented, for example, by the control unit 20.

[0063] The current-temperature correction unit 51 (hereinafter also referred to as "correction unit 51") calculates the initial voltage Vce1_on_ini between the main terminals in the conductive state of the module in its initial state before degradation occurs. The correction unit 51 includes a power semiconductor temperature calculation unit 52 (hereinafter also referred to as "temperature calculation unit 52") and a Vce1_on storage unit 53 (hereinafter also referred to as "storage unit 53").

[0064] First, the temperature calculation unit 52 estimates the temperature Tj of the IGBT chip or FWD chip based on the detected temperature Th of the heat sink, the detected U-phase current iu, and other operating conditions. A known method may be used for estimating the temperature. The storage unit 53 stores in advance the correspondence between temperature Tj, current iu, and initial voltage Vce1_on_ini. The initial voltage Vce1_on_ini is an example of a reference voltage and represents the initial value of the voltage Vce1_on before degradation. The correction unit 51 derives the initial voltage Vce1_on_ini corresponding to the estimated temperature Tj and the detected or commanded value of U-phase current iu based on the correspondence defined in the storage unit 53. The correction unit 51 is an example of a reference voltage derivation unit.

[0065] The subtractor 54 calculates the change in the voltage Vce1_on between the main terminals when the module is conducting due to the progression of degradation, ΔVce1_on, by taking the difference between Vce1_on and Vce1_on_ini. The change ΔVce1_on is an example of a differential voltage.

[0066] The change ΔVce1_on is differentiated by the differentiator 55. The fault prediction unit 56 compares the derivative value ΔVce1_on_s' obtained by the differentiator 55 with a determination threshold and outputs a lift-off detection signal according to the relationship between the derivative value ΔVce1_on_s' and the determination threshold. The derivative value ΔVce1_on_s' is an example of the amount of change in differential voltage per unit time and represents the rate of change of differential voltage. The determination threshold is an example of a predetermined rate of change.

[0067] For example, if a lift-off occurs on the IGBT chip side (e.g., separation of the junction between one end of the wire and the collector electrode), ΔVce1_on' will be a positive value. Therefore, when "ΔVce1_on_s'">"IGBT side judgment threshold (positive value)" is reached, a lift-off detection signal indicating that a lift-off on the IGBT side has been detected is output from the fault prediction unit 56.

[0068] On the other hand, if lift-off occurs on the FWD chip side (for example, separation of the junction between one end of the wire and the anode electrode), ΔVce1_on' becomes a negative value. Therefore, when "ΔVce1_on_s'" < "FWD side judgment threshold (negative value)", a lift-off detection signal indicating that lift-off on the FWD side has been detected is output from the fault prediction unit 56.

[0069] These judgment thresholds may be set individually for each module type, as they differ depending on the number of parallel aluminum wires, etc.

[0070] The lift-off detection signal is input to the latch circuit 57. The latch circuit 57, triggered by the input of the lift-off detection signal, outputs a determination value indicating that there is a precursor to a failure due to lift-off in the semiconductor module.

[0071] Therefore, as shown in Figure 9, similar to the case in Figure 8, notification of a potential failure allows maintenance measures to be taken before a failure occurs on either the IGBT chip Q1 or the FWD chip D1. Furthermore, by executing the degradation determination method described above, the control unit 20 can detect (determine) the occurrence of delamination (lift-off) of the bonding wire joint on either the IGBT chip or the FWD chip connected in antiparallel to it. In addition, since the conditions for determining the sampling timing of the current iu (for example, the current value Ith mentioned above) are not fixed, potential failures are repeatedly determined at relatively narrow timing intervals. As a result, changes in chip temperature are small, preventing false detections.

[0072] Figure 10 shows a third example configuration of a functional block for detecting aluminum wire lift-off. The functional block for detecting aluminum wire lift-off on the IGBT side and the functional block for detecting aluminum wire lift-off on the FWD side may have the same configuration, although various setting constants such as the judgment threshold differ. These functional blocks are implemented, for example, by the control unit 20.

[0073] The sample timing generation unit 66 and the sample and hold unit 65 have the same functions as the sample timing generation unit 41 and the sample and hold unit 42 shown in Figure 8.

[0074] The current-temperature correction unit 61 (hereinafter also referred to as "correction unit 61") calculates the initial voltage Vce1_on_ini between the main terminals in the conductive state of the module in its initial state before degradation occurs. The correction unit 61 includes a power semiconductor temperature calculation unit 62 (hereinafter also referred to as "temperature calculation unit 62"), a Vce1_on storage unit 63 (hereinafter also referred to as "storage unit 63"), and a sample-and-hold unit 64.

[0075] First, the temperature calculation unit 62 estimates the temperature Tj of the IGBT chip or FWD chip based on the detected temperature Th of the heat sink, the detected U-phase current iu, and other operating conditions. A known method may be used for estimating the temperature. The storage unit 63 stores in advance the correspondence between the temperature Tj and the initial voltage Vce1_on_ini. The initial voltage Vce1_on_ini is an example of a reference voltage and represents the initial value of the voltage Vce1_on before degradation. The correction unit 61 derives the initial voltage Vce1_on_ini corresponding to the estimated temperature Tj based on the correspondence defined in the storage unit 63. The correction unit 61 is an example of a reference voltage derivation unit. Vce1_on_ini is sampled and held by the sample and hold unit 64 at the timing generated by the sample timing generation unit 66.

[0076] The subtractor 54 takes the difference between Vce1_on, which is sampled and held by the sample-and-hold unit 65, and Vce1_on_ini, which is sampled and held by the sample-and-hold unit 64. This allows the subtractor 54 to calculate the change in the voltage Vce1_on between the main terminals in the module's conductive state due to the progression of degradation, ΔVce1_on. The change ΔVce1_on is an example of a differential voltage. The subsequent processing is the same as in Figure 9, so its explanation is omitted.

[0077] Therefore, as shown in Figure 10, similar to the cases in Figures 8 and 9, notification of a potential failure allows maintenance measures to be taken before a failure occurs on either the IGBT chip Q1 or the FWD chip D1. Furthermore, by executing the degradation determination method described above, the control unit 20 can detect (determine) the occurrence of delamination (lift-off) of the bonding wire joint on either the IGBT chip or the FWD chip connected in antiparallel to it. Also, in Figure 10, each time iu passes through a predetermined current value Ith, the output value of the storage unit 63 (initial voltage Vce1_on_ini) and the detected value of Vce1_on are sampled and held. As a result, while current dependence was required for the storage unit 53 in Figure 9, current dependence is not required for the storage unit 63 in Figure 10, which has the advantage of reducing the storage capacity of the initial voltage Vce1_on_ini in the storage unit.

[0078] Figure 11 shows a fourth example configuration of a functional block for detecting aluminum wire lift-off and other deterioration. The functional block for detecting aluminum wire lift on the IGBT side and the functional block for detecting aluminum wire lift-off on the FWD side may have the same configuration, although various setting constants such as the judgment threshold differ. These functional blocks are implemented, for example, by the control unit 20.

[0079] The control unit 20 includes a lift-off detection block 71, a bonding material deterioration detection block 72, and a logical OR gate 73.

[0080] The lift-off detection block 71 detects (determines) the occurrence of delamination (lift-off) at the bonding wire joint on the IGBT chip side or the FWD chip side which is antiparallel to it. The lift-off detection block 71 may have any of the configurations shown in Figures 8 to 10 above, or any other configuration.

[0081] The bonding material degradation detection block 72 detects (determines) the degradation of bonding materials such as solder between the chip and the insulating substrate (for example, the bonding materials 131 to 134 mentioned above). The bonding material degradation detection block 72 has a current-temperature correction unit 74 and a fault prediction determination unit 77. The current-temperature correction unit 74 has a power semiconductor temperature calculation unit 75 and a Vce1_on storage unit 76. The bonding material degradation detection block 72 has the configuration of Figure 9, excluding the differentiator 55 and the latch circuit 57.

[0082] The lift-off detection block 71 can detect wire lift-off, but it cannot detect other signs of failure, such as the gradual increase in Vce1_on due to increased thermal resistance caused by the deterioration of bonding materials such as solder. By passing the judgment values ​​of the lift-off detection block 71 and the bonding material deterioration detection block 72 through the OR gate 73, it becomes possible to detect both signs of failure. In other words, the control unit 20 can detect both the gradual change in Von due to the deterioration of bonding materials such as solder, and the minute and sharp change in Von due to wire lift-off.

[0083] Although embodiments have been described above, the present invention is not limited to the embodiments described above. Various modifications and improvements are possible, such as combinations or substitutions with some or all of the other embodiments.

[0084] For example, the semiconductor element is not limited to power transistors such as IGBTs, but can also be a diode, thyristor, gate turn-off thyristor, triac, etc.

[0085] Alternatively, the temperature detection unit may directly measure the temperature of the semiconductor element. [Explanation of symbols]

[0086] 1 case 1a Base board 2 Covers 2a opening 3. Insulating substrate 3a Insulating board 3b metal layer 3c wiring layer 3c1, 3c2, 3c3 wiring patterns 4 load Terminals 5, 6, 7… 10 Main circuit section 11 Semiconductor devices 11a Emitter electrode 11b Guard gate 11c Guard Ring 12 Semiconductor devices 12a Anode electrode 12b Guard Ring 15, 16, 17 wires 20 Control Unit 21(21a,21b) Resin layer (1st resin layer, 2nd resin layer) 22(22a,22b) Resin layer (first resin layer, second resin layer) 23 Gel Filler 30 Current detection unit 33 DC power supply section 80 Heat sink temperature detection unit 101 Power converter 100,102 Semiconductor equipment 111-116 Power semiconductor modules 121-126 Gate drive unit 131~134 Bonding material 141~143 Wiring layer 151-154 Wire

Claims

1. A semiconductor device having a first main electrode and a second main electrode, A first terminal electrically connected to the first main electrode, The wire joined to the second main electrode, A second terminal electrically connected to the second main electrode via the wire, A voltage detection unit that detects the on-voltage, which is the voltage between the first terminal and the second terminal when they are both on, The system includes an output unit that outputs a predetermined signal when the ON voltage detected by the voltage detection unit changes at a predetermined rate or higher due to the peeling of the wire from the second main electrode, The semiconductor element includes a switching element and a diode connected in antiparallel to the switching element. The output unit is, When the ON voltage detected by the voltage detection unit changes at a predetermined first rate of change or higher while current is flowing from the first terminal to the second terminal due to the wire being detached from the second main electrode of the switching element, a predetermined signal is output. A power conversion device that outputs a predetermined signal when the ON voltage detected by the voltage detection unit changes at a predetermined second rate of change or higher while current is flowing from the second terminal to the first terminal due to the wire being detached from the second main electrode of the diode.

2. A current detection unit for detecting the current passing through the first terminal and the second terminal, The system includes a sample-and-hold unit that samples and holds the ON voltage detected by the voltage detection unit in accordance with the timing at which the current detected by the current detection unit passes a predetermined current value, The power conversion device according to claim 1, wherein the output unit outputs a predetermined signal when the on-voltage sampled and held by the sample-and-hold unit changes at a predetermined rate of change or higher.

3. A first semiconductor element having a first main electrode and a second main electrode, A second semiconductor element having a third main electrode and a fourth main electrode, A first terminal electrically connected to the first main electrode and the third main electrode, A first wire, with both ends joined to the second main electrode and the fourth main electrode, The second wire joined to the second main electrode, A second terminal electrically connected to the second main electrode via the second wire, A voltage detection unit that detects the on-voltage, which is the voltage between the first terminal and the second terminal when they are both on, The system includes an output unit that outputs a predetermined signal when the ON voltage detected by the voltage detection unit changes at a predetermined rate or higher due to the peeling of the first wire or the second wire, The output unit is, When the ON voltage detected by the voltage detection unit changes at a rate exceeding a predetermined change rate while current is flowing from the first terminal to the second terminal due to the stripping of the second wire, a predetermined signal is output. When the ON voltage detected by the voltage detection unit changes at a rate exceeding a predetermined change rate while current is flowing from the second terminal to the first terminal due to the stripping of the first wire or the second wire, a predetermined signal is output. A power conversion device.

4. A semiconductor device having a first main electrode and a second main electrode, A first terminal electrically connected to the first main electrode, The wire joined to the second main electrode, A second terminal electrically connected to the second main electrode via the wire, A voltage detection unit that detects the on-voltage, which is the voltage between the first terminal and the second terminal when they are both on, A current detection unit for detecting the current passing through the first terminal and the second terminal, A temperature detection unit for detecting the temperature of the semiconductor element, A power conversion device comprising: an output unit that outputs a predetermined signal when the difference voltage between the ON voltage detected by the voltage detection unit and a reference voltage corresponding to the current and temperature changes at a rate of change or higher than a predetermined rate due to the peeling of the wire from the second main electrode.

5. The system includes a reference voltage derivation unit that derives the reference voltage corresponding to the current detected by the current detection unit and the temperature detected by the temperature detection unit, based on the correspondence between the current, the temperature, and the reference voltage. The power conversion device according to claim 4, wherein the differential voltage is the difference between the ON voltage detected by the voltage detection unit and the reference voltage derived by the reference voltage derivation unit.

6. A reference voltage derivation unit derives the reference voltage corresponding to the temperature detected by the current detection unit based on the correspondence between the temperature and the reference voltage, The system includes a sample-and-hold unit that samples and holds the ON voltage detected by the voltage detection unit and the reference voltage derived by the reference voltage derivation unit, in accordance with the timing at which the current detected by the current detection unit passes a predetermined current value. The power conversion device according to claim 4, wherein the differential voltage is the difference between the ON voltage sampled and held by the sample-and-hold unit and the reference voltage sampled and held by the sample-and-hold unit.

7. A method for determining the degradation of a semiconductor device having a semiconductor element having a first main electrode and a second main electrode, a first terminal electrically connected to the first main electrode, a wire joined to the second main electrode, and a second terminal electrically connected to the second main electrode via the wire, The semiconductor element includes a switching element and a diode connected in antiparallel to the switching element. The voltage detection unit detects the on-voltage, which is the voltage between the first terminal and the second terminal when they are both on. The output section is, When the ON voltage detected by the voltage detection unit changes at a predetermined first rate of change or higher while current is flowing from the first terminal to the second terminal due to the wire being detached from the second main electrode of the switching element, a predetermined signal is output. A degradation determination method comprising outputting a predetermined signal when the ON voltage detected by the voltage detection unit changes at a predetermined second rate of change or more while current is flowing from the second terminal to the first terminal due to the peeling of the wire from the second main electrode of the diode, thereby reducing the ON voltage.

8. A method for determining the degradation of a semiconductor device having a semiconductor element having a first main electrode and a second main electrode, a first terminal electrically connected to the first main electrode, a wire joined to the second main electrode, and a second terminal electrically connected to the second main electrode via the wire, The voltage detection unit detects the on-voltage, which is the voltage between the first terminal and the second terminal when they are both on. The current detection unit detects the current passing through the first terminal and the second terminal, The temperature detection unit detects the temperature of the semiconductor element, The output unit outputs a predetermined signal when the difference voltage between the ON voltage detected by the voltage detection unit and the reference voltage corresponding to the current and temperature changes at a predetermined rate or higher due to the peeling of the wire from the second main electrode.

9. A first semiconductor element having a first main electrode and a second main electrode, A second semiconductor element having a third main electrode and a fourth main electrode, A third semiconductor element having a fifth main electrode and a sixth main electrode, A fourth semiconductor element having a seventh main electrode and an eighth main electrode, A first terminal electrically connected to the first main electrode and the third main electrode, A first wire having one end joined to the second main electrode and the other end electrically connected to the fifth main electrode and the seventh main electrode, A second wire having one end joined to the fourth main electrode and the other end electrically connected to the fifth main electrode and the seventh main electrode, A second terminal is electrically connected to the second main electrode via the first wire and to the fourth main electrode via the second wire, The third wire joined to the sixth main electrode, The fourth wire joined to the eighth main electrode, A third terminal electrically connected to the sixth main electrode via the third wire and electrically connected to the eighth main electrode via the fourth wire, A voltage detection unit that detects a first on-voltage, which is the voltage between the first and second terminals when they are both on, and a second on-voltage, which is the voltage between the second and third terminals when they are both on. The device comprises an output unit that outputs a predetermined signal when the first ON voltage detected by the voltage detection unit changes at a predetermined rate of change or more due to the peeling of the first wire or the second wire, and an output unit that outputs a predetermined signal when the second ON voltage detected by the voltage detection unit changes at a predetermined rate of change or more due to the peeling of the third wire or the fourth wire, The output unit is, When the first ON voltage detected by the voltage detection unit changes at a rate exceeding a predetermined change rate while current is flowing from the first terminal to the second terminal due to the stripping of the first wire, a predetermined signal is output. When the first ON voltage detected by the voltage detection unit changes at a rate exceeding a predetermined change rate while current is flowing from the second terminal to the first terminal due to the stripping of the second wire, a predetermined signal is output. When the second ON voltage detected by the voltage detection unit changes at a rate exceeding a predetermined change rate while current is flowing from the second terminal to the third terminal due to the stripping of the third wire, a predetermined signal is output. A power converter that outputs a predetermined signal when the second ON voltage detected by the voltage detection unit changes at a predetermined rate or higher while current is flowing from the third terminal to the second terminal due to the stripping of the fourth wire.

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