Quantum devices

Abstract

To provide a quantum device that can prevent a wiring board from deforming or the like to improve reliability of a connection between wiring boards.SOLUTION: A quantum device comprises: a plurality of first connection parts that electrically connect a plurality of wires of a wiring layer of a quantum chip to a plurality of wires of a first wiring layer on a first surface of a first wiring board arranged to oppose the wiring layer of the quantum chip; and a plurality of second connection parts that electrically connect a plurality of wires of a second wiring layer on a second surface of the first wiring board to a plurality of wires of a third wiring layer on the first surface of a second wiring board arranged to oppose the second surface of the first wiring board, the quantum device which has one or a plurality of second connection parts arranged at positions corresponding to one or the plurality of first connection parts on the first surface arranged at the first row from an end of the first wiring board and arranged closer to an end side than the positions of the first connection parts arranged at the first row, of the plurality of second connection parts arranged at the first row from the end of the first wiring board.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a quantum device equipped with a superconducting circuit.

Background Art

[0002] A quantum chip equipped with a superconducting circuit such as a superconducting qubit or a coupler is formed on a silicon substrate, for example, by a semiconductor microfabrication process. In order to reduce the pitch of the connection terminals (electrodes) of the quantum chip and to make the wiring finer, the quantum chip is connected to a first wiring substrate (interposer) that performs pitch conversion and wiring routing.

[0003] As the number of connection terminals of the quantum chip increases due to an increase in the number of qubits, etc., in the first wiring substrate (interposer), the connection terminals on the opposite surface of the quantum chip are connected to the connection terminals on the opposite surface via through vias, and signals are transmitted and received from the connection terminals on the opposite surface. The first wiring substrate (interposer) has wiring formed on a silicon substrate, for example, similar to the substrate of the quantum chip. The quantum chip is flip-chip mounted on the first wiring substrate (interposer) with the circuit surface on which the qubits are formed facing down.

[0004] In order to prevent deterioration of the transmission characteristics of the qubits, etc., the first wiring substrate (interposer) needs to have a dielectric other than silicon disposed on the first surface facing the circuit surface of the quantum chip, or to avoid exposure of materials other than superconductors. For this reason, the wiring accommodation rate of the first wiring substrate (interposer) cannot be increased.

[0005] In order to increase the wiring accommodation rate, a configuration in which, for example, a plurality of wiring substrates are stacked is used. That is, the connection terminals on the opposite surface of the quantum chip of the first wiring substrate (interposer) are directly connected to the connection terminals on the opposite surface of the first wiring substrate of the second wiring substrate (also called a package substrate), and connections to the outside, etc., are made from the connection terminals on the second surface opposite to the first surface of the second wiring substrate facing the first wiring substrate. The second wiring substrate uses, for example, a resin-based multilayer substrate, etc.

[0006] In a 3D package consisting of multiple wiring boards including a quantum chip and an interposer, deformation such as warping of the boards, as the thickness of the interposer and other boards decreases, impairs connection reliability. Board warping is also caused by thermal stress resulting from differences in the thermal expansion coefficient (linear expansion coefficient) of the materials when subjected to thermal history.

[0007] Underfill is used to increase the mounting strength of wiring boards on which semiconductor chips are flip-chip mounted. Underfill material (epoxy resin, urethane resin, silicone resin, polyester resin, acrylic resin, etc.) is filled into the gaps between the semiconductor chip and the first wiring board (interposer), and between the first wiring board (interposer) and the second wiring board to relieve stress (see, for example, Patent Document 1). However, it is known that the circuit characteristics deteriorate in the few to tens of GHz (Gigahertz) band, for example, due to the influence of the underfill material, which is an insulating adhesive material used to fix and seal the second wiring board and the first wiring board (interposer). Furthermore, as mentioned above, underfill material is not used in superconducting quantum circuits because it is necessary to avoid characteristic degradation (loss) due to dielectrics. In addition, underfill material is not used in terms of thermal shrinkage because it causes warping, stress, and strain. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] International Publication No. 2020 / 122014 [Overview of the Initiative] [Problems that the invention aims to solve]

[0009] In a three-dimensional quantum device package consisting of multiple wiring boards including a quantum chip and an interposer, deformation such as warping of the substrates, as the thickness of the interposer and other substrates decreases, impairs connection reliability.

[0010] However, underfill is not used in quantum devices. Therefore, new measures (structures, design methods) are needed to suppress deformation such as warping of the substrate due to thermal shrinkage in quantum devices with 3D packaging.

[0011] This disclosure aims to provide a quantum device that suppresses deformation of wiring boards and improves the reliability of connections between wiring boards. [Means for solving the problem]

[0012] According to this disclosure, a quantum device includes a quantum chip having a wiring layer of a superconducting circuit on a first surface of the substrate, a first substrate, a plurality of wirings of a first wiring layer formed on a first surface of the first substrate, a second wiring layer formed on a second surface of the first substrate opposite to the first surface, and a plurality of through vias that penetrate the first substrate and electrically connect the plurality of wirings of the first wiring layer and the plurality of wirings of the second wiring layer, A second wiring substrate comprising a second substrate and a third wiring layer formed on the first surface of the second substrate, A plurality of first connection parts that provide electrical connections between a plurality of wirings in the wiring layer of the quantum chip and a plurality of wirings in the first wiring layer on the first surface of the first wiring substrate, which is arranged opposite to the first surface of the quantum chip, The device comprises a plurality of second connection portions that make electrical connections between a plurality of wirings in the second wiring layer on the second surface of the first wiring board and a plurality of wirings in the third wiring layer on the first surface of the second wiring board, which is positioned opposite the second surface of the first wiring board. The first wiring board has one or more of the second connection portions, which are arranged in a first row when viewed from the edge of the first board, and which are located at positions corresponding to one or more of the first connection portions on the first surface arranged in a first row when viewed from the edge of the first board, and which are located further towards the edge than the positions of the first connection portions arranged in the first row. [Effects of the Invention]

[0013] According to the present disclosure, a quantum device can be provided that suppresses deformation of a wiring board and improves connection reliability between wiring boards.

Brief Description of the Drawings

[0014] [Figure 1] It is a perspective view schematically illustrating an embodiment. [Figure 2] It is a side end face view schematically illustrating an embodiment. [Figure 3] (A) and (B) are plan views schematically illustrating an embodiment. [Figure 4] (A) to (C) are plan views schematically illustrating a modification of FIG. 3. [Figure 5] (A) is a schematic cross-sectional view of a first wiring board of an embodiment, and (B) and (C) are diagrams for explaining the first wiring board. [Figure 6] It is a cross-sectional view schematically illustrating a second wiring board of an embodiment. [Figure 7] (A) and (B) are comparative examples, and (C) is a diagram schematically illustrating an embodiment.

Modes for Carrying Out the Invention

[0015] Embodiments of the present disclosure will be described. FIG. 1 is a diagram illustrating a quantum device 1 of an embodiment. As shown in FIG. 1, the quantum device 1 includes a quantum chip 10, a first wiring board (interposer) 20, and a second wiring board 30.

[0016] The quantum chip 10 has a wiring layer (not shown) in which a superconducting quantum circuit is formed on a first surface (circuit surface) of a substrate 11. The quantum chip 10 is flip-chip mounted on the first wiring board 20 with the first surface facing down. Although not particularly limited, as the superconducting quantum circuit, for example, it includes a quantum bit (for example, a Josephson parametric oscillator) using a Josephson junction.

[0017] The wiring on the first surface (circuit surface) of the substrate 11 of the quantum chip 10 and the wiring of the wiring layer on the surface of the first wiring substrate 20 facing the quantum chip 10 are directly connected (bonded) at the first connection portion 41. The first connection portion 41 is preferably composed of protruding electrodes (metal bumps).

[0018] The substrate 21 of the first wiring substrate 20 is preferably made of the same material as the substrate 11 of the quantum chip 10 in consideration of the linear expansion rate and the like.

[0019] For example, when the substrate 11 of the quantum chip 10 is a silicon substrate, the substrate 21 of the first wiring substrate 20 is preferably made of silicon. In this case, the first wiring substrate 20 is also called a silicon interposer. The wiring layer 12 of the substrate 11 of the quantum chip 10 is manufactured by a semiconductor process (semiconductor microfabrication process). The wiring layer of the first wiring substrate 20 (silicon interposer) may also be manufactured by a semiconductor process. In this case, through vias (Through Silicon Vias: TSVs) that connect the wiring layer (first wiring layer) on the surface of the first wiring substrate 20 facing the quantum chip 10 and the second wiring layer on the side opposite to the first wiring layer through the substrate 11 are also manufactured by a semiconductor process.

[0020] The first connection portion (protruding electrode) 41 may be manufactured by a semiconductor process (metal film deposition and patterning). The first connection portion (protruding electrode) 41 may be configured, for example, by coating the surface of a normal conductor such as copper (Cu) or an insulator (such as SiO2, silicon nitride film, silicon oxynitride film, etc.) with a superconducting film.

[0021] The second wiring substrate 30 is directly connected to the wiring on the back surface of the first wiring substrate 20 (the second surface on the side opposite to the first surface facing the quantum chip 10) at the second connection portion 42. The second connection portion 42 is preferably composed of protruding electrodes (metal bumps).

[0022] The second wiring board 30 is preferably larger in size (area) and thickness than the first wiring board 20 for purposes such as pitch conversion and wiring routing, but is not limited to this. The second wiring board 30 may be made of a multilayer silicon interposer, a resin-based multilayer substrate, a ceramic substrate, a tape substrate, etc., in which insulating layers and conductive layers are alternately formed on both sides of a core material. The second wiring board 30 is also referred to as a package substrate or an interposer (second interposer). The second surface of the second wiring board 30 opposite to the first surface facing the first wiring board 20 may be provided with connection terminals that connect to the wiring on the first surface via through vias or the like.

[0023] According to this embodiment, in the first wiring board 20, on the side opposite to the side (second side) facing the quantum chip 10 (first side), there are one or more second connection parts (protruding electrodes) 42 among a plurality of second connection parts (protruding electrodes) 42 arranged in the first row when viewed from the edge of the board 21, which are positioned at a location corresponding to one or more first connection parts (protruding electrodes) 41 arranged in the first row when viewed from the edge of the board 21, and which are positioned further towards the edge of the board 21 than the position of the first connection parts (protruding electrodes) 41 arranged in the first row. It should be noted that the plurality of second connection parts (protruding electrodes) 42 in the first row when viewed from the edge of the board 21 are not limited to a configuration in which they are aligned on the same line along the X-axis and Y-axis directions in Figure 1 on the second side of the board 21, and of course also include a group of second connection parts (protruding electrodes) 42 that are not arranged on the same line but are each positioned as the first (closest to the edge) when viewed from the edge of the board 21. The same applies to the first connection portion (protruding electrode) 41, which is located in the first row when viewed from the edge of the substrate 21.

[0024] As shown in Figure 1, there is no sealing material (insulating adhesive member) such as underfill material between the quantum chip 10 and the first wiring board 20, and between the first wiring board 20 and the second wiring board 30. Inside the vacuum-evacuated refrigerator, the gap between the quantum chip 10 and the first wiring board 20, and the gap between the first wiring board 20 and the second wiring board 30 are evacuated.

[0025] Note that in Figure 1, for the sake of drawing convenience, the height of the first connection portion (protruding electrode) 41 is shown as being greater than the thickness of the quantum chip 10 and the first wiring board 20. However, the thickness of the quantum chip 10 (silicon chip) and the first wiring board 20 (silicon interposer) is, for example, about 30 to several hundred μm (micrometers) (30 μm or more), and the height of the first connection portion (protruding electrode) 41 is, for example, about 1 to several tens of μm (1 μm or more).

[0026] Furthermore, although Figure 1 shows that one first wiring board 20 is mounted on the second wiring board 30, it is of course possible to mount multiple first wiring boards 20 on a single second wiring board 30.

[0027] Figure 2 is a schematic side view of the quantum device 1 of Figure 1 as seen from the x-axis direction. The wiring layer 12 of the substrate 11 of the quantum chip 10 is made of a superconducting material. Niobium (Nb) is used as the superconducting material. However, it is not limited to niobium (Nb), but may also be niobium nitride such as niobium nitride, aluminum (Al), indium (In), lead (Pb), tin (Sn), rhenium (Re), palladium (Pd), titanium (Ti), tantalum (Ta), tantalum nitride, or alloys containing at least one of these. The first connection part 41 and the second connection part 42 are made of protruding electrodes (metal bumps), and are therefore referred to as the first protruding electrode 41 and the second protruding electrode 42, respectively, below.

[0028] On the first surface of the substrate 11 of the quantum chip 10, the wiring layer 12 may contain nonlinear elements such as Josephson junctions for superconducting quantum circuits and inductors (L) for LC resonant circuits, for example, formed on the wiring layer 12.

[0029] In the first wiring substrate 20, the first wiring layer 22 on the first surface facing the first surface (wiring layer 12) of the quantum chip 10 may be made of a superconducting material. Alternatively, a part of the superconducting quantum circuit of the quantum chip 10 may be formed on the first wiring layer 22 of the first wiring substrate 20. For example, the capacitor (C) of the LC resonant circuit of the superconducting quantum circuit may be composed of a first electrode formed on the wiring layer 12 of the quantum chip 10 and a second electrode formed on the first wiring layer 22 of the first wiring substrate 20 facing the first electrode.

[0030] The first protruding electrode 41 may be fabricated on the first wiring layer 22 during the manufacturing of the first wiring substrate 20. In this case, the first protruding electrode 41 may be joined to the pads (connection terminals) of the wiring layer 12 of the quantum chip 10 by direct bonding by surface activation, ultrasonic bonding, or soldering (superconducting solder) bonding. Alternatively, it may be joined by thermocompression bonding or the like. Preferably, the joining of the first protruding electrode 41 is performed before the joining of the second protruding electrode 42.

[0031] Alternatively, the first protruding electrode 41 may be fabricated on the wiring layer 12 during the manufacturing of the quantum chip 10. In this case, the first protruding electrode 41 may be directly bonded to the pad of the first wiring layer 22 of the first wiring substrate 20 by surface activation, ultrasonic bonding, or solder (superconducting solder) bonding. Alternatively, bonding by thermocompression bonding or the like may be used.

[0032] The diameter (crimping diameter) of the first protruding electrode 41 may be several μm to several tens of μm, for example, 5 μm to 10 μm. The distance between the centers of the first protruding electrodes 41 (bump pitch) is also set to be approximately the same as or greater than the diameter of the first protruding electrode 41.

[0033] The second wiring layer 23 on the second surface of the first wiring board 20 facing the second wiring board 30 is connected to the first protruding electrode 41 by through vias (not shown). In Figure 2, the second wiring layer 23 is shown as a wiring layer extending from one end of the substrate 21 to the other, but the second wiring layer 23 consists of via pads (circular or rectangular planar shapes) of through vias (not shown). The second wiring layer 23 may be made of a superconducting material or a normal conducting material. For example, it may be configured with gold (Au), platinum (Pt), palladium (Pd), etc., deposited on its surface.

[0034] The second wiring board 30 may be made of a multilayer substrate. The third wiring layer 32 of the second wiring board 30 facing the first wiring board 20 may be made of a normal conductive material. The diameter of the second protruding electrode 42 is, for example, about 50 μm to 100 μm. The second protruding electrode 42 may be formed on the second wiring layer 23 of the first wiring board 20. In this case, the second protruding electrode 42 is joined to the wiring pads of the third wiring layer 32 of the second wiring board 30 by, for example, surface activation, ultrasound, soldering, or crimping.

[0035] The fourth wiring layer 33 of the second wiring board 30 may be made of a normal conductive material. The fourth wiring layer 33 may have signal wiring (e.g., readout lines and control lines) that is led out to the outside of the refrigerator and connected to a measuring device installed in the room temperature section (e.g., a readout circuit or a current control circuit that supplies current to generate magnetic flux passing through a SQUID (superconducting quantum interference device) loop such as a qubit).

[0036] On the substrate 21 of the first wiring board 20, for one or more second protruding electrodes 42 arranged in the first row (first) when viewed from the edge of the second surface on which the second wiring layer 23 is formed, one or more second protruding electrodes 42 are provided that are arranged in correspondence with one or more first protruding electrodes 41 arranged in the first row (first) when viewed from the edge of the first surface on which the first wiring layer 22 is formed, and are located further towards the edge than the first protruding electrodes 41.

[0037] Figure 3(A) is a schematic plan view of the first wiring layer 22 of the first wiring board 20 of Figure 2, as seen from above. Figure 3(A) shows area bumps on the entire surface of the quantum chip 10, which is mounted using a flip-chip method, where the first protruding electrodes 41 are formed. The first protruding electrodes 41 connected to the peripheral pads of the quantum chip 10 are schematically shown on the first wiring layer 22 of the first wiring board 20. The second protruding electrodes 42 on the second wiring layer 23, which are located on the outer periphery of the first protruding electrodes 41, are shown as dashed circles (gray inside). Other second protruding electrodes 42, which are not shown, are located inward of the first protruding electrodes 41. The arrangement patterns of the first protruding electrodes 41 inside the peripheral area are arbitrary and are therefore omitted in Figure 3(A).

[0038] Figure 3(B) illustrates the positional relationship between the first protruding electrode 41 and the second protruding electrode 42, schematically showing the positional relationship between the first protruding electrode 41 and the second protruding electrode 42 at the lower left corner of the first wiring layer 22 in Figure 3(A). As shown in Figure 3(B), the distance d1 between the outermost position of the second protruding electrode 42 and the first protruding electrode 41 (the distance when the second protruding electrode 42 is projected onto the same plane as the first protruding electrode 41) is set to, for example, 0.2 times or more the distance d2 between the center position of the first protruding electrode 41 and the outermost position of the first protruding electrode 41 (d1>=0.2×d2). In the example in Figure 3(B), the first protruding electrode 41 is cylindrical (with a circular cross-section), and d2 is the radius of the first protruding electrode 41. Preferably, d1 >= (1 / 3) × d2, or d1 >= 0.4 × d2 may be used.

[0039] On the substrate 21 of the first wiring board 20, a plurality of second protruding electrodes 42 arranged in the first row when viewed from each of the four sides (edges) of the second surface on which the second wiring layer 23 is formed are located further to the edge (outside) than a plurality of first protruding electrodes 41 arranged in the first row when viewed from each of the four sides (edges) of the first surface on which the first wiring layer 22 is formed. With this configuration, by positioning the first connection portion 41 within the deformation suppression region defined by the second connection portion 42 that connects the first wiring board 20 and the second wiring board 30, deformation such as warping of the first wiring board 20 that occurs when cooling to extremely low temperatures can be suppressed. In a configuration where there is no underfill material between the quantum chip 10 and the first wiring board 20, and between the first wiring board 20 and the second wiring board, deformation of the first wiring board 20 is suppressed, preventing breakage of each connection point, and improving the connection reliability between the first and second wiring boards 20 and 30.

[0040] Figure 4 shows a modified example of the arrangement of the second protruding electrode 42 in Figure 3. In the example of Figure 4(A), on the substrate 21 of the first wiring board 20, the second protruding electrode 42A, which is positioned first when viewed from the edge of each corner of the second surface on which the second wiring layer 23 is formed, is located further towards the edge of the corner than the first protruding electrode 41, which is positioned first when viewed from the edge of each corner of the first surface on which the first wiring layer 22 is formed.

[0041] In the example shown in Figure 4(B), on the substrate 21 of the first wiring board 20, each second protruding electrode 42A, which is positioned first when viewed from the edge of each of the four corners of the second surface on which the second wiring layer 23 is formed, and each of at least one second protruding electrode 42B, 42C adjacent to the second protruding electrode 42A, are located further towards the edge than each first protruding electrode 41, which is positioned first when viewed from the edge of each of the four corners of the first surface on which the first wiring layer 22 is formed, and each of at least one first protruding electrode 41 adjacent to the second protruding electrode 42A.

[0042] In the example shown in Figure 4(C), on the substrate 21 of the first wiring board 20, each second protruding electrode 42A positioned first when viewed from the edge of each of the four corners of the second surface on which the second wiring layer 23 is formed, and each second protruding electrode 42D, 42E, 42F in the center of the side between two corners, are located further towards the edges than each first protruding electrode 41 positioned first when viewed from the edge of each of the four corners of the first surface on which the first wiring layer 22 is formed, and the first protruding electrode 41 in the center of the side between two corners.

[0043] At each corner, the length of the multiple second protruding electrodes 42 located closer to the end than the first protruding electrode 41, i.e., (diameter of the second protruding electrode 42 + pitch of the second protruding electrode 42) × (number of second protruding electrodes 42), may be set to be approximately 1 / 3 or less, or approximately 1 / 5 or less, of the length of the second protruding electrodes 42 arranged on one side.

[0044] Furthermore, the length of the multiple second protruding electrodes 42 located in the center of each side that are positioned closer to the edge than the first protruding electrode 41, and therefore (diameter of the second protruding electrode 42 + pitch of the second protruding electrode 42) × (number of second protruding electrodes 42), may be set to be approximately 1 / 3 or less, or approximately 1 / 5 or less, of the length of the second protruding electrodes 42 arranged on one side.

[0045] Figure 5(A) is a schematic diagram showing a cross-section of the first wiring board 20 of Figure 2. The wiring (pads) of the first wiring layer 22 on the first surface of the first wiring board 20 and the wiring (pads) of the second wiring layer 23 on the second surface are connected by through vias 24 formed in the substrate 21.

[0046] A through-silicon via 24 is also called a TSV (through-silicon via) that penetrates the silicon die (silicon wafer) when the substrate 21 is a silicon substrate. A through-silicon via 24 is formed by drilling a hole in the wafer and embedding a conductive material to form a through-electrode. The conductive material embedded in the inner wall of the hole of the through-silicon via 24 may be a superconducting material or a normal conducting material (Cu, Ni, Au, Pt, etc.). The through-silicon via 24 may be formed on the first surface (front) of the wafer before the formation of the first wiring layer 22 (via-first), or it may be formed from the first or second surface (back) of the wafer after the formation of the first wiring layer 22 (via-last).

[0047] In Figure 5(A), the substrate 2 The areas indicated by the dashed circles on both sides of 1 are on the circuit board. 2 On the first surface of 1, exposure other than the superconducting material (substrate) 2 This represents a substrate configuration that avoids exposure of the first surface of 1 as much as possible. In other words, the wiring pattern of the first wiring layer 22 is configured to cover the edge of the substrate 21. 2 On the first surface of 1, the wiring pattern of the first wiring layer 22 has a ground pattern (plane) arranged so as to surround both sides of the signal line waveguide, and the substrate 2 The first surface of 1 is not exposed over a wide area.

[0048] Furthermore, in order to reduce warping of the substrate 21, the first and second surfaces are provided with the same number of wiring layers (first and second wiring layers 22 and 23). If warping can be controlled by the layout and thickness of the wiring layers, the wiring layers 23 on the second wiring substrate side may consist of multiple layers.

[0049] In the example shown in Figure 5(A), the second wiring layer 23 on the first wiring board 20 includes via pads for through-vias 24, i.e., pad electrodes (connection terminals) directly beneath the through-vias 24.

[0050] With respect to the second connection portion (second protruding electrode) 42 located on the outermost periphery, for example as shown in Figure 5(B), the second connection portion (second protruding electrode) 42a located on the outermost periphery of the second connection portions 42 that connect to the wiring of the wiring layer 31 of the second wiring board 30 on the first wiring board 20 may be positioned offset outward from the position of the first connection portion (first protruding electrode) 41a connected via the through via 24a. In this case, the shape of the via pad 23a (wiring) directly below the through via 24a may be a shape that extends outward from the center of the through via 24a, and the positional relationship of the first and second connection portions (first and second protruding electrodes) 41 and 42 may be as shown in Figure 3(B). Alternatively, the second connection portion (second projection electrode) 42a located on the outermost periphery may be positioned inward relative to the second connection portion (second projection electrode) 42a located on the outermost periphery, such that the first connection portion (first projection electrode) 41a, which is located in the center of the via pad 23a of the through via 24a and connected via the through via 24a, is positioned inward.

[0051] In addition, if the first wiring board 20 is configured to connect to the wiring of the wiring layer 31 of the second wiring board 30, and the second connection part (second protruding electrode) 42 which connects to the connection part (first protruding electrode) 41 on the first surface via the through via 24 is connected directly below the through via 24, the signal connection will be made over the shortest distance. However, it is of course not limited to this configuration. For example, as shown in Figure 5(C), on the second surface of the substrate 21 of the first wiring board 20, the via pad 23b of the through via 24b located inward from the edge of the substrate 21 may be routed by wiring to the pad electrode (connection terminal) 23c at the outermost position spaced apart from the placement position of the through via 24b, and the second connection part (second protruding electrode) 42b located at the outermost position of the second connection part (second protruding electrode) 42 which connects to the wiring of the wiring layer 31 of the second wiring board 30 may be joined to the pad electrode 23c. In this case, the second connection portion (second protruding electrode) 42b is located outside the first connection portion (first protruding electrode) 41a, which is located on the outermost periphery. Note that the wiring and pad electrodes may be created by pattern formation, such as in the process of forming the through vias 24 from the second surface of the substrate 21.

[0052] Figure 6 is a schematic diagram showing a cross-section of the second wiring board 30 of Figure 2. As shown in Figure 6, the second wiring board 30 is a 6-layer multilayer board in which conductors 324, insulating layer 313, conductor 322, insulating layer 312, and third wiring layer 32 are stacked on the first surface of the core material 311, the third wiring layer 32 and conductor 322 are connected by via 321, and conductors 322 and conductor 324 are connected by via 323. On the second surface of the core material 311 opposite to the first surface, conductor 334, insulating layer 314, conductor 332, insulating layer 315, and fourth wiring layer 33 are stacked, the conductor of the fourth wiring layer 33 and conductor 332 are connected by via 331, conductor 332 and conductor 334 are connected by via 333, and conductors 324 and 334 are connected by through via 316 that penetrates the core material 311. The core material 311 is made of a silicon substrate to match the linear thermal expansion coefficient of the substrate 11 of the quantum chip 10 and the substrate 21 of the first wiring board 20. In this case, the through-vias 316 are made of TSVs. Furthermore, the wiring layer / insulating layer configuration on both sides of the core material 311 is the same to suppress substrate warping. The built-up conductor may be, for example, copper (Cu) or aluminum, and the insulating layer may be made of silicon oxide, silicon nitride, silicon oxynitride, polyimide resin, acrylic resin, epoxy resin, fluororesin (PolyTetraFluoroEtylene: PTFE), etc.

[0053] Figure 7 is a diagram illustrating a comparative example and an embodiment. Figure 7(A) is a diagram illustrating the configuration of a comparative example. Looking at the first protruding electrode 41 that connects to the quantum chip 10 on the first wiring board 20, the first protruding electrode 41 is located outside the deformation suppression region defined inside the second protruding electrode 42 at the outermost edge (outermost) of the board 21.

[0054] When cooled to extremely low temperatures, the quantum chip 10 and the substrates 11 and 21 of the first wiring board 20 are silicon substrates, so their linear thermal expansion coefficients are considered to be the same. In the substrate 21 of the first wiring board 20, the region inside the second protruding electrode 42 (deformation suppression region) is suppressed from deformation with a large curvature due to the restraining force from the second protruding electrode 42.

[0055] On the other hand, in the substrate 21 of the first wiring board 20, in the region outside the deformation suppression area, the area from the second protruding electrode 42 at the outermost edge (outermost) of the substrate 21 to the edge of the substrate 21 becomes a free end that is not constrained. Unlike the area inside the deformation suppression area, a large curvature deformation (warpage) occurs, as schematically shown in Figure 7(B). It is known that the amount of warpage of the substrate depends on the Young's modulus (longitudinal elastic modulus) E of the substrate material, Poisson's ratio ν, substrate film thickness (inversely proportional to the square of the film thickness), substrate length (proportional to the square of the length), the coefficient of thermal expansion (difference), temperature change, etc.

[0056] The amount of deformation (warpage) due to temperature changes from room temperature to cryogenic temperatures becomes more pronounced as the substrate 21 of the first wiring board 20 becomes thinner, which may cause problems such as poor connections to the second protruding electrode 42. In the example in Figure 7(B), the area from the outermost (outermost) first protruding electrode 41 of the substrate 11 of the quantum chip 10 to the edge of the substrate 11 becomes an unconstrained region (free end), causing warpage due to thermal shrinkage, etc. As a result, the outermost first protruding electrode 41 becomes tilted, which may cause problems such as poor connections due to delamination of the joint (electrode detachment). Note that Figure 7(B) is a schematic diagram illustrating the large curvature warpage of the unconstrained free end of the first wiring board 20, and the warpage of the second wiring board 30 is not shown. This is because the warpage of the second wiring board 30 varies depending on its thickness, size, material, etc.

[0057] In particular, if the second protruding electrode 42 at the outermost edge (outermost) of the substrate 21 of the first wiring board 20 is a ground bump that connects the ground patterns (planes) of the first surface (front) and the second surface (back), since many ground bumps are installed, it will not immediately result in failure. However, if it is a bump for signal transmission (signal bump), it will directly lead to failures such as deterioration of signal characteristics or disconnection.

[0058] Figure 7(C) is a schematic diagram showing the configuration of this embodiment in correspondence with Figure 7(A). According to this embodiment, regarding the first protruding electrode 41 that connects to the quantum chip 10 on the first wiring board 20, the first protruding electrode 41 is positioned within a deformation suppression region defined inside the second protruding electrode 42 at the outermost edge (outermost) of the board 21. The length of the unconstrained region from the second protruding electrode 42 at the outermost edge (outermost) of the board 21 to the edge of the board 21 is shorter than that shown in Figure 7(A).

[0059] By shortening the length of the region (free end) not constrained by the second protruding electrode 42 (a predetermined length, which can be determined by thermal stress analysis, etc.), deformation with a large curvature during thermal contraction is suppressed. Similarly, for the quantum chip 10, the free end from the first protruding electrode 41 at the outermost edge (outermost) of the substrate 11 of the quantum chip 10 to the edge of the substrate 11 is made as short as possible to suppress deformation with a large curvature during thermal contraction. Even if the second protruding electrode 42 at the outermost edge (outermost) of the substrate 21 of the first wiring board 20 is a bump for signal transmission (signal bump), deformation such as warping of the substrate 21 is suppressed, ensuring connection reliability and avoiding degradation of signal characteristics.

[0060] Within the framework of the full disclosure of the present invention (including the claims), further modifications and adjustments to embodiments or examples are possible based on the fundamental technical concept. Furthermore, within the framework of the claims of the present invention, various combinations or selections of various disclosed elements (including each element in each appendix, each element in each embodiment, each element in each drawing, etc.) are possible. In other words, the present invention naturally includes various modifications and alterations that a person skilled in the art could make in accordance with the full disclosure, including the claims, and the technical concept. [Explanation of symbols]

[0061] 1. Quantum devices 10 Quantum Chips 11 circuit boards 12 wiring layer 12a Pad electrode (wiring pad) 20. First wiring board (interposer) 21 circuit boards 22 First wiring layer 23 Second wiring layer 23a, 23b Via Pad 23c pad electrodes 24, 24a, 24b through vias 30. Second wiring board (package board, interposer) 31 Wiring layer 32 Third wiring layer 32a Pad electrode (wiring pad) 33. The fourth wiring layer 41, 41a, 41b First connection part (first protruding electrode) 42, 42a, 42b, 42A~42F Second connection point (second protruding electrode) 311 Core material 312, 313, 314, 315 Insulating layer 316 Through via 321, 323, 331, 333 Beer 322, 324, 332, 334 conductors

Claims

1. A quantum chip having a superconducting circuit wiring layer on the first surface of the substrate, A first wiring substrate comprising: a first substrate; a first wiring layer formed on a first surface of the first substrate; a second wiring layer formed on a second surface of the first substrate opposite to the first surface; and a plurality of through vias that penetrate the first substrate and electrically connect a plurality of wirings of the first wiring layer and a plurality of wirings of the second wiring layer; A second wiring substrate comprising a second substrate and a third wiring layer formed on the first surface of the second substrate, A plurality of first connection parts that provide electrical connections between a plurality of wirings in the wiring layer of the quantum chip and a plurality of wirings in the first wiring layer on the first surface of the first wiring substrate, which is arranged opposite to the first surface of the quantum chip, A plurality of second connection portions that provide electrical connections between a plurality of wirings in the second wiring layer on the second surface of the first wiring board and a plurality of wirings in the third wiring layer on the first surface of the second wiring board, which is positioned opposite the second surface of the first wiring board, Equipped with, The first wiring board has one or more second connection portions, among a plurality of second connection portions arranged in a first row when viewed from the edge of the first board, which are positioned at a location corresponding to one or more first connection portions on the first surface arranged in a first row when viewed from the edge of the first board, such that they are offset from the first connection portions and partially overlap them, and the position closest to the edge of the first board is located further towards the edge than the position closest to the edge of the first connection portion on the first surface arranged in the first row. A quantum device wherein the free end from the second connection portion at the outermost edge of the first substrate to the edge of the first substrate is set to a predetermined length, and the predetermined length corresponds to a length that suppresses deformation of the first substrate during thermal contraction.

2. The distance between a first position on the first surface that is closest to the end of the first board of the first connection portion, and a second position on the second surface that is closest to the end of the first board of the second connection portion, The quantum device according to claim 1, wherein the distance obtained by projecting the first position on the first surface of the first wiring board and the second position on the second surface onto the same plane is set to a predetermined ratio of the distance between the center position of the first connection portion and the first position.

3. In the first wiring board, The quantum device according to claim 1, wherein the second connection portion, which is positioned first when viewed from the edge of each of the four corners of the first substrate, is positioned on the first surface, which is positioned first when viewed from the edge of each of the four corners of the first substrate, at a position corresponding to the first connection portion, such that it is offset from the center of the first connection portion and partially overlaps with it, and the position closest to the edge of each corner is located further toward the edge of each corner than the position of the first connection portion closest to the edge of each corner.

4. In the first wiring board, Of the plurality of second connection portions arranged in the first row of the second surface when viewed from each side of the first substrate, Each of the second connection portions, positioned first when viewed from the edge of each of the four corners of the first substrate, At least one of the second connecting portions is located in the first row when viewed from the side between two adjacent corners of the first substrate, The position closest to each of the aforementioned ends is The first connection portion of the first surface is positioned such that it is the first to be positioned when viewed from the edge of each of the four corners of the first substrate, and is positioned such that it is offset in center from the first to be positioned and partially overlaps with the first to be positioned second connection portion, Arranged in the first row as viewed from the edge between two adjacent corners of the first substrate, and at least one of the first connection portions on the first surface arranged so as to be offset from the center and partially overlapping with at least one of the second connection portions arranged in the first row, From the position closest to the aforementioned end, The quantum device according to claim 1, further located on the end side.

5. In the first wiring board, a plurality of the second connection portions arranged in the first row when viewed from each side of the first board are, Arranged in the first row when viewed from each side of the first substrate, and arranged corresponding to the plurality of second connection portions, the position closest to the end of each of the plurality of first connection portions on the first surface which is offset in center and overlaps with the plurality of second connection portions in part is, Furthermore, the quantum device according to claim 1, which is located on each of the aforementioned sides.

6. In the first wiring board, The plurality of wirings in the second wiring layer on the second surface are The connection terminal of the through-via that penetrates the first substrate, The aforementioned connection terminal is connected to a second connection terminal, which is routed by wiring to a location different from directly below the through via, Includes, The second connection portion connected to the wiring of the third wiring layer of the second wiring board is, The connection terminal on the second surface of the through via of the first wiring board is joined to the connection terminal, or The quantum device according to any one of claims 1 to 5, wherein the quantum device is joined to the second connection terminal on the second surface at a position different from the connection terminal directly below the through via.

7. In the first wiring board, The distance projected onto the same plane between the second position at the outermost end of the second connection portion of the second surface, which is positioned further towards the end than the position of the first connection portion of the first surface, and the first position at the outermost end of the first connection portion of the first surface is: The quantum device according to any one of claims 3 to 6, wherein the distance between the center position of the first connection portion and the first position at the outermost end of the first connection portion is set to one-fifth to one-third or more.

8. The quantum device according to any one of claims 1 to 7, wherein the first connection portion and the second connection portion each include a protruding electrode.

9. The quantum device according to any one of claims 1 to 8, wherein the substrate of the quantum chip and the first substrate of the first wiring board are made of silicon substrates.

10. The quantum device according to any one of claims 1 to 9, wherein the second wiring board is a multilayer substrate in which an insulating layer and a conductive layer are alternately formed on both sides of the core material, in the same number on both sides.

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