comparator
The comparator design with voltage clamping elements improves response characteristics without increasing circuit current, addressing the need for faster operation with reduced power consumption.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- NISSHINBO MICRO DEVICES INC
- Filing Date
- 2021-12-06
- Publication Date
- 2026-06-09
AI Technical Summary
Conventional comparators require increased circuit current to improve response characteristics, which is undesirable for reducing power consumption and contributing to global warming.
A comparator design with a differential input section, folded cascode section, and output circuit, incorporating voltage clamping elements to control the potential of transistors, allowing improved response characteristics without increasing circuit current.
The comparator achieves enhanced response speed with reduced circuit current, thereby contributing to lower power consumption and mitigating global warming.
Smart Images
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Abstract
Description
Technical Field
[0001] The present invention relates to a comparator.
Background Art
[0002] The cause of global warming is considered to be due to the enhanced greenhouse effect of the atmosphere caused by an increase in the concentration of greenhouse gases such as CO2. With the rapid progress of the communication and information society, reducing the power consumption of electronic devices has also become a major issue. Many semiconductor integrated circuits are used in electronic devices, and the comparator widely used in semiconductor integrated circuits has response speed and consumption current as its main performance. Since the response speed and consumption current of a comparator are in an inverse proportional relationship, it is intended to improve the response characteristics to an input signal without increasing the consumption current and contribute to the suppression of global warming.
[0003] As a comparator used in a semiconductor integrated circuit, a circuit as shown in FIG. 4 is known (see, for example, Patent Document 1). The comparator 100 shown in FIG. 4 is composed of a differential input section 102, a folded cascode section 103, and an output circuit 104 as main components.
[0004] The differential input section 102 is composed of differential transistors M1 and M2 whose sources are commonly connected, load resistors R1 and R2 respectively connected to their drains, and a constant current source 21 connected between the common source of the transistors M1 and M2 and the positive power supply voltage VDD.
[0005] The folded cascode section 103 includes transistors M3 and M4, each with its source connected to load resistors R1 and R2, constant current sources 31 and 32, each connected between their drains and the positive power supply voltage VDD, and transistor M5, whose gate and drain are connected to the drain of transistor M4 and whose source is connected to the gate of transistor M4. In the folded cascode section 103, transistors M3 and M4 are connected in a current mirror configuration, and the output is taken from the connection node between the drain of transistor M4 and the constant current source 32.
[0006] Furthermore, transistor M5 is turned on when the current flowing through transistor M2 is greater than the current flowing through transistor M1, thereby suppressing the rise in the gate potential of transistor M6, shortening the propagation delay time, and improving the power supply voltage dependence of the propagation delay time (see, for example, Non-Patent Document 1).
[0007] The output circuit 104 consists of a transistor M6 whose gate is connected to the output of the folded cascode section 103 and whose source is connected to the negative power supply voltage VSS, and a constant current source 41 connected between its drain and the positive power supply voltage VDD. The output signal VOUT is taken from the connection node between transistor M6 and the constant current source 41. [Prior art documents] [Patent Documents]
[0008] [Patent Document 1] Patent No. 4677284 [Non-patent literature]
[0009] [Non-Patent Document 1] Practical Design of CMOS Analog IC Circuits, by Haruhiko Yoshida, CQ Publishing, 2010 (p. 144, Figure 4.10) [Overview of the Initiative] [Problems that the invention aims to solve]
[0010] Conventional comparators with the above configuration had the problem that the circuit current had to be increased in order to improve the response characteristics.
[0011] The present invention has been made in view of the above circumstances, and its object is to provide a comparator with improved response characteristics without increasing the circuit current. [Means for solving the problem]
[0012] To achieve the aforementioned objectives, the comparator according to the present invention is characterized by the following [1] to [7]. [1] A differential input section having a first differential transistor and a second differential transistor through which currents with current ratios corresponding to a first input potential and a second input potential flow, respectively. A folded cascode section having a third transistor connected in a folded cascode to the first differential transistor and a fourth transistor connected in a folded cascode to the second differential transistor, A comparator comprising an output circuit connected to the drain or collector of the fourth transistor to output an output signal, The aforementioned folded cascode section is A first voltage clamping element that limits the rise or fall of the drain potential or collector potential of the fourth transistor when the third transistor is in the off state and the fourth transistor is in the on state, The device includes a second voltage clamping element that limits the decrease or increase in the drain potential or collector potential of the fourth transistor when the third transistor is in the ON state and the fourth transistor is in the OFF state, The first voltage clamping element is composed of a fifth transistor having the same polarity as the third transistor and the fourth transistor, with its source or emitter connected to the drain or collector of the fourth transistor, and its drain or collector and gate or base connected to the drain or collector of the third transistor. It is a comparator. [2] A differential input section having a first differential transistor and a second differential transistor through which currents with current ratios corresponding to a first input potential and a second input potential flow, respectively. A folded cascode section having a third transistor connected in a folded cascode to the first differential transistor and a fourth transistor connected in a folded cascode to the second differential transistor, A comparator comprising an output circuit connected to the drain or collector of the fourth transistor to output an output signal, The aforementioned folded cascode section is A first voltage clamping element that limits the rise or fall of the drain potential or collector potential of the fourth transistor when the third transistor is in the off state and the fourth transistor is in the on state, A second voltage clamping element that limits the decrease or increase in the drain potential or collector potential of the fourth transistor when the third transistor is ON and the fourth transistor is OFF, It has a resistor, The first voltage clamp element is composed of a fifth transistor having the same polarity as the third and fourth transistors, with its source or emitter connected to the drain or collector of the fourth transistor, its drain or collector connected to the drain or collector of the third transistor and one end of the resistor, and its gate or base connected to the other end of the resistor. It is a comparator. [3] The comparator according to [1] or [2], wherein the output circuit has a sixth transistor with its gate or base connected to the drain or collector of the fourth transistor, and the threshold voltage of the sixth transistor is lower than the threshold voltages of the third transistor and the fourth transistor. It is a comparator. [4] The comparator according to any one of [1] to [3], wherein at least one of the first to fifth transistors is composed of a field effect transistor. It is a comparator. [5] The comparator according to [3], wherein the sixth transistor is composed of a field effect transistor. It is a comparator. [6] The comparator according to any one of [1] to [4], wherein At least one of the first to fifth transistors is composed of a bipolar transistor. It is a comparator. [7] [3] The comparator described above, The sixth transistor is composed of a bipolar transistor. It is a comparator. [Effects of the Invention]
[0013] According to the present invention, it is possible to provide a comparator with improved response characteristics without increasing the circuit current.
[0014] The present invention has been briefly described above. Furthermore, the details of the present invention will be further clarified by referring to the attached drawings and reading through the embodiments for carrying out the invention described below (hereinafter referred to as "embodiments"). [Brief explanation of the drawing]
[0015] [Figure 1] Figure 1 is a circuit diagram showing the comparator of the present invention in the first embodiment. [Figure 2] Figure 2 is a circuit diagram showing the comparator of the present invention in a second embodiment. [Figure 3] Figure 3 is a circuit diagram showing the comparator of the present invention in a third embodiment. [Figure 4] Figure 4 is a circuit diagram showing an example of a conventional comparator. [Modes for carrying out the invention]
[0016] Specific embodiments of the present invention will be described below with reference to the figures.
[0017] (First Embodiment) First, the comparator 1 of the first embodiment will be described with reference to Figure 1. As shown in the figure, the comparator 1 compares the inverting input potential INM (= first input potential) input to the inverting input terminal T11 with the non-inverting input potential INP (= second input potential) input to the non-inverting input terminal T12, and outputs the comparison result from the output terminal T3. The comparator 1 comprises a differential input section 2, a folded cascode section 3, and an output circuit 4.
[0018] The differential input section 2 comprises a differential transistor M1 (= first differential transistor) and a differential transistor M2 (= second differential transistor) whose sources are connected in common, load resistors R1 and R2 connected to their drains respectively, and a constant current source 21.
[0019] The differential transistors M1 and M2 are composed of P-channel field-effect transistors. The gate of differential transistor M1 is connected to the inverting input terminal T11, and the gate of differential transistor M2 is connected to the non-inverting input terminal T12. The sources of differential transistors M1 and M2 are connected in common to the constant current source 21.
[0020] The load resistor R1 is connected in series with the differential transistor M1. More specifically, the load resistor R1 is connected between the drain of the differential transistor M1 and the negative power supply terminal T22. The negative power supply voltage VSS is supplied to the negative power supply terminal T22. The load resistor R2 is connected in series with the differential transistor M2. More specifically, the load resistor R2 is connected between the drain of the differential transistor M2 and the negative power supply terminal T22.
[0021] The constant current source 21 is connected between the positive power supply terminal T21 and the sources of the differential transistors M1 and M2, which are connected in common. The positive power supply terminal T21 is supplied with the positive power supply voltage VDD. The differential input section 2 divides the constant current I1 supplied by the constant current source 21 to the differential transistors M1 and M2. The current ratio (division ratio) of the currents flowing through the differential transistors M1 and M2 is a value corresponding to the inverting input potential INM input to the inverting input terminal T11 and the non-inverting input potential INP input to the non-inverting input terminal T12.
[0022] The folded cascode section 3 includes a transistor M3 (= third transistor) connected in a folded cascode to differential transistor M1, a transistor M4 (= fourth transistor) connected in a folded cascode to differential transistor M2, transistors M5 and M7 that clamp the drain potential of transistor M4, and constant current sources 31 and 32. Transistors M3 to M5 and M7 are composed of N-channel field-effect transistors.
[0023] Transistor M3 has its gate and drain connected. Transistor M3's source is connected to the connection point between load resistor R1 and the drain of differential transistor M1, and its drain is connected to constant current source 31. Transistor M4's gate is connected to the gate and drain of transistor M3. Transistor M4's source is connected to the connection point between load resistor R2 and the drain of differential transistor M2, and its drain is connected to constant current source 32.
[0024] Constant current source 31 is connected between the drain of transistor M3 and the positive power supply terminal T21. Constant current source 32 is connected between the drain of transistor M4 and the positive power supply terminal T21.
[0025] Transistor M5 has its gate and drain connected to node A, which connects the drain of transistor M4 to the constant current source 32, and its source connected to the gate and drain of transistor M3 and the gate of transistor M4. Transistor M7 (=5th transistor, voltage clamp element) has its gate and drain connected to the node connecting the drain of transistor M3 to the constant current source 31, and its source connected to node A. In other words, transistor M7 is diode-connected between the drain of transistor M3 and the drain of transistor M4.
[0026] The folded cascode section 3 is configured to take out an output at connection node A between the drain of transistor M4 and the constant current source 32.
[0027] The output circuit 4 includes a transistor M6 (the sixth transistor) and a constant current source 41. Transistor M6 is composed of an N-channel field-effect transistor. The gate of transistor M6 is connected to connection node A, the source is connected to the negative power supply terminal T22, and the drain is connected to the constant current source 41. The constant current source 41 is connected between the drain of transistor M6 and the positive power supply terminal T21.
[0028] Next, we will describe the operation of comparator 1 in the configuration described above. First, we will describe the operation when the inverting input potential INM is higher than the non-inverting input potential INP, and the output signal VOUT of output terminal T3 is in a low state, that is, when the output signal VOUT is approximately the negative power supply voltage VSS.
[0029] When the inverting input potential INM is higher than the non-inverting input potential INP, more current I1 from the constant current source 21 flows through the differential transistor M2 than through the differential transistor M1. As a result, the voltage drop across the load resistor R1 decreases, and the voltage drop across the load resistor R2 increases.
[0030] Then, the gate-source potential difference of transistor M4 becomes smaller than that of transistor M3, and transistor M4 turns off. When transistor M4 is off, the potential of connection node A rises. When the potential of connection node A rises and the gate-source potential difference of transistor M6 reaches the threshold voltage, transistor M6 turns on. As a result, the output signal VOUT of output terminal T3 becomes low.
[0031] Furthermore, when the potential of junction node A rises and the gate-source potential difference of transistor M5 reaches the threshold voltage, transistor M5 turns ON. As a result, the potential of junction node A is clamped by the voltage obtained by adding the drain potential (=gate potential) of transistor M3 to the gate-source potential of transistor M5, and does not rise to near the positive power supply voltage VDD.
[0032] Next, we will describe the operation when the non-inverting input potential INP is higher than the inverting input potential INM, and the output signal VOUT at output terminal T3 is in a high state, that is, when the output signal VOUT is approximately equal to the positive power supply voltage VDD.
[0033] When the non-inverting input potential INP is higher than the inverting input potential INM, more current I1 from the constant current source 21 flows through the differential transistor M1 than through the differential transistor M2. As a result, the voltage drop across the load resistor R2 decreases, and the voltage drop across the load resistor R1 increases.
[0034] Then, the gate-source potential difference of transistor M4 becomes greater than that of transistor M3, and transistor M4 turns on. When transistor M4 turns on, the potential of connection node A decreases. When the potential of connection node A decreases and the gate-source potential difference of transistor M6 falls below the threshold voltage, transistor M6 turns off. As a result, the output signal VOUT of output terminal T3 becomes high.
[0035] Furthermore, when the potential of connection node A decreases and the gate-source potential difference of transistor M7 reaches the threshold voltage, transistor M7 turns ON. As a result, the potential of connection node A is clamped by the voltage obtained by subtracting the gate-source potential of transistor M7 from the drain potential (=gate potential) of transistor M3, and does not drop to near the negative power supply voltage VSS.
[0036] As described above, when the output signal VOUT is in a low state and transistor M4 is off, the rise in the gate potential of transistor M6 is suppressed by the action of transistor M5. Therefore, the time it takes for transistor M6 to switch from on to off can be shortened, and thus the response speed for the output signal VOUT to invert from a low state to a high state can be increased.
[0037] Furthermore, as mentioned above, when the output signal VOUT is in a High state and transistor M4 is ON, the decrease in the gate potential of transistor M6 is suppressed by the action of transistor M7. Therefore, the time it takes for transistor M6 to switch from OFF to ON can be shortened, and thus the response speed for the output signal VOUT to invert from a High state to a Low state can be increased.
[0038] Furthermore, by setting the threshold voltage of transistor M6 lower than that of transistors M3 and M4, the time it takes for transistor M6 to change from the off state to the on state can be further shortened. This further improves the response characteristics of the output circuit 4.
[0039] However, the comparator 1 in the first embodiment is designed to improve response characteristics without increasing the circuit current.
[0040] (Second Embodiment) Next, the comparator 1B of the second embodiment will be described with reference to Figure 2. In Figure 2, components identical to those in the circuit shown in Figure 1 are denoted by the same reference numerals, and their detailed descriptions are omitted.
[0041] The comparator 1B comprises a differential input section 2, a folded cascode section 3B, and an output circuit 4. The differential input section 2 and the output circuit 4 have already been described in the first embodiment described above, so a detailed explanation is omitted here.
[0042] The difference between the folded cascode section 3B of the second embodiment and the folded cascode section 3 of the first embodiment is that a resistor R3 is provided between the drain and gate of transistor M7.
[0043] The comparator 1B of the second embodiment is basically the same as that of the first embodiment, except for the points described later.
[0044] In other words, in the first embodiment, the potential of connection node A when transistor M4 is ON is voltage-clamped by the gate-source potential of transistor M7. In contrast, in the second embodiment, in addition to the gate-source potential of transistor M7, the current from the constant current source 31 and the voltage drop across resistor R3 are added.
[0045] Therefore, when transistor M4 is ON, the potential of connection node A is higher than when resistor R3 is not connected, and the time it takes for transistor M6 to change from OFF to ON is shortened. As a result, the propagation delay time for the output signal VOUT at output terminal T3 to change from High to Low is further shortened compared to the first embodiment.
[0046] However, the comparator 1B in the second embodiment has the effect of improving response characteristics without increasing the circuit current.
[0047]
[0048] (Third embodiment) Next, the comparator 1C of the third embodiment will be described with reference to Figure 3. In Figure 3, components identical to those in the circuit shown in Figure 1 are given the same reference numerals, and their detailed descriptions are omitted.
[0049] As shown in the figure, the comparator 1C includes a differential input section 2C, a folded cascode section 3C, and an output circuit 4C, similar to the first embodiment.
[0050] The difference between the first and third embodiments is that the conductivity types of transistors M1C to M7C, corresponding to transistors M1 to M7, are reversed. Another difference between the first and third embodiments is that the relationship between the positive power supply terminal T21 and the negative power supply terminal T22 is reversed.
[0051] In the third embodiment, when the output signal VOUT is in a high state, transistor M4C is in an off state. When the gate-source potential difference of transistor M4C becomes smaller than the gate-source potential difference of transistor M3C, and transistor M4C is in an off state, the potential of junction node A decreases. When the potential of junction node A decreases and the gate-source potential difference of transistor M5C reaches the threshold voltage, transistor M5C is turned on. Therefore, the potential of junction node A is clamped by a voltage obtained by subtracting the gate-source potential of transistor M5C from the drain potential (=gate potential) of transistor M3C, and does not decrease to near the negative power supply voltage VSS.
[0052] This allows for a shorter on-to-off time for transistor M6C, thereby increasing the response speed of the output signal VOUT from a high state to a low state.
[0053] On the other hand, when the output signal VOUT is low, transistor M4C turns on. When the gate-source potential difference of transistor M4C becomes greater than the gate-source potential difference of transistor M3C, and transistor M4C turns on, the potential of junction node A rises. When the potential of junction node A rises and the gate-source potential difference of transistor M7C reaches the threshold voltage, transistor M7C turns on. Therefore, the potential of junction node A is clamped by the voltage obtained by adding the drain potential (=gate potential) of transistor M3C to the gate-source potential of transistor M7C, and does not rise to near the positive power supply voltage VDD.
[0054] This allows for a shorter on-off to on time for transistor M6C, thereby increasing the response speed of the output signal VOUT from a low state to a high state.
[0055] Similarly, in the second embodiment, the conductivity type of the transistor may be reversed, and the relationship between the positive power supply terminal T21 and the negative power supply terminal T22 may be reversed.
[0056] Furthermore, the present invention is not limited to the embodiments described above, and can be modified, improved, etc., as appropriate. In addition, the material, shape, dimensions, number, placement, etc. of each component in the embodiments described above are arbitrary and not limited, as long as they can achieve the present invention.
[0057] In the first to third embodiments described above, the transistors were composed of field-effect transistors, but this is not limited to them. At least one or more transistors may be replaced with bipolar transistors. In this case, the gate of the transistor can be read as the base, the source as the emitter, and the drain as the collector in the explanation. [Explanation of symbols]
[0058] 1, 1B, 1C Comparator 2. 2C Differential Input Section 3, 3B, 3C Folded Cascode Section 4. 4C output circuit INM inverting input potential (first input potential) INP Non-inverting input potential (second input potential) M1, M1C Differential Transistors (First Differential Transistors) M2, M2C differential transistor (second differential transistor) M3, M3C transistors (third transistors) M4, M4C transistors (fourth transistors) M5, M5C transistors M6, M6C transistors (sixth transistors) M7, M7C transistors (fifth transistor, voltage clamp element) R3 resistor
Claims
1. A differential input section having a first differential transistor and a second differential transistor through which currents with current ratios corresponding to a first input potential and a second input potential flow, respectively. A folded cascode section having a third transistor connected in a folded cascode to the first differential transistor and a fourth transistor connected in a folded cascode to the second differential transistor, A comparator comprising an output circuit connected to the drain or collector of the fourth transistor to output an output signal, The aforementioned folded cascode section is A first voltage clamping element that limits the rise or fall of the drain potential or collector potential of the fourth transistor when the third transistor is in the off state and the fourth transistor is in the on state, The device includes a second voltage clamping element that limits the decrease or increase in the drain potential or collector potential of the fourth transistor when the third transistor is in the ON state and the fourth transistor is in the OFF state, The first voltage clamping element is composed of a fifth transistor having the same polarity as the third and fourth transistors, with its source or emitter connected to the drain or collector of the fourth transistor, and its drain or collector and gate or base connected to the drain or collector of the third transistor. comparator.
2. A differential input section having a first differential transistor and a second differential transistor through which currents with a current ratio corresponding to a first input potential and a second input potential flow, respectively, A folded cascode section having a third transistor connected in a folded cascode to the first differential transistor and a fourth transistor connected in a folded cascode to the second differential transistor, A comparator comprising an output circuit connected to the drain or collector of the fourth transistor to output an output signal, The aforementioned folded cascode section is A first voltage clamping element that limits the rise or fall of the drain potential or collector potential of the fourth transistor when the third transistor is in the off state and the fourth transistor is in the on state, A second voltage clamping element that limits the decrease or increase in the drain potential or collector potential of the fourth transistor when the third transistor is ON and the fourth transistor is OFF, It has a resistor, The first voltage clamp element is composed of a fifth transistor having the same polarity as the third and fourth transistors, with its source or emitter connected to the drain or collector of the fourth transistor, its drain or collector connected to the drain or collector of the third transistor and one end of the resistor, and its gate or base connected to the other end of the resistor. comparator.
3. A comparator according to claim 1 or 2, The output circuit has a sixth transistor whose gate or base is connected to the drain or collector of the fourth transistor. The threshold voltage of the sixth transistor is lower than the threshold voltages of the third and fourth transistors. comparator.
4. A comparator according to any one of claims 1 to 3, At least one of the first to fifth transistors is composed of a field-effect transistor. comparator.
5. A comparator according to claim 3, The sixth transistor is composed of a field-effect transistor. comparator.
6. A comparator according to any one of claims 1 to 4, At least one of the first to fifth transistors is a bipolar transistor. comparator.
7. A comparator according to claim 3, The sixth transistor is composed of a bipolar transistor. comparator.