Signal detection system and memory detection method

Abstract

The present disclosure relates to the field of semiconductor circuit design, and particularly relates to a signal detection system and a memory detection method, which comprises a signal generator, which generates a reference test signal based on external parameters, the reference test signal being a clock signal satisfying a preset duty cycle; the reference test signal is subjected to duty cycle test based on a test circuit to determine whether the function of the test circuit is normal; if the function of the test circuit is normal, different test modules are selected in turn based on a test control signal, and the signals output by the selected test modules are subjected to duty cycle test based on the test circuit; the test module comprises a signal conversion module and a write clock path. The present disclosure selects different test paths to test whether the duty cycle of the high-speed clock signal in different transmission paths meets the requirements, so as to ensure the stability of memory data processing.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor circuit design, and in particular to a signal detection system and a memory detection method. Background Technology

[0002] With the advancement of technology, high-tech products are constantly being updated and upgraded, and their performance is continuously improving. The operation of high-tech products is inseparable from the storage of data by memory. Therefore, improving the data access speed and data access stability of memory is an urgent issue.

[0003] Memory uses clock signals to process data, and the transmission frequency of the clock signal determines the number of operations that the memory can perform in the same amount of time, which determines how fast the memory processes data. Therefore, memory processing based on high-speed clock signals is of great significance to improving memory performance.

[0004] How to test whether the duty cycle of a high-speed clock signal meets the requirements, how to ensure the accuracy of high-speed clock signal testing, and how to generate equidistant parallel clock signals based on high-speed clock signals are urgent problems to be solved. Summary of the Invention

[0005] This disclosure provides a signal detection system and a memory detection method. By selecting different test paths, the duty cycle of the high-speed clock signal in different transmission paths is tested to ensure the stability of memory data processing.

[0006] This disclosure provides a signal detection system applied to a memory, used to perform duty cycle testing on the output signals of each test path in the memory according to a test circuit in the memory. The system includes: a signal generator that generates a reference test signal based on external parameters, the reference test signal being a clock signal that satisfies a preset duty cycle; a test circuit that performs a duty cycle test on the reference test signal to determine if the test circuit functions correctly; if the test circuit functions correctly, different test modules are sequentially selected based on a test control signal, and the duty cycle of the signals output by the selected test modules is tested based on the test circuit; each test module includes: a signal conversion module and a write clock path; wherein the signal conversion module generates an internal clock signal based on the reference test signal; the write clock path includes: a write divider, a write clock tree, and a signal loading circuit; the write divider generates a parallel write clock based on the internal clock signal, the write clock tree adjusts the delay of the parallel write clock, and the signal loading circuit samples preset data based on the parallel write clock to generate a first indicator signal and a second indicator signal.

[0007] The duty cycle of the reference test signal is tested by the test circuit. The duty cycle of the reference test signal is known and used to determine whether the duty cycle test function of the test circuit is normal. If the duty cycle test function of the test circuit is normal, different test modules are selected based on the test control signal. The duty cycle of the output signal of different test modules is tested sequentially by the test circuit to test whether the duty cycle of the output signal of different test modules is normal, thereby completing the functional test of different test modules.

[0008] In addition, the test module also includes a read clock path, which includes a read divider and a read clock conversion circuit. The read divider is used to generate a parallel read clock based on the internal clock signal, and the read clock conversion circuit is used to generate a serial read clock based on the parallel read clock.

[0009] In addition, the memory also includes a clock driver, whose input is connected to the output of the signal conversion module and whose output is connected to the test circuit, to prevent significant signal attenuation during the transmission of the internal clock signal to the test circuit for testing.

[0010] In addition, the test control signal is set to at least four bits to form multiple signal values; one value is configured to select a duty cycle test based on the test circuit for a reference test signal; another value is configured to control the signal conversion module to receive the reference test signal and perform a duty cycle test on the internal clock signal output by the signal conversion module based on the test circuit; another value is configured to select a duty cycle test on the serial read clock output by the read clock path based on the test circuit; and another value is configured to select a duty cycle test on the first and second indicator signals output by the write clock path based on the test circuit. The memory also includes a logic control signal circuit configured to identify the test control signal and generate a corresponding conduction signal based on the test control signal. The conduction signal is used to select the corresponding test module to be turned on, so as to form different test paths. Different test paths output the test signal to the test circuit or an external test system.

[0011] Additionally, the signal generator includes: an oscillation generation module configured to generate an initial oscillation signal based on an oscillation control signal, the oscillation control signal being used to adjust the frequency of the generated initial oscillation signal; a duty cycle correction module connected to the output of the oscillation generation module, configured to adjust the duty cycle of the initial oscillation signal based on the duty cycle control signal to generate an intermediate test signal; and an amplitude adjustment module connected to the output of the duty cycle correction module, configured to adjust the amplitude of the intermediate test signal based on the amplitude adjustment signal to generate a reference test signal.

[0012] In addition, the memory includes: a first output component, connected to the output terminal of the duty cycle correction module, used to output the intermediate test signal to an external test system, which is used to test whether the intermediate test signal meets the preset duty cycle.

[0013] In addition, the memory includes: a signal conversion module for receiving an external clock signal with a preset duty cycle and generating an internal clock signal based on the external clock signal; and a third output component connected to the output end of the write clock tree for outputting the parallel write clock to an external test system, which is used to test whether the parallel write clock is an equidistant clock.

[0014] In addition, the memory also includes: a selection module having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is used to receive a reference test signal, the second input terminal is used to receive an external clock signal, the output terminal is connected to the input terminal of the signal conversion module, and the selection module is used to receive a test control signal and connect the first input terminal and the output terminal or the second input terminal and the output terminal based on the test control signal.

[0015] Additionally, the selection module includes: a first input MOSFET, with its source connected to the output terminal of the amplitude adjustment module and its drain used to output a reference test signal; a second input MOSFET, with its source connected to the drain of the first input MOSFET and its drain connected to the source of the first input MOSFET; and a third input MOSFET, with its source used to receive an external clock signal and its drain connected to the drain of the first input MOSFET, and used to output an external clock signal; the gates of the first input MOSFET, the second input MOSFET, and the third input MOSFET are used to receive test control signals, and the signals received by the gates of the first input MOSFET and the second input MOSFET are inverted signals.

[0016] In addition, the test control signals also include: one value configured to control the memory to output the generated intermediate test signal to an external test system for duty cycle detection; one value configured to select duty cycle testing based on the test circuit against a reference test signal; one value configured to control the memory to output a parallel write clock generated based on an external clock signal to an external test system for duty cycle detection; one value configured to control the memory to output a parallel write clock generated based on a reference test signal to an external test system for duty cycle detection; one value configured to select duty cycle testing based on the internal clock signal output by the signal conversion module based on the reference test signal from the test circuit; and one value configured to select... The duty cycle of the internal clock signal output by the signal conversion module based on the external clock signal is tested using the test circuit. One value is configured to select the serial read clock output by the read clock path based on the reference test signal for duty cycle testing. Another value is configured to select the first and second indicator signals output by the write clock path based on the reference test signal for duty cycle testing. A third value is configured to select the serial read clock output by the read clock path based on the external clock signal for duty cycle testing. Finally, a fourth value is configured to select the first and second indicator signals output by the write clock path based on the external clock signal for duty cycle testing.

[0017] In addition, the amplitude adjustment module includes: a first signal generation unit configured to pull up and output a signal based on an intermediate test signal and pull down and output a signal based on an inverted test signal to generate a reference test signal with the same phase as the intermediate test signal; and a second signal generation unit configured to pull up and output a signal based on an inverted test signal and pull down and output a signal based on an intermediate test signal to generate an inverted reference test signal with the same phase as the inverted test signal; wherein the intermediate test signal and the inverted test signal have the same amplitude but opposite phase.

[0018] Additionally, the write divider includes a four-phase clock generation circuit for receiving an internal clock signal, configured to generate a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal with the same period based on the internal clock signal; the write clock tree includes a signal delay circuit for receiving the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, and a delay command, configured to delay the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal respectively based on the delay command, and the delays between the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are different.

[0019] In addition, the delay commands include a first delay command, a second delay command, a third delay command, and a fourth delay command; the delay circuit includes a first delay sub-circuit, a second delay sub-circuit, a third delay sub-circuit, and a fourth delay sub-circuit; wherein, the first delay sub-circuit is used to delay the first clock signal according to the first delay command, the second delay sub-circuit is used to delay the second clock signal according to the second delay command, the third delay sub-circuit is used to delay the third clock signal according to the third delay command, and the fourth delay sub-circuit is used to delay the fourth clock signal according to the fourth delay command.

[0020] In addition, the signal loading circuit includes: a data generation module for generating four bits of first loading data and second loading data; a data loading module for sampling the first loading data according to a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal to generate a first indication signal; wherein, when the first loading data corresponding to the clock signal sampling edge is high, the generated first indication signal is high; the data loading module is also used to sample the second loading data according to the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal to generate a second indication signal; wherein, when the second loading data corresponding to the clock signal sampling edge is high, the generated second indication signal is high.

[0021] Another embodiment of this disclosure provides a memory testing method, which uses the signal detection system provided in the above embodiments to test the duty cycle of the output signals of each test path in the memory. By selecting different test paths, the method tests whether the duty cycle of the high-speed clock signal in different transmission paths meets the requirements, thereby ensuring the stability of memory data processing. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the structure of a signal detection system provided in an embodiment of the present disclosure;

[0024] Figure 2 This is a schematic diagram of the structure of a signal generator provided in an embodiment of the present disclosure;

[0025] Figure 3 This is a schematic diagram of the structure of a ring oscillator provided in an embodiment of the present disclosure;

[0026] Figure 4 A schematic diagram of the structure of a tetrahedral oscillator provided in an embodiment of this disclosure;

[0027] Figure 5 This is a schematic diagram of the structure of a duty cycle correction module provided in an embodiment of the present disclosure;

[0028] Figure 6 A schematic diagram illustrating the correction principle of the first adjustment unit and the second adjustment unit provided in an embodiment of this disclosure;

[0029] Figure 7 This is a schematic diagram of the structure of the first adjustment unit and the second adjustment unit provided in an embodiment of the present disclosure;

[0030] Figure 8 This is a schematic diagram of the structure of a correction unit provided in an embodiment of the present disclosure;

[0031] Figure 9 A schematic diagram illustrating the correction principle of a correction unit provided in an embodiment of this disclosure;

[0032] Figure 10 This is a schematic diagram of the structure of an amplitude adjustment module provided in an embodiment of the present disclosure;

[0033] Figure 11 A schematic diagram illustrating the adjustment principle of an amplitude adjustment module provided in an embodiment of this disclosure;

[0034] Figure 12 This is a schematic diagram of the structure of a test circuit provided in an embodiment of the present disclosure;

[0035] Figure 13 A schematic diagram of the structure of a first integrating circuit and a second integrating circuit provided in an embodiment of the present disclosure;

[0036] Figure 14 This is a schematic diagram of the structure of a comparison circuit provided in an embodiment of the present disclosure;

[0037] Figure 15 This is a schematic diagram of the pre-storage circuit provided in an embodiment of the present disclosure;

[0038] Figure 16 This is a schematic diagram of the control logic of a control module provided in an embodiment of the present disclosure;

[0039] Figure 17 This is a schematic diagram of the structure of a control module provided in an embodiment of the present disclosure;

[0040] Figure 18 This is a schematic diagram of the structure of a clock generation circuit provided in an embodiment of the present disclosure;

[0041] Figure 19 A timing diagram of a four-phase signal provided in an embodiment of this disclosure;

[0042] Figure 20 A timing diagram illustrating the generation of an equidistant four-phase signal according to an embodiment of this disclosure;

[0043] Figure 21 This is a schematic diagram of the specific structure of the selection module provided in one embodiment of the present disclosure. Detailed Implementation

[0044] How to test whether the duty cycle of a high-speed clock signal meets the requirements, how to ensure the accuracy of high-speed clock signal testing, and how to generate equidistant parallel clock signals based on high-speed clock signals are urgent problems to be solved.

[0045] One embodiment of this disclosure provides a signal detection system that selects different test paths to test whether the duty cycle of a high-speed clock signal in different transmission paths meets the requirements, thereby ensuring the stability of memory data processing.

[0046] It will be understood by those skilled in the art that many technical details have been provided in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.

[0047] Figure 1 This is a schematic diagram of the signal detection system provided in this embodiment. Figure 2 This is a schematic diagram of the signal generator provided in this embodiment. Figure 3 This is a schematic diagram of the ring oscillator provided in this embodiment. Figure 4 This is a schematic diagram of the tetrahedral oscillator provided in this embodiment. Figure 5 This is a schematic diagram of the duty cycle correction module provided in this embodiment. Figure 6 This is a schematic diagram illustrating the correction principle of the first adjustment unit and the second adjustment unit provided in this embodiment. Figure 7 This is a schematic diagram of the structure of the first adjustment unit and the second adjustment unit provided in this embodiment. Figure 8 This is a schematic diagram of the structure of the correction unit provided in this embodiment. Figure 9 This is a schematic diagram illustrating the correction principle of the correction unit provided in this embodiment. Figure 10 This is a schematic diagram of the amplitude adjustment module provided in this embodiment. Figure 11This is a schematic diagram illustrating the adjustment principle of the amplitude adjustment module provided in this embodiment. Figure 12 This is a schematic diagram of the test circuit provided in this embodiment. Figure 13 This is a schematic diagram of the first and second integrating circuits provided in this embodiment. Figure 14 This is a schematic diagram of the comparator circuit provided in this embodiment. Figure 15 This is a schematic diagram of the pre-storage circuit provided in this embodiment. Figure 16 This is a schematic diagram of the control logic of the control module provided in this embodiment. Figure 17 This is a schematic diagram of the control module provided in this embodiment. Figure 18 This is a schematic diagram of the clock generation circuit provided in this embodiment. Figure 19 This is a timing diagram of the four-phase signal provided in this embodiment. Figure 20 This is a timing diagram illustrating the generation of equidistant four-phase signals provided in this embodiment. Figure 21 The following is a detailed structural diagram of the selection module provided in this embodiment. The signal detection system provided in this embodiment will be further described in detail below with reference to the accompanying drawings:

[0048] The signal detection system 1000 is applied to a memory and is used to perform duty cycle testing on the output signals of each test path in the memory according to the test circuit in the memory.

[0049] refer to Figure 1 Signal detection system 1000, including:

[0050] Signal generator 100 generates a reference test signal AltWck based on external parameters. The reference test signal AltWck is a clock signal that satisfies a preset duty cycle.

[0051] The duty cycle of the reference test signal AltWck is tested based on the test circuit 400 to determine whether the test circuit 400 is functioning properly. If the test circuit 400 is functioning properly, different test modules are selected sequentially based on the test control signal DcmCtrl, and the duty cycle of the signals output by the selected test modules is tested based on the test circuit 400.

[0052] The test module includes a signal conversion module 1002 and a write clock path 1003. The signal conversion module 1002 generates an internal clock signal PWCK based on the reference test signal AltWck. The write clock path 1003 includes a write divider 1013, a write clock tree 1023, and a signal loading circuit 805. The write divider 1013 generates a parallel write clock Clk_W based on the internal clock signal PWCK. The write clock tree 1023 has its input connected to the output of the write divider 1013 and is used to adjust the delay of the input signal to generate the parallel write clock Clk_W. The signal loading circuit 805 has its input connected to the output of the write clock tree 1023 and its output connected to the test circuit 400. It is used to sample preset data based on the parallel write clock Clk_W to generate a first indicator signal Pup and a second indicator signal Pdn.

[0053] The duty cycle of the reference test signal AltWck is tested by the test circuit 400. The duty cycle of the reference test signal AltWck is known and used to determine whether the duty cycle test function of the test circuit 400 is normal. If the duty cycle test function of the test circuit 400 is normal, different test modules are selected based on the test control signal DcmCtrl. The duty cycle of the output signal of different test modules is tested sequentially by the test circuit 400 to test whether the duty cycle of the output signal of different test modules is normal, thereby completing the functional test of different test modules.

[0054] Continue to refer to Figure 1 In some embodiments, the test module further includes a read clock path 1004, which includes a read divider 1014 and a read clock conversion circuit 1024. The read divider 1014 is used to generate a parallel read clock Clk_R1 based on the internal clock signal PWCK, and the read clock conversion circuit 1024 is used to generate a serial read clock Clk_R2 based on the parallel read clock Clk_R1.

[0055] It should be noted that, in some embodiments, the write divider 1013 and the read divider 1014 in the memory can be implemented based on a single divider.

[0056] For signal generator 100, refer to Figure 2 The signal generator 100 includes:

[0057] The oscillation generation module 101 is configured to generate an initial oscillation signal Osc0 based on the oscillation control signal OscAdj, wherein the oscillation control signal OscAdj is used to adjust the frequency of the generated initial oscillation signal Osc0.

[0058] The duty cycle correction module 102 is connected to the output of the oscillation generation module 101. The duty cycle correction module 102 is configured to adjust the duty cycle of the initial oscillation signal Osc0 based on the duty cycle control signal Duty in order to generate the intermediate test signal Pretest.

[0059] The amplitude adjustment module 103 is connected to the output terminal of the duty cycle correction module 102. The amplitude adjustment module 103 is configured to adjust the amplitude of the intermediate test signal Pretest based on the amplitude adjustment signal OBControl to generate the reference test signal AltWck.

[0060] For the oscillation generation module 101, refer to Figure 3 In some embodiments, the oscillation generation module 101 includes a ring oscillator. The ring oscillator generates an initial oscillation signal Osc0 based on an oscillation control signal OscAdj, and the oscillation control signal OscAdj is used to adjust the number of inverters connected to the ring oscillator. It is understood that the number of inverters connected to the ring oscillator is related to the oscillation frequency of the initial oscillation signal Osc0; specifically, the more inverters connected to the ring oscillator, the lower the oscillation frequency of the initial oscillation signal Osc0. (Reference) Figure 4In some embodiments, the oscillation generation module 101 includes a tetrahedral oscillator, which comprises an inner-ring inverter and an outer-ring inverter. The outer-ring inverters have the same driving capability, and the inner-ring inverters have the same driving capability, with the driving capability of the inner-ring inverters being 0.3 to 0.8 times that of the outer-ring inverters. For the tetrahedral oscillator, it is used to generate an initial oscillation signal Osc0 based on an oscillation control signal OscAdj, and the oscillation control signal OscAdj is used to adjust the driving capability of the inner-ring inverters. In one example, the oscillation control signal OscAdj is used to adjust the driving capability of the transistors constituting the inner-ring inverters to adjust the driving capability of the inner-ring inverters. It is understandable that the stronger the driving capability of the inner inverter in a tetrahedral oscillator, the smaller the delay caused by the inverter, and the higher the frequency of the initial oscillation signal Osc0 generated by the oscillation generation module 101. In practical applications, the frequency of the initial oscillation signal Osc0 generated by the oscillation generation module 101 can be controlled by changing the ratio of the driving capability of the inner inverter to that of the outer inverter. In one example, the driving capability of the inner inverter can be set to 0.4, 0.5, 0.6, or 0.7 times the driving capability of the outer inverter; preferably, the driving capability of the inner inverter is set to 0.7 times the driving capability of the outer inverter to increase the frequency of the initial oscillation signal Osc0 generated by the oscillation generation module 101. In a specific example, the outer inverter includes: a first inverter 1, a second inverter 2, a third inverter 3, and a fourth inverter 4; the inner inverter includes: a fifth inverter 5, a sixth inverter 6, a seventh inverter 7, and an eighth inverter 8. In this configuration, the output of the first inverter 1 is connected to the input of the second inverter 2; the output of the second inverter 2 is connected to the input of the third inverter 3; the output of the third inverter 3 is connected to the input of the fourth inverter 4; the output of the fourth inverter 4 is connected to the input of the first inverter 1; the input of the fifth inverter 5 is connected to the output of the first inverter 1, and its output is connected to the input of the fourth inverter 4; the input of the sixth inverter 6 is connected to the output of the second inverter 2, and its output is connected to the input of the first inverter 1; the input of the seventh inverter 7 is connected to the output of the third inverter 3, and its output is connected to the input of the second inverter 2; and the input of the eighth inverter 8 is connected to the output of the fourth inverter 4, and its output is connected to the input of the third inverter 3.

[0061] For duty cycle correction module 102, refer to Figure 5The duty cycle correction module 102 includes: a first adjustment unit 112 connected to the oscillation generation module 101, configured to increase the duty cycle of the initial oscillation signal Osc0 to generate a first adjustment signal T1; a second adjustment unit 122 connected to the oscillation generation module 101, configured to decrease the duty cycle of the initial oscillation signal Osc0 to generate a second adjustment signal T2; and a correction unit 132 connected to the first adjustment unit 112 and the second adjustment unit 122, configured to generate an intermediate test signal Pretest based on the duty cycle control signal Duty, the first adjustment signal T1, and the second adjustment signal T2; wherein the duty cycle control signal Duty is used to adjust the signal proportions of the first adjustment signal T1 and the second adjustment signal T2 in the generated intermediate test signal Pretest.

[0062] For the first adjustment unit T1 and the second adjustment unit T2, refer to Figure 6 The first adjustment unit T1 and the second adjustment unit T2 adjust the duty cycle of the signal by delaying the rising edge and falling edge of the signal to different degrees. For example, the delay of the rising edge of the initial signal is t1, and the delay of the falling edge of the initial signal is t2. When t1 > t2, the distance between the rising edge and the falling edge of the delayed signal is shortened, and the duty cycle of the signal decreases. When t1 < t2, the distance between the rising edge and the falling edge of the delayed signal is extended, and the duty cycle of the signal increases.

[0063] In a specific example, refer to Figure 7 The first adjustment unit 112 includes: a first switching P-tube. <kp1>First switch N transistor <kn1>Second switch P-tube <kp2>Second switch N-transistor <kn2>Among them, the first switch P transistor <kp1>The gate and the first switch N-transistor <kn1>The gate of the first switch P transistor is connected to receive the initial oscillation signal Osc0. <kp1>The source is connected to the first pull-up transistor. <lp1>The drain of the first pull-up transistor <lp1>The source is used to receive a high level, and the first switch is an N-transistor. <kn1>The source is connected to the first pull-down transistor. <ln1>The drain of the first pull-down transistor <ln1>The source is used to receive a low level, the first switch P transistor <kp1>The drain and the first switch N-transistor <kn1>The drains are connected and connected to the second switching P-transistor. <kp2>The gate and the second switch N-transistor <kn2>The gate of the second switching P-tube <kp2>The source is connected to the second pull-up transistor. <lp2>The drain of the second pull-up transistor <lp2>The source is used to receive a high level, and the second switch is an N-transistor. <kn2>The source is connected to the second pull-down transistor. <ln2>The drain of the second pull-down transistor <ln2>The source of the second switch P transistor is used to receive a low level. <kp2>Second switch N-transistor <kn2>The drain of the transistor is connected to the output of the first adjustment signal T1. The first pull-up transistor... <lp1>and the first pull-down transistor <ln1>Based on the duty cycle control signal Duty being turned on, and the first pull-down transistor... <ln1>The driving capability is greater than that of the first pull-up transistor. <lp1>Drive capability; second pull-up transistor <lp2>Second pull-down transistor <ln2>Based on the duty cycle control signal Duty being turned on, and the second pull-down transistor... <ln2>The driving capability is less than that of the second pull-up transistor. <lp2>The driving capability. The second adjustment unit 122 includes: a third switching P-tube. <kp3>Third switch N transistor <kn3>Fourth switch P-tube <kp4>and the fourth switch N transistor <kn4>Among them, the third switch P transistor <kp3>The gate and the third switch N-transistor <kn3>The gate of the third switch P transistor is connected to receive the initial oscillation signal Osc0. <kp3>The source is connected to the third pull-up transistor. <lp3>The drain of the third pull-up transistor <lp3>The source is used to receive a high level, and the third switch is an N-transistor. <kn3>The source is connected to the third pull-down transistor. <ln3>The drain of the third pull-down transistor <ln3>The source is used to receive a low level, and the third switch P transistor... <kp3>The drain and the third switch N-transistor <kn3>The drains are connected and connected to the fourth switch P-transistor. <kp4>Gate and fourth switch N-transistor <kn4>The gate of the fourth switch P transistor <kp4>The source is connected to the fourth pull-up transistor. <lp4>The drain of the fourth pull-up transistor <lp4>The source is used to receive a high level, and the fourth switch is the N-transistor. <kn4>The source is connected to the fourth pull-down transistor. <ln4>The drain of the fourth pull-down transistor <ln4>The source is used to receive a low level, the fourth switch P transistor <kp4>and the fourth switch N transistor <kn4>The drain of the transistor is connected to the output of the second adjustment signal T2. The third pull-up transistor... <lp3>and the third pull-down transistor <ln3>Based on the duty cycle control signal Duty being turned on, and the third pull-down transistor... <ln3>The driving capability is greater than that of the third pull-up transistor. <lp3>Drive capability; fourth pull-up transistor <lp4>and the fourth pull-down transistor <ln4>Based on the duty cycle control signal Duty being turned on, and the fourth pull-down transistor... <ln4>The driving capability is less than that of the fourth pull-up transistor. <lp4>The driving capability. It should be noted that the first pull-up transistor... <lp1>First pull-down transistor <ln1>Second pull-up transistor <lp2>Second pull-down transistor <ln2>Third pull-up transistor <lp3>Third pull-down transistor <ln3>Fourth pull-up transistor <lp4>and the fourth pull-down transistor <ln4>It can be turned on directly based on the duty cycle control signal "Duty", or it can be turned on based on the duty cycle enable signal, which is generated based on the duty cycle control signal "Duty". For the first adjustment unit 112, due to the second pull-up transistor... <lp2>The driving capability is greater than that of the second pull-down transistor. <ln2>The driving capability of the first adjustment signal T1 makes it easy to pull up but difficult to pull down; therefore, the rising edge delay of the first adjustment signal T1 is smaller and the falling edge delay is larger compared to the initial oscillation signal Osc0. For the second adjustment unit 122, due to the fourth pull-up transistor... <lp4>The driving capability is less than that of the fourth pull-down transistor. <ln2>The driving capability makes the second adjustment signal T2 easy to pull down but difficult to pull up; therefore, the second adjustment signal T2 has a larger rising edge delay and a smaller falling edge delay compared to the initial oscillation signal Osc0.

[0064] In some embodiments, the first pull-up transistor <lp1>Drive capability, second pull-down transistor <ln2>Drive capability, third pull-down transistor <ln3>Drive capability and fourth pull-up transistor <lp4>They have the same driving capability; the first pull-down transistor <ln1>Drive capability, second pull-up transistor <lp2>Drive capability, third pull-up transistor <lp3>Drive capability and fourth pull-down transistor <ln4>Their driving capabilities are the same. (Continue to refer to...) Figure 7 Specifically, the first pull-up transistor <lp1>Drive capability, second pull-down transistor <ln2>Drive capability, third pull-down transistor <ln3>Drive capability and fourth pull-up transistor <lp4>The driving capability is B; the first pull-down transistor <ln1>Drive capability, second pull-up transistor <lp2>Drive capability, third pull-up transistor <lp3>Drive capability and fourth pull-down transistor <ln4>The driving capability is A; where the driving capability represented by A is greater than the driving capability represented by B. This is achieved by setting the first pull-up transistor. <lp1>Drive capability, second pull-down transistor <ln2>Drive capability, third pull-down transistor <ln3>Drive capability and fourth pull-up transistor <lp4>They have the same driving capability and are configured with a first pull-down transistor. <ln1>Drive capability, second pull-up transistor <lp2>Drive capability, third pull-up transistor <lp3>Drive capability and fourth pull-down transistor <ln4>The driving capabilities are the same. The first adjustment unit 112 has the same ability to adjust the rising edge, and the second adjustment unit 122 has the same ability to adjust the falling edge, controlled by the same transistor. The first adjustment unit 112 has the same ability to adjust the falling edge, and the second adjustment unit 122 has the same ability to adjust the rising edge, so that the total delay of the first adjustment unit 112 for the rising and falling edges is consistent with the total delay of the second adjustment unit 122 for the rising and falling edges, ensuring that the periods of the first adjustment signal T1 and the second adjustment signal T2 are the same, thereby facilitating the correction module 132 to adjust the duty cycle according to the first adjustment signal T1 and the second adjustment signal T2.

[0065] In this embodiment, the first adjustment unit 112 and the second adjustment unit 122 further include a correction transistor group 142. The correction transistor group 142 includes x correction transistors connected in parallel, wherein the driving capability of the nth correction transistor is twice the driving capability of the (n-1)th correction transistor, where x is an integer greater than or equal to 2, and n is any integer less than or equal to x and greater than or equal to 2. Further, the duty cycle control signal Duty is also used to select and turn on the correction transistors in the correction transistor group 142; at this time, the driving capability of the correction transistor group 142 refers to the equivalent driving capability of the multiple turned-on correction transistors. The correction transistor group 142 is connected to the first pull-up transistor. <lp1>First pull-down transistor <ln1>Second pull-up transistor <lp2>Second pull-down transistor <ln2>Third pull-up transistor <lp3>Third pull-down transistor <ln3>Fourth pull-up transistor <lp4>and the fourth pull-down transistor <ln4>The transistors are connected in parallel, and the type of the correction transistor in correction transistor group 142 is the same as the type of the transistors connected in parallel. For a specific example, refer to [reference needed]. Figure 7 The correction transistor group 142 includes a first correction transistor, a second correction transistor, a third correction transistor, a fourth correction transistor, and a fifth correction transistor. The driving capability of the first correction transistor is C, the second correction transistor is 2C, the third correction transistor is 4C, the fourth correction transistor is 8C, and the fifth correction transistor is 16C. The first, second, third, fourth, and fifth driving transistors are selectively turned on based on the duty cycle control signal Duty, thereby controlling the first adjustment unit 112 and the second adjustment unit 122 to delay the initial oscillation signal Osc0 to different degrees. It should be noted that the "C" mentioned above represents a preset unit value, which can be designed according to the circuit design in specific applications. The above description is only to illustrate the multiple relationship of the driving capabilities between the correction transistors. It should be noted that in this embodiment, the multiple correction transistors in the correction transistor group 142 are arranged in parallel. In other embodiments, the multiple correction transistors in the correction transistor group can also be arranged in series, or in a series + parallel combination.

[0066] For correction unit 132, refer to Figure 8 The correction unit 132 includes: a plurality of first driving sub-units arranged in parallel with each other, the input terminal of which is connected to the first adjustment unit 112 and is also used to receive a duty cycle control signal Duty; a plurality of second driving sub-units arranged in parallel with each other, the input terminal of which is connected to the second adjustment unit 122 and is also used to receive a duty cycle control signal Duty; wherein, the duty cycle control signal Duty is used to select and turn on the plurality of first driving sub-units and the plurality of second driving sub-units; a third driving sub-unit 213, the input terminal of which is connected to the output terminal of the first driving sub-unit and the output terminal of the second driving sub-unit, and the output terminal of which is used to output an intermediate test signal Pretest. Specifically, when the driving capability of multiple first driving subunits is greater than the driving capability of multiple second driving subunits, the duty cycle of the intermediate test signal Pretest output by the third driving subunit 213 is more biased towards the first adjustment signal T1. That is, in the intermediate test signal Pretest generated based on the first adjustment signal T1 and the second adjustment signal T2, the first adjustment signal T1 has a larger proportion. When the driving capability of multiple second driving subunits is greater than the driving capability of multiple first driving subunits, the duty cycle of the intermediate test signal Pretest output by the third driving subunit 213 is more biased towards the second adjustment signal T2. That is, in the intermediate test signal Pretest generated based on the first adjustment signal T1 and the second adjustment signal T2, the second adjustment signal T2 has a larger proportion. It can be understood that the driving capability of multiple first driving subunits refers to the equivalent driving capability of the first driving subunit that is turned on among the multiple first driving subunits. Similarly, the driving capability of multiple second driving subunits refers to the equivalent driving capability of the second driving subunit that is turned on among the multiple second driving subunits.

[0067] In this embodiment, refer to Figure 8 The signal generator 100 includes: a first inverter group 211 for receiving a duty cycle control signal Duty; the first inverter group 211 includes a plurality of first adjustable inverters 201 connected in parallel, each first adjustable inverter 201 serving as a first driving sub-unit, and the duty cycle control signal Duty is used to selectively turn on the first adjustable inverters 201 in the first inverter group 211. A second inverter group 212, with its input connected to a second adjustment unit 122, is also used to receive the duty cycle control signal Duty; the second inverter group 212 includes a plurality of second adjustable inverters 202 connected in parallel, each second adjustable inverter 202 serving as a second driving sub-unit, and the duty cycle control signal Duty is used to selectively turn on the second adjustable inverters 202 in the second inverter group 212. The third driving subunit 213 includes a third adjusting inverter 203, whose input terminals are respectively connected to the output terminals of the first inverter group 211 and the second inverter group 212, and whose output terminal is used to output the intermediate test signal Pretest. Since the first inverter group 211 includes multiple parallel first inverters 201 and the second inverter group 212 includes multiple parallel second inverters 202, the more parallel inverters are turned on, the better the driving capability of the first inverter 201 or the second inverter 202 as a whole. That is, by controlling the number of first inverters 201 and second inverters 202 turned on in the first inverter group 211 and the second inverter group 212, the duty cycle of the intermediate test signal Pretest can be adjusted.

[0068] In a specific example, refer to Figure 8 and combined Figure 9 Assuming that the first inverter group 211 includes three first inverters 201 and the second inverter group 212 includes three second inverters 202, that is, the correction unit includes three first driving sub-units and three second driving sub-units, the conduction status of the first driving sub-units and the second driving sub-units can be divided into: (1) 3 first driving sub-units and 0 second driving sub-units are turned on, at which time the duty cycle of the intermediate test signal Pretest is the same as that of the first adjustment signal T1, and the duration of the high-level signal is tpH3; (2) 2 first driving sub-units and (2) 1 second driving subunit, at this time the intermediate test signal Pretest is biased towards the first adjustment signal T1, and the duration of the high level signal is tpH2; (3) 1 first driving subunit and 2 second driving subunits are turned on, at this time the intermediate test signal Pretest is biased towards the second adjustment signal T2, and the duration of the high level signal is tpH1; (4) 0 first driving subunits and 3 second driving subunits are turned on, at this time the duty cycle of the intermediate test signal Pretest and the second adjustment signal T2 is the same, and the duration of the high level signal is tpH0.

[0069] For amplitude adjustment module 103, refer to Figure 10 The amplitude adjustment module 103 includes: a first signal generation unit 113, configured to pull up and output a signal based on the intermediate test signal Pretest, and pull down and output a signal based on the inverted test signal Pretest-, to generate a reference test signal AltWck with the same phase as the intermediate test signal Pretest. A second signal generation unit 123 is configured to pull up and output a signal based on the inverted test signal Pretest-, and pull down and output a signal based on the intermediate test signal Pretest, to generate an inverted reference test signal AltWck- with the same phase as the inverted test signal Pretest-. The intermediate test signal Pretest and the inverted test signal Pretest- have the same amplitude but opposite phase. Specifically, the first driving transistor... <qn1>The gate is used to receive the intermediate test signal Pretest, and the drain is used to receive a high level. The second driver transistor... <qn2>The gate is used to receive the inverted test signal Pretest-, and the source is used to receive a low level. (First driver transistor) <qn1>The source and the second driving transistor <qn2>The drain of the transistor is connected to the output of the reference test signal AltWck. The amplitude control signal OBControl is used to adjust the first driving transistor. <qn1>The driving capability. It should be noted that, in this embodiment, the amplitude control signal OBControl adjusts the first driving transistor... <qn1>The driving capability of the first signal generating unit 113 can be changed by adjusting the driving capability of the second driving transistor; in other embodiments, the amplitude control signal can be configured to change the driving capability of the first signal generating unit by adjusting the driving capability of the second driving transistor or by jointly adjusting the first and second driving transistors. The second signal generating unit 123 includes a third driving transistor and a fourth driving transistor. The third driving transistor... <qn3>The gate is used to receive the intermediate test signal Pretest, and the drain is used to receive a high level. The fourth driver transistor... <qn4>The gate is used to receive the inverted test signal Pretest-, and the source is used to receive a low level. The third driver transistor... <qn3>The source and the fourth driving transistor <qn4>The drain of the transistor is connected to the output of the inverted reference test signal AltWck-. The amplitude control signal OBControl is used to adjust the third driving transistor. <qn3>The driving capability. It should be noted that, in this embodiment, the amplitude control signal OBControl adjusts the third driving transistor... <qn3>The driving capability of the second signal generation unit 123 can be changed by adjusting the driving capability of the fourth driving transistor or by jointly adjusting the third and fourth driving transistors. In other embodiments, the amplitude control signal OBControl can be configured to change the driving capability of the second signal generation unit by adjusting the driving capability of the fourth driving transistor or by jointly adjusting the third and fourth driving transistors. In one example, the amplitude control signal OBControl can change the driving capability of the first driving transistor by adjusting the driving capability of the fourth driving transistor or by adjusting the driving capability of the third driving transistor. <qn1>and the third drive tube <qn3>The aspect ratio or substrate voltage is used to adjust the first drive transistor. <qn1>and the third drive tube <qn3>The driving capability of the first driving transistor can be adjusted similarly to that of the second and fourth driving transistors. Furthermore, the first signal generation unit 113 also includes a first switching transistor. <b1>Second switching transistor <b2>and the first anti-interference transistor <b3>First switching transistor <b1>The source-coupled power node and the drain connected to the first driving transistor <qn1>The drain and gate of the second switching transistor are used to receive the amplitude control signal OBControl. <b2>The source is coupled to the ground node, and the drain is connected to the second driving transistor. <qn2>The drain and gate of the first signal generation unit 113 are used to receive the amplitude control signal OBControl, so that the unit is turned on after receiving the amplitude control signal OBControl, thereby reducing the power consumption of the first signal generation unit 113 during idle time; in addition, the first anti-interference transistor <b3>With the second drive tube <qn2>They are connected in parallel, with the gate used to receive the amplitude control signal OBControl. The amplitude control signal OBControl is also used to adjust the first anti-interference transistor. <b3>The driving capability, thereby adjusting the first anti-interference transistor. <b3>The anti-interference capability. Due to the first driving transistor <qn1>The driving capability can be adjusted based on the amplitude control signal OBControl, that is, when the first driving transistor... <qn1>The driving capability is large, and the amplitude of the output reference test signal AltWck is large, requiring strong anti-interference capability; when the first driving transistor <qn1>The driving capability is small, the amplitude of the output reference test signal AltWck is small, and the required anti-interference capability is weak; therefore, the first anti-interference transistor is adjusted accordingly by the amplitude control signal OBControl. <b3>The anti-interference capability is improved to ensure the accuracy of the reference test signal AltWck generated by the first signal generation unit 113, and to reduce the interference of the first anti-interference transistor. <b3>The power consumption. In this embodiment, the amplitude control signal OBControl is also used to enable the first switching transistor. <b1>Second switching transistor <b2>and the first anti-interference transistor <b3>And simultaneously adjust the first anti-interference transistor <b3>Driving capability; in other embodiments, the first switching transistor, the second switching transistor, and the first anti-interference transistor may be configured to be turned on based on an amplitude enable signal, wherein the amplitude enable signal is generated based on an amplitude control signal. The second signal generation unit 123 further includes: a third switching transistor. <b4>Fourth switching transistor <b5>Second anti-interference transistor <b6>The third switching transistor <b4>The source-coupled power node and the drain-connected fourth driver transistor <qn4>The drain and gate of the fourth switching transistor are used to receive the amplitude control signal OBControl. <b5>The source is coupled to the ground node, and the drain is connected to the fifth driving transistor. <qn5>The drain and gate of the second signal generation unit 123 are used to receive the amplitude control signal OBControl, so that the second signal generation unit 123 is turned on after receiving the amplitude control signal OBControl, thereby reducing the power consumption of the second signal generation unit 123 during idle time; in addition, the second anti-interference transistor <b6>With the fifth drive tube <qn5>They are connected in parallel, with the gate used to receive the amplitude control signal OBControl. The amplitude control signal OBControl is also used to adjust the second anti-interference transistor. <b6>The driving capability is adjusted, thereby adjusting the second anti-interference transistor. <b6>The anti-interference capability. Due to the third drive transistor <qn3>The driving capability can be adjusted based on the amplitude control signal OBControl, that is, when the third driving tube... <qn3>The driving capability is large, and the amplitude of the output inverted reference test signal AltWck- is relatively large, requiring strong anti-interference capability; when the third driving transistor <qn3>The driving capability is small, and the amplitude of the output inverted reference test signal AltWck- is small, requiring weak anti-interference capability; therefore, the second anti-interference transistor is adjusted accordingly by the amplitude control signal OBControl. <b6>To enhance the anti-interference capability of the second signal generation unit 123, ensuring the accuracy of the inverted reference test signal AltWck- generated by the second signal generation unit 123, and reducing the interference of the second anti-interference transistor. <b6>The power consumption. In this embodiment, the amplitude control signal OBControl is also used to enable the third switching transistor. <b4>Fourth switching transistor <b5>Second anti-interference transistor <b6>And simultaneously adjust the second anti-interference transistor <b6>Driving capability; in other embodiments, the third switching transistor, the fourth switching transistor, and the second anti-interference transistor can be configured to be turned on based on an amplitude enable signal, wherein the amplitude enable signal is generated based on an amplitude control signal. It should be noted that this embodiment uses the generation of a reference test signal AltWck by the first signal generation unit 113 and the generation of an inverted reference test signal AltWck- by the second signal generation unit 123 as an example for detailed explanation, and does not constitute a limitation on this embodiment. In other embodiments, the first signal generation unit can generate an inverted test signal, and the second signal generation unit can generate a test signal.

[0070] Specifically, in this embodiment, the amplitude adjustment module 103 further includes a signal generation unit 300, connected to the amplitude adjustment module 103 and the duty cycle correction module 102, configured to generate an inverted test signal Pretest- based on the intermediate test signal Pretest. In a specific example, the first signal generation unit 113 includes a first driving transistor. <qn1>Second drive tube <qn2>.

[0071] In this embodiment, the amplitude control signal OBControl is also used to control the input of the intermediate test signal Pretest and the inverted test signal Pretest-. In a specific example, the signal generator 100 further includes a first driving unit 301 and a second driving unit 302. The first driving unit 301 is used to receive the amplitude control signal OBControl and the intermediate test signal Pretest. The first driving unit 301 is configured to output either the intermediate test signal Pretest or the inverted test signal Pretest- if both the amplitude control signal OBControl and the intermediate test signal Pretest are received simultaneously. The second driving unit 302 is used to receive the amplitude control signal OBControl and the inverted test signal Pretest-. The second driving unit 302 is configured to output either the intermediate test signal Pretest or the inverted test signal Pretest- if both the amplitude control signal OBControl and the inverted test signal Pretest- are received simultaneously. Specifically, if the first driving unit 301 is based on a NAND gate design, and simultaneously receives the amplitude control signal OBControl and the intermediate test signal Pretest, it outputs an inverted test signal Pretest-; if the first driving unit 301 is based on an AND gate design, and simultaneously receives the amplitude control signal OBControl and the intermediate test signal Pretest, it outputs the intermediate test signal Pretest; if the second driving unit 302 is based on a NAND gate design, and simultaneously receives the amplitude control signal OBControl and the inverted test signal Pretest-, it outputs the intermediate test signal Pretest; if the second driving unit 302 is based on an AND gate design, and simultaneously receives the amplitude control signal OBControl and the inverted test signal Pretest-, it outputs the inverted test signal Pretest-. It should be noted that in this embodiment, the amplitude control signal OBControl is also used to enable the first driving unit 301 and the second driving unit 302; in other embodiments, the first driving unit and the driving unit can be configured to be turned on based on an amplitude enable signal, wherein the amplitude enable signal is generated based on the amplitude control signal. (Continue to refer to...) Figure 10 Since the devices of the first driving unit 301 and the second driving unit 302 are far apart from the first signal generating unit 113 and the second signal generating unit 123, the output intermediate test signal Pretest and the inverted test signal Pretest- may experience signal attenuation. In order to avoid this phenomenon, in some embodiments, the amplitude adjustment module 103 further includes: a first input adjustment unit 310, a second input adjustment unit 320, a third input adjustment unit 330 and a fourth input adjustment unit 340. The first input adjustment unit 310, connected to the first signal generation unit 113, is configured to drive the intermediate test signal Pretest provided to the first signal generation unit 113; the second input adjustment unit 320, connected to the second signal generation unit 123, is configured to drive the intermediate test signal Pretest provided to the second signal generation unit 123; the third input adjustment unit 330, connected to the first signal generation unit 113, is configured to drive the inverted test signal Pretest- provided to the first signal generation unit 113; and the fourth input adjustment unit 340, connected to the second signal generation unit 123, is configured to drive the inverted test signal Pretest- provided to the second signal generation unit 123. In one example, the first input adjustment unit 310, the second input adjustment unit 320, the third input adjustment unit 330, and the fourth input adjustment unit 340 include an even number of inverters. In another example, the first input adjustment unit 310, the second input adjustment unit 320, the third input adjustment unit 330, and the fourth input adjustment unit 340 include an odd number of inverters. In this case, the first input adjustment unit 310 is used to provide an inverted test signal Pretest- to the first signal generation unit 113; the second input adjustment unit 320 is used to provide an inverted test signal Pretest- to the second signal generation unit 123; the third input adjustment unit 330 is used to provide an intermediate test signal Pretest to the first signal generation unit 113; and the fourth input adjustment unit 340 is used to provide an intermediate test signal Pretest to the second signal generation unit 123.

[0072] refer to Figure 11 The intermediate test signal Pretest and the inverted test signal Pretest- are processed by the amplitude adjustment module 103 to generate the test signal AltWck and the inverted reference test signal AltWck-. They have the same phase and the amplitude is changed from V1 to V2 to meet the subsequent usage requirements.

[0073] For test circuit 400, refer to... Figure 12 A first integrating circuit 401 is configured to receive a first test signal Test1 and integrate the first test signal Test1 to output a first integrated signal FltNdT. A second integrating circuit 402 is configured to receive a second test signal Test2 and integrate the second test signal Test2 to output a second integrated signal FltNdC. The first test signal Test1 is the signal to be tested input to the test circuit 400. The first test signal Test1 and the second test signal Test2 are inverse signals. The voltage value of the first integrated signal FltNdT is the product of the duty cycle of the first test signal Test1 and the power supply amplitude. The voltage value of the second integrated signal FltNdC is the product of the duty cycle of the second test signal Test2 and the power supply amplitude. The comparator circuit 403 has one input terminal connected to the first integrating circuit 401 and the other input terminal connected to the second integrating circuit 402. The comparator circuit 403 is configured to compare the magnitudes of the first integrating signal FltNdT and the second integrating signal FltNdC. When the first integrating signal FltNdT is greater than the second integrating signal FltNdC, a high-level signal is output; when the second integrating signal FltNdC is greater than the first integrating signal FltNdT, a low-level signal is output.

[0074] Specifically, in this embodiment, reference is made to... Figure 13 The first integrating circuit 401 includes: a first filtering unit 501, a first preprocessing unit 510, and a second preprocessing unit 520. The first filtering unit 501 is used to integrate the received signal, specifically, to integrate the first test signal Test1. The first preprocessing unit 510 includes: a first conducting transistor. <dt1>First pre-charged P tube <yp1>and the first pre-charged N tube <yn1>The first conducting transistor <dt1>The drain of the transistor is used to receive the first test signal Test1, the source is connected to the input terminal of the first filter unit 501, and the gate is used to receive the first switch signal PassA; the first precharge P-tube... <yp1>The source is used to receive a high level, the drain is connected to the input terminal of the first filter unit 501, and the gate is used to receive the integration charging signal ClampF; the first pre-charge N-transistor <yn1>The source is used to receive a low level, the drain is connected to the input terminal of the first filter unit 501, and the gate is used to receive the first integrated discharge signal ClpGnd. Specifically, the first switch signal PassA is used to start the first preprocessing unit 510. When the first switch signal PassA turns on the first turn-on transistor... <dt1>The first filter unit 501 receives the first test signal Test1 and begins to integrate the first test signal Test1; the first pre-charged P-tube... <yp1>Based on the conduction of the integral charging signal ClampF, the input terminal of the first filter unit 501 is indirectly connected to a high level, thereby pulling up the potential of the input terminal of the first filter unit 501; the first pre-charge N-transistor <yn1>Based on the conduction of the first integral discharge signal ClpGnd, the input terminal of the first filter unit 501 is indirectly connected to a low level, thereby pulling down the potential of the input terminal of the first filter unit 501. The second preprocessing unit 520 includes: a second turn-on transistor. <dt2>Second pre-charged P tube <yp2>Second pre-charged N tube <yn2>The second conducting transistor <dt2>The drain of the second precharge P-tube is connected to the output of the first filter unit 501, the source is used to output the first integration signal FltNdT, and the gate is used to receive the second switching signal PassB. <yp2>The source of the second precharge N-transistor is used to receive a high level signal, the drain is connected to the output of the first filter unit 501, and the gate is used to receive the integration charging signal ClampF. <yn2>The drain is used to receive a low level and is connected to the input terminal of the first filter unit 501. The gate is used to receive the first integrated discharge signal ClpGnd. Specifically, the second switch signal PassB is used to start the second preprocessing unit 520. When the second switch signal PassB turns on the second turn-on transistor... <dt2>The first integrated signal FltNdT obtained by the first filter unit 501 can be output to the comparator circuit 403; the second pre-charged P-tube <yp2>Based on the conduction of the integral charging signal ClampF, the output terminal of the first filter unit 501 is indirectly connected to a high level, thereby raising the potential of the output terminal of the first filter unit 501; the second pre-charge N-transistor <yn2>Based on the conduction of the first integrated discharge signal ClpGnd, the output terminal of the first filter unit 501 is indirectly connected to a low level, thereby pulling down the potential of the output terminal of the first filter unit 501. The second integrating circuit 402 includes: a second filter unit 502, a third preprocessing unit 530, and a fourth preprocessing unit 540. The second filter unit 502 is used to integrate the received signal, specifically, it is used to integrate the second test signal Test2. The third preprocessing unit 530 includes: a third turn-on transistor. <dt3>Third pre-charged P tube <yp3>and the third pre-charged N tube <yn3>The third conducting transistor <dt3>The drain of the transistor is used to receive the second test signal Test2, the source is connected to the input of the second filter unit 502, and the gate is used to receive the first switch signal PassA; the third pre-charge P-tube... <yp3>The source and gate are connected and used to receive high levels; the drain is connected to the input of the second filter unit 502; the third pre-charged N-transistor <yn3>The source is used to receive a low level, the drain is connected to the input terminal of the second filter unit 502, and the gate is used to receive the second integral discharge signal Clamp. Specifically, the first switch signal PassA is used to start the third preprocessing unit 530. When the first switch signal PassA turns on the third turn-on transistor... <dt3>The second filter unit 502 receives the second test signal Test2 and begins to integrate the second test signal Test2; the third pre-charged P-tube... <yp3>When both the gate and source receive a high level, the third precharged P-transistor... <yp3>The transistor is in the off state to prevent a high level from pulling up the input of the second filter unit 502; the third pre-charged N-transistor... <yn3>Based on the conduction of the second integral discharge signal Clamp, the input terminal of the second filter unit 502 is indirectly connected to a low level, thereby pulling down the potential of the output terminal of the second filter unit 502. The fourth preprocessing unit 540 includes: a fourth turn-on transistor. <dt3>Fourth pre-charged P tube <yp4>and the fourth pre-charged N tube <yn4>Fourth conducting transistor <dt3>The drain is connected to the output of the second filter unit 502, the source is used to output the second integration signal FltNdC, and the gate is used to receive the second switching signal PassB. The fourth precharge P-tube... <yp4>The source and gate are connected and used to receive high levels; the drain is connected to the output of the second filter unit 502; the fourth precharged N-transistor <yn4>The source is used to receive a low level, the drain is connected to the output of the second filter unit 502, and the gate is used to receive the second integral discharge signal Clamp. Specifically, the second switch signal PassB is used to start the fourth preprocessing unit 540. When the second switch signal PassB turns on the fourth turn-on transistor... <dt3>The second integrated signal FltNdC obtained by the second filter unit 502 can be output to the comparator circuit 403; the fourth pre-charge P-tube <yp4>When both the gate and source receive a high level, the fourth precharged P-transistor... <yp4>The transistor is in the off state to prevent a high level from pulling up the output of the second filter unit 502; the fourth pre-charged N-transistor... <yn4>Based on the conduction of the second integral discharge signal Clamp, the output terminal of the second filter unit 502 is indirectly connected to a low level, thereby pulling down the potential of the output terminal of the second filter unit 502.

[0075] In this embodiment, the first filtering unit 501 is configured as a second-order RC filter; correspondingly, the second filtering unit 502 is also configured as a second-order RC filter. It should be noted that in other embodiments, the first filtering unit and the second filtering unit may be configured as first-order or higher-order RC filters simultaneously; correspondingly, in some embodiments, the orders of the RC filters of the first filtering unit and the second filtering unit may also be set to different orders.

[0076] Continue to refer to Figure 13 In this embodiment, the test circuit 400 further includes a first equalization circuit 521 and a second equalization circuit 522. One end of the first equalization circuit 521 is connected to the input terminal of the first integrating circuit 401, and the other end is connected to the input terminal of the second integrating circuit 402. The first equalization circuit 521 is configured to make the voltages at the input terminals of the first integrating circuit 401 and the second integrating circuit 402 the same based on the first equalization signal EqA. One end of the second equalization circuit 522 is connected to the output terminal of the first integrating circuit 401, and the other end is connected to the output terminal of the second integrating circuit 402. The second equalization circuit 522 is configured to make the initial voltages of the first integrating signal FltNdT and the second integrating signal FltNdC the same based on the second equalization signal EqB. Specifically, in this embodiment, the first equalization circuit 521 includes a first equalization P-tube. <ep1>and the first equalization N-tube <en1>Among them, the first equalization P-tube <ep1>The source and the first equalizing N-tube <en1>The drain of the first equalizing P-tube is coupled to the input terminal of the first integrating circuit 401. <ep1>The drain and the first equalizing N-tube <en1>The source of the first equalizing P-tube is coupled to the input of the second integrator circuit 402. <ep1>The gate and the first equalized N-transistor <en1>The gate of the equalization circuit 522 is used to receive the first equalization signal EqA. The second equalization circuit 522 includes: a second equalization P-transistor. <ep2>Second Equalization N-tube <en2>Among them, the second equalization P-tube <ep2>The source and the second equalization N-tube <en2>The drain of the second equalizing P-tube is coupled to the output of the first integrating circuit 401. <ep2>Drain and second equalization N-tube <en2>The source is coupled to the output of the second integrator circuit 402, and the second equalizing P-tube... <ep2>The gate and the second equalized N-transistor <en2>The gate of the first equalization circuit 521 is used to receive the second equalization signal EqB. One end of the first equalization circuit 521 is connected to the input terminal of the first filter unit 501, and the other end is connected to the input terminal of the second filter unit 502. The first equalization circuit 521 is configured to make the voltages at the input terminals of the first filter unit 501 and the second filter unit 502 the same based on the first equalization signal EqA. One end of the second equalization circuit 522 is connected to the second turn-on transistor. <dt2>The drain of one end is connected to the fourth conducting transistor at the other end. <dt4>The drain of the first equalization circuit 521; the second equalization circuit 522 is configured to make the initial voltages of the first integral signal FltNdT and the second integral signal FltNdC the same based on the second equalization signal EqB. It should be noted that for the first equalization circuit 521 and the second equalization circuit 522, the required equalization transistors can be set according to the actual needs of the test circuit after equalization. For example, if the input terminals of the first filter unit 501 and the second filter unit 502 are required to be at an intermediate level after equalization by the first equalization circuit 521, then the first equalization P-transistor is used. <ep1>The input potentials of the first filter unit 501 and the second filter unit 502 are balanced; if it is required that the inputs of the first filter unit 501 and the second filter unit 502 be at a low level after being balanced by the first equalization circuit 521, then the first equalization N-transistor is used. <en1>The input potentials of the first filter unit 501 and the second filter unit 502 are balanced; if the initial voltages of the first integral signal FltNdT and the second integral signal FltNdC are required to be at an intermediate level after being balanced by the second equalization circuit 522, then the second equalization P-tube is used. <ep2>The initial voltages of the first integral signal FltNdT and the second integral signal FltNdC are equalized. If the initial voltages of the first integral signal FltNdT and the second integral signal FltNdC are required to be low after being equalized by the second equalization circuit 522, then the second equalization N-transistor is used. <en2>The initial voltages of the first integral signal FltNdT and the second integral signal FltNdC are balanced. By balancing the input and output voltages of the first integral circuit 401 and the second integral circuit 402 before integration, the accuracy of the difference between the integrated values ​​of the first integral circuit 401 and the second integral circuit 402 is ensured, further guaranteeing the accuracy of the duty cycle of the subsequently acquired signal. In addition, during the subsequent output of the first integral signal FltNdT and the second integral signal FltNdC, the power consumption of the test circuit can be further reduced by activating the first equalization circuit 521 and the second equalization circuit 522.

[0077] For comparator circuit 403, refer to Figure 14 In this embodiment, the comparator circuit 403 includes: a first input P transistor. <sp1>The gate is used to receive the first integration signal FltNdT, and the source is connected to the third input P-channel transistor. <sp3>The drain is connected to the first comparator P-channel. <bp1>The source. The second input P-tube. <sp2>The gate is used to receive the second integration signal FltNdC, and the source is connected to the third input P-channel transistor. <sp3>The drain is connected to the second comparator P-channel. <bp2>The source of the third input P-tube. <sp3>The gate of the transistor is used to receive the comparator enable signal CkN, and the source is used to receive the high-level signal, i.e., the third input P-transistor. <sp3>As a high-level protection transistor for the comparator circuit 403, the comparator enable signal CkN provides the high level required for the comparator circuit 403 to operate. First input N-transistor <sn1>The gate is used to receive the comparator enable signal CkN, the source is used to receive a low-level signal, and the drain is connected to the first comparator P-transistor. <bp1>The source. The second input N-channel transistor. <sn2>The gate is used to receive the comparator enable signal CkN, the source is used to receive a low-level signal, and the drain is connected to the second comparator P-transistor. <bp2>The source. The third input N-channel transistor. <sn3>The gate is used to receive the comparator enable signal CkN, the source is used to receive a low-level signal, and the drain is connected to the first comparator N-transistor. <bn1>The drain of the fourth input N-channel transistor. <sn4>The gate is used to receive the comparator enable signal CkN, and the source is used to receive a low-level signal. The source is connected to the second comparator N-transistor. <bn2>The drain of the first comparison P-tube. <bp1>The drain connection of the first comparator N-channel transistor <bn1>The drain and gate of the second comparator N-channel transistor are connected. <bn2>The drain of the second comparison P-tube <bp2>The drain of the second comparator N-channel MOSFET is connected. <bn2>The drain and gate are connected to the first comparator N-channel transistor. <bn1>The drain of the first N-type transistor is compared. <bn1>The source is used to receive low-level signals, the drain is used to output the first comparator output signal OutP, and the gate is connected to the second comparator N-transistor. <bn2>The drain of the second comparator N-channel MOSFET <bn2>The source of the first comparator N-transistor is used to receive a low-level signal, the drain is used to output the second comparator output signal OutN, and the gate is connected to the drain of the first comparator N-transistor. One of the first comparator output signal OutP and the second comparator output signal OutN serves as the output signal of the comparator circuit 403, and the other serves as the inverted output signal. (First input P-transistor) <sp1>The gate is used to receive the first integration signal FltNdT, and the second input P-tube <sp2>The gate of the circuit is used to receive the second integral signal FltNdC. At this time, the comparator circuit 403 compares and amplifies the first integral signal FltNdT and the second integral signal FltNdC, generating a first comparison output signal OutP and a second comparison output signal OutN. One of the first comparison output signal OutP or the second comparison output signal OutN is used to characterize the comparison result of the first integral signal FltNdT and the second integral signal FltNdC, while the other serves as the inverted signal of the signal characterizing the comparison result. It should be noted that in this embodiment, the first comparison output signal OutP is used to characterize the comparison result of the first integral signal FltNdT and the second integral signal FltNdC, and the second comparison output signal OutN is used as the inverted signal of the first comparison output signal OutP for detailed explanation. This does not constitute a limitation of this embodiment. In other embodiments, the second comparison output signal can also be used to characterize the comparison result of the first integral signal and the second integral signal. More specifically, for the first integral signal FltNdT and the second integral signal FltNdC, if the integral value is greater than 1 / 2 * power supply amplitude, the corresponding first comparison output signal OutP is high; if the integral value is greater than 1 / 2 * power supply amplitude, the corresponding first comparison output signal OutP is low.

[0078] In this embodiment, reference Figure 15 The test circuit 400 further includes a pre-storage circuit 600, connected to the output of the comparator circuit 400, and receiving a first clock signal Clk and a second clock signal Clklat. The pre-storage circuit 600 is configured to pre-storage the level signal output by the comparator circuit 403 based on the first clock signal Clk, or to output the pre-storage level signal based on the second clock signal Clklat. The pre-storage circuit 600 ensures that the signal output timing of the test circuit 400 is consistent with the signal output timing of the memory to which the test circuit 400 belongs, thus ensuring that the test circuit 400 is applicable to different types of memory. The pre-storage circuit 600 includes a latch 601, one end of which is connected to the output of the comparator circuit 601, and the other end is used to receive the first clock signal Clk. The latch 601 is configured to generate an indication signal Result based on the output level of the comparator circuit when the first clock signal Clk is a valid signal. Register 602 has its input D connected to the output of latch 601, its clock input C for receiving the second clock signal Clklat, and its enable input RN for receiving the output enable signal ComEn. Register 602 is configured to output an indicator signal Result when both the second clock signal Clklat and the output enable signal ComEn are valid. Specifically, latch 601 includes: a first latch NAND gate, with one input for receiving the first comparison output signal OutP and the other input for receiving the first clock signal Clk; a second latch NAND gate, with one input for receiving the second comparison output signal OutN and the other input for receiving the first clock signal Clk; a third latch NAND gate, with one input connected to the output of the first latch NAND gate and the other input connected to the output of the fourth latch NAND gate; and a fourth latch NAND gate, with one input connected to the output of the second latch NAND gate and the other input connected to the output of the third latch NAND gate, and its output being used to output the indicator signal Result. It should be noted that in some embodiments, register 603 can be set using an FF register.

[0079] In this embodiment, reference Figure 16 The test circuit 400 also includes a control module 700, which is configured to provide control signals required for duty cycle detection by the first integrator 401, the second integrator 402, and the comparator 403 based on the control enable signal ControlEn. Specifically, the control signals required for duty cycle detection by the first integrator 401, the second integrator 402, and the comparator 403 include: a first equalization signal EqA and a second equalization signal EqB, an integrator charging signal ClampF, a first integrator discharging signal ClpGnd and a second integrator discharging signal Clamp, a first switch signal PassA and a second switch signal PassB, a comparator enable signal CkN, a first clock signal Clk, a second clock signal Clklat, and an output enable signal ComEn.

[0080] More specifically, see reference Figure 17 The control module 700 includes: a clock unit 710 configured to generate a control clock signal ControlClk based on a control enable signal ControlEn; a timing unit 720 connected to the output of the clock unit 710, storing a signal count value B, and configured to increment the control signal count value B by one when both the control enable signal ControlEn and the control clock signal ControlClk are valid; and a logic unit 730 connected to the output of the timing unit 720, storing the control signal corresponding to the signal count value B, and configured to provide the control signal corresponding to the signal count value B. Specifically, the clock unit 710 uses a ring oscillator, and the control enable signal ControlEn serves as the enable signal for the ring oscillator. The signal count value B is illustrated using a 7-bit signal, but this does not constitute a limitation of this embodiment. In actual configurations, the number of bits in the signal count value can be configured according to actual needs. In some embodiments, the timing unit 720 is further configured to receive a test control signal ProbeMode. When the test control signal ProbeMode is valid, at least one bit of new data bit Bmax is added to the signal count value B. The new data bit Bmax increases the change period of the control clock signal ControlClk by increasing the number of bits in the signal count value B, thereby more accurately controlling the memory in test mode.

[0081] Continue to refer to Figure 1 For the aforementioned signal detection system 1000, the test control signal DcmCtrl is set to at least three bits to form multiple signal values. The memory also includes a logic control signal circuit 1006, which is configured to identify the test control signal DcmCtrl and generate a corresponding conduction signal PathEns based on the test control signal DcmCtrl. The conduction signal PathEns is used to select the corresponding test module to form different test paths. Different test paths output the test signal to be tested to the test circuit 400 or the external test system 10.

[0082] Specifically, one of the values ​​of the test control signal DcmCtrl is configured to select the test circuit 400 to perform a duty cycle test on the reference test signal AltWck; at this time, the conduction signal PathEns is used to conduct the data transmission path between the signal generator 100 and the test circuit 400, so as to test whether the test function of the test circuit 400 is normal by using the reference test signal AltWck with a known duty cycle.

[0083] One value of the test control signal DcmCtrl is configured such that the control signal conversion module 1002 receives the reference test signal AltWck and provides the test circuit with a duty cycle test for the internal clock signal PWCK output by the signal conversion module 1002. At this time, the conduction signal PathEns is used to connect the data transmission path between the signal generator 100 and the signal conversion module 1002, as well as the data transmission path between the signal conversion module 1002 and the test circuit 400, so that the test circuit 400 can test whether the signal conversion module 1002 functions correctly.

[0084] One value of the test control signal DcmCtrl is configured to select the serial read clock Clk_R2 output by the read clock path 1004 based on the test circuit 400 for duty cycle testing; at this time, the conduction signal PathEns is used to conduct the data transmission path between the signal generator 100 and the signal conversion module 1002, the data transmission path between the signal conversion module 1002 and the read clock path 1004, and the data transmission path between the read clock path 1004 and the test circuit 400, so as to test whether the function of the read clock path 1004 is normal through the test circuit 400.

[0085] One of the values ​​of the test control signal DcmCtrl is configured to select the duty cycle test of the first indicator signal Pup and the second indicator signal Pdn output by the write clock path 1003 based on the test circuit 400; at this time, the conduction signal PathEns is used to conduct the data transmission path between the signal generator 100 and the signal conversion module 1002, the data transmission path between the signal conversion module 1002 and the write clock path 1003, and the data transmission path between the write clock path 1003 and the test circuit 400, so as to repeatedly test and adjust the generation of equidistant parallel write clock Clk_W.

[0086] In some embodiments, the memory further includes a clock driver 1005, with its input terminal connected to the output terminal of the signal conversion module 1002 and its output terminal connected to the test circuit 400. The driver is used to drive the internal clock signal PWCK output by the signal conversion module 1002 to prevent significant signal attenuation during the transmission of the internal clock signal PWCK to the test circuit 400 for testing, thereby ensuring the accuracy of the test results of the test circuit 400.

[0087] In some embodiments, the memory further includes: a first output component 1100, connected to a duty cycle correction module 102 (reference). Figure 2 The output terminal of the first output component 1100 is used to output the intermediate test signal Pretest to the external test system 10. The external test system 10 is used to test whether the intermediate test signal Pretest meets the preset duty cycle. That is, the first output component 1100 is used to acquire the intermediate test signal Pretest that meets the preset duty cycle. It should be noted that in some embodiments, during the process of outputting the intermediate test signal Pretest to the external test system, the intermediate test signal Pretest is also divided into frequencies to facilitate the external test system 10 in detecting the frequency of the intermediate test signal Pretest, thereby reducing the detection accuracy requirements of the external test system 10 for the signal frequency.

[0088] The test logic for testing the frequency divider 1013 using test circuit 400 is as follows: (Refer to...) Figure 18 The write divider 1013 includes a four-phase clock generation circuit 801, configured to receive an internal clock signal PWCK and generate a parallel write clock Clk_W based on the internal clock signal PWCK. In this embodiment, the parallel write clock Clk_W consists of a first clock signal WCK2TF0, a second clock signal WCK2TR0, a third clock signal WCK2TR1, and a fourth clock signal WCK2TF1, all with the same period. The write clock tree 1023 includes a signal delay circuit 802, configured to receive the first clock signal WCK2TF0. The second clock signal WCK2TR0, the third clock signal WCK2TR1, the fourth clock signal WCK2TF1, and the delay command are configured to delay the first clock signal WCK2TF0, the second clock signal WCK2TR0, the third clock signal WCK2TR1, and the fourth clock signal WCK2TF1 respectively based on the delay command, and the delays of the first clock signal WCK2TF0, the second clock signal WCK2TR0, the third clock signal WCK2TR1, and the fourth clock signal WCK2TF1 are different.

[0089] In one example, the signal delay inside the four-phase clock generation circuit 801 is relatively large, corresponding to a larger K value for the four-phase clock generation circuit 801. In this case, the period of the generated first clock signal WCK2TR0 can be 5 times or more the period of the internal clock signal PWCK. In another example, the signal delay inside the four-phase clock generation circuit 801 is relatively small, corresponding to a smaller K value for the four-phase clock generation circuit 801. In this case, the period of the generated first clock signal WCK2TR0 can be 4 times or less the period of the internal clock signal PWCK. (Reference) Figure 19 and Figure 20 It should be noted that memory generally uses dual-edge sampling, meaning data is sampled on both the rising and falling edges of the signal, i.e., data is transmitted twice per clock cycle. After being split into four-phase clocks, if sampling is performed once per clock cycle, this corresponds to the sampling number of the internal clock signal PWCK for two cycles. Therefore, in this embodiment, the example of the period of the first clock signal WCK2TR0 being twice the period of the internal clock signal PWCK (i.e., K=2) is used for specific explanation and does not constitute a limitation on this embodiment. In specific applications, the signal delay of the four-phase clock generation circuit 801 can be set according to the required clock frequency and the frequency of the memory's internal clock signal PWCK. It can be understood that since the periods of the first clock signal WCK2TR0, the second clock signal WCK2TF0, the third clock signal WCK2TR1, and the fourth clock signal WCK2TF1 are the same, the periods of the second clock signal WCK2TF0, the third clock signal WCK2TR1, and the fourth clock signal WCK2TF1 are also twice the period of the internal clock signal WCK.

[0090] The signal delay circuit 802 delays the first clock signal WCK2TR0 to generate a first delayed clock signal WCK2TWRTR0, delays the second clock signal WCK2TF0 to generate a second delayed clock signal WCK2TWRTF0, delays the third clock signal WCK2TR1 to generate a third delayed clock signal WCK2TWRTR1, and delays the fourth clock signal WCK2TF1 to generate a fourth delayed clock signal WCK2TWRTF1. (Reference) Figure 19 and Figure 20 The delay of the second delayed clock signal WCK2TWRTF0 relative to the first delayed clock signal WCK2TWRTR0 is Ts1, the delay of the third delayed clock signal WCK2TWRTR1 relative to the second delayed clock signal WCK2TWRTF0 is Ts2, the delay of the fourth delayed clock signal WCK2TWRTF1 relative to the third delayed clock signal WCK2TWRTR1 is Ts3, and the delay of the first delayed clock signal WCK2TWRTR0 relative to the fourth delayed clock signal WCK2TWRTF1 is Ts4.

[0091] In this embodiment, the delay commands include a first delay command cmR0, a second delay command cmF0, a third delay command cmR1, and a fourth delay command cmF1. Correspondingly, the signal delay circuit 802 includes a first delay sub-circuit 901, a second delay sub-circuit 902, a third delay sub-circuit 903, and a fourth delay sub-circuit 904.

[0092] Specifically, the first delay sub-circuit 901 is used to delay the first clock signal WCK2TF0 according to the first delay command cm R0 to generate the first delayed clock signal WCK2TWRTR0; the second delay sub-circuit 902 is used to delay the second clock signal WCK2TF0 according to the second delay command cm F0 to generate the second delayed clock signal WCK2TWRTF0; the third delay sub-circuit 903 is used to delay the third clock signal WCK2TR1 according to the third delay command cm R1 to generate the third delayed clock signal WCK2TWRTR1; and the fourth delay sub-circuit 904 is used to delay the fourth clock signal WCK2TF1 according to the fourth delay command cm F1 to generate the fourth delayed clock signal WCK2TWRTF1.

[0093] In one example, the first delay sub-circuit 901 includes: a first delay inverter 811, whose input is used to receive a first clock signal WCK2TF0; a first second delay inverter 812, whose input is connected to the first delay inverter 811; a first third delay inverter 813, whose input is connected to the first second delay inverter 812; a first fourth delay inverter 814, whose input is connected to the first third delay inverter 813, and whose output is used to output the delayed first clock signal, i.e., the first delayed clock signal WCK2TWRTR0; a first charge / discharge module 851, one end of which is connected to the output of the first delay inverter 811, and the other end is coupled to a low-potential power supply node, which is used to receive a low level; and a fifth charge / discharge module 855, one end of which is connected to the output of the first second delay inverter 812, and the other end is coupled to a low-potential power supply node; the charge / discharge capabilities of the first charge / discharge module 851 and the fifth charge / discharge module 855 are adjusted according to the first delay command cm R0. It should be noted that, in other embodiments, the other end of the first charge / discharge module 851 and the fifth charge / discharge module 855 may also be coupled to a high-potential power node, which is used to receive a high level.

[0094] In one example, the second delay sub-circuit 902 includes: a second first delay inverter 821, whose input is used to receive the second clock signal WCK2TF0; a second second delay inverter 822, whose input is connected to the second first delay inverter 821; a second third delay inverter 823, whose input is connected to the second second delay inverter 822; a second fourth delay inverter 824, whose input is connected to the second third delay inverter 823, and whose output is used to output the delayed second clock signal, i.e., the second delayed clock signal WCK2TWRTF0; a second charge / discharge module 852, one end of which is connected to the output of the second first delay inverter 821, and the other end is coupled to a low-potential power supply node, which is used to receive a low level; and a sixth charge / discharge module 856, one end of which is connected to the output of the second second delay inverter 822, and the other end is coupled to a low-potential power supply node; the charge / discharge capabilities of the second charge / discharge module 852 and the sixth charge / discharge module 856 are adjusted according to the second delay command cm F0. It should be noted that, in other embodiments, the other end of the second charge / discharge module 852 and the sixth charge / discharge module 856 may also be coupled to a high-potential power node, which is used to receive a high level.

[0095] In one example, the third delay sub-circuit 903 includes: a third first delay inverter 831, whose input is used to receive the third clock signal WCK2TR1; a third second delay inverter 832, whose input is connected to the third first delay inverter 831; a third third delay inverter 833, whose input is connected to the third second delay inverter 832; a third fourth delay inverter 834, whose input is connected to the third third delay inverter 833, and whose output is used to output the delayed third clock signal, i.e., the third delayed clock signal WCK2TWRTR1; a third charge / discharge module 853, one end of which is connected to the output of the third first delay inverter 831, and the other end is coupled to a low-potential power supply node, which is used to receive a low level; and a seventh charge / discharge module 857, one end of which is connected to the output of the third second delay inverter 832, and the other end is coupled to a low-potential power supply node; the charge / discharge capabilities of the third charge / discharge module 853 and the seventh charge / discharge module 857 are adjusted according to the third delay command cm R1. It should be noted that, in other embodiments, the other end of the third charge / discharge module 853 and the seventh charge / discharge module 857 can also be coupled to a high-potential power node, which is used to receive a high level.

[0096] In one example, the fourth delay sub-circuit 904 includes: a fourth first delay inverter 841, whose input is used to receive the fourth clock signal WCK2TF1; a fourth second delay inverter 842, whose input is connected to the fourth first delay inverter 841; a fourth third delay inverter 843, whose input is connected to the fourth second delay inverter 842; a fourth fourth delay inverter 844, whose input is connected to the fourth third delay inverter 843, and whose output is used to output the delayed fourth clock signal, i.e., the fourth delayed clock signal WCK2TWRTF1; a fourth charge / discharge module 854, one end of which is connected to the output of the fourth first delay inverter 841, and the other end is coupled to a low-potential power supply node, which is used to receive a low level; and an eighth charge / discharge module 858, one end of which is connected to the output of the fourth second delay inverter 842, and the other end is coupled to a low-potential power supply node; the charge / discharge capabilities of the fourth charge / discharge module 854 and the eighth charge / discharge module 858 are adjusted according to the fourth delay command cm F1. It should be noted that, in other embodiments, the other end of the fourth charge / discharge module 854 and the eighth charge / discharge module 858 can also be coupled to a high-potential power node, which is used to receive a high level.

[0097] Specifically, for the first charging / discharging module 851, the second charging / discharging module 852, the third charging / discharging module 853, and the fourth charging / discharging module 854, the more charge they can store, the faster the discharge speed, and the higher the delay for the rising edge of the signal; for the fifth charging / discharging module 855, the sixth charging / discharging module 856, the seventh charging / discharging module 857, and the eighth charging / discharging module 858, the more charge they can store, the faster the charging speed, and the higher the delay for the falling edge of the signal; by adjusting the charging / discharging capabilities of the first charging / discharging module 851, the second charging / discharging module 852, the third charging / discharging module 853, the fourth charging / discharging module 854, the fifth charging / discharging module 855, the sixth charging / discharging module 856, the seventh charging / discharging module 857, and the eighth charging / discharging module 858, the first clock signal WCK2TF0, the second clock signal WCK2TR0, the third clock signal WCK2TR1, and the fourth clock signal WCK2TF1 are delayed to different degrees.

[0098] Meanwhile, since the first charging / discharging module 851 and the fifth charging / discharging module 855 are controlled by the same delay command, that is, the rising and falling edges of the first clock signal WCK2TF0 are delayed to the same extent, so as to ensure that the duty cycle of the first clock signal WCK2TF0 is not changed; since the second charging / discharging module 852 and the sixth charging / discharging module 856 are controlled by the same delay command, that is, the rising and falling edges of the second clock signal WCK2TR0 are delayed to the same extent, so as to ensure that the duty cycle of the second clock signal WCK2TR0 is not changed. The third charging / discharging module 853 and the seventh charging / discharging module 857 are controlled by the same delay command, that is, the rising edge and falling edge of the third clock signal WCK2TR1 are delayed to the same extent to ensure that the duty cycle of the third clock signal WCK2TR1 is not changed; the fourth charging / discharging module 854 and the eighth charging / discharging module 858 are controlled by the same delay command, that is, the rising edge and falling edge of the fourth clock signal WCK2TF1 are delayed to the same extent to ensure that the duty cycle of the fourth clock signal WCK2TF1 is not changed.

[0099] In this embodiment, the first charging / discharging module 851, the second charging / discharging module 852, the third charging / discharging module 853, the fourth charging / discharging module 854, the fifth charging / discharging module 855, the sixth charging / discharging module 856, the seventh charging / discharging module 857, and the eighth charging / discharging module 858 are implemented using capacitors. The charging / discharging capability of the capacitors depends on the maximum stored charge C and the discharge current I. Specifically, the discharge current I is controlled by a bias transistor, and the delay command cm controls the delay performance of the corresponding first charging / discharging module 851, second charging / discharging module 852, third charging / discharging module 853, fourth charging / discharging module 854, fifth charging / discharging module 855, sixth charging / discharging module 856, seventh charging / discharging module 857, and eighth charging / discharging module 858 by controlling the discharge current I.

[0100] It should be noted that, in some embodiments, the low-level received by the low-potential power supply node coupled to the first delay sub-circuit 901, the second delay sub-circuit 902, the third delay sub-circuit 903, and the fourth delay sub-circuit 904 is adjustable, thereby realizing the overall adjustment of the charging and discharging capabilities of the first delay sub-circuit 901, the second delay sub-circuit 902, the third delay sub-circuit 903, and the fourth delay sub-circuit 904.

[0101] Ideally, the signal delay circuit 802 can generate four-phase clock signals with equal intervals (Ts1=Ts2=Ts3=Ts4). However, due to actual device deviations and other reasons, the corresponding delays of the four-phase clock signals generated by the signal delay circuit 802 are not equal, that is, it is impossible to guarantee that Ts1=Ts2=Ts3=Ts4.

[0102] The signal loading circuit 805 generates a first indicator signal Pup and a second indicator signal Pdn based on the first delayed clock signal WCK2TWRTR0, the second delayed clock signal WCK2TWRTF0, the third delayed clock signal WCK2TWRTR1, and the fourth delayed clock signal WCK2TWRTF1. Specifically, refer to... Figure 18 The signal loading module 805 includes: a data generation module 803, used to generate four-bit first loading data Data1 and second loading data Data2; and a data loading module 804, used to sample the first loading data Data1 according to a delayed first clock signal, a second clock signal, a third clock signal, and a fourth clock signal to generate a first indication signal Pup; wherein, when the first loading data Data1 corresponding to the clock signal sampling edge is high, the generated first indication signal Pup is high, and when the first loading data Data1 corresponding to the clock signal sampling edge is low, the generated first indication signal Pup is low; the data loading module 804 is also used to sample the second loading data Data2 according to the delayed first clock signal, second clock signal, third clock signal, and fourth clock signal to generate a second indication signal Pdn; wherein, when the second loading data Data2 corresponding to the clock signal sampling edge is high, the generated second indication signal Pdn is high. For the data generation module 803, the number of bits in the generated first loaded data Data1 and second loaded data Data2 is equal to the number of clock signals driving the data loading module 804. Since the data loading module 804 can be driven by four clock signals in this embodiment, the first loaded data Data1 and the second loaded data Data2 are four bits. In some embodiments, the data generation module 803 is controlled to start based on a generation control signal. By controlling the data generation module to start only when in use, the power consumption of the clock generation circuit is saved.

[0103] The test circuit 400, connected to the signal loading circuit 805, is configured to perform a duty cycle test based on a first indicator signal Pup and a second indicator signal Pdn. Specifically, the output signal of the test circuit 400 is used to characterize the magnitude relationship between the first indicator signal Pup and the second indicator signal Pdn. If the output signal of the test circuit is high, then the first indicator signal Pup is greater than the second indicator signal Pdn; if the output signal of the test circuit is low, then the second indicator signal Pdn is not less than the first indicator signal Pup.

[0104] Specifically, a first indication signal Pup is generated based on the first delayed clock signal WCK2TWRTR0, the second delayed clock signal WCK2TWRTF0, and the third delayed clock signal WCK2TWRTR1 obtained by delay; a second indication signal Pdn is generated based on the third delayed clock signal WCK2TWRTR1, the fourth delayed clock signal WCK2TWRTF1, and the first delayed clock signal WCK2TWRTR0; combined with Figure 19 and Figure 20 It can be seen that the duty cycle of the first indicator signal Pup is (Ts1+Ts2) / (Ts1+Ts2+Ts3+Ts4), and the duty cycle of the second indicator signal Pdn is (Ts3+Ts4) / (Ts1+Ts2+Ts3+Ts4). If the output signal of the test circuit 400 is high, it proves that the duty cycle of the first indicator signal Pup is greater than the duty cycle of the second indicator signal Pdn, that is, (Ts1+Ts2)>(Ts3+Ts4). At this time, the delay of the first clock signal can be increased while the delay of the second and third clock signals can be decreased, that is, Ts1+Ts2 can be decreased and Ts3+Ts4 can be increased, so that (Ts1+Ts2)=(Ts3+Ts4), and the sum of Ts1+Ts2+Ts3+Ts4 remains unchanged, so as not to change the overall period of the four-phase clock signal. If the output signal of the test circuit 400 is low, it proves that the duty cycle of the first indicator signal Pup is less than the duty cycle of the second indicator signal Pdn, i.e., (Ts1+Ts2) < (Ts3+Ts4). At this time, the delay of the first clock signal can be reduced while the delay of the second and third clock signals can be increased, i.e., Ts1+Ts2 can be increased and Ts3+Ts4 can be decreased, (Ts1+Ts2) = (Ts3+Ts4), and the sum of Ts1+Ts2+Ts3+Ts4 remains unchanged, so as not to change the overall period of the four-phase clock signal. It should be noted that the above example does not show the sampling of the delayed clock signal that is independent of the duty cycle result for the first indicator signal Pup and the second indicator signal Pdn. In practical applications, the first indicator signal Pup and the second indicator signal Pdn are both based on the first delayed clock signal WCK2TWRTR0, the second delayed clock signal WCK2TWRTF0, the third delayed clock signal WCK2TWRTR1, and the fourth delayed clock signal WCK2TWRTF1.

[0105] A third indicator signal Pup is generated based on the delayed first clock signal WCK2TWRTR0 and the second clock signal WCK2TWRTF0; a fourth indicator signal Pdn is generated based on the delayed second clock signal WCK2TWRTF0 and the delayed third clock signal WCK2TWRTR1; combined with Figure 19 and Figure 20 It can be seen that the duty cycle of the third indicator signal Pup is Ts1 / (Ts1+Ts2) and the duty cycle of the fourth indicator signal Pdn is Ts2 / (Ts1+Ts2). If the output signal of the test circuit 400 is high, it proves that the duty cycle of the third indicator signal Pup is greater than the duty cycle of the fourth indicator signal Pdn, that is, Ts1>Ts2. At this time, the delay of the first clock signal can be increased and the delay of the second clock signal can be decreased, that is, Ts1 can be decreased and Ts2 can be increased so that Ts1=Ts2, and the total delay of the first clock signal and the second clock signal remains unchanged, that is, the sum of Ts1+Ts2 remains unchanged, so as to ensure that (Ts1+Ts2)=(Ts3+Ts4). If the output signal of test circuit 400 is low, it proves that the duty cycle of the third indicator signal Pup is less than the duty cycle of the fourth indicator signal Pdn, i.e., Ts1 < Ts2. In this case, the delay of the first clock signal can be reduced and the delay of the second clock signal increased, i.e., Ts1 increased and Ts2 decreased, so that Ts1 = Ts2, and the total delay of the first and second clock signals remains unchanged, i.e., the sum of Ts1 + Ts2 remains unchanged, to ensure (Ts1 + Ts2) = (Ts3 + Ts4). It should be noted that the above example does not demonstrate the sampling of delayed clock signals for the third indicator signal Pup and the fourth indicator signal Pdn, which are independent of the duty cycle result. In practical applications, both the third indicator signal Pup and the fourth indicator signal Pdn are based on the first delayed clock signal WCK2TWRTR0, the second delayed clock signal WCK2TWRTF0, the third delayed clock signal WCK2TWRTR1, and the fourth delayed clock signal WCK2TWRTF1.

[0106] A fifth indicator signal Pup is generated based on the delayed third clock signal WCK2TWRTR1 and the fourth clock signal WCK2TWRTF1, and a sixth indicator signal Pdn is generated based on the delayed fourth clock signal WCK2TWRTF1 and the first clock signal WCK2TWRTR0; combined with Figure 19 and Figure 20 It can be seen that the duty cycle of the fifth indicator signal Pup is Ts3 / (Ts3+Ts4) and the duty cycle of the sixth indicator signal Pdn is Ts4 / (Ts3+Ts4). If the output signal of the test circuit 400 is high, it proves that the duty cycle of the fifth indicator signal Pup is greater than the duty cycle of the sixth indicator signal Pdn, that is, Ts3>Ts4. At this time, the delay of the third clock signal can be increased and the delay of the fourth clock signal can be decreased, that is, Ts3 can be decreased and Ts4 can be increased so that Ts3=Ts4, and the total delay of the third clock signal and the fourth clock signal remains unchanged, that is, the sum of Ts3+Ts4 remains unchanged, so as to ensure that (Ts1+Ts2)=(Ts3+Ts4). If the output signal of test circuit 400 is low, it proves that the duty cycle of the fifth indicator signal Pup is less than that of the sixth indicator signal Pdn, i.e., Ts3 < Ts4. In this case, the delay of the third clock signal can be increased and the delay of the fourth clock signal can be decreased, i.e., Ts3 can be increased and Ts4 decreased, so that Ts3 = Ts4, and the total delay of the third and fourth clock signals remains unchanged, i.e., the sum of Ts3 + Ts4 remains unchanged, to ensure that (Ts1 + Ts2) = (Ts3 + Ts4). It should be noted that the above example does not show the sampling of delayed clock signals that are independent of the duty cycle result for the fifth indicator signal Pup and the sixth indicator signal Pdn. In practical applications, both the fifth indicator signal Pup and the sixth indicator signal Pdn are based on the first delayed clock signal WCK2TWRTR0, the second delayed clock signal WCK2TWRTF0, the third delayed clock signal WCK2TWRTR1, and the fourth delayed clock signal WCK2TWRTF1.

[0107] It should be noted that the above example describes the case where the delays of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal can all be adjusted. In actual implementation, since the rising edge of the first clock signal WCK2TR0 needs to be aligned with the rising edge of the internal clock signal WCK_T, the delay of the first clock signal WCK2TR0 cannot be adjusted. In this case, ignoring the change in the delay of the first clock signal WCK2TR0, the above example still applies.

[0108] Continue to refer to Figure 1 In some embodiments, the memory further includes a second output component 1200, connected to the output of the write clock tree 1023, for outputting the parallel write clock Clk_W to an external test system 10. The external test system 10 is used to test whether the parallel write clock Clk_W is an equidistant clock, that is, after testing and adjusting the write clock tree 1023, the signal loading circuit 805 and the test circuit 400, it determines whether the actually obtained parallel write clock Clk_W is an equidistant clock.

[0109] At this time, one of the test control signals is configured to control the memory to output the parallel write clock from write clock path 1003 to the external test system 10 for duty cycle detection; at this time, the conduction signal PathEns is used to conduct the data transmission path between signal generator 100 and signal conversion module 1002, the data transmission path between signal conversion module 1002 and write clock path 1003, and the data transmission path between write clock path 1003 and external test system, so as to determine whether the parallel write clock Clk_W is an equidistant clock.

[0110] In some embodiments, the signal conversion module 1002 is further configured to receive an external clock signal WCK with a preset duty cycle, and to generate an internal clock signal PWCK based on the external clock signal WCK, wherein the external clock signal WCK is a clock signal required for the normal operation of the memory.

[0111] Accordingly, refer to Figure 1 The memory also includes a selection module 1001, which has a first input terminal, a second input terminal, and an output terminal. The first input terminal is used to receive a reference test signal AltWck, the second input terminal is used to receive an external clock signal WCK, the output terminal is connected to the input terminal of the signal conversion module 1002, and the control terminal is used to receive a test control signal DcmCtrl, and connect the first input terminal and the output terminal or the second input terminal and the output terminal based on the test control signal DcmCtrl.

[0112] In one example, refer to Figure 21 The first input MOSFET has its source connected to the output of the amplitude adjustment module 103, and its drain used to output the reference test signal AltWck. The second input MOSFET has its source connected to the drain of the first input MOSFET, and its drain connected to the source of the first input MOSFET. The third input MOSFET has its source used to receive the external clock signal WCK, and its drain connected to the drain of the first input MOSFET, and is used to output the external clock signal WCK. The gates of the first, second, and third input MOSFETs are used to receive the test control signal DcmCtrl, and the signals received by the gates of the first and second input MOSFETs are inverted signals, that is, the gate of one of the first and second input MOSFETs is used to receive the test control signal DcmCtrl, and the gate of the other is used to receive the inverted test control signal DcmCtrl-. In some embodiments, only one of the first and third input MOSFETs receives the clock signal, and both can be turned on simultaneously; in other embodiments, only one of the first and third input MOSFETs is turned on.

[0113] Accordingly, continue to refer to Figure 1 For the test control signal DcmCtrl, the details are as follows:

[0114] One of the values ​​of the test control signal DcmCtrl is configured to control the memory to output the generated intermediate test signal Pretest to the external test system for duty cycle detection; at this time, the conduction signal PathEns is used to conduct the data transmission path between the signal generator 100 and the external test system 10 to obtain the reference test signal AltWck whose duty cycle meets the preset duty cycle.

[0115] One of the values ​​of the test control signal DcmCtrl is configured to select the duty cycle test of the reference test signal AltWck based on the test circuit; at this time, the conduction signal PathEns is used to conduct the data transmission path between the signal generator 100 and the test circuit 400, so as to test whether the test function of the test circuit 400 is normal by using the reference test signal AltWck with a known duty cycle.

[0116] One value of the test control signal DcmCtrl is configured to select the internal clock signal PWCK output by the signal conversion module 1002 based on the reference test signal AltWck for duty cycle testing based on the test circuit 400. At this time, the conduction signal PathEns is used to conduct the data transmission path between the signal generator 100 and the selection module 1001, the data transmission path between the selection module 1001 and the signal conversion module 1002, and the data transmission path between the signal conversion module 1002 and the test circuit 400, so as to test whether the function of the signal conversion module 1002 is normal when it is working based on the reference test signal AltWck through the test circuit 400.

[0117] One value of the test control signal DcmCtrl is configured to select the duty cycle test of the internal clock signal PWCK output by the signal conversion module 1002 based on the external clock signal WCK, based on the test circuit 400. At this time, the conduction signal PathEns is used to conduct the data transmission path between the selection module 1001 and the data pad (used to receive the external clock signal WCK), the data transmission path between the selection module 1001 and the signal conversion module 1002, and the data transmission path between the signal conversion module 1002 and the test circuit 400, so as to test whether the function of the signal conversion module 1002 is normal when it is working based on the external clock signal WCK through the test circuit 400.

[0118] One value of the test control signal DcmCtrl is configured to select the serial read clock Clk_R2 output by the read clock path 1004 based on the reference test signal AltWck for duty cycle testing based on the test circuit 400. At this time, the conduction signal PathEns is used to conduct the data transmission path between the signal generator 100 and the selection module 1001, the data transmission path between the selection module 1001 and the signal conversion module 1002, the data transmission path between the signal conversion module 1002 and the read clock path 1004, and the data transmission path between the read clock path 1004 and the test circuit 400, so as to test whether the function of the read clock path 1004 based on the reference test signal AltWck is normal through the test circuit 400.

[0119] One value of the test control signal DcmCtrl is configured to select the serial read clock Clk_R2 output by the external clock signal WCK based on the test circuit 400 for duty cycle testing of the read clock path 1004. At this time, the conduction signal PathEns is used to conduct the data transmission path between the selection module 1001 and the data pad (used to receive the external clock signal WCK), the data transmission path between the selection module 1001 and the signal conversion module 1002, the data transmission path between the signal conversion module 1002 and the read clock path 1004, and the data transmission path between the read clock path 1004 and the test circuit 400, so as to test whether the function of the read clock path 1004 based on the external clock signal WCK is normal through the test circuit 400.

[0120] One value of the test control signal DcmCtrl is configured to select the first indicator signal Pup and the second indicator signal Pdn output by the write clock path 1003 based on the reference test signal AltWck for duty cycle testing based on the test circuit 400. At this time, the conduction signal PathEns is used to conduct the data transmission path between the signal generator 100 and the selection module 1001, the data transmission path between the selection module 1001 and the signal conversion module 1002, the data transmission path between the signal conversion module 1002 and the write clock path 1003, and the data transmission path between the write clock path 1003 and the test circuit 400, so as to repeatedly test and adjust the equidistant parallel write clock Clk_W generated based on the reference test signal AltWck.

[0121] One value of the test control signal DcmCtrl is configured to select the first indicator signal Pup and the second indicator signal Pdn output by the write clock path 1003 based on the external clock signal WCK for duty cycle testing based on the test circuit 400. At this time, the conduction signal PathEns is used to conduct the data transmission path between the selection module 1001 and the data pad (used to receive the external clock signal WCK), the data transmission path between the selection module 1001 and the signal conversion module 1002, the data transmission path between the signal conversion module 1002 and the write clock path 1003, and the data transmission path between the write clock path 1003 and the test circuit 400, so as to repeatedly test and adjust the equidistant parallel write clock Clk_W generated based on the external clock signal WCK.

[0122] One value of the test control signal DcmCtrl is configured to control the memory to output the parallel write clock Clk_W generated based on the reference test signal AltWck to the external test system 10 for duty cycle detection. At this time, the conduction signal PathEns is used to conduct the data transmission path between the signal generator 100 and the selection module 1001, the data transmission path between the selection module 1001 and the signal conversion module 1002, the data transmission path between the signal conversion module 1002 and the write clock path 1003, and the data transmission path between the write clock path 1003 and the external test system, so as to determine whether the parallel write clock Clk_W generated based on the reference test signal AltWck is an equidistant clock.

[0123] One value of the test control signal DcmCtrl is configured to control the memory to output the parallel write clock Clk_W generated based on the external clock signal WCK to the external test system 10 for duty cycle detection; at this time, the conduction signal PathEns is used to conduct the data transmission path between the selection module 1001 and the data pad (used to receive the external clock signal WCK), the data transmission path between the selection module 1001 and the signal conversion module 1002, the data transmission path between the signal conversion module 1002 and the write clock path 1003, and the data transmission path between the write clock path 1003 and the external test system, so as to determine whether the parallel write clock Clk_W generated based on the external clock signal WCK is an equidistant clock.

[0124] It should be noted that the "driving capability" mentioned in the embodiments of this disclosure refers to the driving capability of the source and drain current of the transistor when the gate is turned on at the same degree.

[0125] In this embodiment, the duty cycle of the reference test signal AltWck is tested using the test circuit 400. The duty cycle of the reference test signal AltWck is known and used to determine whether the duty cycle test function of the test circuit 400 is normal. If the duty cycle test function of the test circuit 400 is normal, different test modules are selected based on the test control signal DcmCtrl. The duty cycle of the output signals of different test modules is tested sequentially by the test circuit 400 to test whether the duty cycle of the signals output by different test modules is normal, thereby completing the functional test of different test modules.

[0126] All units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this disclosure, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this disclosure; however, this does not mean that other units are absent from this embodiment.

[0127] It should be noted that the features disclosed in the signal detection system provided in the above embodiments can be arbitrarily combined without conflict to obtain new signal detection system embodiments.

[0128] Another embodiment of this disclosure provides a memory testing method. Based on the signal detection system provided in the above embodiment, the duty cycle of the output signal of each test path in the memory is tested. By selecting different test paths, the duty cycle of the high-speed clock signal in different transmission paths is tested to ensure the stability of memory data processing.

[0129] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A signal detection system, applied to a memory, for performing duty cycle testing on the output signals of each test path in the memory according to a test circuit in the memory, characterized in that, include: A signal generator generates a reference test signal based on external parameters, wherein the reference test signal is a clock signal that satisfies a preset duty cycle; The duty cycle of the reference test signal is tested based on the test circuit to determine whether the test circuit is functioning properly. If the test circuit functions normally, different test modules are selected sequentially based on the test control signal, and the duty cycle of the signal output by the selected test module is tested based on the test circuit. The test module includes: a signal conversion module and a write clock path; The signal conversion module is used to generate an internal clock signal based on the reference test signal; the write clock path includes: a write divider, a write clock tree, and a signal loading circuit. The write divider is used to generate a parallel write clock based on the internal clock signal, the write clock tree is used to adjust the delay of the parallel write clock, and the signal loading circuit is used to sample preset data based on the parallel write clock to generate a first indication signal and a second indication signal.

2. The signal detection system according to claim 1, characterized in that, The test module further includes a read clock path, which includes a read divider and a read clock conversion circuit. The read divider is used to generate a parallel read clock based on the internal clock signal, and the read clock conversion circuit is used to generate a serial read clock based on the parallel read clock.

3. The signal detection system according to claim 2, characterized in that, The memory further includes a clock driver, whose input is connected to the output of the signal conversion module and whose output is connected to the test circuit.

4. The signal detection system according to claim 3, characterized in that, The test control signal is set to at least four bits to form multiple signal values; One of the values ​​is configured to select a duty cycle test on the reference test signal based on the test circuit; One of the values ​​is configured to control the signal conversion module to receive the reference test signal and perform a duty cycle test on the internal clock signal output by the signal conversion module based on the test circuit. One of the values ​​is configured to select a duty cycle test for the serial read clock output by the read clock path based on the test circuit; One of the values ​​is configured to select a duty cycle test based on the first indicator signal and the second indicator signal output by the write clock path based on the test circuit; The memory also includes a logic control signal circuit configured to identify the test control signal and generate a conduction signal corresponding to the test control signal based on the test control signal. The conduction signal is used to select and activate the corresponding test module to form different test paths. The different test paths output the test signal to the test circuit or the external test system.

5. The signal detection system according to claim 3, characterized in that, The signal generator includes: An oscillation generation module is configured to generate an initial oscillation signal based on an oscillation control signal, wherein the oscillation control signal is used to adjust the frequency of the generated initial oscillation signal. The duty cycle correction module, connected to the output of the oscillation generation module, is configured to adjust the duty cycle of the initial oscillation signal based on the duty cycle control signal to generate an intermediate test signal. An amplitude adjustment module, connected to the output of a duty cycle correction module, is configured to adjust the amplitude of the intermediate test signal based on an amplitude adjustment signal to generate the reference test signal.

6. The signal detection system according to claim 5, characterized in that, The memory includes: The first output component is connected to the output terminal of the duty cycle correction module and is used to output the intermediate test signal to an external test system. The external test system is used to test whether the intermediate test signal meets the preset duty cycle.

7. The signal detection system according to claim 5, characterized in that, The memory includes: The signal conversion module is also used to receive an external clock signal having the preset duty cycle, and to generate the internal clock signal according to the external clock signal; The second output component is connected to the output end of the write clock tree and is used to output the parallel write clock to an external test system. The external test system is used to test whether the parallel write clock is an equidistant clock.

8. The signal detection system according to claim 7, characterized in that, The memory also includes: The selection module has a first input terminal, a second input terminal, and an output terminal. The first input terminal is used to receive the reference test signal, the second input terminal is used to receive the external clock signal, and the output terminal is connected to the input terminal of the signal conversion module. It is also used to receive the test control signal and connect the first input terminal and the output terminal or the second input terminal and the output terminal based on the test control signal.

9. The signal detection system according to claim 8, characterized in that, The selection module includes: The first input MOSFET has its source connected to the output of the amplitude adjustment module and its drain used to output the reference test signal. The source of the second input MOSFET is connected to the drain of the first input MOSFET, and the drain is connected to the source of the first input MOSFET. The third input MOSFET has its source used to receive the external clock signal, and its drain connected to the drain of the first input MOSFET, and is used to output the external clock signal. The gates of the first input MOS transistor, the second input MOS transistor, and the third input MOS transistor are used to receive the test control signal, and the signals received by the gates of the first input MOS transistor and the second input MOS transistor are inverted signals.

10. The signal detection system according to claim 8, characterized in that, The test control signal also includes: One of the values ​​is configured to control the memory to output the generated intermediate test signal to an external test system for duty cycle detection; One of the values ​​is configured to select a duty cycle test on the reference test signal based on the test circuit; One of the values ​​is configured to control the memory to output the parallel write clock Clk_W generated based on the external clock signal to the external test system for duty cycle detection; One of the values ​​is configured to control the memory to output the parallel write clock Clk_W generated based on the reference test signal to the external test system for duty cycle detection; One of the values ​​is configured to select the duty cycle test of the internal clock signal output by the signal conversion module based on the reference test signal, based on the test circuit. One of the values ​​is configured to select the duty cycle test of the internal clock signal output by the signal conversion module based on the external clock signal, based on the test circuit. One of the values ​​is configured to select the duty cycle test of the serial read clock output by the read clock path based on the reference test signal based on the test circuit; One of the values ​​is configured to select a duty cycle test based on the first indication signal and the second indication signal output by the write clock path based on the reference test signal, using the test circuit. One of the values ​​is configured to select the duty cycle test of the serial read clock output by the read clock path based on the external clock signal based on the test circuit; One of the values ​​is configured to select a duty cycle test based on the first indication signal and the second indication signal output by the write clock path based on the external clock signal, using the test circuit.

11. The signal detection system according to claim 5, characterized in that, The amplitude adjustment module includes: The first signal generation unit is configured to pull up and output a signal based on the intermediate test signal and pull down and output a signal based on the inverted test signal to generate the reference test signal that is in phase with the intermediate test signal. The second signal generation unit is configured to pull up the output signal based on the inverted test signal and pull down the output signal based on the intermediate test signal to generate an inverted reference test signal with the same phase as the inverted test signal. The intermediate test signal and the inverted test signal have the same amplitude but opposite phase.

12. The signal detection system according to claim 1, characterized in that, include: The write divider includes a four-phase clock generation circuit, which receives the internal clock signal and is configured to generate a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal with the same period based on the internal clock signal. The write clock tree includes a signal delay circuit for receiving the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, and a delay command, configured to delay the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal respectively based on the delay command, wherein the delays of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are different.

13. The signal detection system according to claim 12, characterized in that, include: The delay commands include a first delay command, a second delay command, a third delay command, and a fourth delay command; The delay circuit includes a first delay sub-circuit, a second delay sub-circuit, a third delay sub-circuit, and a fourth delay sub-circuit; Wherein, the first delay sub-circuit is used to delay the first clock signal according to the first delay command, the second delay sub-circuit is used to delay the second clock signal according to the second delay command, the third delay sub-circuit is used to delay the third clock signal according to the third delay command, and the fourth delay sub-circuit is used to delay the fourth clock signal according to the fourth delay command.

14. The signal detection system according to claim 12, characterized in that, The signal loading circuit includes: The data generation module is used to generate four bits of first and second loaded data. The data loading module is used to sample the first loaded data according to the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal to generate the first indication signal; Specifically, when the first loading data corresponding to the sampling edge of the clock signal is high, the generated first indication signal is high. The data loading module is further configured to sample the second loaded data according to the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal to generate the second indication signal; Specifically, when the second loading data corresponding to the sampling edge of the clock signal is high, the generated second indication signal is high.

15. A method for detecting a memory, characterized in that, The duty cycle of the output signal of each test path in the memory is tested based on the signal detection system according to any one of claims 1 to 14.

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