comparator

Abstract

To provide a comparator with improved response characteristics without increasing a circuit current.SOLUTION: A differential input part 2 has: a constant current source 21 and a constant current source 22; and a differential transistor M1 and a differential transistor M2 which are supplied with currents from the constant current source 21 and the constant current source 22, respectively. An output unit 3 is made up of transistors, and it outputs a result of comparison between the currents flowing to the differential transistor M1 and the differential transistor M2. A current control unit 4 causes the constant current source 22 to supply the currents to the differential transistor M1 and the differential transistor M2 only during a transition period when the output from the output unit 3 is inverted.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a comparator.

Background Art

[0002] It is considered that the cause of global warming is due to the enhanced greenhouse effect of the atmosphere caused by an increase in the concentration of greenhouse gases such as CO2. Along with the rapid progress of the communication information society, reducing the power consumption of electronic devices has also become a major issue. Many semiconductor integrated circuits are used in electronic devices, and the comparator widely used in semiconductor integrated circuits has response speed and consumption current as its main performances. Since the response speed and consumption current of the comparator are in an inverse relationship, it is intended to improve the response characteristics to an input signal without increasing the consumption current and contribute to the suppression of global warming.

[0003] As a comparator used in a semiconductor integrated circuit, a circuit as shown in FIG. 4 is known (see, for example, Patent Documents 1, 2, etc.). The comparator 100 shown in FIG. 4 is composed of a differential input section 101, an output section 102, and an output buffer circuit 103 as main components.

[0004] The differential input section 101 is composed of differential transistors M1 and M2 whose sources are commonly connected, load transistors M3 and M4 respectively connected to their drains, and a constant current source 21 connected between the common source of the transistors M1 and M2 and the positive power supply voltage VDD.

[0005] The output section 102 consists of transistors M5 and M6 respectively current-mirror connected to the load transistors M3 and M4, and transistors M7 and M8 respectively connected between their drains and the positive power supply voltage VDD. The transistors M7 and M8 are current-mirror connected, and the output is taken out through the output buffer circuit 103 from the connection node between the drain of the transistor M6 and the drain of the transistor M8.

[0006] The conventional comparator 100 described above had the problem that the circuit current had to be increased in order to improve the response characteristics. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Patent No. 5141289 [Patent Document 2] Japanese Patent Application Publication No. 7-245552 [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] The present invention has been made in view of the above circumstances, and its object is to provide a comparator with improved response characteristics without increasing the circuit current. [Means for solving the problem]

[0009] To achieve the aforementioned objectives, the comparator according to the present invention is characterized by the following [1] to [9]. [1] A differential input section having a first current source and a second current source, and a first differential transistor and a second differential transistor, to which currents from the first current source and the second current source are supplied, and which carry currents with a current ratio corresponding to a first input potential and a second input potential, respectively, The output unit consists of transistors and outputs the result of comparing the currents flowing through the first differential transistor and the second differential transistor, The system includes a current control unit that supplies current from the second current source to the first differential transistor and the second differential transistor only during the transition period in which the output of the output unit is inverted, It is a comparator. [2] In the comparator described in [1], The output unit has a first output circuit and a second output circuit that output inverted comparison results. The current control unit has a third transistor and a fourth transistor connected in series between the second current source and the first differential transistor and the second differential transistor, The gate or base of the third transistor is connected to the output of the first output circuit. The gate or base of the fourth transistor is connected to the output of the second output circuit. It is a comparator. [3] In the comparator described in [2], The first output circuit includes a fifth transistor that folds back the current flowing through the first differential transistor, and a sixth transistor that folds back the current flowing through the second differential transistor, with the sixth transistor constituting the output stage. The second output circuit includes a seventh transistor that folds back the current flowing through the first differential transistor and an eighth transistor that folds back the current flowing through the second differential transistor, with the seventh transistor constituting the output stage. It is a comparator. [4] In the comparator described in [3], The differential input section includes a ninth load transistor connected in series with the first differential transistor and a tenth load transistor connected in series with the second differential transistor. The fifth transistor and the seventh transistor are currently mirrored to the ninth load transistor. The sixth transistor and the eighth transistor are currently mirrored to the tenth load transistor. The first output circuit has an eleventh transistor connected in series with the fifth transistor, and a twelfth transistor connected in current mirror to the eleventh transistor, which folds back the current flowing through the eleventh transistor, and the sixth transistor and the twelfth transistor are connected in series, with the connection point being the output. The second output circuit includes a 13th transistor connected in series with the 8th transistor, and a 14th transistor connected to the 13th transistor via a current mirror to fold back the current flowing through the 13th transistor, wherein the 7th transistor and the 14th transistor are connected in series, and the connection point becomes the output. It is a comparator. [5] A differential input section having a first current source and a second current source, and a first differential transistor and a second differential transistor, to which currents from the first current source and the second current source are supplied, and which carry currents with a current ratio corresponding to a first input potential and a second input potential, respectively, The output unit consists of transistors and outputs the result of comparing the currents flowing through the first differential transistor and the second differential transistor, The system includes a current control unit that supplies current from the second current source to the first differential transistor and the second differential transistor only during the transition period in which the output of the output unit is inverted, The output unit has a first output circuit and a second output circuit that output inverted comparison results. The current control unit has a third transistor and a fourth transistor connected in series between the second current source and the first differential transistor and the second differential transistor, The first output circuit includes a fifth transistor that folds back the current flowing through the first differential transistor, and a sixth transistor that folds back the current flowing through the second differential transistor. The second output circuit includes a seventh transistor that folds back the current flowing through the first differential transistor, and an eighth transistor that folds back the current flowing through the second differential transistor. The differential input section includes a ninth load transistor connected in series with the first differential transistor and a tenth load transistor connected in series with the second differential transistor. The fifth transistor and the seventh transistor are currently mirrored to the ninth load transistor. The sixth transistor and the eighth transistor are connected in a current mirror configuration to the tenth load transistor. The first output circuit includes an eleventh transistor connected in series to the fifth transistor, and a twelfth transistor connected in a current mirror configuration to the eleventh transistor and configured to fold back the current flowing through the eleventh transistor. The sixth transistor and the twelfth transistor are connected in series. The second output circuit includes a thirteenth transistor connected in series to the eighth transistor, and a fourteenth transistor connected in a current mirror configuration to the thirteenth transistor and configured to fold back the current flowing through the thirteenth transistor. The seventh transistor and the fourteenth transistor are connected in series. The current control unit includes a fifteenth transistor diode-connected between the sixth transistor and the twelfth transistor, and a sixteenth transistor diode-connected between the seventh transistor and the fourteenth transistor. The gate or base of the third transistor is connected to the gate or base of the fifteenth transistor. The gate or base of the fourth transistor is connected to the gate or base of the sixteenth transistor. to Connected. For the first output circuit, the connection point between the sixth transistor and the fifteenth transistor serves as the output. For the second output circuit, the connection point between the seventh transistor and the sixteenth transistor serves as the output. It is a comparator. [6] In the comparator according to any one of [2] to [5], the output of the first output circuit and the output of the second output circuit are each connected, and it has an output buffer circuit that outputs an output signal. It is a comparator. [7] [3] to [5] any one of the above In the comparator according to the above, The output of the first output circuit and the output of the second output circuit are connected to each other, and the output buffer circuit has an output signal output. The output buffer circuit includes a 17th transistor whose gate or base is connected to the output of the first output circuit, and a 18th transistor whose gate or base is connected to the output of the second output circuit, and the threshold voltages of the 17th transistor and the 18th transistor constitute the output section. The fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor Lower than at least one threshold voltage, It is a comparator. [8] In the comparator described in [4] or [5], At least one of the following transistors is a field-effect transistor: the first differential transistor, the second differential transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth load transistor, the tenth load transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, and the fourteenth transistor. It is a comparator. [9] In the comparator described in either item [4] or [5], At least one of the following transistors is a bipolar transistor: the first differential transistor, the second differential transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth load transistor, the tenth load transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, and the fourteenth transistor. It is a comparator. [Effects of the Invention]

[0010] According to the present invention, a comparator with improved response characteristics can be provided without increasing the circuit current.

[0011] The present invention has been briefly described above. Furthermore, the details of the present invention will be further clarified by referring to the attached drawings and reading through the embodiments for carrying out the invention described below (hereinafter referred to as "embodiments"). [Brief explanation of the drawing]

[0012] [Figure 1] Figure 1 is a circuit diagram showing the comparator of the present invention in the first embodiment. [Figure 2] Figure 2 is a circuit diagram showing the comparator of the present invention in a second embodiment. [Figure 3] Figure 3 is a circuit diagram showing the comparator of the present invention in a third embodiment. [Figure 4] Figure 4 is a circuit diagram showing an example of a conventional comparator. [Modes for carrying out the invention]

[0013] Specific embodiments of the present invention will be described below with reference to the figures.

[0014] (First Embodiment) First, the comparator 1 of the first embodiment will be described with reference to Figure 1. As shown in the figure, the comparator 1 compares the inverting input potential (= first input potential) input to the inverting input terminal T11 with the non-inverting input potential (= second input potential) input to the non-inverting input terminal T12, and outputs the comparison result from the output terminal T3. The comparator 1 includes a differential input section 2, an output section 3, a current control section 4, and an output buffer circuit 5.

[0015] The differential input section 2 includes differential transistors M1 (=first differential transistor) and M2 (=second differential transistor) whose sources are connected in common, load transistors M3 (=ninth load transistor) and M4 (=tenth load transistor), and constant current sources 21 (first current source) and 22 (=second current source).

[0016] The differential transistors M1 and M2 are composed of P-channel field-effect transistors. The gate of differential transistor M1 is connected to the inverting input terminal T11, and the gate of differential transistor M2 is connected to the non-inverting input terminal T12. The sources of differential transistors M1 and M2 are connected in common and are connected to constant current sources 21 and 22.

[0017] The load transistors M3 and M4 are composed of N-channel field-effect transistors. Load transistor M3 is connected in series with differential transistor M1. More specifically, the drain of load transistor M3 is connected to the drain of differential transistor M1, and the source is connected to the negative power supply terminal T22. The negative power supply voltage VSS is supplied to the negative power supply terminal T22. Load transistor M4 is connected in series with differential transistor M2. More specifically, the drain of load transistor M4 is connected to the drain of differential transistor M2, and the source is connected to the negative power supply terminal T22. The gates and drains of load transistors M3 and M4 are connected to each other.

[0018] The constant current sources 21 and 22 are connected in parallel between the positive power supply terminal T21 and the sources of the differential transistors M1 and M2, which are connected in common. The positive power supply terminal T21 is supplied with the positive power supply voltage VDD. The differential input section 2 divides the current (I1 + I2) supplied by the constant current sources 21 and 22 to the differential transistors M1 and M2. The current ratio (division ratio) of the currents flowing through the differential transistors M1 and M2 is a value corresponding to the inverting input potential INM and the non-inverting input potential INP.

[0019] The output unit 3 outputs the comparison result of the currents flowing through differential transistors M1 and M2. In this embodiment, the output unit 3 has an output circuit 31 (= first output circuit) and an output circuit 32 (= second output circuit). Output circuits 31 and 32 output the comparison results which are inverted relative to each other.

[0020] More specifically, when the current flowing through differential transistor M2 is greater than the current flowing through differential transistor M1, output circuit 31 outputs a Low state (= negative power supply voltage VSS), and output circuit 32 outputs a High state (= positive power supply voltage VDD). On the other hand, when the current flowing through differential transistor M1 is greater than the current flowing through differential transistor M2, output circuit 31 outputs a High state, and output circuit 32 outputs a Low state.

[0021] First, let's describe the output circuit 31. The output circuit 31 has transistors M51 and M61, and transistors M71 and M81. Transistors M51 and M61 are N-channel field-effect transistors. Transistor M51 has its gate connected to the gate and drain of load transistor M3, and its source connected to the negative power supply terminal T22. In other words, transistor M51 is current-mirror connected to load transistor M3, copying and folding back the current flowing through load transistor M3. Transistor M61 has its gate connected to the gate and drain of load transistor M4, and its source connected to the negative power supply terminal T22. In other words, transistor M61 is current-mirror connected to load transistor M4, copying and folding back the current flowing through load transistor M4.

[0022] Transistors M71 and M81 are composed of P-channel field-effect transistors. The sources of transistors M71 and M81 are connected in common and connected to the positive power supply terminal T21. The drain of transistor M71 is connected to the drain of transistor M51, and transistors M71 and M51 are connected in series. In addition, the gate of transistor M81 is connected to the gate and drain of transistor M71. That is, transistor M81 is current-mirror connected to transistor M71, copying and folding back the current flowing through transistor M71.

[0023] The drain of transistor M81 is connected to the drain of transistor M61, and transistors M81 and M61 are connected in series to form an output stage. The connection node A between transistors M61 and M81 becomes the output of output circuit 31.

[0024] Next, the output circuit 32 will be described. The output circuit 32 has transistors M52 and M62, and transistors M72 and M82. Transistors M52 and M62 are composed of N-channel field-effect transistors. The gate of transistor M52 is connected to the gate and drain of load transistor M3, and its source is connected to the negative power supply terminal T22. In other words, transistor M52 is current-mirror connected to load transistor M3, copying and folding back the current flowing through load transistor M3. The gate of transistor M62 is connected to the gate and drain of load transistor M4, and its source is connected to the negative power supply terminal T22. In other words, transistor M62 is current-mirror connected to load transistor M4, copying and folding back the current flowing through load transistor M4.

[0025] Transistors M72 and M82 are composed of P-channel field-effect transistors. The sources of transistors M72 and M82 are connected in common and connected to the positive power supply terminal T21. The drain of transistor M82 is connected to the drain of transistor M62, and transistors M82 and M62 are connected in series. In addition, the gate of transistor M72 is connected to the gate and drain of transistor M82. That is, transistor M72 is current-mirror connected to transistor M82, copying and folding back the current flowing through transistor M82.

[0026] The drain of transistor M72 is connected to the drain of transistor M52, so that transistors M72 and M52 are connected in series. The connection node B between transistors M72 and M52 becomes the output of output circuit 32.

[0027] The current control unit 4 supplies current from the constant current source 22 to differential transistors M1 and M2 only during the transition period when the outputs of output circuits 31 and 32 invert. The current control unit 4 has transistors M91 and M92. Transistors M91 and M92 are made up of P-channel field-effect transistors. Transistors M91 and M92 are connected in series between the constant current source 22 and the sources of differential transistors M1 and M2. Transistor M91 has its source connected to the constant current source 22, its drain connected to the source of transistor M92, and its gate connected to connection node A. Transistor M92 has its source connected to the drain of transistor M91, its drain connected to the sources of differential transistors M1 and M2, and its gate connected to connection node B.

[0028] The output buffer circuit 5 is connected to connection nodes A and B respectively and outputs the output signal VOUT. The output buffer circuit 5 has transistors M11 to M16 and an inverter circuit 51. Transistors M11 and M12 are composed of N-channel field-effect transistors. The gate of transistor M11 is connected to connection node A and the source is connected to the negative power supply terminal T22. The gate of transistor M12 is connected to connection node B and the source is connected to the negative power supply terminal T22.

[0029] Transistors M13 to M16 are composed of P-channel field-effect transistors. Transistor M13 has its source connected to the positive power supply terminal T21, its drain connected to the source of transistor M15 (described later), and its gate connected to the drain of transistor M12. Transistor M14 has its source connected to the positive power supply terminal T21, its drain connected to the source of transistor M16 (described later), and its gate connected to the drain of transistor M11.

[0030] Transistor M15 has its source connected to the drain of transistor M13, and its gate and drain connected to the drain of transistor M11. Transistor M16 has its source connected to the drain of transistor M14, and its gate and drain connected to the drain of transistor M12.

[0031] The inverter circuit 51 has the drains of transistor M15 and M11 connected to an input node, and the output terminal T3 connected to an output.

[0032] Next, we will describe the operation of comparator 1 in the configuration described above. First, we will describe the operation when the inverting input potential INM is higher than the non-inverting input potential INP, and the output of output terminal T3 is in a low state, that is, when the output signal is approximately the negative power supply voltage VSS.

[0033] When the inverting input potential INM is higher than the non-inverting input potential INP, more current flows from the constant current source 21 to the differential transistor M2 than to the differential transistor M1, and more current flows to the load transistor M4 than to the load transistor M3. As a result, more current flows to transistors M61 and M62, which are currently mirrored to the load transistor M4, than to transistors M51 and M52, which are currently mirrored to the load transistor M3.

[0034] The small current flowing through transistor M51 flows to transistor M71 and is copied to the drain current of transistor M81. Transistor M81 operates to allow a small current to flow, and transistor M61 operates to allow a large current to flow, so connection node A goes low. When connection node A goes low, transistor M11 turns off. When transistor M11 turns off, the drain potential of transistor M11 rises, so transistor M14 turns off.

[0035] Furthermore, the large current flowing through transistor M62 flows to transistor M82 and is copied to the drain current of transistor M72. Transistor M72 operates to allow a large current to flow, and transistor M52 operates to allow a small current to flow, so connection node B becomes High. When connection node B becomes High, transistor M12 turns on. When transistor M12 turns on, the drain potential of transistor M12 decreases, so transistor M13 turns on.

[0036] As described above, when transistor M11 is off and transistor M13 is on, a high potential is input to the inverter circuit 51, and a low output signal VOUT is output from output terminal T3.

[0037] Furthermore, when the output signal VOUT is in a low state, as described above, connection node A is in a low state and connection node B is in a high state, so transistor M91 is on and transistor M92 is off.

[0038] Next, we will explain the operation when the non-inverting input potential INP is higher than the inverting input potential INM, and the output of output terminal T3 is in a High state, i.e., the output signal VOUT is approximately equal to the positive power supply voltage VDD.

[0039] When the non-inverting input potential INP is higher than the inverting input potential INM, more current flows from the constant current source 21 to the differential transistor M1 than to the differential transistor M2, and more current flows to the load transistor M3 than to the load transistor M4. As a result, more current flows to transistors M51 and M52, which are currently mirrored to the load transistor M3, than to transistors M61 and M62, which are currently mirrored to the load transistor M4.

[0040] The large current flowing through transistor M51 flows to transistor M71 and is copied to the drain current of transistor M81. Transistor M81 operates to allow a large current to flow, and transistor M61 operates to allow a small current to flow, so connection node A becomes High. When connection node A becomes High, transistor M11 turns on. When transistor M11 turns on, the drain potential of transistor M11 decreases, so transistor M14 turns on.

[0041] Furthermore, the small current flowing through transistor M62 flows to transistor M82 and is copied to the drain current of transistor M72. Transistor M72 operates to allow a small current to flow, and transistor M52 operates to allow a large current to flow, so connection node B goes low. When connection node B goes low, transistor M12 turns off. When transistor M12 turns off, the drain potential of transistor M12 rises, so transistor M13 turns off.

[0042] As described above, when transistor M11 is turned on and transistor M13 is turned off, a low potential is input to the inverter circuit 51, and a high output signal VOUT is output from output terminal T3.

[0043] When the output signal VOUT is in a High state, as described above, connection node A is in a High state and connection node B is in a Low state, so transistor M91 is off and transistor M92 is on.

[0044] Next, the operation when the output signal VOUT of output terminal T3 changes from a Low state to a High state is as follows.

[0045] At this time, the potential of connection node A changes from Low to High, and transistor M91 changes from the ON state to the OFF state. Meanwhile, connection node B changes from High to Low, and transistor M92 changes from the OFF state to the ON state.

[0046] As a result, during the period when the potentials of connection node A and connection node B change, there is a period in which transistors M91 and M92 are simultaneously turned on. During that period, in addition to the current supplied from constant current source 21, the current supplied from constant current source 22 flows through transistors M91 and M92 as tail currents of differential transistors M1 and M2.

[0047] Next, the operation when the output signal VOUT of output terminal T3 changes from a High state to a Low state is as follows.

[0048] At this time, the potential of connected node A changes from High to Low, and transistor M91 changes from the off state to the on state. Meanwhile, connected node B changes from Low to High, and transistor M92 changes from the on state to the off state.

[0049] As a result, during the period when the potentials of connection node A and connection node B change, there is a period in which transistors M91 and M92 are simultaneously turned on. During that period, in addition to the current supplied from constant current source 21, the current supplied from constant current source 22 flows through transistors M91 and M92 as tail currents of differential transistors M1 and M2.

[0050] In the first embodiment described above, the tail current is temporarily increased to current (I1+I2) during the transition period when the outputs of output circuits 31 and 32 invert, and after the outputs of output circuits 31 and 32 invert, the tail current is returned to current I1. This has the effect of improving the response characteristics when the output signal VOUT changes without increasing the current consumption.

[0051] Furthermore, in the first embodiment described above, output circuits 31 and 32 are provided, and the gates of transistor M11 and transistor M12, which constitute the output buffer circuit 5, are controlled by the differential output signal generated between connection nodes A and B, thereby improving the response characteristics of the output signal VOUT of the output terminal T3.

[0052] Furthermore, by setting the threshold voltage of transistors M11 and M12 lower than that of at least one of the threshold voltages of transistors M51, M61, M52, and M62 that constitute the output circuits 31 and 32, the time it takes for transistors M11 and M12 to change from the off state to the on state is shortened, and the response characteristics of the output buffer circuit 5 are further improved.

[0053] (Second Embodiment) Next, the comparator 1B of the second embodiment will be described with reference to Figure 2. In Figure 2, components identical to those in the circuit shown in Figure 1 are given the same reference numerals, and their detailed descriptions are omitted.

[0054] As shown in the figure, the comparator 1B, like the first embodiment, includes a differential input section 2, an output section 3 having output circuits 31 and 32, a current control section 4B, and an output buffer circuit 5. Since the differential input section 2, output circuits 31 and 32, and output buffer circuit 5 are the same as those in the first embodiment described above, a detailed explanation is omitted here.

[0055] The difference between the first and second embodiments is that the current control unit 4B has transistors M101 and M102 in addition to transistors M91 and M92.

[0056] Transistors M101 and M102 are composed of P-channel field-effect transistors. Transistor M101 has its source connected to the drain of transistor M81, and its gate and drain connected to the drain of transistor M61 and the gate of transistor M91. Transistor M102 has its source connected to the drain of transistor M72, and its gate and drain connected to the drain of transistor M52 and the gate of transistor M92.

[0057] Next, the operation of comparator 1B in the configuration described above will be explained. In this configuration, comparator 1B is basically the same as in the first embodiment, except for the points described later.

[0058] In other words, in the first embodiment, the gate potential of transistors M91 and M92 when they are off is near the positive power supply voltage VDD, but in the second embodiment, the gate-source potential difference of diode-connected transistors M101 and M102, and the gate potential when they are off, are lower. This reduces the timing delay when transistors M91 and M92 change from the off state to the on state.

[0059] Therefore, the comparator 1B in this second embodiment has the effect of further improving response characteristics without increasing current consumption.

[0060] (Third embodiment) Next, the comparator 1C of the third embodiment will be described with reference to Figure 3. In Figure 3, components identical to those in the circuit shown in Figure 1 are given the same reference numerals, and their detailed descriptions are omitted.

[0061] As shown in the figure, the comparator 1C, similar to the first embodiment, includes a differential input section 2C, output circuits 31C and 32C, a current control section 4C, and an output buffer circuit 5C.

[0062] The difference between the first and third embodiments is that the conductivity types of transistors M1C to M4C, M51C, M52C, M61, M62, M71, M72, M81, M82, M91, M92, and M11 to M16C, corresponding to transistors M1 to M4, M51, M52, M61, M62C, M71C, M72C, M81C, M82C, M91C, M92C, and M11C to M16C, are reversed. Another difference between the first and third embodiments is that the relationship between the positive power supply terminal T21 and the negative power supply terminal T22 is reversed.

[0063] The third embodiment, like the first embodiment, also achieves the effect of further improving response characteristics without increasing current consumption.

[0064] Furthermore, the present invention is not limited to the embodiments described above, and can be modified, improved, etc., as appropriate. In addition, the material, shape, dimensions, number, placement, etc. of each component in the embodiments described above are arbitrary and not limited, as long as they can achieve the present invention.

[0065] For example, in the first to third embodiments described above, transistors M1(C) to M4(C), M51(C), M52(C), M61(C), M62(C), M71(C), M72(C), M81(C), M82(C), M91(C), M92(C), M101, M102, and M11(C) to M16(C) were composed of field-effect transistors, but are not limited to this. At least one of transistors M1(C) to M4(C), M51(C), M52(C), M61(C), M62(C), M71(C), M72(C), M81(C), M82(C), M91(C), M92(C), M101, M102, and M11(C) to M16(C) may be composed of bipolar transistors. In this case, the explanation can be made by using the transistor's gate as the base, replacing the source with the emitter, and the drain with the collector.

[0066] Furthermore, in the first to third embodiments described above, two transistors M51(C) and M52(C) were connected to the gate of one load transistor M3(C), but this is not the only option. Two load transistors M3(C) may be provided, and transistors M51(C) and M52(C) may be connected to each of them. Similarly, two load transistors M4(C) may be provided, and transistors M61(C) and M62(C) may be connected to each of them.

[0067] Furthermore, in the first to third embodiments described above, the output circuits 31(C) and 32(C) consisted of transistors M51(C), M52(C), M61(C), and M62(C) that were currently mirrored with load transistors M3(C) and M4(C), but are not limited to this. The output circuits 31(C) and 32(C) only need to output the comparison result of differential transistors M1(C) and M2(C), and have an inverted output. For example, the output circuits 31(C) and 32(C) may consist of transistors that are folded cascode connected to differential transistors M1(C) and M2(C). [Explanation of symbols]

[0068] 1, 1B, 1C Comparator 2. 2C Differential Input Section 3, 3C output section 4, 4B, 4C current control section 5. 5C output buffer circuit 21, 21C Constant current source (first current source) 22, 22C constant current source (second current source) 31, 31C Output Circuit (First Output Circuit) 32, 32C Output Circuit (Second Output Circuit) INM inverting input potential (first input potential) INP Non-inverting input potential (second input potential) M1, M1C Differential Transistors (First Differential Transistors) M2, M2C differential transistor (second differential transistor) M3, M3C load transistor (9th load transistor) M4, M4C load transistor (10th load transistor) M11, M11C transistors (the 17th transistor) M12, M12C transistors (the 18th transistor) M51, M51C transistors (the fifth transistor) M52, M52C transistors (the seventh transistor) M61, M61C transistors (the sixth transistor) M62, M62C transistors (the 8th transistor) M71, 71C transistor (11th transistor) M72, M72C transistors (the 14th transistor) M81, M81C transistors (the 12th transistor) M82, M82C transistors (the 13th transistor) M91, M91C transistors (third transistors) M92, M92C transistors (fourth transistors) M101 Transistor (15th Transistor) M102 Transistor (16th Transistor) VOUT output signal

Claims

1. A differential input section having a first current source and a second current source, and a first differential transistor and a second differential transistor, to which currents from the first current source and the second current source are supplied, and to which currents with a current ratio corresponding to a first input potential and a second input potential flow, respectively, The output unit consists of transistors and outputs the result of comparing the currents flowing through the first differential transistor and the second differential transistor, The system includes a current control unit that supplies current from the second current source to the first differential transistor and the second differential transistor only during the transition period in which the output of the output unit is inverted, comparator.

2. In the comparator according to claim 1, The output unit has a first output circuit and a second output circuit that output inverted comparison results. The current control unit has a third transistor and a fourth transistor connected in series between the second current source and the first differential transistor and the second differential transistor, The gate or base of the third transistor is connected to the output of the first output circuit. The gate or base of the fourth transistor is connected to the output of the second output circuit. comparator.

3. In the comparator according to claim 2, The first output circuit includes a fifth transistor that folds back the current flowing through the first differential transistor, and a sixth transistor that folds back the current flowing through the second differential transistor, with the sixth transistor constituting the output stage. The second output circuit includes a seventh transistor that folds back the current flowing through the first differential transistor and an eighth transistor that folds back the current flowing through the second differential transistor, with the seventh transistor constituting the output stage. comparator.

4. In the comparator according to claim 3, The differential input section includes a ninth load transistor connected in series with the first differential transistor and a tenth load transistor connected in series with the second differential transistor. The fifth transistor and the seventh transistor are currently mirrored to the ninth load transistor. The sixth transistor and the eighth transistor are currently mirrored to the tenth load transistor. The first output circuit has an eleventh transistor connected in series with the fifth transistor, and a twelfth transistor connected in current mirror to the eleventh transistor, which folds back the current flowing through the eleventh transistor, and the sixth transistor and the twelfth transistor are connected in series, with the connection point being the output. The second output circuit includes a 13th transistor connected in series with the 8th transistor, and a 14th transistor connected to the 13th transistor via a current mirror to fold back the current flowing through the 13th transistor, wherein the 7th transistor and the 14th transistor are connected in series, and the connection point becomes the output. comparator.

5. A differential input section having a first current source and a second current source, and a first differential transistor and a second differential transistor, to which currents from the first current source and the second current source are supplied, and to which currents with a current ratio corresponding to a first input potential and a second input potential flow, respectively, The output unit consists of transistors and outputs the result of comparing the currents flowing through the first differential transistor and the second differential transistor, The system includes a current control unit that supplies current from the second current source to the first differential transistor and the second differential transistor only during the transition period in which the output of the output unit is inverted, The output unit has a first output circuit and a second output circuit that output inverted comparison results. The current control unit has a third transistor and a fourth transistor connected in series between the second current source and the first differential transistor and the second differential transistor, The first output circuit includes a fifth transistor that folds back the current flowing through the first differential transistor, and a sixth transistor that folds back the current flowing through the second differential transistor. The second output circuit includes a seventh transistor that folds back the current flowing through the first differential transistor, and an eighth transistor that folds back the current flowing through the second differential transistor. The differential input section includes a ninth load transistor connected in series with the first differential transistor and a tenth load transistor connected in series with the second differential transistor. The fifth transistor and the seventh transistor are currently mirrored to the ninth load transistor. The sixth transistor and the eighth transistor are currently mirrored to the tenth load transistor. The first output circuit includes an eleventh transistor connected in series with the fifth transistor, and a twelfth transistor connected in a current mirror to the eleventh transistor, which folds back the current flowing through the eleventh transistor, and the sixth transistor and the twelfth transistor are connected in series. The second output circuit includes a 13th transistor connected in series with the 8th transistor, and a 14th transistor connected to the 13th transistor via a current mirror to fold back the current flowing through the 13th transistor, with the 7th transistor and the 14th transistor connected in series. The current control unit includes a 15th transistor diode-connected between the 6th transistor and the 12th transistor, and a 16th transistor diode-connected between the 7th transistor and the 14th transistor. The gate or base of the third transistor is connected to the gate or base of the 15th transistor. The gate or base of the fourth transistor is connected to the gate or base of the sixteenth transistor. The first output circuit has an output at the connection point between the sixth transistor and the fifteenth transistor. The second output circuit has an output at the connection point between the seventh transistor and the sixteenth transistor. comparator.

6. In the comparator according to any one of claims 2 to 5, The output of the first output circuit and the output of the second output circuit are connected to an output buffer circuit that outputs an output signal. comparator.

7. In the comparator according to any one of claims 3 to 5, The output of the first output circuit and the output of the second output circuit are connected to each other, and the output buffer circuit has an output signal output. The output buffer circuit includes a 17th transistor whose gate or base is connected to the output of the first output circuit, and a 18th transistor whose gate or base is connected to the output of the second output circuit, wherein the threshold voltages of the 17th and 18th transistors are lower than the threshold voltage of at least one of the 5th, 6th, 7th, and 8th transistors that constitute the output section. comparator.

8. In the comparator according to claim 4 or 5, At least one of the following transistors is a field-effect transistor: the first differential transistor, the second differential transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth load transistor, the tenth load transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, and the fourteenth transistor. comparator.

9. In the comparator according to claim 4 or 5, At least one of the following transistors is a bipolar transistor: the first differential transistor, the second differential transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth load transistor, the tenth load transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, and the fourteenth transistor. comparator.

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