Memory and its operating method, memory system, word line voltage control circuit

Abstract

One example of the present application discloses a memory, a method of operating the same, a memory system, and a word line voltage control circuit, the memory including an array of memory cells and peripheral circuitry coupled to the array of memory cells, the array of memory cells including a plurality of word lines, the peripheral circuitry being configured to: begin providing a precharge voltage to a selected word line from the plurality of word lines at a first time, wherein a voltage provided to an unselected word line adjacent to the selected word line is changed from a first voltage to a second voltage at a second time before the first time; and begin floating the selected word line at a third time after the first time, wherein a voltage provided to an adjacent unselected word line is changed from a second voltage to a third voltage at a fourth time before the third time and after the first time, wherein the second voltage is lower than the first voltage and the third voltage.

Claims

1. A memory cell array and Multiple word lines coupled to the memory cell, A peripheral circuit connected to the memory cell through the word line, The first voltage on at least one unselected word line adjacent to the selected word line is reduced to a second voltage, After the at least one unselected word line reaches the second voltage, a precharge voltage is provided to the selected word line. After providing a precharge voltage to the selected word line, the second voltage on the unselected word line is raised to a third voltage, After the at least one unselected word line reaches the third voltage, the selected word line is put into a floating state. A peripheral circuit configured to perform the following: A memory device that includes this.

2. The memory device according to claim 1, wherein the first voltage is substantially equal to the third voltage.

3. The memory device according to claim 2, wherein the magnitude of the second voltage is obtained by multiplying the difference between the precharge voltage and the first voltage by a coupling coefficient.

4. The aforementioned peripheral circuit A first voltage transfer circuit configured to supply the first voltage to the at least one unselected word line in response to a first control signal, A second voltage transfer circuit configured to supply the second voltage to the at least one unselected word line in response to a second control signal, The memory device according to claim 2, including the memory device according to claim 2.

5. The aforementioned peripheral circuitry is In response to the enable control signal, the first control signal is provided to the first voltage transfer circuit, and the second control signal is provided to the second voltage transfer circuit. The memory device according to claim 4, further comprising a control signal generation circuit configured to perform the following.

6. The aforementioned peripheral circuitry is The system further includes a plurality of drive circuits configured to connect at least one unselected word line adjacent to the selected word line to the first voltage transfer circuit or the second voltage transfer circuit in response to a main word line selection signal, a word line selection signal, and a precharge control signal. The memory device according to claim 5, wherein the main word line selection signal indicates a selected main word line from a group of main word lines, each corresponding to a subset of the plurality of word lines; the word line selection signal indicates the selected word line from a subset of the word lines corresponding to the selected main word line; and the precharge control signal indicates providing the precharge voltage to the selected word line.

7. The system further includes a first voltage generator and a second voltage generator connected to the control signal generation circuit, The memory device according to claim 6, wherein the control signal generation circuit is connected to the first voltage transfer circuit at the first node and to the second voltage transfer circuit at the second node, and the first voltage transfer circuit and the second voltage transfer circuit are connected to the plurality of drive circuits at the third node.

8. The memory device according to claim 6, wherein the plurality of drive circuits include a plurality of groups of local word line drive circuits, each corresponding to one first voltage generator, one second voltage generator, one first voltage transfer circuit, and one second voltage transfer circuit.

9. The first voltage transfer circuit is, The first transistor, The first terminal of the first transistor receives the first control signal. The second terminal of the first transistor is connected to the first voltage generator. The first transistor includes a third terminal of the first transistor which is connected to the third terminal of the second transistor, The second voltage transfer circuit is, The aforementioned second transistor, The first terminal of the second transistor receives the second control signal. The second terminal of the second transistor is connected to the third terminal of the third transistor, The aforementioned third transistor, The first terminal of the third transistor receives the word line selection signal. The second terminal of the third transistor is connected to the second voltage generator, and the third transistor and The memory device according to claim 7, including the memory device described in claim 7.

10. The first transistor, the second transistor, and the third transistor include metal-oxide-semiconductor field-effect transistors (MOSFETs), The memory device according to claim 9, wherein the first terminal of the MOSFET is the gate, the second terminal of the MOSFET is the source, and the third terminal of the MOSFET is the drain.

11. The memory device according to claim 1, wherein the precharge voltage includes a positive voltage, and the first voltage, the second voltage, and the third voltage include negative voltages.

12. The memory device according to claim 1, wherein the memory device includes a dynamic random access memory (DRAM) device.

13. The memory device according to claim 12, wherein the array of memory cells and the peripheral circuits are bonded together.

14. The memory device according to claim 1, wherein if the selected word line is the Nth word line, the at least one unselected word line includes the (N-1)th word line and the (N+1)th word line.

15. The memory device according to claim 14, wherein the at least one unselected word line further includes a word line that is M word lines away from the selected word line, where M is a natural number and 1 ≤ M ≤ 4.

16. The memory device according to claim 14, wherein the magnitude of the voltage difference between the second voltage and the first voltage decreases as the distance between the at least one unselected word line and the selected word line increases.

17. A memory cell array and Multiple word lines coupled to the memory cell, A peripheral circuit connected to the memory cell through the word line, The first voltage on an unselected word line adjacent to the selected word line is reduced to a second voltage, After the unselected word line reaches the second voltage, a precharge voltage is provided to the selected word line. After providing a precharge voltage to the selected word line, the second voltage on the unselected word line is raised to a third voltage, After the unselected word line reaches the third voltage, the selected word line is put into a floating state. A peripheral circuit configured to perform the following: including at least one memory device, A memory controller configured to control the at least one memory device via the peripheral circuitry, including, Memory system.

18. A method for operating a memory device, A step of determining a word line selected from a plurality of word lines coupled to an array of memory cells of the memory device, The steps include reducing a first voltage on at least one unselected word line adjacent to the selected word line to a second voltage, The steps include providing a precharge voltage to the selected word line after the at least one unselected word line has reached the second voltage, The steps include providing a precharge voltage to the selected word line, and then raising the second voltage on at least one unselected word line to a third voltage, After the at least one unselected word line reaches the third voltage, the selected word line is placed in a floating state. Methods that include...

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