Wiring board and method for manufacturing a wiring board
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- TOPPAN HOLDINGS INC
- Filing Date
- 2026-01-22
- Publication Date
- 2026-06-23
Smart Images

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Figure 0007878610000008 
Figure 0007878610000009
Abstract
Claims
1. A wiring board on which at least one semiconductor element is mounted, The aforementioned wiring board has a core layer, An insulating resin layer is formed on the first and second surfaces of the core layer. Wiring is formed on the aforementioned insulating resin layer. The core layer is provided with at least one through-electrode that penetrates from the first surface to the second surface. At least one bottomed cavity is formed on the surface on which the semiconductor elements of the core layer are mounted. A fine wiring component is placed in the cavity. The inclination angle of the side wall of the bottomed cavity is in the range greater than 4.5° and less than 30°. A wiring board characterized by the following features.
2. The distance between the cavity and the nearest through-electrode is 40 μm or more and 150 μm or less. The wiring board according to feature 1.
3. At least one organic resin layer, greater than 100 nm and less than or equal to 5,000 nm, is formed at the interface between the core layer and the wiring layer, and at the interface between the core layer and the through electrode. The wiring board according to feature 1.
4. The material of the core layer is SiO 2 This glass has a ratio greater than 55% by mass and less than 85.0% by mass. The wiring board according to feature 1.
5. The core layer has cavities of varying depths. The wiring board according to feature 1.
6. In the cavity, a DAF is placed between the bottom of the cavity and the fine wiring member. At least the portion of the bottom of the cavity on which the DAF is placed has irregularities formed with a roughness of Sa greater than 500 nm. A wiring board according to any one of claims 1 to 5.
7. The wiring board according to claim 6, characterized in that the roughness Sa of the irregularities at the bottom of the cavity is 3000 nm or less.
8. In the cavity, a DAF is placed between the bottom of the cavity and the fine wiring member. At least the portion of the cavity's bottom where the DAF is placed has irregularities formed by pointed surfaces with a height of 0.25 to 10.0 μm and a period of 5.0 to 25 μm in the horizontal direction. A wiring board according to any one of claims 1 to 5.
9. Ridges are formed in the longitudinal and transverse directions on the side walls of the cavity. The PV value of the ridges is between 1.2 μm and 4.4 μm, and the depth of the depressions is between 0.5 μm and 4.1 μm. The wiring board according to claim 8, characterized in that way.
10. Multiple substantially rectangular recesses are formed on the side walls of the cavity by multiple vertical and horizontal ridges. The spacing between longitudinal ridges is 5 μm to 15.5 μm, and the spacing between transverse ridges is 2.0 μm to 25 μm. The wiring board according to feature 8.
11. It has a core layer, An insulating resin layer is formed on the first and second surfaces of the core layer. Wiring is formed on the aforementioned insulating resin layer. The core layer is provided with at least one through-electrode that penetrates from the first surface to the second surface. A method for manufacturing a wiring substrate, wherein at least one bottomed cavity is formed on the surface on which the semiconductor element of the core layer is mounted, The process involves irradiating the core layer with a laser to form through electrodes and the cavity to form, and performing an etching process to form the side wall of the cavity with an inclination angle greater than 4.5° and less than 30°. A step of arranging a fine wiring member in the cavity, A method for manufacturing a wiring board having
12. In the process of irradiating the area where the through electrode is to be formed and the area where the cavity is to be formed with a laser, In the area where through electrodes are planned to be formed, the entire core layer is modified in the thickness direction, while in the area where cavities are planned to be formed, the core layer is partially modified in the thickness direction. The method for manufacturing a wiring board according to claim 11.