Power semiconductor devices with moisture barriers

Abstract

The power semiconductor device includes a package, a power semiconductor die within the package, and a moisture barrier on an upper surface and a side surface of an outer surface of the package.

Description

Technical Field

[0001] This application claims the priority of U.S. Patent Application No. 17 / 747,128, filed on May 18, 2022, the entire content of which is incorporated herein by reference.

[0002] The present invention relates to power semiconductor devices, and more particularly to packaged power semiconductor devices.

Background Art

[0003] A power semiconductor device refers to a device including one or more power semiconductor dies designed to carry a large current and / or one or more power semiconductor dies capable of blocking a high voltage. In this specification, a power semiconductor die refers to a semiconductor die that can pass at least 1 Amp of current during normal operation and / or can block at least 100 volts during reverse blocking operation. Power semiconductor dies are often made from wide bandgap semiconductor materials such as silicon carbide (''SiC'') or gallium nitride (''GaN'') based semiconductor materials. Various power semiconductor dies are known in the art, including, for example, power metal oxide semiconductor field effect transistors (''MOSFETs''), power insulated gate bipolar junction transistors (''IGBTs''), power Schottky diodes, and the like. Power semiconductor dies are often packaged to provide a packaged power semiconductor device.

[0004] A power MOSFET is one of the most widely used power semiconductor dies. A power MOSFET is a three-terminal device having a gate terminal, a drain terminal, and a source terminal, and a semiconductor layer structure often called the semiconductor body. The source and drain regions, separated by a channel region, are formed in the semiconductor body, and the gate electrode (which may act as the gate terminal or be electrically connected to the gate terminal) is positioned adjacent to the channel region. A MOSFET may be turned on by applying a bias voltage to the gate electrode (to conduct current through the channel region between the source and drain regions), and may be turned off by removing the bias voltage (or lowering the bias voltage below a threshold) (to block current flowing through the channel region).

[0005] Both discrete power-packaged power semiconductor devices and multi-chip power-packaged power semiconductor devices are commercially available. Discrete power-packaged power semiconductor devices include a single power semiconductor die, such as a packaged MOSFET, Schottky diode, or IGBT. Multi-chip power-packaged power semiconductor devices refer to power semiconductor modules containing two or more power semiconductor dies (typically interconnected) within a common package. Discrete power-packaged power semiconductor devices constitute a large portion of the power electronics industry because they can be implemented at very low cost and can be easily combined to form more complex circuits.

[0006] Packaged power semiconductor devices typically generate a significant amount of heat during operation. To prevent this heat from damaging the device, the semiconductor die is typically mounted on a submount that acts as a heat sink to dissipate heat from the package. For example, copper or aluminum lead frames and / or copper-clad ceramic substrates are commonly used as submounts. The upper side of the submount may be plated with nickel or silver, or another metal that facilitates the mounting of the semiconductor die to the submount. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] IPC / JEDEC J-STD-033 [Overview of the project] [Means for solving the problem]

[0008] According to some embodiments of the present invention, a packaged power semiconductor device is provided, comprising a package, a power semiconductor die within the package, and a moisture barrier on the upper and side surfaces of the outer surface of the package.

[0009] In some embodiments, the package comprises a plastic outer covering. In some embodiments, the moisture barrier is located directly on the plastic outer covering. In some embodiments, the moisture barrier is a conformal moisture barrier that conforms to the plastic outer covering. In some embodiments, the moisture barrier is further located on at least a portion of the bottom of the outer surface of the package.

[0010] In some embodiments, the semiconductor die has a first terminal and a second terminal, and the package further comprises a first lead electrically connected to the first terminal and extending outward from the plastic outer covering, and a second lead electrically connected to the second terminal and extending outward from the plastic outer covering. In some embodiments, the first lead includes a wide segment extending through the outer surface of the plastic outer covering and a narrow segment extending outward from the wide segment, and the moisture barrier covers at least a portion of the wide segment.

[0011] In some embodiments, the package further includes a submount, and the semiconductor die is mounted on the upper surface of the submount.

[0012] In some embodiments, the submount comprises a lead frame or power substrate, and the plastic outer covering and submount enclose the semiconductor die together.

[0013] In some embodiments, the semiconductor die further includes a third terminal located opposite to the first and second terminals of the semiconductor layer structure of the semiconductor die, the third terminal being electrically connected to a submount.

[0014] In some embodiments, the package includes a submount and a housing, and the moisture barrier completely covers the bottom surface of the submount.

[0015] In some embodiments, the moisture barrier comprises at least one of perylene, silicone, polyurethane, or acrylic material.

[0016] In some embodiments, the moisture barrier comprises a coating having a thickness of 1 to 10 microns.

[0017] In some embodiments, the power semiconductor device is provided in combination with a printed circuit board, the power semiconductor device is mounted on the printed circuit board, and a portion of the moisture barrier is located between the package and the printed circuit board.

[0018] In some embodiments, the packaged electronic device is mounted on a metal pad on a printed circuit board, and a moisture barrier electrically insulates the semiconductor die from the metal pad.

[0019] In some embodiments, the moisture barrier is a first moisture barrier, and the power semiconductor device further comprises a second moisture barrier covering the top and side surfaces of the semiconductor die. In some embodiments, the second moisture barrier further covers portions of the first and second leads.

[0020] In some embodiments, the semiconductor die is a silicon carbide-based vertical MOSFET or Schottky diode.

[0021] In some embodiments, the semiconductor die is a first semiconductor die, and the power semiconductor device further comprises a second semiconductor die within the package.

[0022] In some embodiments, the moisture barrier covers not all but part of the portions of the first and second leads outside the plastic outer covering.

[0023] A further embodiment of the present invention provides a power semiconductor device comprising a housing, a semiconductor die having first terminals and second terminals, and moisture barriers on the upper and side surfaces of the semiconductor die, wherein the moisture barriers are positioned between the semiconductor die and the housing.

[0024] In some embodiments, the housing includes a plastic outer covering.

[0025] In some embodiments, the housing and the submount comprise a package for the power semiconductor device, and the semiconductor die is disposed on the upper surface of the submount.

[0026] In some embodiments, the submount comprises a lead frame or a power substrate, and the plastic outer coating and the submount encapsulate the semiconductor die together.

[0027] In some embodiments, the package further comprises a first lead electrically connected to the first terminal and a second lead electrically connected to the second terminal, and the moisture barrier further covers portions of the first and second leads located within the plastic outer coating.

[0028] In some embodiments, the moisture barrier directly contacts both the semiconductor die and the plastic outer coating.

[0029] In some embodiments, the moisture barrier is a conformal moisture barrier that conforms to the semiconductor die.

[0030] In some embodiments, the moisture barrier and the housing are made of different materials.

[0031] In some embodiments, the moisture barrier is a second moisture barrier, and the power semiconductor device further comprises a first moisture barrier located on the outer surface of the plastic outer coating.

[0032] In some embodiments, the plastic outer coating is located on the top surface and the side surfaces of the submount, and at least a portion of the bottom surface of the submount is free of the plastic outer coating.

[0033] In some embodiments, the first moisture barrier covers the bottom surface of the submount.

[0034] In some embodiments, the moisture barrier comprises at least one of perylene, silicone, polyurethane, or an acrylic material.

[0035] In some embodiments, the moisture barrier comprises a coating having a thickness of 1 to 10 microns.

[0036] In some embodiments, the power semiconductor device is provided in combination with a printed circuit board, the power semiconductor device is mounted on the printed circuit board, and a portion of the moisture barrier is located between the plastic outer covering and the printed circuit board.

[0037] In some embodiments, the power semiconductor device includes terminals mounted on a printed circuit board and on a heat sink, and a moisture barrier electrically insulates the semiconductor die from the heat sink.

[0038] A further embodiment of the present invention provides a manufacturing method in which a semiconductor die having a first terminal and a second terminal is packaged in a package including a submount and a housing to provide a spare power semiconductor device. A moisture barrier is formed on the spare power semiconductor device to form a power semiconductor device configured for installation on a printed circuit board.

[0039] In some embodiments, the housing comprises a plastic outer covering. In some embodiments, the moisture barrier is located directly on the outer surface of the plastic outer covering. In some embodiments, the moisture barrier is a conformal moisture barrier that conforms to the outer surface of the plastic outer covering.

[0040] In some embodiments, the package further comprises a first lead and a second lead, and the method further includes electrically connecting the first lead, which extends outward from the plastic outer sheath, to a first terminal, and electrically connecting the second lead, which extends outward from the plastic outer sheath, to a second terminal.

[0041] In some embodiments, the first lead includes a broad segment extending through the outer surface of the plastic outer coating and a narrow segment extending outward from the broad segment, and the moisture barrier covers at least a portion of the broad segment.

[0042] In some embodiments, the submount comprises a lead frame or power substrate, and the plastic outer covering and submount enclose the semiconductor die together.

[0043] In some embodiments, the moisture barrier is formed to completely cover the bottom surface of the package.

[0044] In some embodiments, forming a moisture barrier includes forming a moisture barrier via chemical vapor deposition. In some embodiments, forming a moisture barrier includes forming a moisture barrier by immersing a spare power semiconductor device in a solution of moisture barrier material. In some embodiments, forming a moisture barrier includes spraying moisture barrier material onto a spare power semiconductor device.

[0045] In some embodiments, the method further includes baking the plastic outer coating at a temperature of at least 120°C to remove moisture from the plastic outer coating prior to forming a moisture barrier.

[0046] In some embodiments, the moisture barrier is formed within two hours of the formation of the outer coating plastic or the completion of a baking process applied to the outer coating plastic to remove moisture from it.

[0047] In some embodiments, the moisture barrier comprises at least one of perylene, silicone, polyurethane, or acrylic material.

[0048] In some embodiments, the moisture barrier comprises a coating having a thickness of 1 to 10 microns.

[0049] In some embodiments, the method further includes mounting a power semiconductor device on a printed circuit board such that a portion of the moisture barrier is located between the package and the printed circuit board.

[0050] In some embodiments, the power semiconductor device is mounted on a metal pad on a printed circuit board, and a moisture barrier electrically insulates the semiconductor die from the metal pad.

[0051] In some embodiments, the moisture barrier is a first moisture barrier, and the method further includes forming a second moisture barrier that covers the upper and side surfaces of the semiconductor die and portions of the first and second leads, the second moisture barrier being positioned between the semiconductor die and a second portion of the package. [Brief explanation of the drawing]

[0052] [Figure 1A] This is a top perspective view of a discrete packaged power semiconductor device according to an embodiment of the present invention. [Figure 1B] Figure 1A is a perspective view of a discrete packaged power semiconductor device with the moisture barrier and outer covering package removed. [Figure 1C] Figure 1A is a schematic cross-sectional view of a discrete power semiconductor electronic device. [Figure 2] This is a schematic cross-sectional view of a packaged power semiconductor device according to a further embodiment of the present invention, including a power substrate. [Figure 3] This is a schematic vertical cross-sectional view of a packaged power semiconductor device according to an additional embodiment of the present invention, in which a moisture barrier completely seals the submount. [Figure 4A] This is a schematic cross-sectional view of a packaged power semiconductor device according to a further embodiment of the present invention, which includes an internal moisture barrier. [Figure 4B] This is a schematic cross-sectional view of a modified version of the packaged power semiconductor device shown in Figure 4A, which further includes an external moisture barrier. [Figure 5]This is a schematic vertical cross-sectional view of a packaged power semiconductor device according to a further embodiment of the present invention. [Figure 6] This is a schematic vertical cross-sectional view of a packaged power semiconductor device according to a further embodiment of the present invention. [Figure 7] This is a schematic vertical cross-sectional view of a packaged power semiconductor device according to a further embodiment of the present invention. [Figure 8] This is a flowchart illustrating a method for fabricating a packaged power semiconductor device according to an embodiment of the present invention. [Modes for carrying out the invention]

[0053] It should be noted that when multiple similar elements are shown in a figure, they may be identified using two-part reference numerals. Such elements may be referred individually by their complete reference numerals (e.g., floating lead 136-1) or collectively by the first part of their reference numerals (e.g., floating lead 136).

[0054] Power semiconductor devices are designed to interrupt high voltages during reverse blocking operation and to pass high current levels during on-state operation. For example, power semiconductor devices may need to interrupt hundreds or thousands of volts and / or pass tens or hundreds of amperes. Operation at these voltage and current levels can generate considerable heat within the power semiconductor die. Due to the high heat levels, many discrete power semiconductor devices are packaged in ceramic air cavity packages, in which the power semiconductor die is mounted on a metal submount and sealed within an air cavity of a ceramic housing (these packages are called ceramic air cavity packages). The ceramic housing and metal submount can withstand the heat generated by the power semiconductor die during operation and can efficiently dissipate this heat. However, the use of ceramic air cavity packages increases both the size and cost of the packaged power semiconductor device.

[0055] Most semiconductor devices operating at low power levels are packaged by encapsulating the semiconductor die in a plastic outer covering. In recent years, plastic outer covering encapsulants suitable for use with power semiconductor devices have been developed. When a plastic outer covering encapsulant is used, the semiconductor die is typically mounted on a submount, and leads are electrically connected to corresponding terminals on the semiconductor die. A plastic outer covering material, such as an epoxy molding compound, is then injection molded to encapsulate at least a portion of the power semiconductor die and submount. The leads extend through the plastic outer covering encapsulant to allow electrical connections between the semiconductor die and external devices (e.g., inputs, outputs, bias voltage sources, etc.). The submount, leads, and plastic outer covering encapsulant together constitute a package for the power semiconductor die.

[0056] Discrete packaged power semiconductor devices are typically mounted on printed circuit boards of larger electronic systems. Unfortunately, standard epoxy molding compounds are susceptible to moisture absorption from the environment. This absorption can primarily take the form of direct diffusion of moisture through the epoxy resin. Moisture absorption into power semiconductor dies encapsulated in plastic outer coatings can be problematic. Specifically, moisture absorbed by the plastic outer coating expands during the soldering reflow process used to mount discrete power semiconductor devices to printed circuit boards of larger electronic systems. As the plastic outer coating expands, it can delaminate from the semiconductor die. In some cases, the plastic outer coating may crack or even rupture instead. Generally speaking, delamination of the outer coating encapsulation can lead to premature device failure (for example, if the device experiences thermal cycling during normal operation, delamination may increase, which can weaken or break the connection between the power semiconductor die terminals and the package leads), while cracking (or rupture) of the plastic outer coating typically results in immediate device failure.

[0057] To minimize the likelihood that moisture absorption could lead to device failure, plastic-encased power semiconductor devices may be evaluated based on industry-standardized moisture sensitivity criteria published by IPC International, a global association of entities engaged in the manufacture of electronic equipment. These moisture sensitivity criteria are described in Non-Patent Literature 1. Non-Patent Literature 1 specifies eight different moisture sensitivity levels and, for each level, specifies the maximum length of time that the packaged semiconductor device may be kept outside the moisture barrier bag before being soldered to a printed circuit board. For example, an electronic device with a moisture sensitivity evaluation level of "3" in Non-Patent Literature 1 should not be kept outside the moisture barrier bag for more than one week at temperatures below 30°C and relative humidity below 60% before being soldered to a printed circuit board, in accordance with the standards of Non-Patent Literature 1, in order to ensure that there is no increased risk of moisture-induced failure in the device.

[0058] A higher humidity sensitivity rating can severely limit the time an electronic device can be outside a moisture barrier bag before being soldered to the printed circuit board of a larger system. For example, an electronic device with the humidity sensitivity rating of "5a" in Non-Patent Document 1 can only be kept outside a moisture barrier bag for 24 hours. Electronic equipment manufacturers assembling electronic devices, including discrete packaged power semiconductor devices, must take into account the humidity sensitivity rating of the discrete packaged power semiconductor devices during the fabrication process to ensure that the devices are not exposed to excessive moisture absorption, which can result in damage or destruction of the packaged power semiconductor devices, particularly during solder reflow operations. This can complicate the fabrication process and increase the risk that the larger electronic system may fail prematurely due to moisture-induced failures of power semiconductor devices contained within the larger electronic system.

[0059] According to embodiments of the present invention, a packaged power semiconductor device is provided which includes a package and a separate moisture barrier. The outer coating encapsulant may be formed of a plastic material, such as an epoxy molding compound. The moisture barrier may be conformally coated onto the plastic outer coating encapsulant. As is known in the art, a conformal coating refers to a layer of material that is coated (e.g., formed or deposited) on the surface of an underlying structure, which generally conforms to or "follows" the shape of the surface of the underlying structure. Conformal coatings generally have a uniform thickness (e.g., less than 10-15% variation over flat surfaces of the underlying structure, but slightly larger variation may occur at corners or other non-planar areas). The moisture barrier may include any material that significantly or completely prevents moisture from entering the outer coating encapsulant. For example, acrylic materials, polyurethanes, silicones, and / or parylenes are all materials that can be conformally formed or deposited as a coating that acts as such a moisture barrier. A moisture barrier can be formed on the plastic outer coating encapsulant by, for example, automated ovarian removal, immersion, condensation processes, or chemical vapor deposition. Adding this moisture barrier to a packaged power semiconductor device can significantly extend the time the device can remain outside the moisture barrier bag before being soldered to the customer printed circuit board. The moisture barrier can also reduce the likelihood of moisture-induced device failure during normal device operation. The moisture barrier can be applied immediately after the formation of the plastic outer coating encapsulant (e.g., following a baking operation used to cure the plastic outer coating) or during a later processing step. The packaged power semiconductor device may optionally undergo a slow baking operation designed to remove moisture from the device prior to the application of the moisture barrier.

[0060] In some embodiments, the moisture barrier may be applied to substantially or completely cover the plastic outer covering encapsulation material. In this specification, "substantially" means within + / - 10%. The moisture barrier may not be applied to, or may only partially apply to, exposed metal elements of a packaged power semiconductor device designed to be soldered to external elements such as metal pads. In other embodiments, the moisture barrier may completely encapsulate the entire body of the packaged power semiconductor device, with only the distal portions of the leads not being included. In such embodiments, the moisture barrier may be part of the primary heat dissipation path from the semiconductor die to an external heat sink, such as a heat sink surface-mounted on a customer printed circuit board. The moisture barrier may be thin enough to have good thermal conductivity and electrically isolate the packaged power semiconductor device from the heat sink.

[0061] As described above, the package leads of a plastic-encased packaged power semiconductor device extend through the plastic outer coating so that each lead has both an enclosed segment and an exposed segment. In some embodiments, a moisture barrier may extend over the portion of the exposed segment of a lead adjacent to the plastic outer coating encapsulant. This can help ensure that the lead itself does not provide a path for moisture to enter the outer coating encapsulant. Furthermore, as discussed below, the moisture barrier can favorably increase the "creepage distance" between adjacent leads, which can improve device performance.

[0062] The moisture barrier described above is provided on the outer surface of the plastic outer coating encapsulant (for example, conformally formed on the outer surface), but the teachings of the present invention are not limited thereto. For example, in other embodiments, the moisture barrier may be formed on the semiconductor die, submount, and leads (and optionally bond wires) after the leads are electrically connected to the terminals of the semiconductor die, but before the plastic outer coating is formed to encapsulate the semiconductor die. In such embodiments, the moisture barrier would be located between the semiconductor die and the plastic outer coating encapsulant. This “internal” moisture barrier may be provided as a standalone moisture barrier or may be combined with the above-mentioned moisture barrier formed on the outer surface of the plastic outer coating encapsulant.

[0063] Next, embodiments of the present invention will be discussed in more detail with reference to the attached figures. It will be recognized that the features of the various embodiments disclosed herein can be combined in any way to provide many additional embodiments. Thus, although various features of the present invention are described below with respect to specific examples, it will be recognized that these features can be added to and / or used in place of exemplary features of other embodiments to provide many additional embodiments. Therefore, the present invention should be understood to encompass these various combinations. Furthermore, although the exemplary embodiments focus on MOSFET embodiments, it will be recognized that the same techniques can be used in other packaged electronic devices such as IGBTs, Schottky diodes, gate-controlled thyristors, and so on.

[0064] Figures 1A to 1C schematically show packaged power semiconductor devices according to several embodiments of the present invention. Specifically, Figure 1A is a top perspective view of the packaged power semiconductor device 100, Figure 1B is a perspective view of the packaged power semiconductor device 100 with the moisture barrier and plastic outer coating removed, and Figure 1C is a schematic vertical cross-sectional view of the device 100.

[0065] Referring to Figures 1A to 1C, the packaged power semiconductor device 100 includes a power semiconductor die 110 mounted on the upper surface of a submount, the submount in this embodiment comprising a lead frame 130. The power semiconductor die 110 may be a semiconductor device designed to interrupt high voltage levels (e.g., several hundred volts or more) and / or carry large currents. The power semiconductor die 110 may include a semiconductor layer structure, which is formed using, for example, broad bandgap semiconductor materials such as silicon and / or silicon carbide, and / or gallium nitride-based and / or aluminum nitride-based semiconductor systems (e.g., GaN, AlGaN, InGaN, AlN, etc.). Other broad bandgap materials may be used, such as devices formed in other group III-V or group II-VI semiconductor systems. The power semiconductor die 110 may include, for example, a MOSFET, MISFET, IGBT, Schottky diode, gate-controlled thyristor, etc. The power semiconductor die 110 may have a vertical structure in which the upper side of the die includes at least one terminal and the lower side of the die 110 also includes at least one terminal.

[0066] In the demonstrated embodiment, the power semiconductor die 110 is a discrete power MOSFET having a vertically extending drift region through which current flows during on-state operation. As shown in Figure 1C, the MOSFET includes a semiconductor layer structure 112. The semiconductor layer structure 112 may be formed from a broad-bandgap semiconductor material, such as silicon carbide. The gate terminal 114 and source terminal 116 are located on the upper surface of the semiconductor layer structure 112, and the drain terminal 118 is located on the lower surface of the semiconductor layer structure 112. Each of the terminals 114, 116, and 118 may be mounted as an exposed metal pad. Typically, the gate terminal / pad 114 is smaller than the source terminal / pad 116, and the drain terminal 118 may be approximately the same size as or larger than the source terminal / pad 116. Since the source terminal 116 and drain terminal 118 are located on opposite sides of the semiconductor layer structure 112, the MOSFET 110 is a vertical device.

[0067] The lead frame 130 includes a die mounting area 132 on its upper surface and integrated leads 134. The bottom surface of the MOSFET 110 can be attached to the die mounting area 132 of the lead frame 130 using any suitable bonding material or technique. In the shown embodiment, the MOSFET 110 is coupled to the lead frame 130 using die mounting material 122. The drain terminal 118 of the MOSFET 110 is electrically connected to the integrated leads 134 through the die mounting material 122 and the lead frame 130. A pair of floating leads 136-1, 136-2 are provided, and one or more bond wires 124 physically and electrically connect the gate terminal 114 and source terminal 116 on the upper side of the MOSFET 110 to the respective floating leads 136-1, 136-2. In the illustrated embodiment, a single bond wire 124 connects the gate terminal 114 to the floating lead 136-1, while three bond wires 124 connect the source terminal 116 to the floating lead 136-2. It should be noted that, in this specification, the term “bond wire” is used broadly to cover not only conventional bond wires but also other functionally equivalent structures such as ribbons or clips that may be used in place of pure wires.

[0068] The plastic outer covering encapsulation 150 encapsulates at least the upper surface of the power semiconductor die 110 and the lead frame 130, as well as at least a portion of each side surface of the lead frame 130. The leads 134 and 136 extend through the plastic outer covering encapsulation 150 such that each lead 134 and 136 has a first segment located inside the plastic outer covering encapsulation 150 and a second segment located outside the plastic outer covering encapsulation 150. The plastic outer covering encapsulation 150 covers and protects the MOSFET 110. While embodiments of the present invention are primarily described in relation to devices comprising an epoxy molding compound as the outer covering encapsulation, it will be recognized that embodiments of the present invention are not limited thereto. For example, in other embodiments, the encapsulation may comprise a silicone gel or another compound. The encapsulation 150 can hold the floating leads 136 in their appropriate positions.

[0069] The lead frame 130, leads 134 and 136, and outer covering encapsulation 150 together form a package 120 for the power semiconductor die 110. One integrated lead 134 and two floating leads 136 are provided, but it will be recognized that embodiments of the present invention are not limited thereto. For example, in other embodiments, three floating leads 136 may be provided and the integrated lead 134 may not be provided. It will also be recognized that multiple leads may be provided for one or more of the terminals 114, 116, and 118 of the power semiconductor die 110. For example, the source terminal 116 and / or the drain terminal 118 may each be connected to two leads. It will also be recognized that the number of terminals and / or the number of leads may vary depending on the type of semiconductor die 110. For example, a Schottky diode has only two terminals (anode terminal and cathode terminal), and therefore a packaged Schottky diode may have only two leads. The floating lead 136 may initially be integrated with the lead frame 130, but may be separated from the lead frame 130 during the manufacturing process and may be held in place by the outer covering encapsulant 150.

[0070] As best illustrated in Figure 1C, the moisture barrier 160 is provided on the outer surface of the plastic outer coating encapsulant 150. The moisture barrier 160 may be formed after the outer coating encapsulant 150 has been formed and cured. In some embodiments, the moisture barrier 160 may be conformally formed on the plastic outer coating encapsulant 150. The plastic outer coating encapsulant 150 may include a rigid material to protect the MOSFET 110 during handling. In contrast, the moisture barrier 160 may be made of a less rigid material, such as a material that significantly or completely prevents moisture from entering the outer coating encapsulant and has good coating properties, so that a continuous coating can be applied to provide a barrier against moisture entering the plastic outer coating encapsulant 150. In exemplary embodiments, the moisture barrier may include an acrylic material, a polyurethane material, a silicone material, and / or a parylene material. All of these materials may be conformally formed or deposited as a coating to significantly or completely prevent moisture from entering the outer coating encapsulant.

[0071] The moisture barrier 160 may comprise a thin layer which may be formed / deposited on the outer surface of the plastic outer coating encapsulant 150 and optionally on selected portions of the lead frame 130 and / or leads 134, 136 extending outward from the outer coating encapsulant 150. For example, as shown in Figure 1C, the moisture barrier 160 may extend over some or all of the lateral surfaces of the lead frame 130. The moisture barrier 160 may also partially extend over each portion of leads 134, 136 extending outward from the outer coating encapsulant 150. In exemplary embodiments, the moisture barrier 160 may have a thickness between 1 and 10 microns. In some embodiments, the moisture barrier 160 may conformally coat the plastic outer coating encapsulant.

[0072] The moisture barrier 160 may be formed on the plastic outer coating encapsulant 150 by, for example, a spraying or sputtering process. For example, the moisture barrier may be sprayed onto the outer coating encapsulant 150 in liquid form using an automated spraying process to ensure a substantially consistent thickness of the moisture barrier coating (it should be noted that variations in coating thickness at corners will be expected), and the material may be cured to form the moisture barrier 160. Alternatively, the packaged electronic device 100 may be immersed in a vat of moisture barrier material to form the moisture barrier 160 after the plastic outer coating encapsulant 150 has been formed. The distal ends of the leads 134, 136 are typically not covered with the moisture barrier 160 so that the leads 134, 136 can be connected to an external device (for example, by a bond wire), so the packaged power semiconductor device 100 may be held by one or more of the leads 134, 136 during this immersion process.

[0073] In other embodiments, the moisture barrier 160 may be formed by a chemical deposition process. Specifically, after the plastic outer coating encapsulant 150 is formed (including curing), the packaged power semiconductor device 100 may be placed in a chemical vapor deposition chamber, and the raw material for the moisture barrier 160 may be injected into the chamber in gaseous form. The packaged power semiconductor device 100 may be positioned in another part of the chamber at a lower temperature and / or pressure, and the gaseous material may be condensed on the outer surface of the packaged power semiconductor device 100 to form the moisture barrier 160. During any of the fabrication processes discussed above, the portion of the packaged power semiconductor device 100 to which the moisture barrier should not be applied may be covered with a mask (e.g., Kapton tape, photoresist, etc.). The mask may be removed later along with any moisture barrier material deposited on the mask. In other embodiments, a fixture acting as a mask may be provided. For example, if chemical vapor deposition is used to form a moisture barrier 160, a fixture including an opening that snugly receives each end of the leads 134 and 136 of the packaged power semiconductor device 100 may be provided in the chemical vapor deposition chamber. The packaged power semiconductor device 100 can be placed in the chamber by inserting the ends of the leads 134 and 136 into the fixture. Thus, all parts of the packaged power semiconductor device 100 except for the leads 134 and 136 are exposed, and the moisture barrier 160 can be formed by chemical vapor deposition to cover the entire exterior of the packaged power semiconductor device except for the ends of the leads 134 and 136.

[0074] The moisture barrier 160 may be applied immediately after the formation (including curing) of the plastic outer coating encapsulant 150. This can help ensure that moisture does not enter the plastic outer coating encapsulant 150 prior to the formation of the moisture barrier 160. The packaged power semiconductor device 100 may optionally undergo a slow baking process designed to remove moisture from the device 100 prior to the application of the moisture barrier 160. For example, the packaged power semiconductor device 100 may be baked at a temperature of 125°C for at least 8 hours to remove moisture therefrom, and then the moisture barrier 160 may be formed on the outer coating encapsulant 150. Alternatively, the packaged power semiconductor device 100 may be baked at a lower temperature for a longer period of time, or at a higher temperature for a shorter period of time. Generally speaking, the longer the baking process and the higher the temperature, the greater the baking process's ability to remove moisture present in the device. Slow baking may be performed, for example, when the moisture barrier 160 is not immediately applied after the formation of the outer coating encapsulant 150.

[0075] It will be recognized that the materials discussed above, which may be used to form the moisture barrier 160, and the techniques for forming the moisture barrier 160 discussed above, may be used to form any of the moisture barriers discussed below that are included in the packaged power semiconductor devices according to embodiments of the present invention.

[0076] As shown in Figure 1C, leads 134, 136 extend through the plastic outer covering encapsulant 150 such that each lead 134, 136 has both an encapsulated segment and an exposed segment. In some embodiments, a moisture barrier 160 may extend over the portion of the exposed segments of leads 134, 136 adjacent to the plastic outer covering encapsulant 150. This can help ensure that leads 134, 136 themselves do not provide a path for moisture to enter the outer covering encapsulant 150. Furthermore, the moisture barrier 160 can favorably increase the "creepage distance" between adjacent leads, which refers to the shortest distance along the surface of the dielectric material between two conductive components. In this case, the creepage distance is the distance between the exposed portions of adjacent leads 134, 136 along the surface of the intervening dielectric material. Since the moisture barrier 160 covers a portion of leads 134, 136, the creepage distance is increased. This allows the packaged power semiconductor device 100 to be rated for higher operating voltages and / or to operate in more contaminated environments.

[0077] As the above discussion makes clear, the packaged power semiconductor device 100 includes a semiconductor die 110 having at least a first terminal 114 and a second terminal 116. A package comprising a plastic outer covering 150 covers the semiconductor die 110 at least partially. The package may also include a first lead 136-1 electrically connected to the first terminal 114 and a second lead 136-2 electrically connected to the second terminal 116. The first and second leads 136-1 and 136-2 each extend outward from the plastic outer covering 150. A moisture barrier 160 is located on the upper and side surfaces of the plastic outer covering 150.

[0078] In some embodiments, the moisture barrier 160 may be located directly on the top, side, and bottom surfaces of the outer covering package 150. In some embodiments, the first and second terminals 114, 116 may be located on the first surface of the semiconductor layer structure 112 of the semiconductor die 110, and the semiconductor die 110 may further include a third terminal 118 located on the opposite side of the first and second terminals 114, 116 of the semiconductor layer structure 112. The package 120 may also include a submount 130, and the semiconductor die 110 may be mounted on the top surface of the submount 130. In some embodiments, the moisture barrier 160 may completely cover the bottom surface of the package 120.

[0079] In some embodiments, the moisture barrier 160 comprises at least one of parylene, silicone, polyurethane, or acrylic material, and / or the moisture barrier 160 may have a thickness between 1 and 10 microns. As shown in Figures 1A and 1B, in some embodiments, the first lead 136-1 may include a wide segment extending through the outer surface of the outer covering package 150 and a narrow segment extending outward from the first wide segment, and the moisture barrier 160 may cover at least a portion of the wide segment.

[0080] In some embodiments, the packaged electronic device 100 may be mounted on a printed circuit board, such as a customer printed circuit board, and a portion of the moisture barrier 160 may be located between the outer sheathing package 150 and the printed circuit board. For example, the packaged electronic device 100 may be mounted on a metal pad on the customer printed circuit board (e.g., using screws or clips), and the moisture barrier 160 can electrically insulate the semiconductor die 110 from the metal pad.

[0081] As described above, packaged power semiconductor devices such as device 100 are typically mounted on printed circuit boards of larger electronic systems. These larger printed circuit boards are often referred to as customer motherboards. Packaged power semiconductor device 100 is typically mounted on a heatsink on the customer motherboard so that heat released through the main thermal interface of packaged power semiconductor device 100 (here, through the drain terminal 118 and the lead frame 130) can also be released from the customer motherboard. Often, the heatsink is surface-mounted on the customer motherboard. In some cases, an exposed metal portion of packaged power semiconductor device 100 (e.g., the bottom surface of the submount 130) may be mounted on the heatsink. In some cases, leads 134 and 136 of packaged power semiconductor device 100 may be mounted in their respective plated through-holes on the customer motherboard. In some cases, the exposed metal portion of the packaged power semiconductor device 100 may be mounted on a heat sink, and the leads 134 and 136 may also be mounted in the respective plated through-holes of the customer motherboard.

[0082] As can be seen from Figure 1C, the main thermal interface cannot be electrically isolated from the power semiconductor die 110 because the drain terminal 118 is electrically connected to the bottom of the lead frame 130. It is often necessary to electrically isolate the semiconductor die 110 from the heat sink on the customer motherboard. This can be achieved by interposing a so-called "thermal pad" in the form of a thin dielectric layer (e.g., a silicone layer) between the packaged power semiconductor device 100 and the heat sink on the customer motherboard, electrically isolating the power semiconductor die 110 from the heat sink. The packaged power semiconductor device may be mechanically mounted to the customer motherboard (e.g., a heat sink for the motherboard) with a thermal pad between it and the customer motherboard, for example, using screws or spring clips, and the device leads may be soldered to the motherboard. Using such a thermal pad to electrically isolate the power semiconductor die 110 from the customer motherboard is acceptable and convenient for packaged power semiconductor devices operating at low voltage levels (e.g., tens of volts) and current levels. However, for power semiconductor devices designed to isolate hundreds or even thousands of volts, capacitive coupling across the thermal pad can be strong enough to adversely affect the performance of the semiconductor device and / or degrade the thermal pad material, potentially leading to a short circuit between the main thermal interface and the metal pad on the customer motherboard. Such a short circuit can typically render the packaged power semiconductor device inoperable and may even damage or destroy the device.

[0083] Figure 2 is a schematic cross-sectional view of a discrete packaged power semiconductor device 200 according to a further embodiment of the present invention. The packaged power semiconductor device 200 is similar to the packaged power semiconductor device 100 discussed above in relation to Figures 1A to 1C, but further includes a power substrate 240. As discussed below, the power substrate 240 includes an insulating substrate that electrically isolates the power semiconductor die 110 from the customer motherboard.

[0084] As can be seen by comparing Figure 1C and Figure 2, the only difference between the packaged power semiconductor device 200 and the packaged power semiconductor device 100 is that the packaged power semiconductor device 200 further includes (1) a power substrate 240 attached to the bottom surface of the lead frame 130, and (2) a plastic outer covering 250 and a moisture barrier 260 extending to cover the side surface of the power substrate 240. Accordingly, elements of the packaged power semiconductor device 200 that correspond to or substantially correspond to the corresponding elements of the packaged power semiconductor device 100 are labeled using the same reference numerals used in Figures 1A to 1C, and further description of those similar elements is generally omitted. The same convention applies throughout this application.

[0085] As shown in Figure 2, the power substrate 240 includes a ceramic substrate 242. A lower metal cladding layer 246-1 is formed on the underside of the ceramic substrate 242, and an upper metal cladding layer 246-2 is formed on the upperside of the ceramic substrate 242. The lead frame 130 is mounted on the upper metal cladding layer 246-2 using substrate mounting material 126. In this specification, the term “power substrate” refers to a dielectric substrate having metal cladding layers on both sides thereof. Two main types of power substrates exist. The first type is known as an active metal brazed (AMB) power substrate, which includes first and second metal brazing layers 244-1 and 244-2, used to bond the first and second metal cladding layers 246-1 and 246-2 to the ceramic substrate 242, respectively. In contrast to soldering, brazing can be used to bond metal to a dielectric surface. Metal brazing materials share some similarities with solder, but the bonding process is carried out at higher temperatures, most typically in a vacuum. The resulting bond is more reliable compared to conventional soldering. A second type of power substrate is called a Direct Bonded Substrate (or, more typically, a Direct Bonded Copper (DBC) power substrate, since the metal cladding layers 246-1 and 246-2 are typically copper layers). DBC power substrates are formed by directly pressing metal cladding layers 246-1 and 246-2 onto a dielectric substrate 242 while it undergoes heat treatment in a controlled atmosphere. DBC power substrates are not as reliable as AMB power substrates.

[0086] The plastic outer covering 250 differs from the plastic outer covering 150 in that it extends to cover the side surface of the power substrate 240. The moisture barrier 260 conformally covers the plastic outer covering 250 and selected portions of the power substrate 240 and leads 134, 136. The lead frame 130, leads 134, 136, power substrate 240, and plastic outer covering 250 form the package 220 for the power semiconductor die 110. The moisture barrier 260 protects the package 220 from moisture ingress. The power substrate 240 functions as the primary thermal interface for dissipating heat generated in the power semiconductor die 110 from the device package 220.

[0087] The packaged power semiconductor device 200 includes both a lead frame 130 and a power substrate 240, although the lead frame 130 may be omitted in other embodiments, and the integrated leads 134 of the lead frame may be replaced with third floating leads 136. In such embodiments, the power semiconductor die 110 may be mounted directly on the upper cladding layer 246-2 via a die mounting material 122.

[0088] The packaged power semiconductor devices 100 and 200 in Figures 1A to 1C and Figure 2 include moisture barriers 160 and 260 that do not cover most of the exposed bottom surface of the submounts 130 and 240. Figure 3 is a schematic vertical cross-sectional view of a discrete packaged power semiconductor device 300 according to a further embodiment of the present invention, which includes a moisture barrier 360 that completely covers the exposed bottom surface of the submount 130.

[0089] As can be seen by comparing Figure 1C and Figure 3, the packaged power semiconductor device 300 may be identical to the packaged power semiconductor device 100, except that it includes a moisture barrier 360 that extends substantially or completely over the bottom surface of the lead frame 130. Thus, the moisture barrier 360 can completely enclose the entire body of the package 120 such that the moisture barrier 360 cannot be present only on the distal portions of the leads 134 and 136. The moisture barrier 360 may be part of a heat dissipation path from the semiconductor die 110 to an external heat sink, such as a heat sink on a customer printed circuit board. Since the moisture barrier 360 completely encloses the lead frame 130 (except for the integrated leads 134), the moisture barrier 360 electrically isolates the packaged electronic device 300 from the printed circuit board or heat sink (not shown) on which the packaged electronic device 300 is installed. Furthermore, since the moisture barrier 360 can be very thin, it can exhibit good thermal conductivity and therefore does not interfere with heat dissipation paths extending through the moisture barrier 360. In some embodiments, the moisture barrier 360 can eliminate the need for a thermal pad between the packaged power semiconductor device and the heat sink, as well as the need to include a power substrate in the packaged power semiconductor device. In other words, in some embodiments, the lead frame of the packaged power semiconductor device can be mounted directly to the heat sink without an intervening thermal pad, since the moisture barrier 360 can electrically isolate the lead frame 130 from the customer motherboard / heat sink.

[0090] It will be understood that the packaged power semiconductor device 300 includes a lead frame 130, but may also include a power substrate 240 (similar to the packaged power semiconductor device 200 in Figure 2), or may include a power substrate that replaces the lead frame 130.

[0091] As discussed above, packaged power semiconductor devices, including plastic outer covering encapsulants, can be particularly susceptible to moisture-related damage during the solder reflow process often used to mount the device onto customer printed circuit boards. As noted above, moisture accumulation within the plastic outer covering can lead to delamination of the plastic outer covering from the semiconductor die, or cracking of the plastic outer covering encapsulant. Furthermore, much smaller amounts of moisture can also cause problems if they penetrate the power semiconductor die. Power semiconductor dies typically include a passivation layer that acts as a moisture barrier, but the top surface of most power semiconductor dies has metal bonding pads that act as terminals for the device. The passivation layer does not cover these pads, allowing bond wires or leads to be soldered to them. The seams between the metal bonding pads and the passivation on the top surface of the semiconductor die can be susceptible to moisture intrusion.

[0092] The moisture barriers 160, 260, and 360 described above are provided on the outer surface of the plastic outer coating encapsulant (for example, conformally formed on the outer surface), but the teachings of the present invention are not limited thereto. Specifically, according to further embodiments of the present invention, a packaged power semiconductor device is provided which includes an internal moisture barrier, which is conformally coated onto the semiconductor die and submount after electrical connection to the terminals of the power semiconductor die has been made, but prior to the application of the plastic outer coating encapsulant. The internal moisture barrier may be positioned between the power semiconductor die and the outer coating encapsulant.

[0093] Figure 4A is a schematic vertical cross-sectional view of a packaged power semiconductor device 400 according to a further embodiment of the present invention, which includes such an internal moisture barrier 470. As shown in Figure 4A, the packaged power semiconductor device 400 may be very similar to the packaged power semiconductor device 100 discussed above in relation to Figures 1A-1C. The packaged power semiconductor device 400 differs from the packaged power semiconductor device 100 in two respects. First, the packaged power semiconductor device 400 does not include the external moisture barrier 160 included in the packaged electronic device 100. Second, the packaged power semiconductor device 400 includes an internal moisture barrier 470 conformally coated over a portion of the semiconductor die 110, lead frame 130, bond wire 124, and leads 134, 136. The internal moisture barrier 470 is formed after the power semiconductor die 110 is mounted on the lead frame 130 and the wire bond 124 is coupled to terminals 114, 116 and floating leads 136. Therefore, the internal moisture barrier 470 does not adversely affect the electrical connection with the device 400. The internal moisture barrier 470 can completely cover the top and side surfaces of the power semiconductor die 110. The internal moisture barrier 470 may also cover part or all of the top and / or side surfaces of the lead frame 130. The internal moisture barrier 470 may also cover parts of the leads 134, 136 and the bond wire 124 (the internal moisture barrier covering the bond wire 124 is not shown in Figures 4A-4B).

[0094] Accordingly, the packaged power semiconductor device 400 includes a semiconductor die 110 having a first terminal 114 and a second terminal 116, a first lead 136-1 electrically connected to the first terminal 114 and a second lead 136-2 electrically connected to the second terminal 116, an internal moisture barrier 470 covering the upper and side surfaces of the semiconductor die 110 and a portion of the first and second leads 136-1 and 136-2, and a plastic outer covering 150 covering the internal moisture barrier 470. In some embodiments, the internal moisture barrier 470 may be a conformal internal moisture barrier 470.

[0095] Figure 4B is a schematic cross-sectional view of a modified version 400' of the packaged power semiconductor device 400 shown in Figure 4A. The packaged power semiconductor device 400' is identical to the packaged power semiconductor device 400, except that it further includes the external moisture barrier 160 discussed above in relation to Figures 1A-1C. Therefore, further explanation of the packaged power semiconductor device 400' is omitted.

[0096] Figure 5 is a schematic vertical cross-sectional view of a packaged power semiconductor device 500 according to a further embodiment of the present invention. The packaged power semiconductor device 500 is similar to the packaged power semiconductor device 200, except that the need for bond wires is eliminated by directly soldering leads 136-1 and 136-2 to terminals 114 and 116, respectively. Leads 136-1 and 136-2 are both shown extending from different sides of the device 500, as is better seen in the cross-sectional view of Figure 5. It will be recognized that any embodiment of the present invention discussed herein may have such directly soldered leads used in place of floating leads 136 that are physically and electrically connected to terminals 114 and 116 via bond wires 124.

[0097] Figure 6 is a schematic vertical cross-sectional view of a packaged power semiconductor device 600 according to a further embodiment of the present invention. The packaged power semiconductor device 600 is similar to the packaged power semiconductor device 100, except that the integrated leads 134 are replaced by third floating leads 136-3. The electrical connection between the drain of the power semiconductor die 110 and the third floating leads 136-3 is through the drain terminal 118, die mounting material 122, lead frame 130, and bond wire 124. It will be recognized that any embodiment of the present invention discussed herein may have the lead arrangement shown in Figure 6.

[0098] While embodiments of the present invention have been primarily discussed in relation to discrete packaged power semiconductor devices comprising a single semiconductor die 110, it will be recognized that embodiments of the present invention are not limited thereto. For example, Figure 7 shows a packaged power semiconductor device 700 in the form of a power semiconductor module comprising two power semiconductor dies 110-1, 110-2. In an exemplary embodiment, the two power semiconductor dies 110-1, 110-2 may be power MOSFETs electrically connected, for example, in series or in parallel. As shown in Figure 7, pairs of floating gate leads 136-1, 136-2 are electrically connected by bond wires 124 to the gate terminals 114-1, 114-2 of each power semiconductor die 110-1, 110-2 (in other embodiments, both gate terminals 114 may be connected to a single floating gate lead 136). The source terminals 116-1, 116-2 of each die 110 may be connected to one or more floating source leads 136. Drain terminals 118-1 and 118-2 are connected to their respective integrated drain leads 134-1 and 134-2 (in other embodiments, a single drain lead 134 may be provided that is electrically connected to the drain terminals of both power semiconductor dies 110-1 and 110-2). The power semiconductor dies 110-1 and 110-2 are enclosed within an outer covering package 150, and a moisture barrier 160 (e.g., a conformal moisture barrier 160) covers at least the upper and side surfaces of the plastic outer covering encapsulant 150. The moisture barrier 160 may also partially extend over the bottom surface of the plastic outer covering 150 (or completely cover the bottom surface). It will therefore be recognized that the moisture barrier according to embodiments of the present invention may also be applied to multi-chip modules. It will also be recognized that the multi-chip module may instead or in addition include the internal moisture barrier 470 discussed above in relation to Figures 4A and 4B.

[0099] When a packaged power semiconductor device according to an embodiment of the present invention includes a plurality of power semiconductor dies 110, it will be recognized that the semiconductor dies 110 may be the same or different, and may be electrically connected to each other and to the package leads 134, 136 in various ways. Thus, exemplary embodiments may include a plurality of power MOSFETs connected in series or in parallel, a plurality of power Schottky diodes connected in series or in parallel, or one or more power MOSFETs and one or more power Schottky diodes connected in series or in parallel.

[0100] Figure 8 is a flowchart of a method for fabricating a packaged power semiconductor device according to an embodiment of the present invention. As shown in Figure 8, the process begins with a semiconductor die having a first terminal and a second terminal being placed on a submount (block 800). A first lead is electrically connected to the first terminal, and a second lead is electrically connected to the second terminal (block 810). A plastic outer covering is formed to enclose at least a portion of the semiconductor die and submount (block 820). Thus, blocks 800-820 show that the semiconductor die is packaged in a package including the submount, leads, and housing (in this case, the plastic outer covering) to provide a spare power semiconductor device. A moisture barrier is formed on the spare power semiconductor device to provide a power semiconductor device configured for installation on a printed circuit board such as a customer motherboard (block 830).

[0101] In some cases, a moisture barrier is formed on the customer motherboard to protect it from ambient conditions. This may help protect components on the motherboard (including any packaged power semiconductor devices mounted on the motherboard) from subsequent moisture ingress, but it does not provide protection from moisture damage that may occur during the solder reflow process used to mount packaged electronic devices onto the motherboard. Furthermore, in many cases, it may be desirable to perform a slow baking operation on the electronic devices to remove moisture from the devices prior to applying any moisture protection. In some cases, it may be impossible to perform such a slow baking operation on the printed circuit board because the printed circuit board may contain components that cannot undergo such a slow baking process.

[0102] While embodiments of the present invention have been discussed above in relation to packaged power semiconductor devices including power semiconductor dies, it will be recognized that embodiments of the present invention are not limited thereto. For example, all embodiments disclosed herein may include one or more radio frequency ("RF") semiconductor dies instead of power semiconductor dies. For example, a semiconductor die included in a packaged power semiconductor device may comprise a high-power, high-electron-mobility transistor ("HEMT") designed to amplify RF signals.

[0103] Packaged power semiconductor devices according to embodiments of the present invention may be designed to interrupt voltages of 500 volts or more and may be rated for currents of at least 25 amp. In some embodiments, packaged power semiconductor devices may be designed to interrupt voltages of at least 750 volts, 1000 volts, or 1500 volts and / or may be rated for currents of at least 50 amp, at least 75 amp, or at least 100 amp. In some embodiments, packaged power semiconductor devices according to embodiments of the present invention may be designed to interrupt voltages between 650 volts and 1700 volts and may be rated for currents between 25 amp and 100 amb.

[0104] Embodiments of the present invention have been described above with reference to the accompanying drawings illustrating embodiments of the present invention. However, it will be recognized that the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments described above. Rather, these embodiments are provided so that the present disclosure may be thorough and complete and to fully convey the scope of the invention to those skilled in the art. Throughout, similar numbers refer to similar elements.

[0105] Terms such as "first," "second," etc., are used throughout this specification to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used simply to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be called a second element, and similarly, a second element may be called a first element. The term "and / or" includes any combination of one or more of the relevant listed articles.

[0106] The technical terms used herein are solely for the purpose of describing specific embodiments and are not intended to limit the invention. In this specification, the singular forms “a,” “an,” and “the” are intended to include the plural form unless the context clearly indicates otherwise. It will be further understood that, when used herein, the terms “equipped,” “equipped,” “contain,” and / or “contain,” specify the presence of the described feature, complete, step, process, element, and / or component, but do not exclude the presence or addition of one or more other features, complete, step, process, element, component, and / or group thereof.

[0107] When an element such as a layer, region, or substrate is considered to be located "on top of" another element or to extend "on top of" another element, it will be understood that such an element may be located directly on top of or to extend directly onto another element, or there may be intervening elements. In contrast, when an element is considered to be located "directly on top of" another element or to extend "directly onto" another element, there are no intervening elements. When an element is considered to be "attached," "connected," or "linked" to another element, it will also be understood that the element may be directly attached, directly connected, or to the other element, or there may be intervening elements. In contrast, when an element is considered to be "directly attached," "directly connected," or "directly linked" to another element, there are no intervening elements.

[0108] In this specification, relative terms such as “below” or “above” or “top” or “bottom” or “summit” may be used to describe the relationship between one element, layer, or region and another, as shown in the figure. It will be understood that these terms are intended to encompass various orientations of the device, in addition to the orientation shown in the figure.

[0109] In this specification, the term "multiple" means "two or more."

[0110] Embodiments of the present invention are described herein with reference to schematic cross-sectional views of ideal embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Furthermore, variations from the figures are expected, for example, as a result of manufacturing techniques and / or tolerances.

[0111] Typical embodiments of the present invention are disclosed in the drawings and this specification, and certain terms are used, but these are used merely in a general and descriptive sense and not for the purpose of limitation, and the scope of the present invention is set out in the following claims.

Claims

1. A package comprising an outer covering encapsulant, A power semiconductor die within the package, comprising a power semiconductor die having a first terminal, A first lead electrically connected to the first terminal, the first lead extending through the first side of the outer covering and encapsulation body such that the first lead has an external section located outside the outer covering and encapsulation body, The moisture barrier on the outer surface of the outer covering and sealing body A power semiconductor device comprising, The moisture barrier comprises a first section extending along the first side of the outer covering encapsulant and a second section extending along the outer section of the first lead. A power semiconductor device in which the second section extends outward from the first section at an oblique angle and extends only along a portion of the length of the outer section of the first lead, such that the moisture barrier does not extend to the end of the outer section of the first lead.

2. The power semiconductor device according to claim 1, wherein the moisture barrier is formed on a portion, but not the entire, bottom of the outer surface of the outer covering encapsulant.

3. The semiconductor die has a second terminal, and the package is A second lead electrically connected to the second terminal, the second lead extending outward from the second side of the outer covering encapsulant. Furthermore, The power semiconductor device according to claim 1, wherein the moisture barrier has a third section extending along the second lead wire, and the third section extends from the first section at a second oblique angle.

4. The power semiconductor device according to claim 3, wherein the first lead includes a wide segment extending through the first side of the outer covering encapsulant and a narrow segment extending outward from the wide segment, and the moisture barrier covers at least a portion of the wide segment.

5. The power semiconductor device according to claim 3, wherein the package further comprises a submount, the semiconductor die is mounted on the upper surface of the submount, the submount comprises a lead frame or power substrate, and the outer covering encapsulant and the submount together encapsulate the semiconductor die.

6. The power semiconductor device according to claim 5, wherein the semiconductor die further includes a third terminal located on the opposite side of the semiconductor layer structure of the semiconductor die from the first and second terminals, and the third terminal is electrically connected to the submount.

7. The power semiconductor device according to claim 1, wherein the moisture barrier comprises at least one of parylene, silicone, polyurethane, or acrylic material.

8. The power semiconductor device according to claim 1, wherein the power semiconductor device is combined with a printed circuit board and mounted on the printed circuit board, a portion of the moisture barrier is located between the package and the printed circuit board, the power semiconductor device is mounted on a metal pad on the printed circuit board, and the moisture barrier electrically insulates the semiconductor die from the metal pad.

9. The power semiconductor device according to claim 3, wherein the moisture barrier is a first moisture barrier, and the power semiconductor device further comprises a second moisture barrier covering the upper and side surfaces of the semiconductor die.

10. The power semiconductor device according to claim 9, wherein the second moisture barrier further covers portions of the first and second leads.

11. The power semiconductor device according to claim 3, wherein the moisture barrier covers not all but part of the portions of the first and second leads located outside the outer covering encapsulant.

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