Semiconductor substrate, semiconductor stacked structure, semiconductor device, method for manufacturing a semiconductor substrate, method for manufacturing a semiconductor stacked structure, and method for manufacturing a semiconductor device

Abstract

The present invention relates to a substrate (1) which is for forming a semiconductor device, and has: a diamond substrate (10); and a silicon carbide layer (20) disposed on a portion or the entirety of one surface (10a) of the diamond substrate (10), wherein the thickness of the silicon carbide layer (20) is at most 20 nm, and an arithmetic mean roughness Ra of a surface (20a) of the silicon carbide layer (20) is at most 0.5 nm.

Description

[Technical Field]

[0001] The present invention relates to a substrate for forming a semiconductor device, a semiconductor stacked structure, a semiconductor device, a method for manufacturing a substrate for forming a semiconductor device, a method for manufacturing a semiconductor stacked structure, and a method for manufacturing a semiconductor device. This application claims priority based on Japanese Patent Application No. 2022-144364, filed in Japan on September 12, 2022, and the contents of that application are incorporated herein by reference. [Background technology]

[0002] In recent years, with the increasing power output, speed, and integration of semiconductor devices (semiconductor equipment), there has been a demand for semiconductor equipment substrates with high thermal conductivity. Diamond substrates with high thermal conductivity of 500 W / mK or more are attracting attention as such semiconductor equipment substrates. Generally, diamond substrates have a rough surface, which presents a problem in that they are difficult to bond with semiconductor layers.

[0003] To address these problems, for example, Non-Patent Document 1 proposes a semiconductor multilayer structure in which thin silicon films are deposited on the surface of a diamond substrate and the surface of gallium nitride, respectively, and the silicon films are joined together to bond the diamond substrate and the gallium nitride.

[0004] For example, Non-Patent Document 2 proposes a semiconductor laminated structure in which a gallium nitride element is fabricated on a silicon carbide substrate, the silicon carbide substrate is ground down to a thickness of 50 μm, and this silicon carbide substrate and a diamond substrate are bonded together via a thin titanium film.

[0005] For example, Patent Document 1 proposes a semiconductor device in which a silicon carbide substrate implanted with hydrogen ions is bonded to a diamond substrate, the silicon carbide substrate is smart-cut by heat treatment, and gallium nitride crystals are grown on the thinned silicon carbide substrate. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] Z. Cheng, et al., “Interfacial Thermal Conductance across Room-Temperature Bonded GaN-Diamond Interfaces for GaN-on-Diamond Devices,” ACS Appl. Mater. Interfaces 12, pp. 8376-8384 (2020). [Non-Patent Document 2] Yuichi Minoura, et al., “Surface activated bonding of SiC / diamond for thermal management of high-output power GaN HEMTs,” Jpn. J. Appl. Phys. 59, SGGD03 (2020). [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2016-139655 [Overview of the project] [Problems that the invention aims to solve]

[0008] However, the semiconductor multilayer structure described in Non-Patent Document 1 has a problem in that when heat treatment is performed at high temperatures of 800°C or higher, a reaction called meltback occurs at the interface between gallium nitride and silicon, forming voids and reducing the reliability when a semiconductor device (semiconductor device) is formed.

[0009] The semiconductor multilayer structure described in Non-Patent Document 2 has a silicon carbide substrate and a diamond substrate joined together via a thin titanium film. However, titanium has a lower thermal conductivity than silicon carbide and therefore has poor heat dissipation, which presents a problem.

[0010] It is unclear whether gallium nitride can be grown on a silicon carbide substrate after smart cut in Patent Document 1. Furthermore, there is a problem that the silicon carbide substrate is thick and has poor heat dissipation.

[0011] Therefore, an object of the present invention is to provide a substrate for forming a semiconductor device, a semiconductor laminated structure, a semiconductor device, and manufacturing methods thereof, which can easily bond a diamond substrate and a semiconductor layer and have excellent heat dissipation and heat resistance.

Means for Solving the Problems

[0012] The present invention has the following aspects. [1] A substrate for forming a semiconductor device, comprising a diamond substrate and a silicon carbide layer located on a part or all of one surface of the diamond substrate, where the thickness of the silicon carbide layer is 20 nm or less, and the arithmetic mean roughness Ra of the surface of the silicon carbide layer is 0.5 nm or less. [2] The substrate for forming a semiconductor device according to [1], wherein a part or all of the silicon carbide contained in the silicon carbide layer is amorphous.

[0013] 》[3] A semiconductor laminated structure, comprising a diamond substrate, a semiconductor layer located on a part or all of one surface of the diamond substrate, and a silicon carbide layer located between the diamond substrate and the semiconductor layer, where the semiconductor layer contains a nitride or an oxide, the silicon carbide layer is a single layer, and the thickness of the silicon carbide layer is 20 nm or less. [4] The semiconductor laminated structure according to [3], wherein the arithmetic mean roughness Ra of the surface of the silicon carbide layer at the interface between the silicon carbide layer and the semiconductor layer is 0.5 nm or less. [5] The semiconductor laminated structure according to [3] or [4], wherein a part or all of the silicon carbide contained in the silicon carbide layer is amorphous.

[0014] A semiconductor device including the semiconductor laminated structure according to any one of [6] to [5], wherein part or all of the silicon carbide contained in the silicon carbide layer is polycrystalline.

[0015] [7] A method for manufacturing a substrate for forming a semiconductor device, comprising a deposition step of depositing silicon carbide on part or all of one surface of a diamond substrate to form a silicon carbide layer having a thickness of 20 nm or less and an arithmetic mean roughness Ra of the surface of 0.5 nm or less. [8] A step of manufacturing a substrate for forming a semiconductor device by the method for manufacturing a substrate for forming a semiconductor device according to [7], Next, a bonding step of bonding the surface of the silicon carbide layer and a semiconductor layer containing a nitride or an oxide, which is a method for manufacturing a semiconductor laminated structure. [9] A step of manufacturing a semiconductor laminated structure by the method for manufacturing a semiconductor laminated structure according to [8], A heat treatment step of subjecting the semiconductor laminated structure to a heat treatment at 800 °C or higher, which is a method for manufacturing a semiconductor device. [Effect of the Invention]

[0016] According to the substrate for forming a semiconductor device, the semiconductor laminated structure, the semiconductor device, and the manufacturing methods thereof of the present invention, a diamond substrate and a semiconductor layer can be easily bonded, and the heat dissipation property and heat resistance are excellent. [Brief Description of the Drawings]

[0017] [Figure 1] It is a cross-sectional view of a substrate for forming a semiconductor device according to an embodiment of the present invention. [Figure 2] It is a cross-sectional view of a semiconductor laminated structure according to an embodiment of the present invention. [Figure 3] It is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. [Figure 4] It is a flowchart showing a part of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 5] It is a flowchart showing a part of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6]This is a flowchart showing a part of the manufacturing method for a semiconductor device according to one embodiment of the present invention. [Figure 7] This is a transmission electron microscope (TEM) image of a cross-section of a semiconductor multilayer structure according to one embodiment of the present invention before heat treatment. [Figure 8] This is a TEM image of a cross-section of a semiconductor stacked structure after heat treatment, according to one embodiment of the present invention. [Modes for carrying out the invention]

[0018] [Substrate for forming semiconductor devices] The semiconductor device substrate of the present invention comprises a diamond substrate and a silicon carbide layer located on part or all of one surface of the diamond substrate.

[0019] Hereinafter, a semiconductor device substrate according to one embodiment of the present invention will be described with reference to the drawings. As shown in Figure 1, the semiconductor device substrate 1 comprises a diamond substrate 10 and a silicon carbide layer 20 located on one surface 10a of the diamond substrate 10. The thickness T1 of the semiconductor device substrate 1 is preferably 1 to 500 μm, more preferably 10 to 400 μm, and even more preferably 50 to 300 μm. If the thickness T1 is above the lower limit, the physical strength of the semiconductor device can be increased. If the thickness T1 is below the upper limit, the size of the semiconductor device can be made more compact. The thickness T1 can be measured, for example, with a digital caliper. In this specification, "thickness T1" is the arithmetic mean of 10 randomly selected thicknesses.

[0020] Thickness T of the diamond substrate 10 10 For example, the thickness T is preferably 10 to 500 μm, more preferably 30 to 400 μm, and even more preferably 50 to 300 μm. 10 If the thickness T is greater than or equal to the lower limit mentioned above, the physical strength of the semiconductor device can be further increased. 10 If the above upper limit is below this value, the size of the semiconductor device can be made more compact. Thickness T 10 can be measured, for example, with a digital caliper or the like. In this specification, "thickness T" 10 10 shall be the arithmetic mean value of the thicknesses at 10 randomly selected locations.

[0021] The diamond substrate 10 has a high thermal conductivity, and a semiconductor device including the diamond substrate 10 can have improved heat dissipation performance. The thermal conductivity of the diamond substrate 10 is preferably, for example, 500 W / m·K or more, more preferably 700 W / m·K or more, and even more preferably 1000 W / m·K or more. When the thermal conductivity of the diamond substrate 10 is at least the above lower limit value, the heat dissipation performance of the semiconductor device can be further improved. The upper limit value of the thermal conductivity of the diamond substrate 10 is not particularly limited, and is, for example, 3000 W / m·K. The thermal conductivity of the diamond substrate 10 is preferably 500 to 3000 W / m·K, more preferably 700 to 3000 W / m·K, and even more preferably 1000 to 3000 W / m·K. The thermal conductivity of the diamond substrate 10 can be measured, for example, by the temperature gradient method, the disk calorimeter method, or the like. The thermal conductivity of the diamond substrate 10 can be adjusted by the purity, crystallinity, crystal type, density of the diamond constituting the diamond substrate 10, and combinations thereof, etc.

[0022] The thickness T of the silicon carbide layer 20 20 20 is 20 nm or less, preferably 1 nm or more and 18 nm or less, more preferably 2 nm or more and 16 nm or less, and even more preferably 5 nm or more and 15 nm or less. When the thickness T 20 20 is at least the above lower limit value, the arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 can be further reduced. When the thickness T 20 20 is at most the above upper limit value, the heat dissipation performance of the semiconductor device can be further improved. The thickness T 20 20 can be determined, for example, by observing a cross section in the thickness direction of the substrate 1 for forming a semiconductor device with an electron microscope or the like. As the electron microscope, for example, a transmission electron microscope (TEM) can be used.<000​​​" is the arithmetic mean of the thicknesses of 10 randomly selected locations.

[0023] The silicon carbide layer 20 has a higher thermal conductivity than a layer of pure silicon. Therefore, a semiconductor device equipped with a silicon carbide layer 20 can achieve better heat dissipation than a semiconductor device equipped with a layer of pure silicon of the same thickness. The thermal conductivity of the silicon carbide layer 20 is preferably 100 W / m·K or higher, more preferably 150 W / m·K or higher, and even more preferably 200 W / m·K or higher. If the thermal conductivity of the silicon carbide layer 20 is above the lower limit, the heat dissipation of the semiconductor device can be further improved. The upper limit of the thermal conductivity of the silicon carbide layer 20 is not particularly limited, but for example, it is set to 450 W / m·K. The thermal conductivity of the silicon carbide layer 20 is preferably 100 to 450 W / m·K, more preferably 150 to 450 W / m·K, and even more preferably 200 to 450 W / m·K. The thermal conductivity of the silicon carbide layer 20 can be measured, for example, by the temperature gradient method, the disk heat flow meter method, or the like. The thermal conductivity of the silicon carbide layer 20 can be adjusted by the purity, crystallinity, crystal type, density, and combinations thereof of the silicon carbide constituting the silicon carbide layer 20.

[0024] The arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 is 0.5 nm or less, preferably 0.45 nm or less, and more preferably 0.4 nm or less. When the arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 is below the above upper limit, the bonding with the semiconductor layer in the semiconductor stacked structure described later can be further improved. Therefore, the heat dissipation and heat resistance of the semiconductor device can be further improved. The lower limit of the arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 is not particularly limited, and is, for example, 0.01 nm. The arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 is preferably 0.01 to 0.5 nm, more preferably 0.01 to 0.45 nm, and even more preferably 0.01 to 0.4 nm. The arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 can be determined, for example, by analysis using an atomic force microscope (AFM). The measurement conditions for the atomic force microscope (AFM) can be those described in the examples below.

[0025] Preferably, some or all of the silicon carbide contained in the silicon carbide layer 20 is amorphous. When the silicon carbide is amorphous, the arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 can be further reduced. Whether or not silicon carbide is amorphous can be determined by observing a cross-section of the semiconductor device substrate 1 in the thickness direction using an electron microscope. For example, if no striped structure is observed in the silicon carbide layer 20 of the semiconductor device substrate 1, and the silicon carbide does not fall under any of cubic, hexagonal, or rhombohedral crystal structures, it can be determined that "at least a portion of the silicon carbide contained in the silicon carbide layer 20 is amorphous." For example, a transmission electron microscope (TEM) can be used as the electron microscope.

[0026] [Semiconductor stacked structure] The semiconductor laminated structure of the present invention comprises a diamond substrate, a semiconductor layer located on part or all of one surface of the diamond substrate, and a silicon carbide layer located between the diamond substrate and the semiconductor layer. The semiconductor layer contains nitride or oxide, the silicon carbide layer is a single layer, and the thickness of the silicon carbide layer is 20 nm or less.

[0027] A semiconductor stacked structure according to one embodiment of the present invention will be described below with reference to the drawings. As shown in Figure 2, the semiconductor multilayer structure 2 comprises a diamond substrate 10, a silicon carbide layer 20 located on one surface 10a of the diamond substrate 10, and a semiconductor layer 30 located on the surface 20a of the silicon carbide layer 20. In other words, the semiconductor multilayer structure 2 comprises a diamond substrate 10, a semiconductor layer 30 located on one surface 10a of the diamond substrate 10, and a silicon carbide layer 20 located between the diamond substrate 10 and the semiconductor layer 30. In the following, components identical to those in Figure 1 will be denoted by the same reference numerals, and their explanations will be omitted.

[0028] The thickness T2 of the semiconductor stacked structure 2 is preferably, for example, 2 to 1000 μm, more preferably 5 to 700 μm, and even more preferably 10 to 500 μm. If the thickness T2 is above the lower limit, the physical strength of the semiconductor device can be increased. If the thickness T2 is below the upper limit, the size of the semiconductor device can be made more compact. The thickness T2 can be measured, for example, with a digital caliper. In this specification, "thickness T2" is the arithmetic mean of 10 randomly selected thicknesses.

[0029] The arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 at the interface between the silicon carbide layer 20 and the semiconductor layer 30 is preferably 0.5 nm or less, more preferably 0.45 nm or less, and even more preferably 0.4 nm or less. When the arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 is below the above upper limit, the bonding with the semiconductor layer 30 can be further improved. This allows for improved heat dissipation and heat resistance in the semiconductor device. The lower limit of the arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 is not particularly limited and can be, for example, 0.01 nm. The arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 is preferably 0.01 to 0.5 nm, more preferably 0.01 to 0.45 nm, and even more preferably 0.01 to 0.4 nm. The arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 can be determined, for example, by removing the semiconductor layer 30 and then analyzing it using an atomic force microscope (AFM). The measurement conditions for the atomic force microscope (AFM) can be those described in the examples below.

[0030] The silicon carbide layer 20 is a single layer. Here, "single layer" means a single layer formed in one process, without any bonding interfaces inside, and may contain amorphous silicon carbide and be formed in layers or streaks. Whether the silicon carbide layer 20 is a single layer can be determined, for example, by observing a cross-section of the semiconductor stacked structure 2 in the thickness direction using a transmission electron microscope (TEM), and by elemental distribution analysis using energy-dispersive X-ray spectroscopy (EDX) associated with the TEM. If the silicon carbide layer 20 is not a single layer, that is, a boundary line (bonding interface) parallel to the interface between the silicon carbide layer 20 and the semiconductor layer 30 can be confirmed within the silicon carbide layer-silicon carbide layer, and elements originating from the bonding (e.g., iron) can be detected at that location. By making the silicon carbide layer 20 a single layer, a semiconductor laminated structure 2 is realized with fewer bonding interfaces compared to the case where silicon carbide layers are formed on both the bonding surface of the diamond substrate 10 and the bonding surface of the semiconductor layer 30, and these silicon carbide layers are bonded to each other. As a result, thermal resistance caused by bonding interfaces can be reduced, and heat dissipation and heat resistance can be further improved.

[0031] The semiconductor layer 30 contains a nitride or oxide. Examples of nitrides include gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN), and mixed crystals thereof. The semiconductor layer 30 may also have a multilayer structure made of these nitrides. Examples of oxides include gallium oxide (Ga2O3), aluminum oxide (Al2O3), and mixed crystals thereof. The semiconductor layer 30 may also have a multilayer structure made of these oxides.

[0032] Thickness T of semiconductor layer 30 30 For example, the thickness T is preferably 0.1 to 50 μm, more preferably 0.2 to 20 μm, and even more preferably 0.5 to 10 μm. 30 If the value is above the lower limit mentioned above, the output of the semiconductor device can be increased. Thickness T 30 If the value is below the above upper limit, the temperature rise of the semiconductor device due to the thermal resistivity of the nitride or oxide contained in the semiconductor layer 30 is suppressed, and the bonding with the diamond substrate 10 is further improved. As a result, the heat dissipation and heat resistance of the semiconductor device can be further improved. Thickness T 30This can be determined, for example, by observing a cross-section of the semiconductor stacked structure 2 in the thickness direction using an electron microscope. For example, a transmission electron microscope (TEM) can be used as the electron microscope. In this specification, "thickness T 30 " is the arithmetic mean of the thicknesses of 10 randomly selected locations.

[0033] [Semiconductor device] The semiconductor device of the present invention includes the semiconductor stacked structure of the present invention, wherein some or all of the silicon carbide contained in the silicon carbide layer is polycrystalline.

[0034] A semiconductor device according to one embodiment of the present invention will be described below with reference to the drawings. As shown in Figure 3, the semiconductor device 3 comprises a diamond substrate 10, a semiconductor layer 30 located on a part of one surface 10a of the diamond substrate 10, and a silicon carbide layer 20 located between the diamond substrate 10 and the semiconductor layer 30. In the semiconductor device 3, a portion of the semiconductor layer 30 and silicon carbide layer 20 of the semiconductor stacked structure 2 has been removed. Of the silicon carbide layer 20 and semiconductor layer 30 remaining on the diamond substrate 10, a gate electrode 41, a source electrode 42, and a drain electrode 43 are formed on the surface of the semiconductor layer 30. In the following, components identical to those in Figure 2 will be denoted by the same reference numerals, and their explanations will be omitted.

[0035] Any known material can be used to constitute the gate electrode 41. Examples of materials for the gate electrode 41 include nickel, gold, and palladium. Any known material can be used to constitute the source electrode 42. Examples of materials for the source electrode 42 include titanium, aluminum, nickel, gold, and multilayer structures thereof. Any known material can be used to constitute the drain electrode 43. Examples of materials for the drain electrode 43 include titanium, aluminum, nickel, gold, and multilayer structures thereof.

[0036] The thickness of the gate electrode 41 is preferably, for example, 0.1 to 20 μm, more preferably 0.5 to 15 μm, and even more preferably 1 to 10 μm. If the thickness of the gate electrode 41 is above the lower limit, the output of the semiconductor device 3 can be increased. If the thickness of the gate electrode 41 is below the upper limit, miniaturization of the gate electrode 41 becomes possible, and the operating frequency of the semiconductor device 3 is improved. In addition, if the thickness of the gate electrode 41 is below the upper limit, the production efficiency of the semiconductor device 3 can be increased. The thickness of the source electrode 42 is the same as the thickness of the gate electrode 41. The thickness of the drain electrode 43 is the same as the thickness of the gate electrode 41. The electrode thickness can be measured using, for example, a digital caliper. The electrode thickness is the arithmetic mean of the thicknesses of 10 randomly selected locations.

[0037] The shapes of the gate electrode 41, source electrode 42, and drain electrode 43 patterns are not particularly limited and can be determined as appropriate depending on the application of the semiconductor device 3.

[0038] In the semiconductor stacked structure 2, the shape of the patterns of the semiconductor layer 30 and silicon carbide layer 20 to be removed is not particularly limited and can be appropriately determined according to the application of the semiconductor device 3.

[0039] In the semiconductor device 3, some or all of the silicon carbide contained in the silicon carbide layer 20 is polycrystalline. If the silicon carbide is polycrystalline, the bonding strength between the silicon carbide layer 20 and the semiconductor layer 30 can be further increased. Therefore, the heat dissipation and heat resistance of the semiconductor device 3 can be further improved. Whether or not silicon carbide is polycrystalline can be determined by observing a cross-section of the semiconductor device 3 in the thickness direction using an electron microscope. For example, if a striped structure is observed in a part of the silicon carbide layer, it means that the atoms in that part are arranged periodically, i.e., that it is crystallized. Thus, if a striped structure is observed in at least a part of the silicon carbide layer, it is determined that "at least a part of the silicon carbide contained in the silicon carbide layer 20 is polycrystalline." For example, a transmission electron microscope (TEM) can be used as the electron microscope.

[0040] [Method for manufacturing substrates for semiconductor device formation] The present invention relates to a method for manufacturing a semiconductor device substrate, which includes a deposition step of depositing silicon carbide on part or all of one surface of a diamond substrate to form a silicon carbide layer with a thickness of 20 nm or less and an arithmetic mean surface roughness Ra of 0.5 nm or less.

[0041] The deposition process involves depositing silicon carbide onto part or all of one side of a diamond substrate to form a silicon carbide layer with a thickness of 20 nm or less and an arithmetic mean surface roughness Ra of 0.5 nm or less. Methods for depositing silicon carbide include, for example, sputtering, vacuum deposition, chemical deposition, and physical deposition. As a method for depositing silicon carbide, sputtering is preferred because it allows for a uniform and thinner silicon carbide layer.

[0042] Examples of sputtering methods include the two-electrode method, magnetron method, reactive sputtering, ion beam sputtering, and electron cyclotron resonance (ECR) sputtering. Among sputtering methods, the magnetron method is preferred because it can stably deposit silicon carbide and easily achieve a surface arithmetic mean roughness Ra of 0.5 nm or less.

[0043] [Method for manufacturing a multilayer structure] The present invention provides a method for manufacturing a semiconductor laminate structure, comprising the steps of: manufacturing a semiconductor device substrate using the present invention's semiconductor device substrate manufacturing method; and subsequently, a bonding step of bonding the surface of a silicon carbide layer to a semiconductor layer containing a nitride or oxide. The process for manufacturing a substrate for forming a semiconductor device is the same as the method for manufacturing a substrate for forming a semiconductor device described above.

[0044] The bonding process is a step that follows the process of manufacturing a substrate for semiconductor device formation, in which the surface of the silicon carbide layer is bonded to a semiconductor layer containing nitride or oxide. Methods for joining a silicon carbide layer and a semiconductor layer include, for example, surface activated bonding (SAB), high-pressure bonding, and high-vacuum bonding. The SAB method involves cleaning the surfaces to be joined with a chemical solution and pure water, activating them with plasma or ions in a vacuum chamber, and then joining them in a low-temperature atmosphere ranging from room temperature (e.g., 25°C) to 400°C. The high-pressure joining method involves cleaning the surfaces to be joined with a chemical solution and pure water, then heating them in the air and applying a high pressure of 0.1 MPa to 10 MPa to join them. The high vacuum bonding method involves cleaning the surfaces to be bonded with a chemical solution and pure water, and then 10 -6 Pa to 10 -3 This method involves joining under a high vacuum atmosphere of approximately Pa. As a method for joining the silicon carbide layer and the semiconductor layer, surface activation bonding is preferred because it can be performed at room temperature (e.g., 5-30°C) and is easier to perform.

[0045] The temperature during the bonding process (bonding temperature) is preferably 0 to 400°C, more preferably 0 to 100°C, and even more preferably 5 to 30°C (room temperature), from the viewpoint of suppressing degradation of the silicon carbide layer and the semiconductor layer.

[0046] [Manufacturing method for semiconductor devices] The present invention provides a method for manufacturing a semiconductor device, comprising the steps of: manufacturing a semiconductor stacked structure using the semiconductor stacked structure manufacturing method of the present invention; and a heat treatment step of subjecting the semiconductor stacked structure to a heat treatment at 800°C or higher.

[0047] The method for manufacturing the semiconductor device of this embodiment will be described below with reference to the drawings. As shown in Figures 4 to 6, the semiconductor device manufacturing method of this embodiment comprises steps A-1, A-2, A-3, B-1, B-2, B-3, and B-4.

[0048] As shown in Figure 4, step A-1 is a step in which a nitride or oxide is grown on a crystal growth substrate to obtain a semiconductor layer and a first laminate. Examples of substrates for crystal growth include silicon substrates, silicon carbide substrates, and sapphire substrates, with silicon substrates being preferred from a cost perspective. Examples of crystal growth methods include metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), sublimation, and flux methods. From the viewpoint of crystal quality, MOCVD is preferred as the crystal growth method.

[0049] Step A-2 is a process of bonding the surface of the semiconductor layer of the first laminate to the support substrate to obtain the second laminate. The support substrate is not particularly limited as long as it is suitable for supporting the semiconductor layer until the crystal growth substrate is removed from the semiconductor layer in a subsequent process and the silicon carbide layer is bonded to the semiconductor layer. Examples of support substrates include silicon substrates, silicon carbide substrates, molybdenum substrates, and glass substrates. The method for joining the semiconductor layer and the support substrate is not particularly limited, but from the viewpoint of easy attachment and detachment and sufficient support for the semiconductor layer, wax bonding, brazing material, solder, etc., are preferred.

[0050] Step A-3 is a process in which the crystal growth substrate is removed from the second laminate obtained in step A-2, the back surface of the semiconductor layer is polished, and a third laminate is obtained. The method for removing the crystal growth substrate is not particularly limited and includes methods such as cutting, grinding, polishing, and etching. Methods for polishing the back surface of a semiconductor layer include, for example, chemical mechanical polishing (CMP).

[0051] As shown in Figure 5, step B-1 is a step in which silicon carbide is deposited on a diamond substrate to form a silicon carbide layer and obtain a fourth laminate (substrate for semiconductor device formation). Methods for depositing silicon carbide on a diamond substrate include, for example, sputtering, vacuum deposition, chemical deposition, and physical deposition. Sputtering is preferred as a method for depositing silicon carbide because it allows for a uniform and thinner silicon carbide layer.

[0052] Step B-2 is a process in which the semiconductor layer of the third laminate obtained in step A-3 and the silicon carbide layer of the fourth laminate obtained in step B-1 are joined together to obtain a fifth laminate. Methods for joining the semiconductor layer of the third laminate to the silicon carbide layer of the fourth laminate include, for example, the SAB method, high-pressure bonding method, and high-vacuum bonding method. The SAB method is preferred because it can be used at room temperature and is easier to use.

[0053] As shown in Figure 6, step B-3 is the process of removing the support substrate from the fifth laminate obtained in step B-2 to obtain the sixth laminate (semiconductor laminate structure). Methods for removing the support substrate from the fifth laminate include, for example, detachment, separation, grinding, polishing, and etching.

[0054] Step B-4 is a process in which the sixth laminate is subjected to a process including mesa formation and heat treatment to impart a device structure to the semiconductor layer. Here, the device structure refers to a structure having a buffer layer, a channel layer, a barrier layer, and a contact layer from the side closest to the silicon carbide layer. The heating temperature during the heat treatment is preferably 800°C or higher, more preferably 850°C or higher, and even more preferably 900°C or higher. If the heating temperature is above the lower limit, the semiconductor layer can be sufficiently given a device structure. The upper limit of the heating temperature is not particularly limited, but from the viewpoint of suppressing degradation of the semiconductor layer, it is, for example, 1200°C. The heating temperature during the heat treatment is preferably 800 to 1200°C, more preferably 850 to 1200°C, and even more preferably 900 to 1200°C.

[0055] By applying heat treatment to the sixth laminate, the polycrystalline structure of silicon carbide in the silicon carbide layer of the sixth laminate is promoted. When silicon carbide is polycrystalline, the bonding strength between the silicon carbide layer and the semiconductor layer can be further increased. As a result, the heat dissipation and heat resistance of the semiconductor device can be further improved.

[0056] After heat treatment is applied to the sixth laminate, lithography is performed on this laminate to process the silicon carbide layer and semiconductor layer on the diamond substrate into the desired shape, and then gate electrodes, source electrodes and drain electrodes are laminated to obtain a semiconductor device (semiconductor device). For example, known metals such as nickel, gold, titanium, aluminum, palladium, and multilayer structures thereof can be used as materials for the gate electrode, source electrode, and drain electrode. The gate electrode, source electrode, and drain electrode are obtained by forming a metal multilayer film by vacuum deposition or the like. When forming the source electrode and drain electrode, a heat treatment is performed after the formation of the metal multilayer film to react with nitrides or oxides contained in the semiconductor layer. The heating temperature for this is preferably 650°C or higher, more preferably 700°C or higher, and even more preferably 800°C or higher.

[0057] Through the above process, a semiconductor device (semiconductor device) is obtained in which a silicon carbide layer located on the surface of a diamond substrate is bonded to a semiconductor layer, and a gate electrode, source electrode, and drain electrode are formed on the surface of the semiconductor layer. [Examples]

[0058] The present invention will be described in more detail below using examples, but the present invention is not limited to these examples.

[0059] A rectangular diamond substrate with a length of 4 mm, a width of 4 mm, and a thickness of 350 μm was prepared. One side of this diamond substrate was analyzed using an atomic force microscope (AFM), and the arithmetic mean roughness Ra was found to be 0.77 nm. Silicon carbide was deposited on one side of this diamond substrate by sputtering to form a silicon carbide layer with a thickness of 13 nm, and the fourth laminate was obtained (Step B-1). The surface of the silicon carbide layer of the fourth laminate was analyzed using AFM, and the arithmetic mean roughness Ra was found to be 0.37 nm. The measurement conditions for the arithmetic mean roughness Ra are shown below. • Measuring device: SPM-9600 (manufactured by Shimadzu Corporation) • Measurement probe: NCHR (manufactured by NanoWorld) • Measurement range: 1 μm 2 Next, a silicon substrate with a diameter of 4 inches (101.6 mm) and a thickness of 500 μm was prepared as a crystal growth substrate. Gallium nitride was grown on one side of this silicon substrate by MOCVD to form a semiconductor layer with a thickness of 1 μm, obtaining the first laminate (Step A-1). Next, the semiconductor layer of the first laminate was cut into a rectangle with a length of 10 mm and a width of 12 mm. A rectangular silicon substrate with a length of 20 mm, a width of 20 mm, and a thickness of 500 μm was bonded to the support substrate with wax to obtain the second laminate (Step A-2). Next, the crystal growth substrate of the second laminate was removed by etching with a hydrofluoric acid-nitric acid mixture, and the back surface of the semiconductor layer was polished by CMP to obtain the third laminate (Step A-3).

[0060] Next, the semiconductor layer of the third laminate and the silicon carbide layer of the fourth laminate were joined by the SAB method to obtain the fifth laminate (Step B-2). The support substrate of the obtained fifth laminate was removed by etching with a hydrofluoric acid-nitric acid mixture to obtain the sixth laminate (semiconductor laminate structure) (Step B-3). The cross-section of the sixth laminate obtained in the thickness direction was observed using TEM. The results are shown in Figure 7. As shown in Figure 7, it was confirmed that a 13 nm thick silicon carbide (SiC thin layer) was formed between the diamond substrate and the semiconductor layer (gallium nitride, GaN). No striped structure was observed in the silicon carbide thin layer, confirming that at least a portion of the silicon carbide contained in the silicon carbide layer was amorphous.

[0061] Next, the sixth laminate was heat-treated at 1000°C for 3 minutes (Step B-4). The cross-section of the semiconductor laminate structure in the thickness direction after heat treatment was observed by TEM. The results are shown in Figure 8. As shown in Figure 8, a striped structure was observed in an image of a portion of the silicon carbide layer (SiC thin layer) magnified 1.5 times, confirming that some of the silicon carbide contained in the silicon carbide layer is polycrystalline. Furthermore, as shown in Figure 8, no meltback occurred at the interface between the silicon carbide layer and the semiconductor layer, confirming that the semiconductor multilayer structure possesses sufficient heat resistance. [Explanation of symbols]

[0062] 1. Substrate for forming semiconductor devices 2. Semiconductor Stacked Structures 3 Semiconductor devices 10 Diamond substrate 10a One side of the diamond substrate 20 Silicon Carbide Layer 20a Surface of the silicon carbide layer 30 Semiconductor Layers 41 Guard gate 42 Source electrodes 43 Drain electrode

Claims

1. A substrate for forming a semiconductor device, having a diamond substrate and a silicon carbide layer located on part or all of one surface of the diamond substrate, The thickness of the silicon carbide layer is 20 nm or less. The arithmetic mean roughness Ra of the surface of the silicon carbide layer is 0.5 nm or less. A semiconductor device substrate, wherein some or all of the silicon carbide contained in the silicon carbide layer is amorphous, and this amorphous state is confirmed by observing a cross-section of the semiconductor device substrate in the thickness direction with a transmission electron microscope (TEM), which shows that no striped structure is observed in the silicon carbide layer and that the silicon carbide does not correspond to any of cubic, hexagonal, or rhombohedral crystal structures.

2. Diamond substrate and A semiconductor layer located on part or all of one side of the diamond substrate, A semiconductor laminated structure having a silicon carbide layer located between the diamond substrate and the semiconductor layer, The semiconductor layer contains nitride or oxide, and the silicon carbide layer is a single layer. The thickness of the silicon carbide layer is 20 nm or less. A semiconductor laminated structure in which some or all of the silicon carbide contained in the silicon carbide layer is amorphous, and this amorphous state is confirmed by observing a cross-section of the semiconductor laminated structure in the thickness direction with a transmission electron microscope (TEM), which shows that no striped structure is observed in the silicon carbide layer and that the silicon carbide does not correspond to any of cubic, hexagonal, or rhombohedral crystal structures.

3. The semiconductor laminated structure according to claim 2, wherein the arithmetic mean roughness Ra of the surface of the silicon carbide layer at the interface between the silicon carbide layer and the semiconductor layer is 0.5 nm or less.

4. A method for manufacturing a semiconductor device substrate, comprising a deposition step of depositing silicon carbide on part or all of one surface of a diamond substrate to form a silicon carbide layer with a thickness of 20 nm or less and an arithmetic mean surface roughness Ra of 0.5 nm or less, A method for manufacturing a semiconductor device substrate, wherein some or all of the silicon carbide contained in the silicon carbide layer is amorphous, and the amorphous nature of some or all of the silicon carbide is confirmed by observing a cross-section of the substrate in the thickness direction with a transmission electron microscope (TEM), which shows that no striped structure is observed in the silicon carbide layer and that the silicon carbide does not correspond to any of cubic, hexagonal, or rhombohedral crystal structures.

5. A semiconductor device substrate is manufactured by the method for manufacturing a semiconductor device substrate according to claim 4, Next, a method for manufacturing a semiconductor stacked structure, comprising joining the surface of the silicon carbide layer with a semiconductor layer containing a nitride or oxide.

6. A semiconductor stacked structure is manufactured by the method for manufacturing a semiconductor stacked structure described in claim 5. A method for manufacturing a semiconductor device, comprising subjecting the semiconductor stacked structure to a heat treatment at 800°C or higher.

7. A semiconductor laminated structure comprising a diamond substrate, a semiconductor layer located on part or all of one surface of the diamond substrate, and a silicon carbide layer located between the diamond substrate and the semiconductor layer, The thickness of the silicon carbide layer is 20 nm or less. The arithmetic mean roughness Ra of the surface of the silicon carbide layer is 0.5 nm or less. A semiconductor laminated structure in which some or all of the silicon carbide contained in the silicon carbide layer is amorphous, and this amorphous state is confirmed by observing a cross-section of the semiconductor laminated structure in the thickness direction with a transmission electron microscope (TEM), which shows that no striped structure is observed in the silicon carbide layer and that the silicon carbide does not correspond to any of cubic, hexagonal, or rhombohedral crystal structures.

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