Plasma processing apparatus with adjustable electrical properties

Abstract

The plasma processing apparatus includes a plasma processing chamber, a source power coupling element configured to generate a plasma inside the plasma processing chamber by coupling a source power to the plasma processing chamber, a DC pulse generator configured to generate a DC pulse train at a DC pulse frequency, a substrate holder disposed inside the plasma processing chamber, a DC coupling element coupled to the DC pulse generator, a DC current path including the DC coupling element, a plasma, and a reference potential node in a series configuration, the DC coupling element configured to bias the substrate holder with respect to the reference potential node using the DC pulse train and a capacitive precoat layer disposed between the DC coupling element and the plasma, the capacitive precoat layer increasing an RC time constant of the DC current path according to the DC pulse frequency.

Description

[Technical Field]

[0001] Cross-reference of related applications This application claims the benefit of U.S. Nonprovisional Patent Application No. 17 / 337,067, filed 2 June 2021, which is incorporated herein by reference in its entirety.

[0002] The present invention generally relates to plasma processing, and in specific embodiments, to apparatus and methods for plasma processing using a plasma processing apparatus having adjustable electrical properties. [Background technology]

[0003] Device formation within microelectronic workpieces can involve a series of manufacturing techniques, including the formation, patterning, and removal of multiple material layers on a substrate. To achieve the physical and electrical specifications of current and next-generation semiconductor devices, processing flows that allow for reduction of feature dimensions while maintaining structural integrity are desirable for various patterning processes.

[0004] Plasma processes are generally used to form devices in microelectronic workpieces. For example, plasma etching and plasma deposition are common process steps in semiconductor device fabrication. A combination of source power and bias power can be used to generate and direct the plasma during plasma processing. During the plasma process, a series of direct current (DC) pulses may be applied as a bias voltage. Short DC pulse trains (i.e., sequences) can be used to increase the flux of high-energy ions onto the substrate.

[0005] Various parameters, such as DC pulse frequency and duty cycle, affect the ion-to-radical ratio and other plasma parameters. The DC pulse frequency and duty cycle also influence charge accumulation on the biased electrode. Charge on the biased electrode reduces the voltage, leading to an unwanted decrease in ion flux on the substrate. However, since the ion energy distribution function (IEDF) depends on the DC pulse frequency and duty cycle, manipulating these parameters to reduce substrate charge is undesirable. [Overview of the Initiative] [Means for solving the problem]

[0006] According to one embodiment of the present invention, a plasma processing apparatus includes a plasma processing chamber, a source power coupling element configured to generate plasma inside the plasma processing chamber by coupling source power to the plasma processing chamber, a DC pulse generator configured to generate a DC pulse train at a DC pulse frequency, a substrate holder disposed inside the plasma processing chamber, a DC coupling element coupled to the DC pulse generator, a DC current path including the DC coupling element, plasma, and a reference potential node in series configuration, wherein the DC coupling element is configured to bias the substrate holder and a capacitive pre-coat layer disposed between the DC coupling element and the plasma with respect to the reference potential node using a DC pulse train. The capacitive pre-coat layer increases the RC time constant of the DC current path according to the DC pulse frequency.

[0007] According to another embodiment of the present invention, the plasma processing apparatus includes a plasma processing chamber, a source power coupling element configured to generate plasma inside the plasma processing chamber by coupling source power to the plasma processing chamber, a DC pulse generator configured to generate a DC pulse train including a DC pulse frequency, a substrate holder disposed inside the plasma processing chamber, a DC coupling element coupled to the DC pulse generator, a DC current path including the DC coupling element, plasma, a reference potential node in series configuration, and a regulating circuit coupled between the DC coupling element and the DC pulse generator. The DC coupling element is configured to bias the substrate holder with respect to the reference potential node using a DC pulse train. The regulating circuit includes a variable capacitance. The regulating circuit is configured to adjust the RC time constant of the DC current path by changing the variable capacitance according to the DC pulse frequency.

[0008] According to yet another embodiment of the present invention, a method for adjusting the electrical characteristics of a plasma processing chamber of a plasma processing apparatus includes: determining a capacitance value from a range of capacitance values ​​according to the DC pulse frequency of a DC pulse train generated by a DC pulse generator of the plasma processing apparatus; adjusting the electrical characteristics by selecting the determined capacitance value using an adjustment circuit coupled between a DC coupling element and a DC pulse generator, the adjustment circuit including a variable capacitance adjustable within a range of capacitance values; and biasing the DC coupling element with respect to a reference potential node by generating a DC pulse train at a DC pulse frequency using the DC pulse generator.

[0009] To fully understand the present invention and its advantages, refer here to the following description, which should be read in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0010] [Figure 1] A schematic timing diagram of an exemplary plasma processing method according to one embodiment of the present invention is shown. [Figure 2]A qualitative graph of voltage as a function of time and a corresponding qualitative graph of the ion energy distribution function for several RC time constants at a fixed DC pulse frequency are shown according to one embodiment of the present invention. [Figure 3] A schematic diagram of an exemplary plasma processing apparatus, according to one embodiment of the present invention, is shown, which includes a DC current path between a bias power supply and a reference potential node. [Figure 4] A schematic diagram of an exemplary plasma processing apparatus comprising an optional capacitive precoat layer and an optional resistive precoat layer, according to one embodiment of the present invention, is shown. [Figure 5] A schematic diagram of an exemplary plasma processing apparatus comprising a control circuit with variable capacitance, according to one embodiment of the present invention, is shown. [Figure 6] A schematic diagram of an exemplary plasma processing apparatus according to one embodiment of the present invention, comprising an optional capacitive precoat layer and an optional resistive precoat layer, along with a control circuit, is shown. [Figure 7] A schematic diagram of an exemplary adjustment circuit comprising a single-pole switch and a plurality of capacitors, according to one embodiment of the present invention, is shown. [Figure 8] A schematic diagram of an exemplary adjustment circuit comprising a single-pole switch and a plurality of variable capacitors, according to one embodiment of the present invention, is shown. [Figure 9] A schematic diagram of an exemplary adjustment circuit according to one embodiment of the present invention, comprising a single-pole switch and a plurality of capacitors including a fixed capacitor and a variable capacitor, is shown. [Figure 10] A schematic diagram of an exemplary adjustment circuit comprising a single-pole switch and a plurality of capacitors, according to one embodiment of the present invention, is shown. [Figure 11] A schematic diagram of an exemplary plasma processing apparatus according to one embodiment of the present invention is shown, comprising a capacitive pre-coat layer covering the upper electrode and an adjustment circuit coupled to the upper electrode. [Figure 12] An exemplary method of plasma processing according to one embodiment of the present invention is shown. [Modes for carrying out the invention]

[0011] Corresponding numbers and symbols across different drawings generally refer to the corresponding elements unless otherwise specified. Drawings are drawn to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to exact scale. The edges of features depicted in the drawings do not necessarily indicate the end of the feature's extent.

[0012] The following sections describe in detail the creation and use of various embodiments. However, it should be understood that the various embodiments described herein are applicable in a variety of specific contexts. The specific embodiments described herein are merely illustrative of specific ways of creating and using various embodiments and should not be construed as limiting the scope.

[0013] DC pulse trains can help generate a large flux of high-energy ions on a substrate. For example, a DC pulse train can accelerate ions toward the substrate by creating a voltage difference between the substrate and the plasma. Short DC pulse trains may also be applied as part of a pulsed plasma process during the plasma afterglow phase (e.g., applying pulsed power and bias power). DC pulse trains can be useful in a variety of applications, including gate etching, patterning, high aspect ratio contact (HARC) etching, and memory manufacturing.

[0014] However, the ion flux and energy depend on the ability to maintain the voltage difference between the plasma and the substrate surface. Charging of the substrate reduces this voltage difference, thus decreasing the effectiveness of the applied voltage over time. Therefore, the effect of each DC pulse must be controlled by electrodes (e.g., electrodes covered with a dielectric material).

[0015] Conventional DC pulse implementations have various drawbacks. The problem arises from the difference between the optimal parameter values ​​for a given process (pulse length, pulse frequency, duty cycle, etc.) and the parameter values ​​required to maintain the plasma sheath. For example, changing the DC pulse frequency and duty cycle of a given process may be undesirable, even if it could reduce charging. Therefore, a plasma processing apparatus that can reduce the charging rate of the substrate without changing the DC pulse frequency or duty cycle may be desirable.

[0016] The RC electrical characteristics of the plasma processing chamber (i.e., those observed with the DC power supply) significantly affect the charging and discharging of the substrate when a DC bias voltage is applied. Therefore, the period during which the sheath voltage can be maintained is mainly determined by the chamber's RC time constant τ. Generally, it is desirable to maintain the sheath voltage through as many DC pulses as possible. The DC voltage response at the substrate during the application of a DC pulse train can be controlled to any desired pulse length, pulse frequency, and duty cycle by controlling the RC time constant τ.

[0017] The RC time constant τ can be adjusted by changing the resistance and / or capacitance of the DC current path between the DC power supply and the reference potential (e.g., the ground potential of the grounding wall of the plasma processing chamber). Capacitance adjustment can be achieved by adding one or more capacitors between the DC coupling element (e.g., an electrostatic chuck) and the DC power supply. Alternatively, a capacitive pre-coat layer can be formed on the DC coupling element, resulting in a significant increase in capacitance. Similarly, resistance can be adjusted by applying a resistive pre-coating to various inner surfaces of the plasma processing chamber, or by adding resistance at various points along the DC current path.

[0018] The adjustment circuit may be included between the DC pulse generator and the DC coupling element. The adjustment circuit may include various capacitors, such as fixed capacitors and variable capacitors. The capacitors may be arranged as a bank of capacitors in parallel. Individual capacitors, banks of capacitors, or other subsets of capacitors may be selectable using one or more switches. A short-circuit path between the DC pulse generator and the DC coupling element may also be included and may be selectable by one or more switches.

[0019] The plasma processing apparatus and plasma processing methods described herein can advantageously provide greater margin and effectiveness to DC pulse train processes. For example, at low DC pulse frequencies, substrate charging can reduce or eliminate the desirable effects of the DC pulse train. The apparatus and methods described herein can advantageously reduce the effects of substrate charging at lower DC pulse frequencies.

[0020] Reducing substrate charge can offer the advantage of enabling control of IEDF (Integrated Ion Flux). In particular, compared to conventional DC pulse train processes, this can lead to reduced ion energy spread, increased average ion energy, and increased high-energy ion flux in the substrate. Controlling the energy distribution and ion energy flux may be desirable to approach an ideal single-energy flux of appropriate size for a given process.

[0021] Various embodiments described herein can advantageously enable the tuning of the electrical characteristics of a plasma processing apparatus to different DC pulse frequencies. For example, by utilizing a tuning circuit including a variable capacitance, an appropriate capacitance (and / or resistance) can be selected to tune the electrical characteristics of the plasma processing chamber as seen from the bias power supply according to a desired DC pulse frequency.

[0022] The embodiments provided below describe various apparatuses and methods for plasma processing, particularly apparatuses and methods for plasma processing including adjustable electrical characteristics. In the following description, those embodiments are explained. Using FIG. 1, an exemplary schematic timing diagram of a plasma processing method according to an embodiment is shown. Various qualitative graphs of voltage as a function of time, and a qualitative IEDF graph corresponding to a plasma processing method according to an embodiment at a given DC pulse frequency, are explained using FIG. 2. FIG. 3 is used to explain an embodiment of a plasma processing apparatus. A plurality of other embodiments of the plasma processing apparatus are explained using FIGS. 4 - 6. An embodiment of an adjustment circuit is explained using FIG. 7. Next, three further embodiments of the adjustment circuit are explained using FIGS. 8 - 10. Another embodiment of the plasma processing apparatus is explained using FIG. 11. An embodiment of the method is explained using FIG. 12.

[0023] FIG. 1 shows a schematic timing diagram of an exemplary plasma processing method according to an embodiment of the present invention.

[0024] Referring to FIG. 1, the schematic timing diagram 100 shows the application of source power (SP) and bias power applied as a DC voltage within a plasma processing apparatus. The SP pulse 111 and a DC pulse train 115 including a series of DC pulses 113. The SP pulse 111 and the DC pulse train 115 can be one cycle of a process repeated at the SP pulse period T SP . Each SP pulse 111 has an SP pulse duration t SP indicating the length of time during which source power is continuously applied in a given cycle. The SP duty ratio D SP can be defined as t SP / T SP . Similarly, each DC pulse has a DC pulse duration t DC and a DC pulse period T DC , and the DC duty ratio D DC is defined as t DC / T DC . As shown, a plurality of DC pulses 113 (i.e., a plurality of periods T DC ) are within the SP pulse period T SPApplied every 50% DC duty cycle (D DC =0.5) is shown, but D DC and D SP Both can be any value between 0 and 1.

[0025] Source power can be alternating current (AC) power. For example, source power is SP frequency f SP It may also be radio frequency (RF) power having a delay t. d This may be included between the application of source power and the application of bias power in the form of a DC pulse train 115. In some cases, a delay may be included between the DC pulse train 115 and the subsequent SP pulse 111.

[0026] The DC pulse train 115 has a DC pulse frequency f that corresponds to the rate at which the consecutive DC pulses 113 are applied. DC Applied by (i.e., f DC = 1 / T DC ). DC pulse frequency f DC The SP frequency is f SP It is less than. In various embodiments, f DC The frequency is less than approximately 1000 kHz. In some embodiments, f DC f is less than approximately 20kHz and may be less than approximately 1kHz. DC DC pulse period T DC (f DC =1000kHz, T DC = 1 μs, f DC =20kHz, T DC (e.g., 50 μs)

[0027] Even at higher DC pulse frequencies (e.g., above 100 kHz), the DC pulse train 115 does not oscillate due to bias power, but instead, 1-D DC Unlike the application of low-frequency RF power, a portion of each cycle equal to f is removed. However, the various advantages of applying a short DC pulse train are that f DC If it increases beyond 1000kHz, it may decrease somewhat (for example, due to limitations on rise and fall rates).

[0028] SP pulse period T SP The DC pulse period T DC It is considerably longer than that. For example, the SP pulse 111 can be applied at a frequency of about 1 kHz to about 10 kHz in one embodiment, but it may be much lower than this. This is about 10 μs to about 1 ms T SP This corresponds to t. SP This can range from approximately 5 μs to approximately 25 μs or more.

[0029] Note that the relative power levels of the source power and bias power are not shown in timing diagram 100. Similarly, for ease of understanding, the relative pulse lengths and the number of DC pulses within the SP period are also not shown in timing diagram 100. In other words, as implicitly shown in the frequency and pulse length examples above, it is not uncommon for more than 50 DC pulses to occur within a given SP period.

[0030] Figure 2 shows a qualitative graph of voltage as a function of time and a corresponding qualitative graph of the ion energy distribution function for several RC time constants at a fixed DC pulse frequency, according to one embodiment of the present invention.

[0031] Referring to Figure 2, qualitative graph 200 shows the DC pulse frequency f at 400 kHz. DC and a duty cycle of 50% (D DC This shows the effect of changing the time constant τ while maintaining τ = 0.5). Throughout the voltage graph in the top row, the response of the rod electrodes (e.g., of the DC coupling element) remains constant and is shown as the dashed curve 120. As τ increases from τ = 0.2 μs to τ = 20 μs, the voltage response at the substrate surface is shown as the solid curves 121-125. In this example, the voltage at the substrate surface is shown as negative, but it can also be positive depending on the configuration of the reference potential and supplied bias power.

[0032] As shown by curve 121, at τ = 0.2 μs, the voltage at the substrate surface initially decreases with the response of the rod electrode, but then increases sharply due to charging before even reaching the minimum voltage of the rod electrode. This results in a steep return slope that deviates significantly from the approximate square wave response of the rod electrode. At τ = 1 μs (curve 122), the slope is smaller, but the voltage has not yet reached the minimum voltage of the rod electrode, and the voltage overshoot at the rising edge of the rod voltage is more pronounced. At τ = 5 μs, the slope at the bottom of surface curve 123 begins to approach the flat square waveform of the rod voltage. The surface voltage reaches the minimum voltage and increases by only about 15% over the duration of the DC pulse of 1.25 μs.

[0033] As τ increases to 10 μs and then to 20 μs, the gradient continues to flatten, but the return decreases because the gradient almost reflects the rod's response. Thus, the gradient at the bottom of curve 124 is very similar to the gradient at the bottom of curve 125. On the other hand, the voltage overshoot changes more dramatically from τ=10 μs to τ=20 μs because it also begins to approach the response of the rod electrode.

[0034] IEDF graphs 131–135 show the IEDF results on the substrate surface, corresponding to curves 121–125, respectively. Because the surface spends a short time under negative voltage, the IEDF at τ = 0.2 μs, shown in graph 131, exhibits low energy (approximately 700 eV) and large spread (indicated by double-headed arrows). Similarly, at τ = 1 μs (graph 132), the ion energy increases overall, but still only reaches approximately 950 eV, with a spread of approximately 500 eV. Lower ion energy can be disadvantageous because more voltage is required to reach the desired ion energy. However, large energy spread may be even more undesirable, as many ions reaching the substrate do not possess the energy necessary to produce the desired effect. This can lead to reduced process efficiency and potentially make some processes impractical.

[0035] In contrast, Graph 133 shows that the ion energy reaching 1 keV at τ = 5 μs corresponds to an applied voltage of -1 kV. In addition, the flattening of the gradient significantly reduces the energy spread to approximately 200 eV. Graphs 134 and 135 show that as τ increases to 10 μs and 10 μs, the energy spread continues to decrease and the number of high-energy ions increases.

[0036] f DC = Period T of 400kHz DC τ = 5μs. As can be seen from the above analysis, τ = 5μs offers various advantages to the surface voltage and the resulting IEDF. Since 5μs is twice the period of 2.5μs, given f DC A generally useful target for τ is τ≧2 / f DC This is a possibility. In other words, the RC time constant is at least twice the reciprocal of the DC pulse frequency. For this goal, as an example, f DC For 1000kHz, τ=2μs, f DC For a frequency of 20kHz, τ = 100μs.

[0037] However, it should be noted that this goal may or may not accurately represent the desired τ in a given application, depending on the specific details. For example, given f DC Increasing τ yields beneficial effects not only when a specific goal is reached, but also continuously from the beginning. Therefore, in some applications, if this value is far greater, τ < 2 / f DC (For example, 2 / f DC In cases where this is unrealistic, we may use τ = 2 / f. DC It is often close to this value, but in applications where a nearly perfect square wave response at the substrate surface is desired, this value may be much higher.

[0038] Duty cycle D DC This may affect the target of τ. For example, the spread of IEDF is D DC As the value increases (>0.5), D increases. DCAs it decreases (<0.5), it may decrease. Therefore, compared to the target τ at a duty cycle of 50% in a given plasma process, a higher D DC Higher τ and lower D DC In some cases, a lower τ-share is desirable.

[0039] Figure 3 shows a schematic diagram of an exemplary plasma processing apparatus according to one embodiment of the present invention, which includes a DC current path between a bias power supply and a reference potential node. The plasma processing apparatus of Figure 3 may be configured, for example, to carry out the plasma processing method described herein, for example, according to the timing diagram of Figure 1.

[0040] Referring to Figure 3, the plasma processing apparatus 300 includes a plasma processing chamber 302 coupled to a source power supply 307 and a bias power supply 309. The source power supply 307 is configured to generate plasma 306 inside the plasma processing chamber 302 303. The source power supply 307 can generate capacitively coupled plasma (CCP) (e.g., as shown in Figure 11), inductively coupled plasma (ICP), surface wave plasma (SWP), etc. For example, the source power may be coupled to a helical resonator antenna that generates plasma 306 inside the plasma processing chamber 302.

[0041] In this schematic example, the source power supply 307 is coupled to the top of the plasma processing chamber 302, and the bias power supply 309 is coupled to the substrate holder 304 inside the plasma processing chamber 302 303, but other configurations are possible. The substrate holder 304 is configured to support the substrate 305. For example, the substrate holder 304 may be an electrostatic chuck (ESC). Alternatively, the substrate holder may be a vacuum chuck or other suitable support structure.

[0042] The DC pulse generator 308 is coupled between the bias power supply 309 and the substrate holder 304. The DC pulse generator 308 is configured to generate a DC pulse train at a DC pulse frequency. For example, the DC pulse generator 308 combined with the bias power supply 309 may be configured to apply a DC pulse train to the substrate holder, as shown in timing diagram 100 of Figure 1.

[0043] The reference potential node 345 is coupled to the plasma processing chamber 302. In one embodiment, the reference potential node 345 is coupled to the wall of the plasma processing chamber 302 as shown in the figure. In one embodiment, the reference potential node 345 is grounded. The reference potential node 345 forms a DC current path 340 between the bias power supply 309 and the reference potential node 345. The behavior of the DC current path 340 can be modeled as including a resistive component 341 and a capacitive component 343.

[0044] The plasma 306 itself is supplied to the conductive portion of the DC current path 340. Note that the dashed boundary of the plasma 306 is drawn to stop before the walls of the plasma processing chamber 302 and the substrate holder 304 / substrate 305 for readability purposes only. In reality, the plasma 306 extends to and contacts the walls of the plasma processing chamber 302, the substrate holder 304, and the substrate 305.

[0045] Furthermore, it is important to recognize that this simplified model is conceptual. The actual current paths contributing to the resistive component 341 and the capacitive component 343 may be far more complex than those illustrated. In other words, plasma currents can flow along all surfaces of the chamber. The chamber surfaces may contain inductive, resistive, and capacitive components that contribute to the operation of the entire circuit. Many other sources of contribution to the resistive component 341 and the capacitive component 343 may also exist (many of which are described below).

[0046] The resistive component 341 and capacitive component 343 of the DC current path 340 contribute to the electrical characteristics of the plasma processing chamber 302 as seen from the bias power supply 309. In this simplified model, the DC current path 340 is a series RC circuit with a time constant τ equal to RC, where R is the resistance of the resistive component 341 and C is the capacitance of the capacitive component 343. As previously mentioned with reference to Figure 2, adjusting the time constant τ can improve the voltage response at the substrate 305, which is advantageous as it reduces the ion energy spread at the substrate 305, increases the ion energy, and increases the ion flux.

[0047] Of course, several physical components may contribute to either or both of the resistive component 341 and the capacitive component 343. As will be apparent from the following description, the positions of the resistive component 341 and the capacitive component 343 can represent the positions of the corresponding physical components, but the specific positions are also variable within the plasma processing apparatus.

[0048] Figure 4 shows a schematic diagram of an exemplary plasma processing apparatus according to one embodiment of the present invention, comprising an optional capacitive precoat layer and an optional resistive precoat layer. The plasma processing apparatus of Figure 4 may be a specific implementation of other plasma processing apparatuses described herein, such as the plasma processing apparatus of Figure 3. Similarly labeled elements may be as described above.

[0049] Referring to Figure 4, the plasma processing apparatus 400 includes a substrate holder 404 located inside a plasma processing chamber 402, which is coupled to a source power supply 407 configured to generate plasma 406. A bias power supply 409 is coupled to a DC pulse generator 408, which in turn is coupled to a DC coupling element 453 located within the substrate holder 404.

[0050] Hereafter, conventions are adopted for brevity and clarity, and it should be noted that in this case, elements following pattern [x10] may be relevant implementations of plasma processing chambers in various embodiments. For example, plasma processing chamber 402 may be identical to plasma processing chamber 302 unless otherwise specified. Similar rules are adopted for other elements as will be evident from the use of similar terminology in combination with the aforementioned three-digit notation.

[0051] The reference potential node 445 is coupled to the wall of the plasma processing chamber 402. The DC current path is generated from the bias power supply 409, through the DC coupling element 453 and the plasma 406, to the reference potential node 445.

[0052] The substrate holder 404 is configured to support the substrate 405. The capacitive pre-coat layer 444 may be placed on the upper surface of the substrate holder 404 between the substrate holder 404 and the substrate 405. However, other configurations are also possible. In some embodiments, the capacitive pre-coat layer 444 may also be omitted (for example, in favor of alternatives or in mounting configurations that utilize only additional resistive components).

[0053] The capacitive pre-coat layer 444 increases the capacitance of the DC current path (acting as a capacitive component). For example, the capacitance of the capacitive pre-coat layer 444 is given by C = εA C / l C It can be written as follows, where ε is the dielectric constant, and A C l is the area, C ε is the thickness of the capacitive precoat layer 444. Many configurations are possible, depending on the details of a given application, but one example set of values ​​is ε = 6 nF / m, A C =(100mm) 2 , and l C This can be set to 600 μm, which yields a capacitance C of 100 nF.

[0054] For a given substrate size (e.g., wafer size), A may remain constant, but the dielectric constant ε (i.e., relative permittivity / dielectric constant) and thickness l may remain constant. C A can be varied to achieve the desired capacitance C. In applications involving substrates of different sizes (e.g., larger wafers), A can be varied by increasing the capacitance, with ε and l being different. C This may influence the selection. In some cases, a material with a higher or lower dielectric constant may be required to ensure an appropriate thickness of the capacitive precoat layer.

[0055] The capacitive precoat layer 444 comprises a dielectric material in various embodiments, and in some embodiments, a ceramic material. The capacitive precoat layer 444 may contain silicon, and in one embodiment, silica (SiO2). In another embodiment, the capacitive precoat layer 444 contains yttria (Y2O3).

[0056] However, various dielectric materials may be suitable for use as the capacitive precoat layer 444. As shown in the above formula, to use a material with a higher or lower dielectric constant, simply increase the thickness accordingly. C It may be necessary to increase or decrease it. Other considerations such as process suitability, potential dielectric breakdown, and other material properties may also be taken into account.

[0057] It is recognized that the relative permittivity of a given material depends on various factors. For example, a person skilled in the art would recognize that relative permittivity depends on frequency. In the context of this disclosure, it is assumed that the relative permittivity (and thus the permittivity) in the capacitance equation is considered under applied frequency operating conditions (e.g., DC pulse frequency). Considering the description herein, it is assumed that a person skilled in the art can appropriately adjust the thickness of the capacitive precoat layer based on various details of a given application.

[0058] Thickness l RThe resistive precoat layer 442 may be included on the surface of the interior 403 of the plasma processing chamber 402. Here, the resistive precoat layer 442 is included on the surface of the plasma processing chamber 402, but other configurations are possible (e.g., depending on the location and configuration of the reference potential node 445). In some embodiments, the resistive precoat layer 442 may be omitted (e.g., in favor of alternatives, or in implementations that utilize only additional capacitive components).

[0059] Similar to the capacitive pre-coat layer 444 described above, the resistive characteristics of the resistive pre-coat layer 442 increase the resistance of the DC current path (which functions as a resistive component). The shape of the plasma processing chamber 402 affects the resistance R of the resistive pre-coat layer 442. For example, resistance R = ρl / A R Here, ρ is the resistivity, and A R l is the cross-sectional area perpendicular to the direction of DC current flow, and l is the length of the resistive pre-coat layer 442 in the direction of DC current flow. Although the resistive pre-coat layer 442 is shown only to cover the vertical sides of the plasma processing chamber 402, it should be understood that it can also cover other surfaces such as the top surface of the plasma processing chamber 402 or the sides of the substrate holder 404.

[0060] Assuming that the current flows along the surface of the plasma processing chamber 402, A R is 2πr × l R It can be approximated as follows, where r is the radius of the plasma processing chamber 402 (this is for a cylindrical chamber, but any suitable chamber shape can be used). Then the length l is the average distance the current must travel before reaching the reference potential node. As can be imagined, many configurations are possible and depend on various specific factors of a given application. An example set of values ​​is ρ = 10 -5 Ω·m, A R =2π(0.15m)(100nm)≈10 -7 m 2 And l can be set to 0.1m, which makes the resistance R approximately 1kΩ.

[0061] The use of the capacitive pre-coat layer 444 and the resistive pre-coat layer 442 can favorably achieve a τ value over a wide frequency range that significantly improves the voltage response on the surface of the substrate 405. For example, with C=100nF and R=1kΩ, τ=100μs (=2 / 20kHz). Doubling C and R results in τ=400μs, and f DC This corresponds to 5kHz. While there may be practical limitations on the maximum values ​​of C and R, the effect of charging is advantageous at low DC pulse frequencies f. DC This can be reduced over most of the duration of each DC pulse.

[0062] The resistant precoat layer 442 comprises a resistant material in various embodiments. In one embodiment, the resistant precoat layer 442 comprises amorphous carbon (aC). In another embodiment, the resistant precoat layer 442 comprises graphite carbon. The resistant precoat layer 442 may also comprise a graphite carbon-based material. In addition, the resistant precoat layer 442 may comprise silicon-like materials, or silica-like materials, and others. Since the resistant precoat layer 442 is exposed to plasma 406 and substrate 405, the choice of material may be influenced by process suitability. For example, a carbon-based resistant precoat layer may be suitable for Si and SiO2 etching processes.

[0063] Figure 5 shows a schematic diagram of an exemplary plasma processing apparatus comprising a regulating circuit with variable capacitance, according to one embodiment of the present invention. The plasma processing apparatus of Figure 5 may be a specific implementation of other plasma processing apparatuses described herein, such as the plasma processing apparatus of Figure 3. Similarly labeled elements may be the same as those described above.

[0064] Referring to Figure 5, the plasma processing apparatus 500 includes a substrate holder 504 located inside a plasma processing chamber 502, which is configured to support a substrate 505 and coupled to a source power supply 507 configured to generate plasma 506. A regulating circuit 501 is coupled between a DC pulse generator 508 and a DC coupling element 553 located inside the substrate holder 504. A bias power supply 509 is coupled to the DC pulse generator 508. A reference potential node 545 is coupled to the plasma processing chamber 502.

[0065] The adjustment circuit 501 has a variable capacitance. That is, the capacitance of the adjustment circuit 501 can be changed to adjust the electrical characteristics of the plasma processing chamber 502. In one embodiment, the electrical characteristic is the time constant τ of the DC current path between the bias power supply 509 and the reference potential node 545. The capacitance of the adjustment circuit 501 may be adjusted manually or automatically during or between operations of the plasma processing apparatus 500. The capacitance of the adjustment circuit 501 can be selected mechanically, electronically, electromechanically, or using other appropriate selection mechanisms.

[0066] The adjustment circuit 501 may also include static or variable resistor components. In some cases, it may be desirable to incorporate such additional resistor components between the board 505 and the reference potential node 545, rather than between the board 505 and the bias power supply 509, in order to prevent unnecessary voltage drops between the board 505 and the bias power supply 509.

[0067] Figure 6 shows a schematic diagram of an exemplary plasma processing apparatus according to one embodiment of the present invention, comprising a control circuit along with an optional capacitive precoat layer and an optional resistive precoat layer. The plasma processing apparatus of Figure 6 may be a specific implementation of other plasma processing apparatuses described herein, such as the plasma processing apparatus of Figure 3. Similarly labeled elements may be the same as those described above.

[0068] Referring to Figure 6, the plasma processing apparatus 600 includes a substrate holder 604 configured to support a substrate 605 and located inside 603 of the plasma processing chamber 602. A regulating circuit 601 is coupled between a DC pulse generator 608 and a DC coupling element 653 located inside the substrate holder 604. A bias power supply 609 is coupled to the DC pulse generator 608. A reference potential node 645 is coupled to the plasma processing chamber 602.

[0069] A source power supply 607 configured to generate plasma 506 is coupled to a source power coupling element 651. In one embodiment, the source power coupling element 651 is an inductive coupling element that couples the source power to the plasma processing chamber 602 via an insulator 655 (as shown in the figure), but other configurations are also possible.

[0070] A capacitive pre-coat layer 644 may be placed on the upper surface of the substrate holder 604 between the substrate holder 604 and the substrate 605. A resistive pre-coat layer 642 may be included on the surface of the interior 603 of the plasma processing chamber 602. In some embodiments, the capacitive pre-coat layer 644 or the resistive pre-coat layer 642 may be omitted.

[0071] In embodiments that include both the adjustment circuit 601 and the capacitive pre-coat layer 644, the total capacitance C in the DC current path between the bias power supply 609 and the reference potential node 645 is the combination of both capacitive components. Since the adjustment circuit 601 is in series with the capacitive pre-coat layer 644, C = (1 / C) 固定 +1 / C 調整 ) -1 That is the case.

[0072] Because it is in the form of a series capacitor equation, C is always C 固定 It becomes smaller, C 調整 As it gets very large C 固定 It approaches. In some cases, the adjustment circuit 601 is such that when C is selected, C is C 固定 A short-circuit option may be included that does not add capacitance to make it equal to C. 調整 The value of C 固定Even if it far exceeds (for example, 10 times), C is still C 固定 Since it is only 91% of C, 固定 If equality is desired, the adjustment circuit 601 can be bypassed using a short-circuit option.

[0073] Figure 7 shows a schematic diagram of an exemplary tuned circuit comprising a single-pole switch and a plurality of capacitors according to one embodiment of the present invention. The tuned circuit of Figure 7 may be a specific implementation of other tuned circuits described herein, such as the tuned circuits of Figures 5 and 6. Similarly, the labeled elements may be as described above.

[0074] Referring to Figure 7, the adjustment circuit 701 includes a first adjustment input / output 757 (for example, for coupling to a DC coupling element) and a second adjustment input / output 759 (for example, for coupling to a DC pulse generator). The adjustment circuit 701 further includes a plurality of capacitors 760, which may include fixed capacitors 762 as shown. In various embodiments, the fixed capacitors 762 are reliable capacitors. In some embodiments, some or all of the fixed capacitors 762 are vacuum capacitors. In some embodiments, some or all of the fixed capacitors 762 are ceramic capacitors.

[0075] The first single-pole switch 771 includes a single pole (input) coupled to the first adjustment input / output 757 and at least one on (output) coupled to a subset of the capacitors 760. An optional second single-pole switch 772 may be coupled between the subset of the capacitors 760 and the second adjustment input / output 759 (for example, to further isolate unselected current paths from selected current paths). The positions of the first single-pole switch 771 and the optional second single-pole switch 772 may be swapped. Optionally, a short-circuit path 764 is also included between the first adjustment input / output 757 and the second adjustment input / output 759.

[0076] In some embodiments, the first single-pole switch 771 (and an optional second single-pole switch 772) is a mechanical switch. In one embodiment, the mechanical switch is an electromechanical switch. In other embodiments, other suitable switches, such as electrical switches, may be used. However, it should be noted that care must be taken to avoid parasitic failure or dielectric breakdown due to the application of high voltage.

[0077] In one embodiment, the first single-pole switch 771 is a single-pole multi-throw switch (as shown in the figure) that includes multiple outputs coupled to multiple subsets of multiple capacitors 760. In another embodiment, the first single-pole switch 771 is a single-pole single-throw switch, and the adjustment circuit 701 includes an additional single-pole single-throw switch coupled to multiple capacitors. Of course, other combinations of single-pole switches are also possible.

[0078] Multiple capacitors 760 may be arranged as a capacitor bank 763. In one embodiment, a capacitor bank 763 is a physical group of separate capacitors. One (or two, if optional switches are included) single-pole multi-throw switches can be used to select a bank of capacitors that are completely isolated from each other. In another embodiment, a capacitor bank 763 is a logical grouping (for example, some or all of the capacitors are used in two or more logical banks).

[0079] Multiple subsets of capacitors 760 may be mutually exclusive. However, using the same capacitor in two or more subsets may reduce the number of capacitors required to achieve a given variable capacitance range, but it may also increase the complexity of the adjustment circuit or introduce parasitic currents within the adjustment circuit. In one particular example, the first single-pole switch 771 is a rotary switch with an output coupled to n fixed capacitors 762. The rotary switch has n+1 positions, including positions for coupling capacitors numbered 1 through n and a position for coupling a zero-coupled capacitor (short-circuit path 764). In a modified example, the short-circuit path 764 is omitted, and only n positions are included.

[0080] In another specific example, the capacitors are arranged in a bank of n capacitors each having a capacitance of 2 m , where the range of m is from 0 to n-1. Next, n single-pole single-throw switches can be used to select combinations of banks that result in 1 to n-1 coupled capacitors. If the short-circuit path 764 is included, an additional single-pole single-throw switch may enable the selection of the short-circuit path 764.

[0081] In practice, a selected subset of the plurality of capacitors 760 forms the capacitance C 調整 described above. Since the constituent capacitors of the plurality of capacitors need not be identical, C 調整 can be adjusted as needed according to a given application. However, a simple example of n identical fixed capacitors 762 each having a capacitance C0 is useful for explaining the function of the tuning circuit 701. And C 調整 = nC0. If there are no other capacitive components, the variable capacitance of the tuning circuit 701 ranges from 0 to nC0 in discrete steps of C0.

[0082] However, if another capacitive component (such as a capacitive precoat layer) is also included in series, the total capacitance C n = (1 / C 固定 + 1 / nC0) -1 . Note that n cannot be set to zero in this equation, but in the case of n = 0 (when the short-circuit path is selected), C = C 固定 as described above. In a specific example where C 固定 = 100 nF and C0 = 5 nF, C n=1、2、3 ... = {4.8 nF, 9.1 nF, 13 nF,...}. Of course, fixed capacitors with capacitance values lower and higher than 5 nF are available.

[0083] The increase in the total capacitance for each additional capacitor decreases as n increases. For example, if C 20 = 50 nF, but C 30=60nF. In particular, C 固定 If C does not exist, 20 =100nF and C 30 = 150nF. Therefore, a high maximum capacitance (e.g., 100nF) is desirable, but if there is not enough space to place many capacitors in the adjustment circuit, a combination of a capacitive pre-coat layer and an adjustment circuit may be preferable. The relatively small number of capacitors in the adjustment circuit allows for finer selection of capacitance in a lower range, such as approximately 5nF (n=1) to approximately 33nF (n=10).

[0084] Figure 8 shows a schematic diagram of an exemplary adjustment circuit comprising a single-pole switch and a plurality of variable capacitors according to one embodiment of the present invention. The adjustment circuit in Figure 8 may be a specific implementation of other adjustment circuits described herein, such as the adjustment circuit in Figure 7. Similarly labeled elements may be the same as those described above.

[0085] Referring to Figure 8, the adjustment circuit 801 includes a first adjustment input / output 857, a second adjustment input / output 859, and a plurality of capacitors 860, which may include a variable capacitor 861 located in a capacitor bank 863 as shown. In various embodiments, the variable capacitor 861 is a reliable capacitor. In some embodiments, some or all of the variable capacitor 861 are vacuum capacitors. In some embodiments, some or all of the variable capacitor 861 are ceramic capacitors. The adjustment circuit 801 further includes a first single-pole switch 871, and may also include an optional second single-pole switch 872. An optional short-circuit path 864 may also be included.

[0086] The adjustment circuit 801 differs from the adjustment circuit 701 in that it uses a variable capacitor 861 instead of a fixed capacitor. This may have the additional advantage of allowing for a smooth capacitance transition across the available range of the variable capacitance. However, variable capacitors have lower capacitance than fixed capacitors and can be larger and more expensive.

[0087] Figure 9 shows a schematic diagram of an exemplary adjustment circuit according to one embodiment of the present invention, comprising a single-pole switch and a plurality of capacitors, including a fixed capacitor and a variable capacitor. The adjustment circuit of Figure 9 may be a specific implementation of other adjustment circuits described herein, such as the adjustment circuit of Figure 7. Similarly labeled elements may be the same as those described above.

[0088] Referring to Figure 9, the adjustment circuit 901 includes a first adjustment input / output 957, a second adjustment input / output 959, and a plurality of capacitors 960, which may include a variable capacitor 961 and a fixed capacitor 962 arranged in a capacitor bank 963 as shown in the figure. The adjustment circuit 901 further includes a first single-pole switch 971, and may also include an optional second single-pole switch 972. An optional short-circuit path 964 may also be included.

[0089] The adjustment circuit 901 differs from adjustment circuits 701 and 801 in that it utilizes both a variable capacitor 961 and a fixed capacitor 962. This advantageously expands the range of the variable capacitance while simultaneously improving the fine-tuning of the capacitance.

[0090] Figure 10 shows a schematic diagram of an exemplary tuned circuit comprising a single-pole switch and a plurality of capacitors according to one embodiment of the present invention. The tuned circuit of Figure 10 may be a specific implementation of other tuned circuits described herein, such as the tuned circuit of Figure 7. Similarly labeled elements may be the same as those described above.

[0091] Referring to Figure 10, the adjustment circuit 1001 includes a first adjustment input / output 1057, a second adjustment input / output 1059, and a plurality of capacitors 1060, which may include a fixed capacitor 1062 located in a capacitor bank 1063 as shown in the figure. The adjustment circuit 1001 further includes a first single-pole switch 1071, and may also include an optional second single-pole switch 1072.

[0092] The adjustment circuit 1001 is a specific implementation of the adjustment circuit 701 in which the short-circuit path is omitted. This configuration may be useful, for example, when the capacitive pre-coat layer is omitted. As mentioned above, a variable capacitor can also be used instead of, or in addition to, the fixed capacitor 1062.

[0093] Figure 11 shows a schematic diagram of an exemplary plasma processing apparatus according to one embodiment of the present invention, comprising a capacitive pre-coat layer covering an upper electrode and a regulating circuit coupled to the upper electrode. The plasma processing apparatus of Figure 11 may be a specific implementation of other plasma processing apparatuses described herein, such as the plasma processing apparatus of Figure 3. Similarly labeled elements may be the same as those described above.

[0094] Referring to Figure 11, the plasma processing apparatus 1100 includes a substrate holder 1104 configured to support a substrate 1105 and located inside the plasma processing chamber 1102 1103. A source power supply 1107 configured to generate plasma 1106 is coupled to a source power coupling element 1151. A regulating circuit 1101 is coupled between a DC pulse generator 1108 and the DC coupling element 1153. A bias power supply 1109 is coupled to the DC pulse generator 1108. A reference potential node 1145 is coupled to the substrate holder 1104.

[0095] The plasma processing apparatus 1100 differs from the plasma processing apparatus shown in Figure 3 in that the DC coupling element 1153 is mounted as an upper electrode above the interior 1103 of the plasma processing chamber 1102. The voltage applied to the DC coupling element 1153 by the DC pulse generator 1108 may be positive (but not negative) to generate a potential gradient that accelerates cations toward the substrate 1105, which may be or may be close to a reference potential. In this case, a DC current path exists from the bias power supply 1109 to the reference potential node 1145.

[0096] An optional capacitive precoat layer 1144 can be included on the DC coupling element 1153. In addition, since the reference potential node 1145 is coupled to the substrate holder 1104 rather than the wall of the plasma processing chamber 1102, a resistive component may be included between the substrate 1105 and the reference potential node 1145. For example, an optional resistive precoat layer (not shown) can be included on the surface of the substrate holder 1104. Alternatively or additionally, resistors may be included to increase resistance.

[0097] Figure 12 shows an exemplary method of plasma treatment according to one embodiment of the present invention. The method of Figure 12 may be carried out using the systems and apparatus described herein in combination with other methods. For example, the method of Figure 12 may be combined with any of the embodiments of Figures 1 to 11. The configuration and numbering of the steps in Figure 12 are illustrated in a logical order, but are not intended to be limiting. The method steps of Figure 12 may be carried out in any suitable order or concurrently with each other, as may be apparent to those skilled in the art.

[0098] Referring to Figure 12, step 1201 of the plasma processing method 1200 includes determining a capacitance value from a range of capacitance values ​​according to the DC pulse frequency of the DC pulse train generated by the DC pulse generator of the plasma processing apparatus. Step 1202 includes adjusting the electrical characteristics by selecting the determined capacitance value using an adjustment circuit coupled between a DC coupling element and the DC pulse generator, the adjustment circuit comprising a variable capacitance that is adjustable within a range of capacitance values.

[0099] Plasma is optionally generated in the plasma processing chamber of the plasma processing apparatus by applying source power to the plasma processing chamber in an optional step 1203. Alternatively, plasma may already be present in the plasma processing chamber. Step 1204 includes biasing a DC coupling element with respect to a reference potential node by generating a DC pulse train at a DC pulse frequency using a DC pulse generator. The DC coupling element may be biased during the afterglow phase of the plasma (e.g., after the source power is removed).

[0100] Herein, exemplary embodiments of the present invention are summarized. Other embodiments will also be understood from the entirety of this specification and the claims filed herein. [Examples]

[0101] Example 1. A plasma processing apparatus comprising: a plasma processing chamber; an SP coupling element configured to generate plasma inside the plasma processing chamber by coupling source power to the plasma processing chamber; a DC pulse generator configured to generate a DC pulse train at a DC pulse frequency; a substrate holder disposed inside the plasma processing chamber; a DC coupling element coupled to the DC pulse generator; a DC current path including the DC coupling element, plasma, and a reference potential node in series configuration, wherein the DC coupling element is configured to bias the substrate holder with respect to the reference potential node using a DC pulse train; and a capacitive precoat layer disposed between the DC coupling element and the plasma, the capacitive precoat layer increasing the RC time constant of the DC current path according to the DC pulse frequency.

[0102] Example 2. The plasma processing apparatus according to Example 1, wherein the capacitive pre-coat layer increases the RC time constant to at least twice the reciprocal of the DC pulse frequency.

[0103] Example 3. The plasma processing apparatus according to Example 1 or 2, wherein the capacitance of the capacitive pre-coat layer is approximately 100 nF.

[0104] Example 4. A plasma processing apparatus according to any one of Examples 1 to 3, wherein the thickness of the capacitive precoat layer is approximately 600 nm.

[0105] Example 5. The plasma processing apparatus according to any one of Examples 1 to 4, wherein the capacitive precoat comprises silicon, silica, or yttria.

[0106] Example 6. A plasma processing apparatus according to any one of Examples 1 to 5, further comprising a resistive precoat layer disposed on the inner surface of a plasma processing chamber, a reference potential node coupled to the plasma processing chamber, the resistive precoat layer positioned between the plasma and the reference potential node, and the resistive precoat layer further increasing the RC time constant of the DC current path according to the DC pulse frequency.

[0107] Example 7. The plasma processing apparatus according to Example 6, wherein the resistance of the resistive pre-coat layer is approximately 1 kΩ.

[0108] Example 8. The plasma processing apparatus according to Example 6 or 7, wherein the thickness of the resistant pre-coat layer is approximately 100 nm.

[0109] Example 9. The plasma apparatus according to any one of Examples 6 to 8, wherein the resistant precoat layer comprises amorphous carbon, graphite carbon, silicon-like material, or silica-like material.

[0110] Example 10. The plasma processing apparatus according to any one of Examples 1 to 9, further comprising a regulating circuit coupled between a DC coupling element and a DC pulse generator, the regulating circuit including a variable capacitance.

[0111] Example 11. The plasma processing apparatus according to any one of Examples 1 to 10, wherein the substrate holder is an electrostatic chuck (ESC).

[0112] Example 12. The plasma processing apparatus according to any one of Examples 1 to 11, wherein a DC coupling element is positioned above the substrate holder and a reference potential node is coupled to the substrate holder.

[0113] Example 13. A plasma processing apparatus comprising: a plasma processing chamber; an SP coupling element configured to generate plasma inside the plasma processing chamber by coupling source power to the plasma processing chamber; a DC pulse generator configured to generate a DC pulse train including a DC pulse frequency; a substrate holder disposed inside the plasma processing chamber; a DC current path comprising a DC coupling element coupled to the DC pulse generator, a DC coupling element, plasma, and a reference potential node in a series configuration, wherein the DC coupling element is configured to bias the substrate holder with respect to the reference potential node using a DC pulse train; and a regulating circuit coupled between the DC coupling element and the DC pulse generator, wherein the regulating circuit includes a variable capacitance and is configured to adjust the RC time constant of the DC current path by changing the variable capacitance according to the DC pulse frequency.

[0114] Example 14. The plasma processing apparatus according to Example 13, wherein the adjustment circuit includes a variable capacitor.

[0115] Example 15. The plasma processing apparatus according to Example 13 or 14, wherein the adjustment circuit includes a plurality of capacitors and a first unipolar switch having an input coupled to either a DC coupling element or a DC pulse generator and a first output coupled to a first subset of the plurality of capacitors.

[0116] Example 16. The plasma processing apparatus according to Example 15, wherein the first single-pole switch is a mechanical switch.

[0117] Example 17. The plasma processing apparatus according to Example 16, wherein the first single-pole switch is an electromechanical switch.

[0118] Example 18. The plasma processing apparatus according to any one of Examples 15 to 17, wherein the adjustment circuit further includes a second unipolar switch having an input coupled to a DC pulse generator and an output coupled to a first subset of a plurality of capacitors, the first unipolar switch being coupled to a DC coupling element.

[0119] Example 19. A plasma processing apparatus according to any one of Examples 15 to 18, wherein the plurality of capacitors include a bank of plurality of capacitors coupled in parallel with each other.

[0120] Example 20. The plasma processing apparatus according to any one of Examples 15 to 19, wherein the first single-pole switch is a multi-throw switch having a second output coupled to a second subset of a plurality of capacitors.

[0121] Example 21. The plasma processing apparatus according to Example 20, wherein the first single-pole multi-throw switch is a rotary switch.

[0122] Example 22. The plasma apparatus according to Example 20 or 21, wherein the first subset of capacitors and the second subset of capacitors are mutually exclusive.

[0123] Example 23. A plasma processing apparatus according to any one of Examples 15 to 18, wherein the first single-pole switch is a single-throw switch, and the adjustment circuit further includes a second single-pole single-throw switch having an input coupled to the input of the first single-pole single-throw switch and an output coupled to a second subset of a plurality of capacitors.

[0124] Example 24. A plasma processing apparatus according to any one of Examples 15 to 23, wherein the plurality of capacitors include a plurality of fixed capacitors.

[0125] Example 25. The plasma processing apparatus according to Example 24, wherein the plurality of capacitors further include a variable capacitor.

[0126] Example 26. A plasma processing apparatus according to any one of Examples 15 to 25, wherein the first unipolar switch includes a second output coupled to either a DC pulse generator or a DC coupling element, and as a result a short-circuit path is formed between the DC coupling element and the DC pulse generator when the second output is selected.

[0127] Example 27. A plasma processing apparatus according to any one of Examples 13 to 26, further comprising a resistive precoat layer disposed on the inner surface of a plasma processing chamber, a reference potential node coupled to the plasma processing chamber, the resistive precoat layer positioned between the plasma and the reference potential node, and the resistive precoat layer further increasing the RC time constant of the DC current path according to the DC pulse frequency.

[0128] Example 28. The plasma apparatus according to Example 27, further comprising a capacitive precoat layer disposed between a DC coupling element and a plasma, the capacitive precoat layer increasing the RC time constant of the DC current path according to the DC pulse frequency.

[0129] Example 29. A method for adjusting the electrical characteristics of a plasma processing chamber of a plasma processing apparatus, comprising: determining a capacitance value from a range of capacitance values ​​according to the DC pulse frequency of a DC pulse train generated by a direct current (DC) pulse generator of the plasma processing apparatus; adjusting the electrical characteristics by selecting the determined capacitance value using a tuning circuit coupled between a DC coupling element and a DC pulse generator, the tuning circuit including a variable capacitance adjustable within a range of capacitance values; and biasing the DC coupling element with respect to a reference potential node by generating a DC pulse train at a DC pulse frequency using a DC pulse generator.

[0130] Example 30. The method according to Example 29, further comprising generating plasma in the plasma processing chamber by applying source power to the plasma processing chamber before biasing the DC coupling element, and biasing the DC coupling element in the afterglow of the plasma after the source power has been removed.

[0131] Example 31. The method according to Example 29 or 30, wherein biasing the DC coupling element includes negatively biasing the substrate holder in the plasma processing chamber with respect to a reference potential node by generating a DC pulse train at a DC pulse frequency using a DC pulse generator.

[0132] Example 32. The method according to any one of Examples 29 to 31, wherein the electrical characteristics include the RC time constant of a DC current path including a DC coupling element, plasma in a plasma processing chamber, and a reference potential node.

[0133] Example 33. The method according to Example 32, wherein the RC time constant is at least twice the reciprocal of the DC pulse frequency.

[0134] Example 34. The method according to Example 33, wherein the DC pulse frequency is less than approximately 400 kHz.

[0135] Example 35. The method according to Example 34, wherein the DC pulse frequency is less than approximately 20 kHz.

[0136] While the present invention has been described with reference to exemplary embodiments, this specification is not intended to be constrained. Those skilled in the art will find various modifications and combinations of those exemplary embodiments, as well as other embodiments of the present invention, readily apparent by reference to this specification. Therefore, the appended claims are intended to encompass all such modifications or embodiments.

Claims

1. A plasma processing apparatus, Plasma processing chamber and A source power (SP) coupling element is configured to generate plasma inside the plasma processing chamber by coupling source power to the plasma processing chamber, A DC pulse generator configured to generate a DC pulse train at a direct current (DC) pulse frequency, A substrate holder disposed inside the plasma processing chamber, A DC coupling element coupled to the DC pulse generator, A DC current path comprising the DC coupling element, the plasma, and a reference potential node in series configuration, wherein the DC coupling element is configured to bias the substrate holder with respect to the reference potential node using the DC pulse train, A capacitive pre-coat layer disposed between the DC coupling element and the plasma, the capacitive pre-coat layer which increases the RC time constant of the DC current path according to the DC pulse frequency, An adjustment circuit coupled between the DC coupling element and the DC pulse generator, the adjustment circuit including a variable capacitance A plasma processing device, including a plasma treatment device.

2. The plasma processing chamber further comprises a resistant pre-coat layer disposed on the inner surface, The reference potential node is coupled to the plasma processing chamber. The resistive pre-coat layer is placed between the plasma and the reference potential node. The resistive pre-coat layer further increases the RC time constant of the DC current path according to the DC pulse frequency. The plasma processing apparatus according to claim 1.

3. The DC coupling element is positioned above the substrate holder, The reference potential node is coupled to the substrate holder. The plasma processing apparatus according to claim 1.

4. A plasma processing apparatus, Plasma processing chamber and A source power (SP) coupling element is configured to generate plasma inside the plasma processing chamber by coupling source power to the plasma processing chamber, A DC pulse generator configured to generate a DC pulse train including a DC pulse frequency, A substrate holder disposed inside the plasma processing chamber, A DC coupling element coupled to the DC pulse generator, A DC current path comprising the DC coupling element, the plasma, and a reference potential node in series configuration, wherein the DC coupling element is configured to bias the substrate holder with respect to the reference potential node using the DC pulse train, A control circuit coupled between the DC coupling element and the DC pulse generator, wherein the control circuit is equipped with a variable capacitance and is configured to adjust the RC time constant of the DC current path by changing the variable capacitance according to the DC pulse frequency, A plasma processing apparatus equipped with the following features.

5. The adjustment circuit, Multiple capacitors, A first single-pole switch having an input coupled to either the DC coupling element or the DC pulse generator and a first output coupled to a first subset of the plurality of capacitors, The plasma processing apparatus according to claim 4, comprising:

6. The adjustment circuit, The system further comprises a second single-pole switch having an input coupled to the DC pulse generator and an output coupled to the first subset of the plurality of capacitors, wherein the first single-pole switch is coupled to the DC coupling element. The plasma processing apparatus according to claim 5.

7. The plasma processing apparatus according to claim 5, wherein the plurality of capacitors comprises a bank of a plurality of capacitors connected in parallel with one another.

8. The plasma processing apparatus according to claim 5, wherein the first single-pole switch is a multi-throw switch having a second output coupled to a second subset of the plurality of capacitors.

9. The first single-pole switch is a single-throw switch, The adjustment circuit further comprises a second single-pole single-throw switch having an input coupled to the input of the first single-pole single-throw switch and an output coupled to a second subset of the plurality of capacitors. The plasma processing apparatus according to claim 5.

10. The plasma processing apparatus according to claim 5, wherein the plurality of capacitors comprises a plurality of fixed capacitors.

11. The plasma processing apparatus according to claim 5, wherein the first single-pole switch has a second output coupled to either the DC pulse generator or the DC coupling element, and as a result a short circuit is formed between the DC coupling element and the DC pulse generator when the second output is selected.

12. The plasma processing chamber further comprises a resistant pre-coat layer disposed on the inner surface, The reference potential node is coupled to the plasma processing chamber. The resistive pre-coat layer is placed between the plasma and the reference potential node. The resistive pre-coat layer further increases the RC time constant of the DC current path according to the DC pulse frequency. The plasma processing apparatus according to claim 4.

13. A capacitive precoat layer disposed between the DC coupling element and the plasma, wherein the capacitive precoat layer increases the RC time constant of the DC current path according to the DC pulse frequency. The plasma processing apparatus according to claim 12, further comprising the following:

14. A method for adjusting the electrical characteristics of a plasma processing chamber of a plasma processing apparatus, The capacitance value is determined from a range of capacitance values ​​according to the DC pulse frequency of the DC pulse train generated by the DC pulse generator of the plasma processing apparatus, The electrical characteristics are adjusted by selecting the determined capacitance value using an adjustment circuit coupled between a DC coupling element and the DC pulse generator, wherein the adjustment circuit comprises a variable capacitance adjustable within the range of capacitance values. By generating the DC pulse train at the DC pulse frequency using the DC pulse generator, the DC coupling element is biased with respect to the reference potential node. A method that includes this.

15. Before biasing the DC coupling element, source power is applied to the plasma processing chamber to generate plasma within the plasma processing chamber. It further includes, Biasing the DC coupling element includes biasing the DC coupling element in the afterglow of the plasma after the source power has been removed. The method according to claim 14.

16. The method according to claim 14, wherein biasing the DC coupling element includes negatively biasing the substrate holder in the plasma processing chamber with respect to the reference potential node by generating the DC pulse train at the DC pulse frequency using the DC pulse generator.

17. The method according to claim 14, wherein the electrical characteristics include the RC time constant of the DC current path including the DC coupling element, the plasma in the plasma processing chamber, and the reference potential node.

18. The method according to claim 17, wherein the RC time constant is at least twice the reciprocal of the DC pulse frequency.

19. The method according to claim 18, wherein the DC pulse frequency is less than approximately 400 kHz.

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