Memory devices and systems, and decoding circuits

Abstract

Examples of the present application provide a memory device and system, and a decoding circuit, wherein the memory device includes a memory cell array and peripheral circuitry coupled to the memory cell array, the memory cell array including at least one block, the block having a plurality of rows of word lines, a plurality of columns of bit lines, and memory cells coupled between the word lines and the bit lines, the peripheral circuitry including a column decoding circuit coupled to the plurality of columns of bit lines and configured to receive column address signals, perform multi-stage decoding on the column address signals, and output column select signals indicating enabling of respective bit lines of the block.

Description

Technical Field

[0001] Examples of the present application relate to the technical field of semiconductors, and in particular, to memory devices and systems, as well as decoding circuits.

Background Art

[0002] Memory devices and their systems are storage devices for storing information in modern information technology. As the requirements for storage devices are increasing further, there is still room for improvement in memory devices and their systems.

Summary of the Invention

[0003] Examples of the present application provide a memory device and a decoding circuit, as well as a memory device and a system.

[0004] In a first aspect, an example of the present application provides a memory device including a memory cell array and a peripheral circuit coupled to the memory cell array, The memory cell array includes at least one block, and the block includes a plurality of rows of word lines, a plurality of columns of bit lines, and memory cells coupled between the word lines and the bit lines, The peripheral circuit includes a column decoding circuit, and the column decoding circuit is coupled to a plurality of columns of bit lines, receives a column address signal, performs multi-stage decoding on the column address signal, and outputs a column selection signal indicating enabling each bit line of the block.

[0005] In some examples, the column decoding circuit is a first-stage column decoding circuit including a first input interface and a first output interface, the first input interface receives at least a column address signal, the first output interface outputs a preliminary column decoding signal, and the number of transmission lines corresponding to the column address signal is less than the number of transmission lines corresponding to the preliminary column decoding signal, the first-stage column decoding circuit; A second-stage column decoding circuit comprising a second input interface and a second output interface, wherein the second input interface is coupled to a first-stage column decoding circuit and receives a preliminary column decoding signal, and the second output interface is coupled to a plurality of bit lines of a block and outputs a column decoding signal indicating that one of the plurality of bit lines of a block is enabled, and the number of transmission lines corresponding to the preliminary column decoding signal is less than the number of transmission lines corresponding to the column decoding signal.

[0006] In some examples, a memory cell array includes multiple banks, each containing blocks of several rows and blocks of several columns. Each bank corresponds to multiple first-stage column decoding circuits and multiple second-stage column decoding circuits, each first-stage column decoding circuit corresponds to one column block, and each second-stage column decoding circuit corresponds to one block within one column block. Each second input interface of the second-stage column decoding circuit is coupled to the first-stage column decoding circuit, and the second output interface is coupled to multiple bit lines of one of the blocks, with the column decoding signal indicating that each bit line of the selected block is enabled.

[0007] In some examples, the column address signal contains multiple bits of data, and the first stage of the column decoding circuit is: A first decoding circuit configured to perform decoding on a plurality of consecutive lower bits of a column address signal in order to obtain a first decoded signal, The second decoding circuit is configured to perform a decoding operation on the remaining multiple consecutive high-order bits of the column address signal in order to obtain a second decoded signal, wherein the first decoded signal and the second decoded signal are configured to together form a preliminary column decoded signal.

[0008] In some examples, the first-stage column decoding circuit further includes a synchronization control signal generation circuit configured to generate a synchronization control signal corresponding to a clock period shorter than the clock period corresponding to the first and second decoding signals. The second input interface of the second-stage column decoding circuit further receives a synchronization control signal, and the second-stage column decoding circuit is configured to output a column decoding signal in response to the enable state of the synchronization control signal and the normal outputs of the first and second decoding signals.

[0009] In some examples, the second-stage column decoding circuit receives a synchronization control signal and a semiconductor element enable signal, and when both the synchronization control signal and the block enable signal are enabled, it outputs a column decoding signal to enable the bit lines of the selected block corresponding to the enabled data bits of the preliminary column decoding signal, and the fact that the block enable signal is enabled indicates that a block is selected.

[0010] In some examples, the first-stage column decoding circuit further comprises a drive circuit including multiple drivers. Each driver is connected to one of several transmission lines corresponding to the first decoded signal and the second decoded signal, respectively, and is configured to perform power amplification processing on the decoded signal of the respective transmission line.

[0011] In some examples, a block contains a first region and a second region, and the number of bit lines placed in the first and second regions is the same. The first stage column decoding circuit further comprises a third decoding circuit, a first region selection circuit, and a second region selection circuit. The third decoding circuit is configured to perform decoding on the remaining multiple consecutive high-order bits of the column address signal in order to obtain the third decoded signal, wherein the third decoded signal and the second decoded signal are the same. The first region selection circuit is connected to the second decoding circuit and is configured to output the second decoding signal when the first region enable signal is enabled. The second region selection circuit is connected to the third decoding circuit and is configured to output the third decoding signal when the second region enable signal is enabled, and the presence of the first region enable signal / second region enable signal indicates that the first region / second region of the block is selected.

[0012] In some examples, the first-stage column decoding circuit further includes a buffer. The buffer is connected to the first decoding circuit and is configured to perform timing adjustments to the first decoding signal in order to synchronize with the output signals of both the first and second region selection circuits.

[0013] In some examples, the column address signal is 6 bits of binary data, the pre-column decoded signal corresponds to 24 transmission lines, the first region of the block contains 64 bit lines, and the second region of the block contains 64 bit lines.

[0014] In some examples, memory comprises multiple address transmission lines and multiple data transmission lines. The first-stage column decoding circuit, corresponding to one row of blocks, is connected to the second-stage column decoding circuit, corresponding to each block in the row, via multiple address transmission lines. Each block in a row is connected to a data transmission line. Multiple address transmission lines and multiple data transmission lines are located on the same metal layer.

[0015] In some examples, the memory cell array is arranged in a first semiconductor structure, the peripheral circuits are arranged in a second semiconductor structure, and the first and second semiconductor structures are stacked and electrically connected by junctions. Each of the column decoding circuits in the first stage is positioned on the side of each column of the block. Each of the second-stage column decoding circuits is positioned at the orthogonal projection position of each block in the plane where the second semiconductor structure is located, along with the sense amplifier and word line driver corresponding to each block.

[0016] In some examples, the memory device includes dynamic random access memory.

[0017] In a second aspect, the example of this application includes the memory device described in the above solution, A memory system is provided that includes a memory device and a memory controller that is coupled to the memory device and controls the memory device.

[0018] In a second aspect, an example of the present application is a decoding circuit, A first-stage decoding circuit comprising a first input interface and a first output interface, wherein the first input interface receives at least the signal to be decoded, the first output interface outputs a preliminary decoding signal, and the number of transmission lines corresponding to the signal to be decoded is less than the number of transmission lines corresponding to the preliminary decoding signal; A decoding circuit is provided comprising a second stage decoding circuit having a second input interface and a second output interface, wherein the second input interface is coupled with a first stage decoding circuit to receive a preliminary decoded signal, and the second output interface is coupled with a plurality of structures selected in a semiconductor device to output a decoding signal indicating that one structure selected in the semiconductor device is enabled, and the number of transmission lines corresponding to the preliminary decoded signal is less than the number of transmission lines corresponding to the decoding signal.

[0019] In some examples, there are multiple second-stage decoding circuits, each corresponding to a single semiconductor element. Each second input interface of the decoding circuit of the second stage is coupled to the decoding circuit of the first stage, the second output interface is coupled to a plurality of structures to be decoded of one semiconductor element, and the decoding signal indicates to enable each structure of the selected semiconductor element to be decoded.

[0020] In some examples, the signal to be decoded includes multi-bit data, and the decoding circuit of the first stage includes a first decoding circuit configured to perform a decoding process on a plurality of consecutive lower-bit data of the signal to be decoded to obtain a first decoding signal, and a second decoding circuit configured to perform a decoding process on the remaining plurality of consecutive upper-bit data of the signal to be decoded to obtain a second decoding signal, wherein the first decoding signal and the second decoding signal are configured to form a preliminary decoding signal together.

[0021] In some examples, the decoding circuit of the first stage further includes a synchronization control signal generation circuit configured to generate a synchronization control signal corresponding to a clock period shorter than the clock periods corresponding to the first decoding signal and the second decoding signal, the second input interface of the decoding circuit of the second stage further receives the synchronization control signal, and the decoding circuit of the second stage is configured to output a decoding signal in response to the enabled state of the synchronization control signal and the normal outputs of the first decoding signal and the second decoding signal.

[0022] In some examples, the decoding circuit of the second stage receives a synchronization control signal and a semiconductor element enable signal, and outputs a decoding signal to enable a structure to be selected in the selected semiconductor element corresponding to the enabled data bits of the preliminary decoding signal when both the synchronization control signal and the semiconductor element enable signal are enabled. The enabling of the semiconductor element enable signal indicates that the semiconductor element is selected.

[0023] In some examples, the first-stage decoding circuit further includes a drive circuit containing multiple drivers. Each driver is connected to one of several transmission lines corresponding to the first decoded signal and the second decoded signal, respectively, and is configured to perform power amplification processing on the decoded signal of the respective transmission line.

[0024] In some examples, the first-stage decoding circuit further comprises a third decoding circuit, a first region selection circuit, and a second region selection circuit. The third decoding circuit is configured to perform decoding on the remaining multiple consecutive higher bits of the signal to be decoded in order to obtain the third decoded signal, wherein the third decoded signal and the second decoded signal are the same. The first region selection circuit is connected to the second decoding circuit and is configured to output the second decoding signal when the first region enable signal is enabled. The second region selection circuit is connected to the third decoding circuit and is configured to output the third decoding signal when the second region enable signal is enabled. The fact that the first region enable signal / second region enable signal is enabled indicates that the first region / second region of the semiconductor element is selected.

[0025] In some examples, the first-stage decoding circuit further includes a buffer. The buffer is connected to the first decoding circuit and is configured to perform timing adjustments to the first decoding signal in order to synchronize with the output signals of both the first and second region selection circuits.

[0026] In some examples, the first region selection circuit / second region selection circuit comprises a first NAND gate and a second NAND gate, The input terminal of the first NAND gate is connected to the output of the second / third decoding circuit, and the other input terminal is configured to receive the partition enable signal. The presence of the partition enable signal indicates that the semiconductor element is assisting in partition selection. The input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, the other input terminal is configured to receive the first region enable signal / second region enable signal, and the output terminal is connected to the first output interface.

[0027] In some examples, the signal to be decoded comprises a column address signal, the transmission line comprises an address transmission line, the semiconductor element comprises a block, the selected multiple structures comprises multiple bit lines, and the decoded signal indicates one of the selected multiple bit lines. [Brief explanation of the drawing]

[0028] In the drawings, unless otherwise specified, similar reference numerals used throughout multiple drawings refer to the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings illustrate only some embodiments of this application and should not be considered as limitations on the scope of this application. [Figure 1] This is a block diagram showing the configuration of a typical electronic device as an example of this application. [Figure 2A] This is a block diagram of a typical solid-state drive (SSD) or universal flash storage (UFS) configuration as an example of this application. [Figure 2B] This is a block diagram of a typical internal memory configuration for the example in this application. [Figure 3] This is a schematic diagram of a typical dynamic random access memory configuration example of the present application. [Figure 4] This is a schematic diagram of the word lines, bit lines, and memory cell connections of a typical dynamic random access memory example of this application. [Figure 5A]This is a schematic distribution diagram of the memory cell array and peripheral circuits in a typical memory device of the present application. [Figure 5B] This is a top view of the distribution of memory cell arrays and peripheral circuits in a typical memory device of the present application. [Figure 5C] This is a top view of the distribution of block and column decoding circuits in a typical bank of examples of this application. [Figure 6A] This is a top view of the distribution of block and column decoding circuits in a typical bank of another example of this application. [Figure 6B] This is a top view of the distribution of block and column decoding circuits in a typical bank of yet another example of this application. [Figure 7A] This is a schematic diagram of the distribution of memory cell arrays and peripheral circuits in a typical memory device of another example of this application. [Figure 7B] This is a top view of the distribution of memory cell arrays and peripheral circuits in a typical memory device of another example of this application. [Figure 8A] This is a block diagram of a typical column decoding circuit configuration for the example of this application. [Figure 8B] This is a schematic diagram of a typical implementation circuit of a typical column decoding circuit as an example of this application. [Figure 8C] This is a schematic diagram of the voltage timing of some signals in a typical column decoding circuit of the present application. [Figure 9A] This is a block diagram of a typical column decoding circuit configuration for another example of this application. [Figure 9B] This is a schematic diagram of a typical implementation circuit of a typical column decoding circuit, another example of this application. [Modes for carrying out the invention]

[0029] Typical embodiments of this application are described in detail below with reference to the drawings. While the drawings illustrate typical embodiments of this application, it should be understood that this application can be implemented in any form not limited to the typical embodiments described herein. Rather, these implementations are provided for a more thorough understanding of this application and can fully convey its scope to those skilled in the art.

[0030] The following description presents many typical details to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application may be carried out without one or more of these details. In other examples, some technical features well known in the art are not described in order to avoid confusion with this application. That is, not all features of the actual examples are described herein, and well known functions and structures are not described in detail.

[0031] In the drawings, the sizes and relative sizes of layers, areas, and elements may be exaggerated for clarity. Similar reference numbers indicate similar elements throughout.

[0032] Where an element or layer is referred to as "on top of," "adjacent to," "connected to," or "combined with" another element or layer, it should be understood that it may be directly on top of, adjacent to, connected to, or combined with the other element or layer, or that one or more intervening elements or layers may exist. In contrast, where an element is referred to as "directly on top of," "directly adjacent to," "directly connected to," or "directly combined with" another element or layer, there are no intervening elements or layers. Terms such as first, second, and third may be used to describe various elements, components, regions, layers and / or parts, but it should be understood that these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, the first element, component, region, layer or part described below may be represented as the second element, component, region, layer or part without departing from the teachings of this application. When a second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in this application.

[0033] Spatially relative terms such as “beneath,” “below,” “lower,” “under,” “over,” and “upper” may be used herein to facilitate descriptions of the relationship between one element or feature and another, as shown in the figures. It should be understood that spatially relative terms are intended to further encompass various orientations of a device in use or operation, in addition to the orientations shown in the figures. For example, if a device in a drawing is inverted, an element or feature described as “below,” “under,” or “beneath” will be oriented to be “above” the other element or feature. Therefore, typical terms like “below” and “beneath” can include both up and down orientations. A device may be oriented in other directions (it may be rotated 90 degrees or in other directions), and the spatially descriptive terms used herein will be interpreted on a case-by-case basis.

[0034] The terms used herein are intended solely for illustrative purposes and are not intended to limit this application. Where used herein, unless otherwise specified in the context, the singular forms “a,” “one,” and “the” are also intended to include the plural forms. Where used herein, the terms “consist of” and / or “comprise” determine the presence of features, integers, steps, actions, elements, and / or components, but should not be understood as excluding the presence or addition of one or more other features, integers, steps, actions, elements, components, and / or groups. Where used herein, the terms “and / or” include any combination of the enumerated related items. The units of transmission line “stick,” “strip,” and “piece” are synonymous.

[0035] To provide a more detailed understanding of the features and technical content of the examples of this application, embodiments of the examples of this application will be described in detail later with reference to the drawings, and the accompanying drawings are used for reference and illustrative purposes only, and not to limit the examples of this application.

[0036] Figure 1 shows a block diagram of a typical electronic device configuration according to an example of the present application. Electronic device 1 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, pointing device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having internal storage. As shown in Figure 1, electronic device 1 may comprise a host HOST and a memory system 30, the memory system 30 comprising a memory controller 10 and one or more memory devices 20. The host HOST may be the processor of the electronic device (e.g., a central processing unit (CPU)) or a graphics processing unit (GPU). The host HOST may be configured to send and receive data to and from the memory devices 20. The memory controller 10 is coupled to the memory devices 20 and the host HOST and is configured to control the memory devices 20. The memory controller 10 can manage the data stored in the memory devices 20 and communicate with the host HOST.

[0037] The memory controller 10 can be configured to control the operation of the memory device 20, such as read, erase, write, and refresh operations. In some embodiments, the memory controller 10 is further configured to process error correction codes (ECC) with respect to data read from and written to the memory device 20. The memory controller 10 can further perform any other suitable functions, such as formatting the memory device 20.

[0038] In some examples, the memory controller 10 and one or more memory devices 20 can all be integrated into various types of electronic devices. For example, the memory controller 10 may be integrated into the northbridge of a computer motherboard or directly into a computer CPU, and the multiple memory devices 20 may be integrated into a memory bar. In other words, the memory system 30 can be implemented and packaged into different types of final electronic products.

[0039] The memory controller 10 can send and receive data to and from the host HOST, and can send a command CMD and address ADDR to the memory device 20. The memory controller 10 may include a command generator 110, an address generator 120, a device interface 130, and a host interface 140. The host interface 140 can receive a command CMD and address ADDR from the host HOST, and the command generator 110 can generate access commands and raw hammer refresh commands by decoding the command CMD received from the host HOST, and can provide the access commands and raw hammer refresh commands to the memory device 20 via the device interface 130. An access command may be a signal instructing the memory device 20 to access a row in the memory cell array 220 corresponding to address ADDR and write or read data. A raw hammer refresh command may be a signal instructing the memory device 20 to perform an additional refresh operation on a word line adjacent to a word line that is frequently accessed in a short period of time. In other words, an additional refresh operation may be performed on a word line adjacent to a word line that is accessed multiple times in a short period of time.

[0040] The address generator 120 of the memory controller 10 can generate the addresses of the rows and columns of the memory cell array 220 to be accessed by decoding the address ADDR received from the host interface 140. Furthermore, the memory device 20 can generate the addresses of the banks to be accessed if the memory cell array 220 includes multiple banks.

[0041] Furthermore, the memory controller 10 can control memory operations such as writing and reading by providing various signals to the memory device 20 via the device interface 130. For example, the memory controller 10 can provide a write command to the memory device 20. A write command is used to instruct the memory device 20 to perform a write operation to save data to the memory device 20.

[0042] In some examples, the memory device 20 comprises a memory cell array 220 and peripheral circuits 210, the memory cell array 220 comprising multiple banks, each bank comprising multiple blocks, each block comprising rows of multiple memory cells and columns of multiple memory cells, each row of memory cells being coupled to a corresponding word line, and each column of memory cells being coupled to a corresponding bit line. The peripheral circuits 210 can write or read data to or from the memory cell array 220 based on a command CMD and address ADDR received from the memory controller 10, and can provide a control signal CTRL for refreshing the memory cells contained in the memory cell array 220 to the row and column decoding circuits. In other words, the peripheral circuits 210 can perform all operations for processing the data of the memory cell array 220. The peripheral circuits 210 may comprise control circuits corresponding to each block, such as a sensing amplifier (SA) and a word line driver (WLD), control circuits corresponding to each bank, such as a row and column decoding circuit, and control circuits corresponding to all banks, such as a command buffer, a command decoder, an address buffer, a data input / output buffer, and a mode register.

[0043] The memory device 20 may be a random access memory (RAM) such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), double data rate SDRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, phase-change RAM (PRAM), magnetic RAM (MRAM), and resistive RAM (RRAM). In the following description, only DRAM will be used as an example.

[0044] Figure 2A is a block diagram of a typical SSD / UFS configuration of an example of this application. Here, the SSD / UFS can be understood as one of the memory systems shown in Figure 1, in which case DRAM may be used as buffer memory.

[0045] As shown in Figure 2A, the SSD / UFS 30' may comprise an SSD / UFS controller 10', a buffer memory 20', and a non-volatile memory 40. The SSD / UFS controller 10' may provide a physical connection between the host HOST and the SSD / UFS 30'. That is, the SSD / UFS controller 10' can provide an interface between the host HOST and the SSD / UFS 30' according to the host's bus format. The SSD controller 10' can decode instructions given by the host HOST. The SSD / UFS controller 10' can access the non-volatile memory 40 based on the decoded result. The buffer memory 20' can temporarily store write data given by the host HOST or data read from the non-volatile memory 40. When the host HOST issues a read request, if data residing in the non-volatile memory 40 is cached, the buffer memory 20' can assist the caching function by directly providing the cached data to the host HOST. The data transfer speed via the host's bus format (e.g., SATA or SAS) is much faster than the data transfer speed of the SSD / UFS30' memory channels. That is, if the host interface speed is significantly faster, the performance degradation due to the speed difference can be minimized by providing a large-capacity buffer memory 20'. Furthermore, the buffer memory 20' can store the address mapping table for the non-volatile memory 40. The buffer memory 20' may include, but is not limited to, DRAM. The non-volatile memory 40 can be configured as the storage medium for the SSD / UFS30'. The non-volatile memory 40 may include, but is not limited to, NAND memory.

[0046] Figure 2B is a block diagram of a typical internal memory configuration in the example of this application. Here, the internal memory can be understood as one of the memory systems in Figure 1, and in this example, DRAM can be used as the storage medium.

[0047] As shown in Figure 2B, the internal memory 30” is easily installable, fitted, or detachable from the electronic device 1 via the illustrated interface. The internal memory 30” may comprise multiple volatile memories 20” (e.g., DRAM) and an internal memory controller 10”. The memory module memory 30” can be used to write, store, retrieve (or read) data, and / or erase data under the control of a computer processor. In some examples, the memory controller 10” can communicate with the DRAM using at least one communication protocol or technical standard commonly associated with, for example, dual inline internal memory (DIMM), registered DIMM (RDIMM), load reduction DIMM (LRDIMM), and unregistered DIMM (UDIMM).

[0048] The buffer memory 20' in Figure 2A and the volatile memory 20'' in Figure 2B are application scenarios for the memory device 20 in Figure 1, respectively, and it should be noted that they may also be applicable to other application scenarios not limited to those shown here.

[0049] Figure 3 is a schematic diagram of the typical configuration of a dynamic random access memory example of this application. Figure 4 is a schematic diagram of the connection relationships between bit lines, word lines, and memory cells of a typical dynamic random access memory example of this application.

[0050] Figure 3 shows the circuitry of a DRAM memory cell on the right. The DRAM comprises at least one DRAM die, each DRAM die comprising a memory cell array, the memory cell array comprising a plurality of memory cells 201 arranged in an array, each memory cell 201 comprising one transistor T and one capacitor C. The main functional principle of a memory cell is to represent a binary bit as l or 0 using a certain amount of charge stored in the capacitor. The memory cells are arranged in an array, and the array can be considered a typical mesh structure, for which Figure 4 can be seen in detail. The memory cell array is addressed using rows and columns. By specifying the intersections of rows and columns (specifying the row and column addresses of the DRAM), the memory controller can independently access each memory cell on the DRAM die and perform read, write, or refresh operations on the data stored in the memory cells.

[0051] Figure 3 shows a portion of the DRAM memory cell array and peripheral circuitry on the left. Note that the row decoder selects word lines so that it can select the row of memory cell to access, depending on the address input to the row decoder. The row decoder decodes the input address and activates the word line corresponding to the decoded address. The column decoder selects one or more bit lines to input user output data into the portion of the memory cell row corresponding to the selected word line.

[0052] Figure 5A is a distribution diagram of the memory cell array and peripheral circuits in a typical memory device of the present application. Figure 5B is a top view of the distribution of the memory cell array and peripheral circuits in a typical memory device of the present application. Figure 5C is a top view of the distribution of block and column decoding circuits in a typical bank of the present application.

[0053] As shown in Figure 5A, the memory cell array 220 and the peripheral circuitry 210 are arranged side by side. In this example, the memory cell array has M banks, each bank has N blocks, the control circuit corresponding to each block is located on at least one side of the block, and the control circuit corresponding to each bank is located on at least one side of the bank. Each of the K banks in the M banks forms a row of banks, the M banks form a row of M / K banks, and the peripheral circuitry corresponding to all banks is located between two rows of intermediate banks. Note that M, N, and K are all positive integers, and M is an integer multiple of K.

[0054] In the example, as shown in Figure 5B, the memory cell array 220 comprises 16 banks, Bank0 to Bank15, each bank comprising multiple blocks, with SAs and WLDs corresponding to each block arranged opposite each other around the block, and column and row decoding circuits corresponding to each bank arranged on two sides of the bank. Four banks each constitute a bank column, the 16 banks constitute four bank columns, and control circuits corresponding to all banks are located between the two intermediate bank columns. It should be noted that the number of banks and the positional relationship of the circuits in Figure 5B are used as examples only and are not used to limit the number of banks and the positional relationship of the circuits in the memory of this application.

[0055] As shown in Figure 5C, each bank contains multiple row blocks and multiple column blocks, with each column of a block corresponding to one column decoding circuit (corresponding to YDEC in Figure 5C), which is configured to receive a column address signal, perform direct or one-step decoding on the column address signal, and output a column selection signal indicating that each bit line of the selected block is enabled. The column decoding circuits are located on the side of each column of the block and are connected to each block of each column via column address transmission lines. For example, if one column contains multiple blocks, each of which is selected collectively and contains 64 bit lines, then the column decoding circuits need to be connected to the 64 bit lines of each block of each column, each via 64 column address transmission lines. If a column contains multiple blocks, each selected by subblocks (e.g., left and right blocks), and each subblock contains 64 bit lines, then the column decoding circuit needs to be connected to the 64 bit lines of the left and right blocks of each block in each column via 128 column address transmission lines (Y128:0> in Figure 5C represents the case of 128 column address lines). Here, the column address transmission lines are also called long-span address transmission lines because they extend across the entire column of blocks in a long-span domain.

[0056] On the other hand, as shown in Figure 5C, each block in a column and the data must be similarly connected via data transmission lines, where each block in the column and the data are connected via data transmission line pairs DL<31:0> / DL_n<31:0>, i.e., 64 data transmission lines. In the current case of increasingly high storage density requirements, it will be understood that the area of ​​the memory cell array is relatively small, and the area of ​​each column in a block is also very small. As shown in Figure 5C, where 128 column address transmission lines and 64 data transmission lines must be connected to each column in a block, when it is required to connect a large number of address transmission lines and data transmission lines to each column in a block, it is very difficult to place the column address transmission lines and data transmission lines on the same metal layer (or wiring layer) considering the need to place structures to prevent crosstalk between transmission lines. For example, the column address transmission lines are placed on the fourth metal layer, while the data transmission lines are placed on the fifth metal layer (solid and dashed lines are used in Figure 5C to show that the column address transmission lines and data transmission lines are not on the same metal layer). If column address transmission lines and data transmission lines are not located on the same metal layer, delay mismatches and significant discrepancies can occur between column address signals and data signals under process voltage temperature (PVT). In some cases, trim bits such as compensation circuits may be added for improvement, but mismatches between circuit and wiring delays still exist.

[0057] Based on this, in various examples of this application, the column decoding circuit is improved from a single-stage decoding to a multi-stage decoding to reduce the total number of column address transmission lines, and area savings are achieved by a rational arrangement of the positions of the various stages of decoders.

[0058] An example of this application provides a memory device including a memory cell array and peripheral circuits coupled to the memory cell array. The memory cell array includes at least one block, the block comprising multiple rows of word lines, multiple columns of bit lines, and memory cells coupled between the word lines and bit lines. The peripheral circuitry includes a column decoding circuit, which is coupled with the bit lines of multiple columns, receives a column address signal, performs multi-stage decoding on the column address signal, and outputs a column selection signal indicating that each bit line of a block is enabled.

[0059] Here, the memory device can be understood by referring to the memory device shown in Figure 1, and in some examples, memory device 20 is a dynamic random access memory. All the following explanations will be based on memory device 20, which is a DRAM, as an example. The typical compositional structure of a DRAM can be understood by referring to the compositional structure of the DRAM shown in Figure 3.

[0060] In some embodiments, a column decoder (also known as a column decoder) is coupled to the bit lines of a memory cell array via a sense amplifier (also known as a sense amplifier). The column decoder may comprise a multi-stage decoder that accomplishes the task of decoding the column address signals together, i.e., instructing each bit line of a block to be enabled. The multi-stage decoder may include two, three, or more stages. In some examples, the column decoder comprises a two-stage decoder.

[0061] It will be understood that a two-stage decoding circuit can function to reduce the number of column address transmission lines without adding excessive circuitry that would incur the burden of an excessive increase in area.

[0062] In some examples, the column decoding circuit is a first-stage column decoding circuit having a first input interface and a first output interface, wherein the first input interface receives at least a column address signal, the first output interface outputs a preliminary column decoding signal, and the number of transmission lines corresponding to the column address signal is less than the number of transmission lines corresponding to the preliminary column decoding signal. A second-stage column decoding circuit comprising a second input interface and a second output interface, wherein the second input interface is coupled to a first-stage column decoding circuit and receives a preliminary column decoding signal, and the second output interface is coupled to a plurality of bit lines of a block and outputs a column decoding signal indicating that one of the plurality of bit lines of a block is enabled, and the number of transmission lines corresponding to the preliminary column decoding signal is less than the number of transmission lines corresponding to the column decoding signal.

[0063] Here, the first-stage and second-stage column decoding circuits are cascaded in series, the first output interface of the first-stage column decoding circuit is coupled to the second input interface of the second-stage column decoding circuit, and the second output interface of the second-stage column decoding circuit is coupled to multiple bit lines of the block. Each column of blocks in each bank of the memory device corresponds to one column decoding circuit, each column decoding circuit comprises one first-stage decoding circuit and one or more second-stage column decoding circuits. In some examples, the number of second-stage column decoding circuits included in each column decoding circuit is the same as the number of blocks included in one column of blocks in the bank. In the example, the number of blocks included in one column of blocks in the bank is 64, and the number of second-stage column decoding circuits included in each column decoding circuit is also 64, with each second-stage column decoding circuit corresponding one-to-one with a block in one column of blocks.

[0064] In some examples, a memory cell array includes multiple banks, each containing blocks of several rows and blocks of several columns. Each bank corresponds to multiple first-stage column decoding circuits and multiple second-stage column decoding circuits, each first-stage column decoding circuit corresponds to one column block, and each second-stage column decoding circuit corresponds to one block within one column block. Each second input interface of the second-stage column decoding circuit is coupled to the first-stage column decoding circuit, and the second output interface is coupled to multiple bit lines of one of the blocks, with the column decoding signal indicating that each bit line of the selected block is enabled.

[0065] Here, the first output interface of the first-stage column decoding circuit must be coupled to the second input interface of all the second-stage column decoding circuits, and the second-stage column decoding circuits are arranged in accordance with the blocks located next to them. Thus, the first address transmission line between the first output interface of the first-stage column decoding circuit and the second input interface of all the second-stage column decoding circuits extends across the entire column of the block, and the long-span region has a length similar to the long column address transmission line described above.

[0066] Note that the number of first address transmission lines is required to represent each bit line entering a block. If the number of bit lines in each block is M, and the address signal of each address transmission line can be a high logic level "1" or a low logic level "0", then from 2N=M, we can see that M bit lines can be represented by at least N address transmission lines, where M and N are both positive integers. For example, if each block is selected as a whole and contains 64 bit lines, the number of first address transmission lines is 16. If each block is selected by subblocks (e.g., left and right blocks), and each subblock contains 64 bit lines, the number of first address transmission lines is 24. In this example, compared to the above cases of 64 or 128 long column address transmission lines, the number of lines is significantly reduced in the cases of 16 or 24 first address transmission lines, which is advantageous for reducing area, so that the column address transmission lines and data transmission lines corresponding to one column of blocks are all laid out on the same metal layer.

[0067] Here, since the second output interface of the second-stage column decoder must be coupled to all the bit lines of a block, the number of second address transmission lines between the second output interface of each second-stage column decoder and each bit line of a block is related to the number of bit lines in each block. For example, if each block is selected collectively and contains 64 bit lines, the number of second address transmission lines is 64. If each block is selected by subblocks (e.g., left and right blocks) and each subblock contains 64 bit lines, the number of second address transmission lines is 128.

[0068] Since the second-stage column decoding circuit is positioned in relation to the block adjacent to the second-stage column decoding circuit, the second address transmission line is not very long, and it should be noted that this second address transmission line does not belong to the same concept as the long address transmission line described above.

[0069] In some examples, the column decoding circuit of each first stage is located on the side of each column of the block. The column decoding circuit of the first stage may be located on the side of each column of the block, along the direction in which the columns of the block extend.

[0070] The second-stage column decoding circuit must be located near its corresponding block, and the position of the second-stage column decoding circuit can be arranged in various ways, two examples of which are shown below.

[0071] In some examples, as shown in Figure 6A, the first-stage column decoding circuit for each column of a block (corresponding to YDEC_1st in Figure 6A) is located alongside each column of the block. The second-stage column decoding circuit (corresponding to YDEC_2nd in Figure 6A) is located alongside each block, on the side where the block's sense amplifier (SA) is located, to facilitate wiring. For example, considering that SAs can be located on two sides of a single block, as shown in Figure 5B, if the second-stage column decoding circuit is located (this case is not shown in Figure 6A), a design could be considered in which each second-stage column decoding circuit is split into two to align with the SA.

[0072] When the second-stage column decoding circuit is placed alongside each block, the overall structure of the corresponding memory device can be seen by referring to the structure shown above in Figures 5A and 5B.

[0073] In some other examples, as shown in Figure 6B, the first-stage column decoding circuit for each column of a block (corresponding to YDEC_1st in Figure 6B) is located beside each column of the block. The second-stage column decoding circuit (corresponding to YDEC_2nd in Figure 6B) and each block are arranged on top of each other. In the examples, the second-stage column decoding circuit may be located on top of each block, or the blocks may be located on top of each second-stage column decoding circuit.

[0074] Please note that Figures 6A and 6B merely illustrate the relative orientation of each block in the second-stage column decoding circuit and do not limit the typical placement of the second-stage column decoding circuit.

[0075] In some examples, memory comprises multiple address transmission lines and multiple data transmission lines. The first-stage column decoding circuit, corresponding to one row of blocks, is connected to the second-stage column decoding circuit, corresponding to each block in the row, via multiple address transmission lines. Each block in a row of blocks is connected to a data transmission line. Multiple address transmission lines and multiple data transmission lines are located on the same metal layer.

[0076] As described above, the first address transmission line between the first output interface of each first-stage column decoding circuit and the second input interface of all second-stage column decoding circuits is significantly reduced compared to the long column address transmission line described above. As shown in Figure 6A or Figure 6B, the first address transmission line between the first output interface of each first-stage column decoding circuit and the second input interface of all second-stage column decoding circuits is reduced from 128 lines as shown in Figure 5C to 24 lines AY<23:0>, and can be placed on the same metal layer as the 64 data transmission lines DL<31:0> / DL_n<31:0>. In the example, all first address transmission lines and data transmission lines are placed on the fifth metal layer. In Figures 6A and 6B, AY<23:0> and DL<31:0> / DL_n<31:0> are shown with solid lines to indicate that they are both located on the same metal layer. It can be understood that when address transmission lines and data transmission lines are laid out on the same metal layer, the problem of internal block asynchronousness between column address signals and data signals can be improved, and the effects of PVT can be mitigated by adding compensation circuits.

[0077] When arranging the second-stage column decoding circuit and each block in a stacked configuration, it is necessary to adjust the overall structure and layout of the memory device accordingly.

[0078] In some examples, the memory cell array is arranged in a first semiconductor structure, the peripheral circuits are arranged in a second semiconductor structure, and the first and second semiconductor structures are stacked and electrically connected by junctions. Each of the column decoding circuits in the first stage is positioned on the side of each column of the block. Each of the second-stage column decoding circuits is positioned at the orthogonal projection position of each block in the plane where the second semiconductor structure is located, along with the sense amplifier and word line driver corresponding to each block.

[0079] Figure 7A is a schematic diagram of the distribution of memory cell arrays and peripheral circuits in a typical memory of another example of this application. Figure 7B is a top view of the distribution of memory cell arrays and peripheral circuits in a typical memory of another example of this application.

[0080] As shown in Figure 7A, the first semiconductor structure 100 is positioned above the second semiconductor structure 200. The first semiconductor structure 100 includes a memory cell array 220, and the second semiconductor structure 200 includes peripheral circuits 210.

[0081] The first semiconductor structure in Figure 7B, which corresponds to Figure 7A, is located above the second semiconductor structure. Note that in Figure 7B, the solid lines represent structures located in the first semiconductor structure, and the dashed lines represent structures located in the second semiconductor structure. To facilitate understanding, perspective views of the structures in the second semiconductor structure are presented. That is, in the enlarged views corresponding to each block in Figure 7B, the solid lines represent the enlarged portion of the block, and the dashed lines represent the structures in the second semiconductor structure located directly below the block.

[0082] In the example, as shown in Figure 7B, the memory cell array 220 comprises 16 banks, Bank0 to Bank15, each containing multiple blocks. Directly beneath each block are a sense amplifier (SA), a second-stage column decoding circuit YDEC_2nd, and a coupling circuit between the sense amplifier (SA) and the second-stage column decoding circuit YDEC_2nd. The word line driver is located directly beneath the gap between two adjacent blocks along the direction of extension of the block's column. In some examples, the word line driver may comprise an odd word line driver (Odd WLD) and an even word line driver (Even WLD), located on each side of the block, respectively.

[0083] Please note that the positions of the sense amplifier (SA), the second-stage column decoding circuit YDEC_2nd, the coupling circuit Conjunction, the odd word line driver Odd WLD, and the even word line driver Even WLD in Figure 7B are for illustrative purposes only and do not limit the positions of each circuit in the memory of this application.

[0084] In some examples, means for joining the memory cell array 220 to the peripheral circuit 210 include, but are not limited to, hybrid junctions, anode junctions, fusion bonding, transfer junctions, adhesive junctions, and eutectic junctions.

[0085] When the memory device employs a stacked arrangement via bonding, the additional circuits in the example of this application, such as the second-stage address decoding circuit, the SA and WLD-related circuits, etc., can be located beneath the memory cell array. The stacked arrangement does not result in any loss of extra area for the added circuits.

[0086] Typical circuit embodiments of each of the two-stage decoding circuits are described in detail below.

[0087] In some examples, the column address signal contains multiple bits of data, and the first-stage column decoding circuit 231 is: A first decoding circuit 2311 is configured to perform decoding on a plurality of consecutive lower bits of the column address signal in order to obtain a first decoded signal, A second decoding circuit 2312 is configured to perform a decoding process on the remaining multiple consecutive high-order bits of the column address signal in order to obtain a second decoded signal, wherein the first decoded signal and the second decoded signal are configured to together form a preliminary column decoded signal.

[0088] Here, the column address signal is a signal that represents information about the address of a column. In some examples, the column address signal is multi-bit binary data, and the number of bits in the column address signal is related to the number of bit lines contained in the block. If the number of bit lines in each block is M, and the column address signal is N bits of binary data, then 2N = M. In the example, if each block contains 64 bit lines, the column address signal could be 6 bits of binary data.

[0089] Given that the number of bit lines is generally large and one decoding circuit may be insufficient, here the first decoding circuit 2311 and the second decoding circuit 2312 are used to decode different portions of consecutive data bits of the column address signal, and then the two decoded signals combine to form the output of the first stage decoding circuit 231. In the example, the first decoding circuit 2311 and the second decoding circuit 2312 are responsible for decoding the same number of data bits. In the example, as shown in Figure 8A, the column address signal AY_9_4_<9:4> is 6 bits of binary data, the first decoding circuit 2311 decodes the three lower bits AY_9_4_<6:4> of the column address signal, and the second decoding circuit 2312 decodes the three upper bits AY_9_4_<9:7> of the column address signal.

[0090] In some examples, the first decoding circuit 2311 and the second decoding circuit 2312 may each include one or more decoders, such as a 2-to-4 decoder and a 3-to-8 decoder. Decoding of different numbers of data bits can be achieved using different combinations of 3 to 8 decoders.

[0091] In the example, as shown in Figure 8B, the column address signal is 6-bit binary data, and the first decoding circuit 2311 and the second decoding circuit 2312 each have one 3-to-8 decoder, and the two 3-to-8 decoders can achieve 6-to-16 bit decoding.

[0092] In the example, the column address signal is 12-bit binary data, and the first decoding circuit 2311 and the second decoding circuit 2312 each have two 3-to-8 decoders, each of which two 3-to-8 decoders can achieve exactly 6-to-16 bit decoding, and four 3-to-8 decoders can achieve 12-to-32 bit decoding.

[0093] In the example, the column address signal is 4-bit binary data, and the first decoding circuit 2311 and the second decoding circuit 2312 each have one 3-to-8 decoder, and the two 3-to-8 decoders each decode two of the 4 bits into 4 bits (discarding some bits) to achieve 4-to-8 bit decoding. Furthermore, the first decoding circuit 2311 and the second decoding circuit 2312 each have one 2-to-4 decoder, and the two 2-to-4 decoders can achieve 4-to-8 bit decoding.

[0094] In some examples, the first-stage column decoding circuit 231 further includes a synchronization control signal generation circuit 2314 configured to generate synchronization control signals corresponding to clock periods shorter than the clock periods corresponding to the first and second decoding signals.

[0095] The second input interface of the second-stage column decoding circuit 232 further receives a synchronization control signal, and the second-stage column decoding circuit 232 is configured to output a column decoding signal in response to the enable state of the synchronization control signal and the normal outputs of the first decoding signal and the second decoding signal.

[0096] To synchronize the timing of the first-stage column decoding circuit 231 and the second-stage decoding circuit, the synchronization control signal generation circuit 2314 is positioned to impose timing constraints, similar to Figure 8A. The clock period corresponding to the synchronization control signal is shorter than the clock periods corresponding to the first and second decoding signals. In some examples, the clock period corresponding to the synchronization control signal is half the clock periods corresponding to the first and second decoding signals.

[0097] In the example, as shown in Figure 8B, the synchronous control signal generation circuit 2314 may be a rectangular signal generation circuit, and the waveform of the synchronous control signal may refer to the Y pulse shown in Figure 8C. Also, Figure 8B shows a schematic diagram of the synchronous control signal generation circuit 2341. As shown in Figure 8B, the synchronous control signal generation circuit 2341 may comprise an inverter, a time delay circuit, and an exclusive OR gate. The input terminal of the inverter receives a clock signal AY_CLK, where the clock period of the clock signal may be the same as the clock period corresponding to the first and second decoded signals. The output terminal of the inverter is connected to the input terminal of the time delay circuit, which is configured to perform a time delay on the clock signal, for example, a half-period time delay. The first input terminal of the exclusive OR gate is connected to the output terminal of the time delay circuit, the second input terminal of the exclusive OR gate receives the clock signal, and the output terminal of the exclusive OR gate outputs a synchronous control signal.

[0098] As shown in Figure 8C, under the influence of the synchronization control signal Ypulse, the periods of the preliminary column decoding signals AY_6_4_BUF<7:0> and AY_9_7_BUF<7:0> are narrowed. Therefore, the period of the column decoding signal AY_Y<63:0> and the period of the synchronization control signal Ypulse are always narrowed to half the period of the preliminary column decoding signals AY_6_4_BUF<7:0> and AY_9_7_BUF<7:0>. In other words, the synchronization control signal acts as a timing constraint.

[0099] Please note that Figure 8B merely illustrates an example of a synchronous control signal generation circuit and is not intended to limit the typical circuit of the synchronous control signal generation circuit in the example of this application.

[0100] It will be understood that the column decoding circuit comprises a first-stage column decoding circuit and a second-stage column decoding circuit. The second-stage column decoding circuit adds synchronous control operations. Consistency between the address and data timing of the column in a block is advantageous for timing adjustment during high-speed operation.

[0101] In some examples, the second-stage column decoding circuit 232 receives a synchronization control signal and a semiconductor element enable signal, and when both the synchronization control signal and the block enable signal are enabled, it is configured to output a column decoding signal to enable the bit lines of the selected block corresponding to the enabled data bits of the preliminary column decoding signal, and the fact that the block enable signal is enabled indicates that a block has been selected.

[0102] Here, the second-stage column decoding circuit 232 is configured to receive the first decoding signal, the second decoding signal, the synchronization control signal, and the block enable signal, and to perform operations on the first decoding signal, the second decoding signal, the synchronization control signal, and the block enable signal to obtain a decoded signal. For a block of bit lines, the decoding signal corresponding to a bit line is enabled when both the signals for each bit of the first decoding signal and each bit of the second decoding signal corresponding to that bit line are enabled, and both the synchronization control signal and the block enable signal are also enabled. In this case, the decoding signals corresponding to other bit lines are disabled. It should be noted that the enabled and disabled states of the decoding signals mentioned here can be understood as the signal being at a specific logic level indicating activation or deactivation of a particular bit line.

[0103] A typical configuration of the second-stage column decoding circuit 232 can be seen in Figure 8B. Note that Figure 8B shows only one second-stage column decoding circuit 232. As described above, each block corresponds to one second-stage column decoding circuit 232, and each second-stage column decoding circuit is connected to the output of the first-stage column decoding circuit. Different blocks correspond to different block enable signals. For example, the block enable signal corresponding to a selected block is at a high logic level "1", and the block enable signal corresponding to an unselected block is at a logic level "0" which is ground.

[0104] As shown in Figure 8B, the second-stage column decoding circuit 232 comprises the same number of circuits as the number of bit lines, as shown in the dashed boxes. The circuits shown in the dashed boxes comprise one NOR gate and two NAND gates. The first input terminal of one NAND gate receives the block enable signal, and the second input terminal receives the signal of the data bit of the first decoded signal in the preliminary column decoding signal corresponding to the bit line. The first input terminal of the other NAND gate receives the synchronous control operation signal lypulse, which corresponds to the synchronous control operation signal lypulse (where the synchronous control operation signal lypulse is obtained by performing an AND operation between the synchronous control operation signal Ypulse and the block enable signal Blk_en), and the second input terminal receives the signal of the data bit of the second decoded signal in the preliminary column decoding signal corresponding to the bit line. The output terminals of the two NAND gates are connected to the input terminals of the NOR gate, and the output terminal of the NOR gate outputs the column decoding signal. Each data bit of the column decoding signal corresponds to one bit line.

[0105] Note that in the examples of this application, each second-stage column decoding circuit 232 comprises the same number of circuits as the number of bit lines, as shown in the dashed boxes. The input terminals of the circuits, as shown in the dashed boxes, each receive a composite signal of any data bits contained in the first decoded signal and any data bits contained in the second decoded signal. In the example, the first decoded signal contains 8 bits of data, and the second decoded signal contains 8 bits of data. Next, there are 64 circuits, as shown in the dashed boxes, and the input of each circuit, as shown in the dashed boxes, is a combination of any data bits from the 8 bits of data contained in the first decoded signal and any data bits from the 8 bits of data contained in the second decoded signal.

[0106] Please note that Figure 8B merely presents an example of the second-stage column decoding circuit 232 and is not intended to limit the typical circuit of the second-stage column decoding circuit 232 in the example of this application.

[0107] In some examples, the first-stage column decoding circuit 231 further comprises a drive circuit 2315 including multiple drivers. Each driver is connected to one of several transmission lines corresponding to the first decoded signal and the second decoded signal, respectively, and is configured to perform power amplification processing on the decoded signal of the respective transmission line.

[0108] Here, as shown in Figure 8A, a driver may be placed on each transmission line. Each transmission line may have the first address transmission line described above between the first output interface of each first stage column decoding circuit 231 and the second input interface of all second stage column decoding circuits, and may further have a transmission line for the synchronization control signal generated by the synchronization control signal generation circuit 2314.

[0109] In some examples, as shown in 8B, the driver may have an even number of inverters cascaded in series, typically two, four, or more. The driver may be configured to increase the transmission power, thereby avoiding or improving transmission failure problems caused by excessively long transmission lines and excessive power loss.

[0110] Since the driver 2315 is positioned corresponding to each transmission line, it will be understood that in the example of this application, the number of drivers can be reduced while also reducing the number of address transmission lines, thereby reducing the overall circuit area.

[0111] The blocks of the column decoding circuit 230 described above are selected and deselected collectively. In some examples, blocks may also be selected on a partition basis, or it may be said that they are selected by the blocks. A typical embodiment of the column decoding circuit 230 in partition-based selected blocks is described below.

[0112] In some examples, a block contains a first region and a second region, and the number of bit lines placed in the first and second regions is the same. The first stage column decoding circuit 231 further comprises a third decoding circuit 2313, a first region selection circuit 2316, and a second region selection circuit 2317. The third decoding circuit 2313 is configured to perform decoding on the remaining multiple consecutive high-order bits of the column address signal in order to obtain the third decoded signal, wherein the third decoded signal and the second decoded signal are the same. The first region selection circuit 2316 is connected to the second decoding circuit 2312 and is configured to output the second decoding signal when the first region enable signal is enabled. The second region selection circuit 2317 is connected to the third decoding circuit 2313 and is configured to output a third decoding signal when the second region enable signal is enabled, and the fact that the first region enable signal / second region enable signal is enabled indicates that the first region / second region of the block is selected.

[0113] In some examples, the first-stage column decoding circuit 231 further includes a buffer 2318. Buffer 2318 is connected to the first decoding circuit and is configured to perform timing adjustments to the first decoding signal in order to synchronize with the output signals of both the first and second region selection circuits.

[0114] Here, as shown in Figure 9A, the first-stage column decoding circuit 231 may further comprise a third decoding circuit 2313, a first region selection circuit 2316, and a second region selection circuit 2317, where the third decoding circuit 2313 may be a duplicate of the second decoding circuit 2312, i.e., capable of decoding the three upper bits AY_9_4_<9:7> of the column address signal. A typical implementation of the third decoding circuit 2313 can also be understood by referring to the second decoding circuit 2312 described above.

[0115] The first region selection circuit 2316 and the second region selection circuit 2317 are configured to select a block region, respectively. The first region selection circuit 2316 is connected to the second decoding circuit 2312 and is configured so that the second decoding signal continues to be transmitted backward through the first region selection circuit 2316 when the first region enable signal is enabled. When the first region enable signal is disabled, the second decoding signal transmits a signal with a fixed logic level, for example, a signal where all data bits are "0". The second region selection circuit 2317 is connected to the third decoding circuit 2313 and is configured so that the third decoding signal continues to be transmitted backward through the second region selection circuit 2317 when the second region enable signal is enabled. When the second region enable signal is disabled, the third decoding signal transmits a signal with a fixed logic level, for example, a signal where all data bits are "0".

[0116] In some examples, as shown in Figure 9B, the first region selection circuit 2316 and the second region selection circuit 2317 may each comprise two NAND gates cascaded in series. The first input terminal of one NAND gate is connected to the output terminal of the second decoding circuit 2312 or the output terminal of the third decoding circuit 2313, and the second input terminal receives a partition enable signal, which indicates that the block assists in partition-level selection. The first input terminal of the other NAND gate is connected to the output terminal of the previous NAND gate, and the second input terminal receives a partition enable signal, which indicates that the block assists in partition-level selection. The output terminal of the other NAND gate outputs a second or third decoding signal.

[0117] After adding the first region selection circuit 2316 and the second region selection circuit 2317, in order to synchronize the timing of the branch circuit where the first decoding circuit 2311 is located with the timing of the second decoding circuit 2312 and the third decoding circuit 2313, it is necessary to add a buffer 2318 as shown in Figure 9A to the branch circuit where the first decoding circuit 2311 is located.

[0118] In some examples, as shown in Figure 9B, the buffer 2318 may include a NAND gate and an inverter cascaded in series, with the first input terminal of the NAND gate connected to the output terminal of the first decoding circuit 2311, and the second input terminal receiving a fixed logic level signal, for example VDD2H, i.e., a high logic level "1", and its output terminal connected to the input terminal of the inverter. The input terminal of the inverter outputs the first decoded signal correctly.

[0119] It should be noted that the output terminals of buffer 2318, the first region selection circuit 2316, and the second region selection circuit 2317 can be connected to the input terminals of the above-mentioned drive circuit to amplify power.

[0120] Note that adjustments to the second-stage column decoding circuit 232 are also necessary. As shown in Figure 9B, for each partition of the block, the circuit needs to be duplicated in the dashed box in Figure 8B above, with different partitions corresponding to different input signals. In the example, the input terminals of the circuits shown in the dashed box corresponding to the first region each receive a composite signal of arbitrary data bits from the first decoded signal and arbitrary data bits from the second decoded signal. The input terminals of the circuits shown in the dashed box corresponding to the second region each receive a composite signal of arbitrary data bits from the first decoded signal and arbitrary data bits from the third decoded signal.

[0121] In the example, the first region of the block contains 64 bit lines, and the second region of the block also contains 64 bit lines. The column address signal is 6 bits of binary data. The auxiliary column decoding signals correspond to 24 transmission lines, with the first decoding signal containing 8 bits of data, the second decoding signal containing 8 bits of data, and the third decoding signal also containing 8 bits of data. Next, there are 128 circuits, as shown in the dashed boxes. The input to the circuit shown in each dashed box corresponding to the first region is a combination of any data bit in the 8 bits of data contained in the first decoding signal and any data bit in the 8 bits of data contained in the second decoding signal. The input to the circuit shown in each dashed box corresponding to the second region is a combination of any data bit in the 8 bits of data contained in the first decoding signal and any data bit in the 8 bits of data contained in the third decoding signal.

[0122] In the example of this application, the column decoding circuit comprises a first-stage column decoding circuit and a second-stage column decoding circuit. A column address decoding circuit (second-stage column decoding circuit) is added after the column to transmit the last decoding circuit of the column address (second-stage column decoding circuit) to each block, and synchronous control is added to the second-stage column decoding circuit. In this way, the decoding circuit provided in the embodiment of this application can significantly reduce the number of long column address lines and can transmit both the column address and data using the same metal layer. As a result the column address and data are synchronized in the block, the effects of PVT are reduced and timing adjustments during high-speed operation are facilitated.

[0123] Furthermore, if the memory device employs a stacked arrangement using a bonding method, the additional circuits in the example of this application, such as the second-stage address decoding circuit, the SA and WLD-related circuits, etc., may be located beneath the memory cell array. The stacked arrangement of memory cells and peripheral circuits results in closer address-data matching of the columns, and the additional circuits do not result in the loss of extra area.

[0124] An example of this application is a memory system, One or more of the above-mentioned memory devices provided in the example of this application, A memory system is provided that includes a memory device and a memory controller that is coupled to the memory device and controls the memory device.

[0125] Here, the internal configuration of the memory system can be understood by referring to Figure 1 above, and some application scenarios of the memory system can be understood by referring to Figures 2A and 2B above, which will not be repeated here.

[0126] An example of this application is a decoding circuit, A first-stage decoding circuit comprising a first input interface and a first output interface, wherein the first input interface receives at least the signal to be decoded, the first output interface outputs a preliminary decoding signal, and the number of transmission lines corresponding to the signal to be decoded is less than the number of transmission lines corresponding to the preliminary decoding signal; A decoding circuit is provided comprising a second-stage decoding circuit having a second input interface and a second output interface, wherein the second input interface is coupled with a first-stage decoding circuit to receive a preliminary column decoding signal, and the second output interface is coupled with a plurality of structures selected in a semiconductor device to output a decoding signal indicating that one structure selected in the semiconductor device is enabled, and the number of transmission lines corresponding to the preliminary decoding signal is less than the number of transmission lines corresponding to the decoding signal.

[0127] Here, the decoding circuit is not limited to the column decoding circuit of the memory described above, but may be a decoding circuit for other electronic devices. The decoding circuit is configured to perform a decoding process to indicate the activation of a selected structure in a semiconductor element included in the electronic device.

[0128] It should be noted that the first-stage decoding circuit here can be understood by referring to the first-stage column decoding circuit above, the second-stage decoding circuit here can be understood by referring to the second-stage column decoding circuit above, the signal to be decoded can be understood by referring to the column address signal above, the semiconductor element can be understood by referring to the block above, and the selected structure can be understood by referring to the bit line above.

[0129] In some examples, there are multiple second-stage decoding circuits, each corresponding to a single semiconductor element. Each second input interface of the second-stage decoding circuit is coupled to the first-stage decoding circuit, and the second output interface is coupled to multiple structures of a single semiconductor element to be decoded, with the decoded signal indicating that each structure of the selected semiconductor element is to be decoded.

[0130] In some examples, the signal to be decoded contains multiple bits of data, and the first stage decoding circuit is: A first decoding circuit configured to perform a decoding process on a plurality of consecutive lower bits of the signal to be decoded in order to obtain a first decoded signal, The second decoding circuit is configured to perform a decoding process on the remaining multiple consecutive higher bits of data of the signal to be decoded in order to obtain a second decoded signal, wherein the first decoded signal and the second decoded signal are configured to together form a preliminary decoded signal.

[0131] In some examples, the first-stage decoding circuit further includes a synchronization control signal generation circuit configured to generate a synchronization control signal corresponding to a clock period shorter than the clock period corresponding to the first and second decoding signals. The second input interface of the second-stage decoding circuit further receives a synchronization control signal, and the second-stage decoding circuit is configured to output a decoded signal in response to the enable state of the synchronization control signal and the normal outputs of the first and second decoded signals.

[0132] In some examples, the second-stage decoding circuit is configured to receive a synchronization control signal and a semiconductor element enable signal, and when both the synchronization control signal and the semiconductor element enable signal are enabled, to output a decoding signal to enable the selection of a structure in the selected semiconductor element corresponding to the enabled data bits of the pre-decoded signal, and the enabling of the semiconductor element enable signal indicates that the semiconductor element is selected.

[0133] In some examples, the first-stage decoding circuit further includes a drive circuit containing multiple drivers. Each driver is connected to one of several transmission lines corresponding to the first decoded signal and the second decoded signal, respectively, and is configured to perform power amplification processing on the decoded signal of the respective transmission line.

[0134] In some examples, the first-stage decoding circuit further comprises a third decoding circuit, a first region selection circuit, and a second region selection circuit. The third decoding circuit is configured to perform decoding on the remaining multiple consecutive higher bits of the signal to be decoded in order to obtain the third decoded signal, wherein the third decoded signal and the second decoded signal are the same. The first region selection circuit is connected to the second decoding circuit and is configured to output the second decoding signal when the first region enable signal is enabled. The second region selection circuit is connected to the third decoding circuit and is configured to output the third decoding signal when the second region enable signal is enabled. The fact that the first region enable signal / second region enable signal is enabled indicates that the first region / second region of the semiconductor element is selected.

[0135] In some examples, the first-stage decoding circuit further includes a buffer. The buffer is connected to the first decoding circuit and is configured to perform timing adjustments to the first decoding signal in order to synchronize with the output signals of both the first and second region selection circuits.

[0136] In some examples, the first region selection circuit / second region selection circuit comprises a first NAND gate and a second NAND gate, The input terminal of the first NAND gate is connected to the output of the second / third decoding circuit, and the other input terminal is configured to receive the partition enable signal. The enabled partition enable signal indicates that the semiconductor element is assisting in the selection of partition units. The input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, the other input terminal is configured to receive the first region enable signal / second region enable signal, and the output terminal is connected to the first output interface.

[0137] A typical configuration of the first-stage decoding circuit described herein can be understood by referring to the typical configuration of the first-stage column decoding circuit described above, and a typical configuration of the second-stage decoding circuit described herein can be understood by referring to the typical configuration of the second-stage column decoding circuit described above.

[0138] In some examples, the signal to be decoded comprises a column address signal, the transmission line comprises an address transmission line, the semiconductor element comprises a block, the selected multiple structures comprises multiple bit lines, and the decoded signal indicates one of the selected multiple bit lines.

[0139] Throughout this specification, any reference to “Example” or “Example” should be understood as meaning that a typical feature, structure, or characteristic associated with the example is included in at least one example of this application. Therefore, “In an example” or “In an example” as used throughout this specification does not necessarily refer to the same example. Furthermore, these typical features, structures, or characteristics can be incorporated into one or more examples in any suitable manner. It should be understood that in the various examples of this application, the sequence numbers of the processes described above do not indicate the order of execution, and the order of execution of the various processes is determined by their functionality and inherent logic, and does not constitute a limitation on the implementation processes of the examples of this application. The sequence numbers of the examples of this application are for illustrative purposes only and do not represent the advantages or disadvantages of the examples.

[0140] The above description is merely a preferred example of the present application and is not intended to limit the scope of the patent. Equivalent structural transformations, or direct / indirect applications to other related technical fields, made using the contents of the specification and drawings of the present application under the inventive concept of the present application are included within the scope of the patent protection of the present application.

Claims

1. A memory device, A memory cell array, A memory cell array comprising at least one block having rows of word lines, columns of bit lines, and memory cells coupled between the word lines and the bit lines, A peripheral circuit coupled to the aforementioned memory cell array, A column decoding circuit coupled to the aforementioned sequence of bit lines, Receive the column address signal, Perform multi-stage decoding of the aforementioned column address signal, A peripheral circuit comprising a column decoding circuit configured to output a column decoding signal indicating that one of the selected bit lines of the block is enabled, The aforementioned column decoding circuit is The first stage is a column decoding circuit, A first input interface configured to receive the column address signal, A first stage column decoding circuit includes a first output interface configured to output a preliminary column decoding signal, The second stage is a column decoding circuit, A second input interface is coupled to the column decoding circuit of the first stage and configured to receive the preliminary column decoding signal, The second stage of the column decoding circuit includes a second output interface which is coupled to the bit lines of the block and configured to output the column decoding signal, The memory cell array comprises a plurality of banks, each of which comprises an array of blocks arranged in rows and columns. A memory device in which each of the banks corresponds to a plurality of first-stage column decoding circuits and a plurality of second-stage column decoding circuits, each of the first-stage column decoding circuits corresponds to a column of blocks, and each of the second-stage column decoding circuits corresponds to one block within a column of blocks.

2. The first number of transmission lines corresponding to the column address signal is less than the second number of transmission lines corresponding to the preliminary column decoding signal, The memory device according to claim 1, wherein the second number of transmission lines corresponding to the preliminary sequence decoding signal is less than the third number of transmission lines corresponding to the sequence decoding signal.

3. The column decoding circuit of the first stage is, A first decoding circuit is configured to perform a decoding process on consecutive lower bits of the data of the column address signal in order to obtain a first decoded signal, The system includes a second decoding circuit configured to perform decoding on consecutive high-order bits of the data in the column address signal in order to obtain a second decoded signal. The memory device according to claim 1 or 2, wherein the first decoded signal and the second decoded signal are configured to together form the pre-sequence decoded signal.

4. A memory device, A memory cell array, A memory cell array comprising at least one block having rows of word lines, columns of bit lines, and memory cells coupled between the word lines and the bit lines, A peripheral circuit coupled to the aforementioned memory cell array, A column decoding circuit coupled to the aforementioned sequence of bit lines, Receive the column address signal, Perform multi-stage decoding of the aforementioned column address signal, A peripheral circuit comprising a column decoding circuit configured to output a column decoding signal indicating that one of the selected bit lines of the block is enabled, The aforementioned column decoding circuit is The first stage is a column decoding circuit, A first input interface configured to receive the column address signal, Includes a first output interface configured to output a preliminary sequence decoding signal, A first-stage column decoding circuit in which the first number of transmission lines corresponding to the column address signal is less than the second number of transmission lines corresponding to the preliminary column decoding signal, The second stage is a column decoding circuit, A second input interface is coupled to the column decoding circuit of the first stage and configured to receive the preliminary column decoding signal, The second stage of the column decoding circuit includes a second output interface which is coupled to the bit lines of the block and configured to output the column decoding signal, The second number of transmission lines corresponding to the preliminary sequence decoding signal is less than the third number of transmission lines corresponding to the sequence decoding signal. The column decoding circuit of the first stage is, A first decoding circuit is configured to perform a decoding process on consecutive lower bits of the data of the column address signal in order to obtain a first decoded signal, The system includes a second decoding circuit configured to perform decoding on consecutive high-order bits of the data in the column address signal in order to obtain a second decoded signal. The first decoded signal and the second decoded signal are configured to together form the preliminary sequence decoded signal. The first stage column decoding circuit further includes a synchronization control signal generation circuit configured to generate a synchronization control signal corresponding to a clock period shorter than a first clock period corresponding to the first decoding signal and a second clock period corresponding to the second decoding signal, A memory device in which the second input interface of the second stage column decoding circuit is further configured to receive the synchronization control signal, and the second stage column decoding circuit is configured to output the column decoding signal in response to the enable state of the synchronization control signal, the first decoding signal, and the second decoding signal.

5. The second stage column decoding circuit is, The system receives the synchronization control signal and a block enable signal indicating one of the selected blocks. The memory device according to claim 4, further configured to output the column decoding signal in response to the pre-row decoding signal, the synchronization control signal, and the block enable signal, in order to enable the selected one of the selected bit lines of the block.

6. The memory device according to claim 3, wherein the column decoding circuit of the first stage further comprises a drive circuit comprising a plurality of drivers, each connected to a transmission line corresponding to the first decoded signal and the second decoded signal, and configured to perform power amplification processing on the first decoded signal or the second decoded signal of the transmission line.

7. A memory device, A memory cell array, A memory cell array comprising at least one block having rows of word lines, columns of bit lines, and memory cells coupled between the word lines and the bit lines, A peripheral circuit coupled to the aforementioned memory cell array, A column decoding circuit coupled to the aforementioned sequence of bit lines, Receive the column address signal, Perform multi-stage decoding of the aforementioned column address signal, A peripheral circuit comprising a column decoding circuit configured to output a column decoding signal indicating that one of the selected bit lines of the block is enabled, The aforementioned column decoding circuit is The first stage is a column decoding circuit, A first input interface configured to receive the column address signal, Includes a first output interface configured to output a preliminary sequence decoding signal, A first-stage column decoding circuit in which the first number of transmission lines corresponding to the column address signal is less than the second number of transmission lines corresponding to the preliminary column decoding signal, The second stage is a column decoding circuit, A second input interface is coupled to the column decoding circuit of the first stage and configured to receive the preliminary column decoding signal, The second stage of the column decoding circuit includes a second output interface which is coupled to the bit lines of the block and configured to output the column decoding signal, The second number of transmission lines corresponding to the preliminary sequence decoding signal is less than the third number of transmission lines corresponding to the sequence decoding signal. The column decoding circuit of the first stage is, A first decoding circuit is configured to perform a decoding process on consecutive lower bits of the data of the column address signal in order to obtain a first decoded signal, The system includes a second decoding circuit configured to perform decoding on consecutive high-order bits of the data in the column address signal in order to obtain a second decoded signal. The first decoded signal and the second decoded signal are configured to together form the preliminary sequence decoded signal. The first number of the first subset of bit lines arranged in the first region of the block is the same as the second number of the second subset of bit lines arranged in the second region of the block. The column decoding circuit of the first stage is, A third decoding circuit is configured to perform a decoding process on the data of the consecutive higher bits of the column address signal in order to obtain a third decoded signal, A first region selection circuit is connected to the second decoding circuit and configured to output the second decoding signal in response to the first region enable signal indicating that the first region of the block has been selected, A memory device further comprising: a second region selection circuit connected to the third decoding circuit and configured to output the third decoding signal in response to a second region enable signal indicating that the second region of the block has been selected.

8. The column decoding circuit of the first stage is, The memory device according to claim 7, further comprising a buffer connected to the first decoding circuit and configured to perform timing adjustments to the first decoding signal in order to synchronize with the output signals of the first and second region selection circuits.

9. The aforementioned column address signal is 6-bit binary data, The aforementioned preliminary sequence decoding signals correspond to 24 transmission lines, The first region of the block includes 64 bit lines, The memory device according to claim 7, wherein the second region of the block includes 64 bit lines.

10. A plurality of address transmission lines connected between the first stage column decoding circuit and the second stage column decoding circuit, The array of the aforementioned blocks further includes a plurality of data transmission lines connected to the array of the aforementioned blocks, The memory device according to claim 2, wherein the plurality of address transmission lines and the plurality of data transmission lines are arranged on the same metal layer.

11. The first semiconductor structure, including the memory cell array, is stacked and bonded perpendicularly to the second semiconductor structure, including the peripheral circuitry. Each of the column decoding circuits in the first stage is located next to one of the corresponding columns in the block, The memory device according to claim 2, wherein each of the second-stage column decoding circuits is positioned perpendicularly to a corresponding block.

12. It is a memory system, One or more memory devices, A memory cell array, A memory cell array comprising at least one block having rows of word lines, columns of bit lines, and memory cells coupled between the word lines and the bit lines, A peripheral circuit, coupled to the memory cell array and the column of bit lines, receiving a column address signal and performing multi-stage decoding of the column address signal, One or more memory devices, each comprising: a peripheral circuit having a column decoding circuit configured to output a column decoding signal indicating that one of the selected bit lines of the block is enabled; The system comprises a memory controller that is coupled to one or more memory devices and controls one or more memory devices, The aforementioned column decoding circuit is The first stage is a column decoding circuit, A first input interface configured to receive the column address signal, A first stage column decoding circuit includes a first output interface configured to output a preliminary column decoding signal, The second stage is a column decoding circuit, A second input interface is coupled to the column decoding circuit of the first stage and configured to receive the preliminary column decoding signal, The second stage of the column decoding circuit includes a second output interface which is coupled to the bit lines of the block and configured to output the column decoding signal, The memory cell array comprises a plurality of banks, each of which comprises an array of blocks arranged in rows and columns. A memory system in which each of the banks corresponds to a plurality of first-stage column decoding circuits and a plurality of second-stage column decoding circuits, each of the first-stage column decoding circuits corresponds to a column of blocks, and each of the second-stage column decoding circuits corresponds to one block within a column of blocks.

13. A decoding circuit, The first stage is a column decoding circuit, A first input interface configured to receive a column address signal to be decoded, Includes a first output interface configured to output a preliminary sequence decoding signal, A first-stage column decoding circuit in which the first number of transmission lines corresponding to the column address signal is less than the second number of transmission lines corresponding to the preliminary column decoding signal, The second stage is a column decoding circuit, A second input interface is coupled to the first stage column decoding circuit and configured to receive the preliminary column decoding signal, It includes a second output interface which is coupled to multiple bit lines of a block of memory devices and is configured to output a column decoding signal indicating that one of the selected bit lines of the block is enabled, The second stage of the column decoding circuit includes a second number of transmission lines corresponding to the preliminary column decoding signal, wherein the second number of transmission lines corresponding to the column decoding signal is less than the third number of transmission lines corresponding to the column decoding signal. The column decoding circuit of the first stage is, A first decoding circuit is configured to perform a decoding process on consecutive lower bits of the data of the column address signal in order to obtain a first decoded signal, The system includes a second decoding circuit configured to perform decoding on consecutive high-order bits of the data in the column address signal in order to obtain a second decoded signal, The first decoded signal and the second decoded signal are configured to together form the preliminary sequence decoded signal. The first stage column decoding circuit further includes a synchronization control signal generation circuit configured to generate a synchronization control signal corresponding to a clock period shorter than a first clock period corresponding to the first decoding signal and a second clock period corresponding to the second decoding signal, The second input interface of the second stage column decoding circuit is further configured to receive the synchronization control signal, The second stage column decoding circuit is a decoding circuit configured to output the column decoding signal in response to the enable state of the synchronization control signal, as well as the first decoding signal and the second decoding signal.

14. The second stage column decoding circuit is, The system receives the synchronization control signal and a block enable signal indicating one of the selected blocks. The decoding circuit according to claim 13, further configured to output the column decoding signal in response to the pre-row decoding signal, the synchronization control signal, and the block enable signal, in order to enable the selected one of the selected bit lines of the block.

15. The decoding circuit according to claim 14, wherein the first stage column decoding circuit further comprises a drive circuit having a plurality of drivers, each connected to a single transmission line corresponding to the first decoding signal and the second decoding signal, and configured to perform power amplification processing on the first decoding signal or the second decoding signal.

16. The first number of the first subset of bit lines arranged in the first region of the block is the same as the second number of the second subset of bit lines arranged in the second region of the block. The column decoding circuit of the first stage is, A third decoding circuit is configured to perform a decoding process on the data of the consecutive higher bits of the column address signal in order to obtain a third decoded signal, A first region selection circuit is connected to the second decoding circuit and configured to output the second decoding signal in response to the first region enable signal indicating that the first region of the block has been selected, The decoding circuit according to claim 14, further comprising: a second region selection circuit connected to the third decoding circuit and configured to output the third decoding signal in response to a second region enable signal indicating that the second region of the block has been selected.

17. The column decoding circuit of the first stage is, The decoding circuit according to claim 16, further comprising a buffer connected to the first decoding circuit and configured to perform timing adjustments to the first decoding signal in order to synchronize with the output signals of the first and second region selection circuits.

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