Operation of secure code segments on the processor core of the processing unit

Abstract

A computer-implemented method, computer system, and computer program product for operating secure code segments on a processor core of a processing unit, the processing unit being configured with at least one processor core. The method includes requesting exclusive secure execution of the secure code segments of the program code on the at least one processor core. The method also includes configuring the at least one processor core for exclusive secure execution for the secure code segments. The method further includes uninterruptibly executing the secure code segments on the at least one processor core. Additionally, the method includes clearing the architected and unarchitected state of the physical processor core from the at least one processor core. Finally, the method includes configuring the at least one processor core to a first execution mode for the program code on the at least one processor core.

Description

Technical Field

[0001] The present invention generally relates to data processing systems, and more particularly to a computer-implemented method, a computer system, a computer program product, and a data processing system for operating a secure code segment on a processor core of a processing unit.

Background Art

[0002] A multi-threaded processor can include a plurality of hardware threads that can be executed simultaneously. An example of a multi-threaded processor is a simultaneous multi-thread (SMT) processor. In simultaneous multi-threading, instructions from two or more threads can be executed at any given instruction pipeline stage at one time. Thus, simultaneous multi-threading can enable multiple independent execution threads to better utilize the resources provided by the processor architecture. With simultaneous multi-threading, each processor of a virtual machine can be presented to an application as n processors called threads.

[0003] Processes or threads from different customers within the cloud or on-premises can be virtualized on a virtual machine (VM) or a container and run on the same physical core. It is common to require threads to run in single-thread mode.

[0004] One implementation of a pipeline for secure multithreaded execution may be an integrated circuit for executing instructions, the integrated circuit including a processor pipeline configured to execute instructions from two or more threads in parallel using execution units of the processor pipeline, and a thread hazard circuit configured to detect when an instruction of a first thread is designated as a sensing instruction and, in response to the detection of a sensing instruction, to prevent instructions of threads other than the first thread from being executed using the execution units of the processor pipeline while the sensing instruction is being executed by the execution units of the processor pipeline.

[0005] In this implementation, only a single instruction can be protected to verify that the thread's design state is isolated; the non-design state cannot be considered.

[0006] While it's possible to permanently reserve cores for all secure tasks, this can effectively reduce overall processor performance if secure tasks aren't performed constantly. Furthermore, this doesn't extend even if the majority of the work on the computer system requires execution in a secure environment. [Overview of the project]

[0007] A computer implementation method is proposed for running a secure code segment on the processor cores of a processing unit, wherein the processing unit is configured to run a first execution mode by at least one processor core to execute program code on at least one processor core and to execute program code of operation instructions on at least one processor core. The method includes at least (i) requesting exclusive secure execution of the secure code segment of program code on at least one processor core, (ii) setting at least one processor core to exclusive secure execution for the secure code segment, (iii) executing the secure code segment irrevocably on at least one processor core, (iv) clearing the design state and non-design state of the physical processor core from at least one processor core, and (v) setting at least one processor core to a first execution mode for executing program code on at least one processor core.

[0008] According to the proposed method, a secure code segment can request an exclusive secure context for at least a minimum amount of time and a minimum number of operation instructions. This includes, under hardware control, at least reliably setting the physical core to an exclusive secure mode, executing without interruption for a minimum amount of time and / or operation instructions, and finally, clearing at least the designed and undesigned states of the physical core from cache storage or registers or memory when the secure code segment is terminated or when an interruption occurs after the initial period and / or number of operation instructions.

[0009] Advantageously, interference between different code segments within a processor core can be avoided. The number of execution failures of code segments can be reduced. Furthermore, preferably, the proposed method for secure operation of secure code segments within a processor core can improve the performance of the computer system.

[0010] In one embodiment of the present invention, additionally or alternatively, the design and undesign states of the physical processor core can be saved before setting the processor core to exclusive secure mode. Therefore, after the execution of the secure code segment has finished, the design and undesign states of the physical processor core can be recovered, allowing for the continuation of normal program code execution.

[0011] In one embodiment of the present invention, additionally or alternatively, the design and undesign states of the physical processor core can be restored before setting the processor core to a first execution mode. Therefore, after the execution of the secure code segment has ended, the design and undesign states of the physical processor core can be restored to continue the normal execution of the program code.

[0012] One embodiment of the present invention allows for the additional or alternative removal of undesigned state of a physical processor core, particularly from at least one cache storage of the physical processor core, before executing a secure code segment. This prevents interference with already existing data when the secure code segment is executed.

[0013] In one embodiment of the present invention, the undesigned state of a physical processor core can be additionally or alternatively wiped out in a hardware-controlled manner by the processing unit's hardware. Preferably, this reduces the risk of software failures and subsequent inadequate wipeouts.

[0014] In one embodiment of the present invention, the first execution mode of the processor core can be additionally or alternatively set to a concurrent multithreading mode. Concurrent multithreading allows multiple independent execution threads to make better use of the resources provided by the processor architecture, which is the normal execution mode of the processor core.

[0015] One embodiment of the present invention allows for the additional or alternative definition of uninterrupted execution of a secure code segment for a minimum duration, a minimum number of instructions, or both. Therefore, uninterrupted execution of the secure code segment can be guaranteed for efficient processing.

[0016] In one embodiment of the present invention, the uninterruptible execution of a secure code segment can be additionally or alternatively controlled by a state machine. The state machine can be an efficient method for controlling the uninterruptible execution of a secure code segment.

[0017] One embodiment of the present invention allows for the prevention of interruptions during the execution of a secure code segment, either additionally or alternatively. Preferably, the secure code segment can be executed without disruption for a minimum amount of time, a minimum number of operational instructions, or both.

[0018] In one embodiment of the present invention, the clearing of designed and undesigned states from at least one processor core after the execution of a secure code segment can be initiated by an interruption request, either additionally or alternatively. Thus, further normal execution of the program code in the first execution state can be achieved without interference with the remaining data from the execution of the secure code segment.

[0019] One embodiment of the present invention allows for the additional or alternative implementation of operational instructions on a virtual machine or container. Preferably, processes / threads running on the same physical core from different customers in the cloud or on-premises can be virtualized on a virtual machine or container.

[0020] Furthermore, a computer system is proposed for running a secure code segment on a processor core of a processing unit, the processing unit comprising at least one processor core. The computer system comprises at least one processor unit having at least one processor core, the processor core being configured to run a first execution mode to execute program code on at least one processor core and to execute program code of operation instructions on at least one processor core. The computer system is configured to perform a method that at least includes (i) requesting exclusive secure execution of a secure code segment of program code on at least one processor core, (ii) setting at least one processor core to exclusive secure execution for the secure code segment, (iii) executing the secure code segment irrevocably on at least one processor core, (iv) clearing the design state and non-design state of the physical processor core from at least one processor core, and (v) setting at least one processor core to a first execution mode for executing program code on at least one processor core.

[0021] By running on the proposed computer system, a secure code segment can request an exclusive secure context for at least a minimum amount of time, a minimum number of operation instructions, or both. This includes, under hardware control, at least reliably setting the physical core to an exclusive secure mode, executing without interruption for a minimum amount of time, a minimum number of operation instructions, or both, and finally, clearing at least the designed and undesigned state from the physical core's cache storage or registers or memory when the secure code segment terminates, or when an interruption occurs after the initial period, a minimum number of operation instructions, or both.

[0022] Advantageously, interference between different code segments within a processor core can be avoided. The number of execution failures of code segments can be reduced. Furthermore, preferably, the proposed method for secure operation of secure code segments within a processor core can improve the performance of the computer system.

[0023] In one embodiment of the present invention, the computer system may be configured to save at least the design and undesign states of the physical processor core before setting the processor core to exclusive secure mode. Therefore, after the execution of a secure code segment has finished, the design and undesign states of the physical processor core can be recovered to continue the normal execution of the program code.

[0024] In one embodiment of the present invention, the computer system may be configured to restore at least the designed and undesigned states of the physical processor core before the processor core is set to a first execution mode. Thus, after the execution of the secure code segment has finished, the designed and undesigned states of the physical processor core can be restored to allow the normal execution of the program code to continue.

[0025] According to one embodiment of the present invention, additionally or alternatively, the computer system can be configured to clear the non-designed state of the physical processor core, especially from at least one cache storage of the physical processor core, before the secure code segment is executed. This can prevent interference with the existing data when the secure code segment is executed.

[0026] According to one embodiment of the present invention, additionally or alternatively, the computer system can be configured to hardware-control clear the non-designed state of the physical processor core by the hardware of the processing unit. Preferably, it can reduce the risk of software failures and subsequent insufficient clearing.

[0027] <统一替换为空行,此处无实际意义,不翻译>According to one embodiment of the present invention, additionally or alternatively, the first execution mode of the processor core can be a simultaneous multi-threading mode. Simultaneous multi-threading enables multiple independent execution threads to better utilize the resources provided by the processor architecture, which is the normal execution mode of a normal processor core.

[0028] According to one embodiment of the present invention, additionally or alternatively, the computer system can be configured to execute the secure code segment in an interrupt-inhibited manner for a minimum period or a minimum number of instructions or both. Therefore, it can ensure the unhindered execution of the secure code segment for efficient processing.

[0029] According to one embodiment of the present invention, additionally or alternatively, the interrupt-inhibited execution of the secure code segment can be controlled by a state machine. The state machine can be an efficient method for controlling the interrupt-inhibited execution of the secure code segment.

[0030] <统一替换为空行,此处无实际意义,不翻译>According to one embodiment of the present invention, additionally or alternatively, the computer system can be configured to prevent interruptions during the execution of the secure code segment. Preferably, the secure code segment can be executed without disruption for a minimum amount of time or a number of operation instructions or both. According to one embodiment of the present invention, additionally or alternatively, sweeping the design and non-design states from at least one processor core after the execution of the secure code segment can be initiated by an interrupt request. Thus, further normal execution of the program code in the first execution state can be achieved without interference with the remaining data from the execution of the secure code segment.

[0031] According to one embodiment of the present invention, additionally or alternatively, operation instructions can be implemented on a virtual machine or a container. Preferably, processes / threads running on the same physical core from different customers within the cloud or on-premises can be virtualized on a virtual machine or a container.

[0032] Furthermore, a preferred computer program product for operating a secure code segment on a processor core of a processing unit is proposed, the processing unit being constituted by at least one processor core. The computer system comprises at least one processor unit having at least one processor core, the processor core being configured to run in a first execution mode to execute program code on at least one processor core and to execute program code of operation instructions on at least one processor core.

[0033] A computer program product comprises a computer-readable storage medium on which a program instruction is executed, and the program instruction is executable to cause a computer system to perform a method including (i) requesting exclusive secure execution of a secure code segment of program code on at least one processor core; (ii) setting at least one processor core to exclusive secure execution for the secure code segment; (iii) executing the secure code segment irrevocably on at least one processor core; (iv) clearing the design state and non-design state of the physical processor core from at least one processor core; and (v) setting at least one processor core to a first execution mode for executing program code on at least one processor core.

[0034] Furthermore, a data processing system is proposed for executing a data processing program, which includes computer-readable program instructions for performing the method described above.

[0035] The present invention, in conjunction with the above and other objects and advantages, can be best understood from the following detailed description of the embodiments, but is not limited to these embodiments. [Brief explanation of the drawing]

[0036] [Figure 1] This is a flowchart of a computer implementation method for running a secure code segment on the processor core of a processing unit according to one embodiment of the present invention. [Figure 2] This figure shows an exemplary embodiment of a data processing system for performing the method according to the present invention. [Modes for carrying out the invention]

[0037] In the drawings, similar elements are referenced by the same reference numeral. These drawings are merely schematic representations and are not intended to illustrate the specific parameters of the invention. Furthermore, these drawings are intended to show only typical embodiments of the invention and should not be considered to limit the scope of the invention.

[0038] The exemplary embodiments described herein provide a computer system for running secure code segments on a processor core of a processing unit, the processing unit comprising at least one processor core. The computer system comprises at least one processor unit having at least one processor core, the processor core being configured to run a first execution mode to execute program code on at least one processor core and to execute program code of operation instructions on at least one processor core.

[0039] Exemplary embodiments can be used in a method that includes at least: (i) requesting exclusive secure execution of a secure code segment of program code on at least one processor core; (ii) setting at least one processor core to exclusive secure execution for the secure code segment; (iii) executing the secure code segment irrevocably on at least one processor core; (iv) clearing the at least one processor core of designed and undesigned states; and (v) setting at least one processor core to a first execution mode for program code on at least one processor core.

[0040] Figure 1 shows a flowchart of a computer implementation method for running a secure code segment on the processor core of the processing unit 216 shown in Figure 2, according to one embodiment of the present invention.

[0041] The processing unit 216 is configured to run a first execution mode on at least one processor core, thereby executing program code as normal on at least one processor core.

[0042] The first execution mode of a processor core can be simultaneous multithreading mode. Simultaneous multithreading allows multiple independent execution threads to better utilize the resources provided by the processor architecture, and this is the normal execution mode of a processor core.

[0043] Operational instructions can be implemented on a virtual machine or container. Preferably, processes / threads running on the same physical core from different customers in the cloud or on-premises can be virtualized on a virtual machine or container.

[0044] In step S100, the program code of the operation instruction is executed on at least one processor core in the first execution mode.

[0045] In step S102, an exclusive secure mode is requested for the exclusive secure execution of a secure code segment of program code on at least one processor core.

[0046] Optionally, in step S104, the design and undesign states of the physical processor core can be saved before setting the processor core to exclusive secure mode. Therefore, after the execution of the secure code segment is completed, the design and undesign states of the physical processor core can be restored, allowing for the normal execution of the program code to continue.

[0047] Next, in step S106, at least one processor core is configured for exclusive secure execution for the secure code segment.

[0048] Alternatively, in step S108, the undesigned state of the physical processor core can be cleared before executing the secure code segment. In particular, the undesigned state can be cleared from at least one cache storage or register or memory of the physical processor core. Clearing the undesigned state of the physical processor core can be performed in a hardware-controlled manner by the hardware of the processing unit 216. Preferably, this reduces the risk of software failure and subsequent insufficient clearing. This prevents interference with already existing data when the secure code segment is executed.

[0049] Next, in step S110, a secure code segment is executed on at least one processor core. The secure code segment is executed uninterrupted for a minimum duration, a minimum number of instructions, or both. The uninterrupted execution of the secure code segment can be controlled by a state machine. The state machine can be an efficient method for controlling the uninterrupted execution of the secure code segment.

[0050] During the execution of a secure code segment, interruptions can be prevented. Therefore, for efficient processing, the uninterrupted execution of the secure code segment can be guaranteed. Preferably, the secure code segment can be executed without disruption for a minimum amount of time or number of operational instructions, or both.

[0051] After the execution of the secure code segment has finished, in step S112, the designed and undesigned states can be cleared from at least one cache storage or register or memory of at least one processor core. Clearing the designed and undesigned states from at least one processor core after the execution of the secure code segment can be initiated by an interruption request. Thus, further normal execution of the program code in the first execution state can be achieved without interference with the remaining data from the execution of the secure code segment.

[0052] If, optionally, the design and non-design states are saved in step S104, then in step S112, at least the design and non-design states of the physical processor core can be restored before setting the processor core to the first execution mode. Therefore, after the execution of the secure code segment is completed, the design and non-design states of the physical processor core can be restored, and the normal execution of the program code can continue.

[0053] Next, in step S114, at least one processor core is set to a first execution mode for program code on at least one processor core, and normal execution continues in step S116.

[0054] Referring next to Figure 2, a schematic diagram of an example of a data processing system 210 is shown. The data processing system 210 is merely an example of a preferred data processing system and is not intended to imply any limitation on the use or functional scope of the embodiments of the present invention described herein. Nevertheless, the data processing system 210 may be implemented in any of the functions described herein, or perform any of the functions described herein, or both.

[0055] A computer system / server 212 is provided within the data processing system 210, and the computer system / server 212 operates in a number of other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, that can be suitably used with the computer system / server 212 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices.

[0056] The computer system / server 212 can be described in the general context that computer system executable instructions, such as program modules, are executed by the computer system. Generally, program modules can include routines, programs, objects, components, logic, data structures, etc., that perform a specific task or implement a specific abstract data type. The computer system / server 212 can be implemented in a distributed cloud computing environment where tasks are executed by remote processing devices linked over a communication network. In a distributed cloud computing environment, program modules can reside in both local and remote computer system storage media, including memory storage devices.

[0057] As shown in Figure 2, the computer system / server 212 within the data processing system 210 is shown in the form of a general-purpose computing device. The components of the computer system / server 212 may include, but are not limited to, one or more processors or processing units 216, system memory 228, and a bus 218 that connects various system components, including the system memory 228, to the processing units 216.

[0058] Bus 218 represents one or more of several types of bus structures, including memory buses or memory controllers, peripheral buses, accelerated graphics ports, and processor or local buses using any of the various bus architectures. Examples, but not limited to, such architectures include the Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

[0059] The computer system / server 212 typically includes various computer system-readable media. Such media can be any available media accessible by the computer system / server 212, and such media include both volatile and non-volatile media, and both removable and non-removable media.

[0060] System memory 228 may include computer system-readable media in the form of volatile memory, such as random access memory (RAM) 230 or cache memory 232 or both. The computer system / server 212 may further include other removable / non-removable volatile / non-volatile computer system storage media. For illustrative purposes only, storage system 234 may be provided for reading from and writing to a non-removable non-volatile magnetic medium (not shown, but typically called a “hard drive”). Not shown, a magnetic disk drive may be provided for reading from and writing to a removable non-volatile magnetic disk (e.g., a “floppy disk”), and an optical disk drive may be provided for reading from or writing to a removable non-volatile optical disk, such as a CD-ROM, DVD-ROM, or other optical medium. In such cases, each may be connected to bus 218 by one or more data medium interfaces. Further illustrated and described later, memory 228 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of embodiments of the present invention.

[0061] For example, but not limited to, a program / utility 240 having a set (at least one) of program modules 242 can be stored in memory 228, as well as an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data, or a combination thereof, may include one implementation of a networking environment. The program modules 242 generally perform the functions and / or methods of the embodiments of the present invention described herein.

[0062] The computer system / server 212 can also communicate with one or more external devices 214, such as a keyboard, pointing device, or display 224; one or more devices that enable a user to interact with the computer system / server 212; or any device that enables the computer system / server 212 to communicate with one or more other computing devices (e.g., a network card, modem, etc.), or a combination thereof. Such communication can be performed via the input / output (I / O) interface 222. Furthermore, the computer system / server 212 can communicate with one or more networks, such as a local area network (LAN), a general-purpose wide area network (WAN), or a public network (e.g., the Internet), or a combination thereof, via the network adapter 220. As shown, the network adapter 220 communicates with other components of the computer system / server 212 via the bus 218. It should be understood that other hardware and / or software components, or both, may also be used with the computer system / server 212, although these are not shown. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data storage systems.

[0063] The present invention may be a system, method, or computer program product, or a combination thereof. The computer program product may include a computer-readable storage medium (or more mediums) having computer-readable program instructions for causing a processor to implement aspects of the present invention.

[0064] A computer-readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but is not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any preferred combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random-access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random-access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital multipurpose disks (DVDs), memory sticks, floppy disks, mechanically encoded devices such as punch cards, or raised structures in grooves on which instructions are recorded, and any preferred combination thereof. In this specification, computer-readable storage media should not be interpreted as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through optical fiber cables), or transient signals themselves, such as electrical signals transmitted through wires. The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface within each computing / processing device receives computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in a computer-readable storage medium within each computing / processing device. The computer-readable program instructions for performing the operations of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk and C++, and conventional procedural programming languages ​​such as the C programming language or similar programming languages. The computer-readable program instructions may run entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or wide area network (WAN), or it may be connected to an external computer (for example, via the Internet using an Internet service provider). In some embodiments, an electronic circuit including, for example, a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer-readable program instructions by utilizing state information of computer-readable program instructions for personalizing the electronic circuit in order to perform an aspect of the present invention. Aspects of the present invention will be described herein with reference to flowcharts or block diagrams, or both, of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It will be understood that each block in the flowchart or block diagram, or both, and any combination of blocks in the flowchart or block diagram, or both, can be implemented by computer-readable program instructions.

[0065] These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing device so that instructions executed via the processor of a computer or other programmable data processing device provide a means for implementing functions / operations specified in one or more blocks of a flowchart or block diagram, or both, thereby creating a machine. These computer-readable program instructions can also be stored in a computer-readable storage medium so that the storage medium containing the instructions comprises a product containing instructions that implements modes of functions / operations specified in one or more blocks of a flowchart or block diagram, or both, and can instruct a computer, programmable data processing device, or other device, or a combination thereof, to function in a particular manner.

[0066] Computer-readable program instructions can also be loaded into a computer, other programmable device, or other device so that the instructions executed on the computer, other programmable device, or other device implement a function / operation specified in one or more blocks of a flowchart or block diagram, or both, causing the computer, other programmable device, or other device to perform a series of operational steps and creating a computer implementation process.

[0067] The flowcharts and block diagrams in these figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, and an instruction contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions described within a block may be performed in an order other than that shown in these figures. For example, depending on the functions involved, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may be executed in reverse order. It should also be noted that each block in a block diagram or flowchart, or both, and any combination of blocks in a block diagram or flowchart, or both, may be implemented by a special purpose hardware-based system that performs a specified function or operation or implements a combination of special purpose hardware and computer instructions.

[0068] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or limiting to the embodiments disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments described. The terminology used herein has been selected to best describe the principles of the embodiments, practical applications, or technical improvements to the art available on the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0069] Further exemplary embodiments of this disclosure are described in the following numbered clauses.

[0070] Numbered Clause 1: A computer implementation method for running a secure code segment on the processor cores of a processing unit (216), wherein the processing unit (216) is configured to run a first execution mode by at least one processor core to execute program code on at least one processor core and to execute program code of operation instructions on at least one processor core, and this method is (i) requiring exclusive secure execution of a secure code segment of program code on at least one processor core, (ii) Setting at least one processor core to exclusive secure execution for a secure code segment, (iii) The secure code segment is executed uninterrupted on at least one processor core, (iv) Clearing the design state and non-design state of the physical processor core from at least one processor core, (v) A method comprising setting at least one processor core to a first execution mode for executing program code on at least one processor core.

[0071] Numbered Clause 2: The method according to Numbered Clause 1, further comprising preserving at least the design state and non-design state of the physical processor core before setting the processor core to exclusive secure mode.

[0072] Numbered Clause 3: The method according to Numbered Clause 1 or 2, further restoring at least the design state and non-design state of the physical processor core before setting the processor core to a first execution mode.

[0073] Numbered Clause 4: The method of any one of Numbered Clauses 1 through 3, further clearing the non-design state of a physical processor core from at least one cache storage of the physical processor core before executing a secure code segment.

[0074] Numbered Clause 5: The method of Numbered Clause 4, wherein the undesigned state of the physical processor core is performed in a hardware-controlled manner by the hardware of the processing unit (216).

[0075] Numbered Clause 6: The method according to any one of the numbered clauses 1 through 5, wherein the first execution mode for executing program code on the processor core is a concurrent multithreading mode.

[0076] Numbered Clause 7: The method of any one of Numbered Clauses 1 through 6, wherein the uninterrupted execution of a secure code segment on at least one processor core is defined for a minimum duration, a minimum number of instructions, or both.

[0077] Numbered Clause 8: The method according to any one of the numbered clauses 1 through 7, wherein the execution of a secure code segment irrevocably on at least one processor core is controlled by a state machine. Numbered Clause 9: The method described in any one of the numbered clauses 1 through 8, which prevents interruption of the execution of a secure code segment.

[0078] Numbered Clause 10: The method of any one of Numbered Clauses 1 through 9, wherein the design state and non-design state of a physical processor core are cleared from at least one processor core after the execution of a secure code segment, initiated by an interruption request.

[0079] Numbered Clause 11: The method described in any one of the numbered clauses 1 through 10, wherein the operational instructions are implemented on a virtual machine or container.

[0080] Numbered Clause 12: A computer system (212) for running a secure code segment on a processor core of a processing unit (216), wherein the processing unit (216) comprises at least one processor core, and the computer system (212) comprises at least one processor unit (216) having at least one processor core, the processor core being configured to run a first execution mode to execute program code on at least one processor core, and to execute program code of operation instructions on at least one processor core, and the computer system (212) (i) requiring exclusive secure execution of a secure code segment of program code on at least one processor core, (ii) Setting at least one processor core to exclusive secure execution for a secure code segment, (iii) The secure code segment is executed uninterrupted on at least one processor core, (iv) Clearing the design state and non-design state of the physical processor core from at least one processor core, (v) A computer system configured to perform the method described in any one of the numbered clauses 1 through 11, which at least includes setting at least one processor core to a first execution mode for executing program code on at least one processor core.

[0081] Numbered Clause 13: The computer system described in Numbered Clause 12, configured to save at least the design state and non-design state of a physical processor core before setting the processor core to exclusive secure mode.

[0082] Numbered Clause 14: The computer system described in Numbered Clause 12 or 13, which is configured to restore at least the design state and non-design state of the physical processor core before the processor core is set to a first execution mode.

[0083] Numbered Clause 15: A computer system as described in any one of the numbered clauses 12 through 14, configured to clear the non-design state of a physical processor core from at least one cache storage of a physical processor core before a secure code segment is executed.

[0084] Numbered Clause 16: A computer system as described in any one of the numbered clauses 12 through 15, configured to clear the non-design state of a physical processor core in a hardware-controlled manner by the hardware of the processing unit.

[0085] Numbered Clause 17: A computer system as described in any one of the numbered clauses 12 through 16, wherein the first execution mode for executing program code on a processor core is concurrent multithreading mode.

[0086] Numbered Clause 18: A computer system as described in any one of the numbered clauses 12 through 17, configured to uninterrupt a secure code segment on at least one processor core for a minimum duration, a minimum number of instructions, or both.

[0087] Numbered Clause 19: A computer system as described in any one of the numbered clauses 12 through 18, wherein the uninterrupted execution of a secure code segment on at least one processor core is controlled by a state machine.

[0088] Numbered Clause 20: A computer system as described in any one of the numbered clauses 12 through 19, configured to prevent interruption during the execution of a secure code segment.

[0089] Numbered Clause 21: A computer system as described in any one of the numbered clauses 12 through 20, in which the design state and non-design state of a physical processor core are cleared from at least one processor core after the execution of a secure code segment, initiated by an interruption request.

[0090] Numbered Clause 22: A computer system as described in any one of the numbered clauses 12 through 21, in which operational instructions are implemented on a virtual machine or container.

[0091] Numbered Clause 23: A computer program product for running a secure code segment on the processor cores of a processing unit (216), wherein the processing unit (216) is configured to run a first execution mode by at least one processor core to execute program code on at least one processor core and to execute program code of operation instructions on at least one processor core, the computer program product comprises a computer-readable storage medium on which the program instructions are executed, and the program instructions are executed by a computer system (212), (i) requiring exclusive secure execution of a secure code segment of program code on at least one processor core, (ii) Setting at least one processor core to exclusive secure execution for a secure code segment, (iii) The secure code segment is executed uninterrupted on at least one processor core, (iv) Clearing the design state and non-design state of the physical processor core from at least one processor core, (v) A computer program product that is executable to cause a computer system (212) to perform the method described in any one of the numbered clauses 1 to 11, which includes setting at least one processor core to a first execution mode for executing program code on at least one processor core.

[0092] Numbered Clause 24: A data processing system (210) for executing a data processing program (240) which includes computer-readable program instructions for performing the method described in any one of the numbered clauses 1 through 11.

[0093] Numbered Clause 25: An integrated circuit for executing instructions to operate a secure code segment on a processor core of a processing unit, wherein the processing unit comprises at least one processor core, and the computer system comprises at least one processor unit having at least one processor core, the processor core being configured to run a first execution mode to execute program code on at least one processor core, and to execute program code of operation instructions on at least one processor core, and the integrated circuit, (i) requiring exclusive secure execution of a secure code segment of program code on at least one processor core, (ii) Setting at least one processor core to exclusive secure execution for a secure code segment, (iii) The secure code segment is executed uninterrupted on at least one processor core, (iv) Clearing the design state and non-design state of the physical processor core from at least one processor core, (v) an integrated circuit configured to perform the method described in any one of the numbered clauses 1 to 11, which at least includes setting at least one processor core to a first execution mode for executing program code on at least one processor core.

Claims

1. A computer implementation method for running a secure code segment on the processor core of a processing unit, wherein the processing unit is configured to run a first execution mode by at least one processor core to execute program code on the at least one processor core and to execute program code of operation instructions on the at least one processor core, and the method is To request exclusive secure execution of the secure code segment of the program code on at least one processor core, Setting at least one of the processor cores to exclusive secure execution for the secure code segment, The secure code segment is to be executed uninterrupted on at least one processor core, The process of clearing the design state and non-design state of the physical processor core from at least one of the aforementioned processor cores, Setting the at least one processor core to the first execution mode for executing program code on the at least one processor core; The following are defined for a minimum duration and a minimum number of instructions, wherein the execution of the secure code segment uninterrupted on at least one processor core is defined as follows: Computer implementation method.

2. The computer implementation method according to claim 1, further comprising saving at least the design state and the non-design state of the physical processor core before setting the processor core to exclusive secure mode.

3. The computer implementation method according to claim 1, further comprising restoring at least the design state and the non-design state of the physical processor core before setting the processor core to the first execution mode.

4. The computer implementation method according to claim 1, further comprising clearing the undesigned state of the physical processor core from at least one cache storage of the physical processor core before executing the secure code segment.

5. The computer implementation method according to claim 4, wherein the removal of the undesigned state of the physical processor core is performed in a hardware-controlled manner by the hardware of the processing unit.

6. The computer implementation method according to claim 1, wherein the first execution mode for executing program code on the processor core is a simultaneous multithreading mode.

7. The computer implementation method according to claim 1, wherein the execution of the secure code segment irrevocably on at least one processor core is controlled by a state machine.

8. The computer implementation method according to claim 1, wherein interruption during execution of the secure code segment is prevented.

9. The computer implementation method according to claim 1, wherein, after the execution of the secure code segment, the design state and the non-design state of the physical processor core are cleared from the at least one processor core, and this is initiated by an interruption request.

10. The computer implementation method according to claim 1, wherein operational instructions are implemented on a virtual machine or container.

11. A computer system for running a secure code segment on the processor core of a processing unit, wherein the processing unit is comprised of at least one processor core, and the computer system comprises at least one processor unit having at least one processor core, the processor core being configured to run a first execution mode to execute program code on the at least one processor core, and to execute program code of operation instructions on the at least one processor core, and the computer system is To request exclusive secure execution of the secure code segment of the program code on at least one processor core, Setting at least one of the processor cores to exclusive secure execution for the secure code segment, The secure code segment is to be executed uninterrupted on at least one processor core, The process of clearing the design state and non-design state of the physical processor core from at least one of the aforementioned processor cores, Setting the at least one processor core to the first execution mode for executing program code on the at least one processor core; It is configured to perform a method that includes at least the following: The secure code segment is configured to execute uninterruptedly on at least one processor core for the minimum duration and minimum number of instructions. Computer system.

12. The computer system according to claim 11, configured to save at least the design state and the non-design state of the physical processor core before setting the processor core to exclusive secure mode.

13. The computer system according to claim 11, wherein the processor core is configured to recover at least the design state and the non-design state of the physical processor core before the processor core is set to the first execution mode.

14. The computer system according to claim 11, wherein the system is configured to clear the non-design state of the physical processor core from at least one cache storage of the physical processor core before the secure code segment is executed.

15. The computer system according to claim 14, wherein the undesigned state of the physical processor core is configured to be cleared in a hardware-controlled manner by the hardware of the processing unit.

16. The computer system according to claim 11, wherein the first execution mode for executing program code on the processor core is a simultaneous multithreading mode.

17. The computer system according to claim 11, wherein the uninterrupted execution of the secure code segment on at least one processor core is controlled by a state machine.

18. The computer system according to claim 11, configured to prevent interruption during the execution of the secure code segment.

19. The computer system according to claim 11, wherein, after the execution of the secure code segment, the design state and the non-design state of the physical processor core are cleared from the at least one processor core, and this is initiated by an interruption request.

20. The computer system according to claim 11, wherein operational instructions are implemented on a virtual machine or container.

21. Program code for causing a processor core to execute the computer implementation method described in any one of claims 1 to 10.

22. A data processing system for executing a data processing program, which includes computer-readable program instructions for executing the computer implementation method described in any one of claims 1 to 10.

23. An integrated circuit for executing instructions to operate a secure code segment on the processor core of a processing unit, wherein the processing unit comprises at least one processor core, the integrated circuit comprises at least one processor unit having at least one processor core, the processor core is configured to run a first execution mode to execute program code on the at least one processor core, and to execute program code of operation instructions on the at least one processor core, and the integrated circuit is To request exclusive secure execution of the secure code segment of the program code on at least one processor core, Setting at least one of the processor cores to exclusive secure execution for the secure code segment, The secure code segment is to be executed uninterrupted on at least one processor core, The process of clearing the design state and non-design state of the physical processor core from at least one of the aforementioned processor cores, Setting the at least one processor core to the first execution mode for executing program code on the at least one processor core; It is configured to perform a method that includes at least the following: The secure code segment is configured to execute uninterruptedly on at least one processor core for the minimum duration and minimum number of instructions. Integrated circuit.

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