High-efficiency solar cell structure and manufacturing method

Abstract

To provide a method for manufacturing a solar cell that provides high operating efficiency and can be produced cost-effectively.SOLUTION: A method for manufacturing a solar cell includes the steps of depositing a passivated silicon oxide layer on a crystalline silicon substrate, depositing an amorphous silicon layer containing a dopant on the silicon oxide layer, heat-treating the amorphous silicon layer at a temperature of 500°C or higher to activate the dopant and initiate crystallization of the amorphous silicon layer into a doped polysilicon layer, and forming a metal electrode in contact with the doped polysilicon layer.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] This invention relates to solar cells. More specifically, this invention relates to an improved solar cell structure for higher battery efficiency and a method for manufacturing the same. [Background technology]

[0002] Related application information This application claims the benefit of a prior U.S. provisional application filed on April 21, 2009, and assigned application number 61 / 171,194, entitled “High-Efficiency Solar Cell Structures and Methods of Manufacture.” This application is hereby incorporated herein by reference in its entirety. All aspects of the present invention may be utilized in combination with any disclosure of the aforementioned application.

[0003] Solar cells are bringing widespread benefits to society by converting virtually unlimited amounts of solar energy into usable electricity. As the use of solar cells increases, certain economic factors such as mass production and efficiency become important.

[0004] Mass production is generally considered to be highly cost-effective and efficient when the number of manufacturing steps and the complexity of each step can be minimized.

[0005] In this industry, it is highly desirable for the efficiency of a completed solar cell to be 20% or higher, but known embodiments of batteries with such efficiency often suffer from problems of complex battery structure and / or manufacturing complexity. [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] Therefore, there is a need for solar cells that can achieve high operating efficiency and be manufactured at a high cost-effectiveness. [Means for solving the problem]

[0007] The present invention overcomes the shortcomings of the prior art and provides further advantages, but in one embodiment of the present invention, its scope extends to any one or a combination thereof of the solar cell structures disclosed below, generally comprising a central substrate, a conductive layer (and multiple conductive layers), an antireflective layer (and multiple antireflective layers), a deactivating layer (and multiple deactivating layers), and / or electrodes (and multiple electrodes). The multifunctional layer realizes a combination of functions consisting of deactivation, permeability, sufficient conductivity for vertical carrier flow, junctions, and / or varying degrees of antireflectiveness. Also disclosed are improved manufacturing methods including a single-sided CVD deposition process and heat treatment for layer formation and / or layer conversion.

[0008] In one embodiment, the present invention includes a method for manufacturing any of these structures, comprising the steps of: preparing a wafer as a central substrate; depositing or growing an interface deactivating layer over the substrate; depositing a conductive layer over the deactivating layer; performing a heat treatment; an optional step of depositing a non-reflective layer (including a rear mirror in some cases); and applying a metal coating as an electrode.

[0009] In one embodiment, the present invention includes the step of performing a heat treatment to produce a multifunctional film that is separated into an interface layer that inactivates the surface and a highly permeable, highly doped polycrystalline inactivating layer.

[0010] In one embodiment, the present invention includes a step of depositing an amorphous silicon-containing compound and a step of initiating crystallization into a polycrystalline film using heat treatment.

[0011] In one embodiment, the present invention includes the steps of depositing an amorphous silicon-containing compound and using heat treatment to induce crystallization of the film and increase its optical transmittance.

[0012] In one embodiment, the present invention includes the steps of depositing an amorphous silicon-containing compound and activating doping atoms in the compound using heat treatment.

[0013] In one embodiment, the present invention includes the steps of depositing an amorphous silicon-containing compound and activating doping atoms in the compound using a heat treatment above 500°C, thereby causing the dopant atoms to diffuse into the substrate wafer and forming a high-low junction or a pn junction.

[0014] Furthermore, systems and computer program products corresponding to the methods outlined above are described and claimed herein.

[0015] Furthermore, the technology of the present invention realizes additional features and advantages. Other embodiments and aspects of the present invention are described in detail herein and are considered to be part of the claimed invention. [Brief explanation of the drawing]

[0016] The subject matter considered to be the present invention is described in detail and explicitly claimed in the last claim of this specification. The aforementioned and other objects, features, and advantages of the present invention will become apparent from the following detailed description in combination with the accompanying drawings.

[0017] [Figure 1] This is an energy band diagram of an n-type crystalline silicon solar cell with a doped polysilicon layer and an inactivated interface. [Figure 2] This is a partial cross-sectional view of a solar cell showing minority carrier flow and majority carrier flow of one type of front-junction p-type wafer. [Figure 3] This is a partial cross-sectional view of a solar cell showing minority carrier flow and majority carrier flow of one type of p-type wafer at the rear junction. [Figure 4]This is a partial cross-sectional view of a solar cell showing minority carrier flow and majority carrier flow of one type in a forward-junctioned n-type wafer. [Figure 5] This is a partial cross-sectional view of a solar cell showing minority carrier flow and majority carrier flow of one type of back-bonded n-type wafer. [Figure 6] This is a partial cross-sectional view of a solar cell having an n-type front portion, an n-type wafer or a p-type wafer, and a p-type rear portion. [Figure 7] This is a partial cross-sectional view of a solar cell having a double-sided configuration, comprising an n-type front portion, an n-type wafer or a p-type wafer, and a p-type rear portion. [Figure 8] This is a partial cross-sectional view of a solar cell having an n-type front section, an n-type wafer, and a p-type rear section, and including an insulating non-reflective coating. [Figure 9] This is a partial cross-sectional view of a solar cell having an n-type front section, an n-type wafer, and a p-type rear section, and including a multifunctional, transparent, and conductive highly doped silicon compound layer. [Figure 10] This is a partial cross-sectional view of a solar cell having an n-type wafer or a p-type wafer, an n-type front portion having several improvements to the front layer, and a p-type rear portion. [Figure 11] This is a partial cross-sectional view of a solar cell having a p-type front portion, an n-type wafer, or a p-type wafer and an n-type rear portion. [Figure 12] This is a partial cross-sectional view of a solar cell having a p-type front portion and an n-type wafer, or a p-type wafer and an n-type rear portion, in a double-sided configuration. [Figure 13] This is a partial cross-sectional view of a solar cell having a p-type front section, a p-type wafer, and an n-type rear section, and including an insulating non-reflective coating. [Figure 14] This is a partial cross-sectional view of a solar cell having a p-type front section, a p-type wafer, and an n-type rear section, and including a multifunctional, transparent, and conductive highly doped silicon compound layer. [Figure 15] This is a partial cross-sectional view of a solar cell having an n-type wafer or a p-type wafer, a p-type front portion having several improvements to the front layer, and an n-type rear portion. [Figure 16]This is a partial cross-sectional view of a solar cell having a glass or other permeable film with embedded electrodes that are crimped or bonded to a battery. [Figure 17] This is a partial cross-sectional view of a solar cell having a glass or other permeable film with embedded electrodes that are crimped or bonded to a battery, and which have localized electrodes on the rear portion. [Figure 18] This is a partial cross-sectional view of a solar cell with an additional silicon buffer layer formed inside.

[0018] All of these drawings are in accordance with the present invention. [Modes for carrying out the invention]

[0019] Referring to the energy band diagrams and partial cross-sectional views of exemplary solar cells in Figures 1 to 5, it is preferably assumed that solar radiation irradiates one surface of the solar cell, usually called the front surface. To achieve high energy conversion efficiency from incident photons to electrical energy, efficient photon absorption within the silicon substrate material forming this cell is crucial. This can be achieved by low parasitic photon absorption in all layers except the substrate itself.

[0020] For simplicity, the geometric surface shape of the layer surface (e.g., it is possible to form surface textures such as pyramids or other surface textures on the layer surface) is not shown in these drawings, but it will be understood that the geometric shape and / or surface may be textured in any shape that is beneficial to improving the efficiency of the solar cell and is within the scope of the present invention.

[0021] One important parameter for high solar cell efficiency is surface deactivation. Surface deactivation results in the suppression of electron-hole recombination at or near a certain physical surface within the solar cell. Surface recombination can be reduced by coating with dielectric layers. These layers reduce the interfacial density of states and therefore the number of recombination centers. Two examples are thermally grown silicon oxide and PECVD-deposited silicon nitride. Another example of a layer that deactivates the surface is true sex This is amorphous silicon. Furthermore, these layers can generate charges that reduce the number of heteropolar carriers and decrease the recombination rate through this mechanism. Two examples are silicon nitride and aluminum oxide.

[0022] Another method for reducing the amount of certain types of carriers near the surface is the diffusion of doping atoms of the same or reverse doping type in layer doping. In this case, a level of doping beyond layer doping is required to obtain high-low junctions (also commonly called back-surface fields or front-surface fields) or pn junctions. This can be combined with the other surface deactivation methods described above.

[0023] Surface deactivation can play a crucial role in realizing high-efficiency solar cells. In most of the solar cell structures described below according to the present invention, multilayer or multifunctional layers can achieve excellent surface deactivation. This can be achieved by additional interface deactivation by using layers with a very steep doping profile and low interfacial density of states and a high band gap, which provide a tunnel barrier through which minority carriers of the substrate pass. The corresponding energy band diagrams are shown in Figure 1. The solid line shows the case of an n-type crystalline silicon wafer with an deactivated interface and a doped polycrystalline silicon deactivation layer. The dashed line shows the case of an n-type crystalline silicon wafer and a true crystalline silicon wafer, sometimes called a heterojunction cell. sex This example shows a two-layer structure in which a doped amorphous silicon layer is formed on top of amorphous silicon.

[0024] These structures offer another advantage to high-efficiency solar cells: recombination in the region below the contacts can be reduced to the same level as in the region without contacts. These contacts can be shielded by deactivation. As a result, the optical properties of this contact region can be optimized, and therefore resistive losses can be reduced, while carrier recombination is reduced.

[0025] Depending on the choice of material, dope type, and dope concentration, the disclosed battery structures can be classified as front-junction or back-junction batteries. In front-junction batteries, minority carriers (which are electrons in the case of p-type wafers) are concentrated on the irradiated side. In back-junction batteries, minority carriers are concentrated on the side opposite to the irradiated side. Generally, the current patterns are shown in the partial cross-sectional views of solar cells in Figures 2 to 5 for p-type and n-type wafers.

[0026] Figure 2 shows the carrier flow for the solar cell 20. In the solar cell 20, minority carriers (solid line) flow from the p-type wafer 25 with a front junction to the front electrode 21. Electrons must utilize lateral flow within the thin n-type emitter 22 to reach the electrode 21, and the lateral sheet resistance of the emitter 22 increases resistive losses. Majority carriers (dashed line) can utilize the shortest geometric path to the entire rear electrode 29.

[0027] Figure 3 shows the carrier flow for a solar cell 30 from a p-type wafer 35 with a back junction. Majority carriers (dashed line) can utilize the overall wafer conductivity to reach the front electrode 31. Minority carriers (solid line) can utilize the shortest geometric path to reach the back n-type emitter 38, and their transport within the emitter is predominantly vertical rather than lateral. This back junction structure reduces the requirement for lateral conductivity in the emitter layer.

[0028] Figure 4 shows the carrier flow for the solar cell 40. In the solar cell 40, minority carriers (solid line) flow from the n-type wafer 45 with a front junction to the front electrode 41. Holes need to utilize the lateral flow within the thin p-type emitter 42 to reach the electrode 41, and the lateral conductivity of the emitter causes resistive losses. Majority carriers (dashed line) can utilize the shortest geometric path to the entire rear electrode 49.

[0029] Figure 5 shows the carrier flow for a solar cell 50 from an n-type wafer 55 with a back junction. Majority carriers (dashed line) can utilize the overall wafer conductivity to reach the front electrode 51. Minority carriers (solid line) can utilize the shortest geometric path to reach the back p-type emitter 58, and these transports within the emitter are predominantly vertical rather than lateral. This back junction structure reduces the requirement for lateral conductivity in the emitter layer.

[0030] A rear-junction battery with full rear contacts has the advantage that minority carriers do not need to flow laterally through the emitter to reach the contacts, and that these transports within the emitter are primarily vertical. This reduces the losses associated with the lateral transport of minority carriers within the emitter. Shielded contacts are important because covering all contact areas is a requirement for reaping the benefits of this property of the structure. This is because, for example, metal is in contact with this layer at all positions ("covering all contact areas"), so that minority carriers do not need to flow laterally towards the nearest contact, as is the case in the emitter in Figure 4. Exemplary battery structure: n-type front section, n-type wafer or p-type wafer, p-type rear section

[0031] Figure 6 is a partial cross-sectional view of a solar cell 60 having an n-type front section, an n-type wafer or a p-type wafer, and a p-type rear section.

[0032] Metal electrodes 61 and 69 are positioned on outer layers 62 and 68, respectively. This has the advantage that this metal does not need to penetrate the lower layer until it contacts the wafer. Further, the silicon bulk wafer 65 is shielded from these contact interfaces, and thus carrier recombination at the contact interfaces is minimized. This structure has an n-type front surface which, for the p-type wafer 65, collects minority carriers (electrons) on the front portion. Thus, a maximum lateral sheet resistivity of, for example, 500 Ohm / square for the combined layers 62, 63, and 64 is required. For the n-type wafer, this structure collects minority carriers (holes) on the rear portion. Thus, the current pattern in this solar cell is different and the requirements for lateral conductivity of layer 62 become relatively less important. Exemplary layers of cell 60 include the following.

[0033] 61: Front metal electrode.

[0034] 62: Permeable conductive film. The refractive index is in the range of 1.4 < n < 3, the thickness is in the range of 20 nm < thickness < 110 nm, the sheet resistivity is less than 500 Ohm / square for the p-type wafer (front junction solar cell), and the resistivity is in the range of rho < 1000 Ohm·cm for the n-type wafer (rear junction solar cell). Examples include permeable conductive oxides such as indium tin oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, tantalum oxide, antimony tin oxide, germanium oxide, zirconium oxide, titanium oxide, gallium oxide, cadmium antimonate.

[0035] 63: Conductive film that electrically deactivates. 1e18cm -3 <N D <5e21cm -3 highly n-doped and the thickness is in the range of 2 nm < thickness < 50 nm, and the resistivity is in the range of rho < 1000 Ohm·cm. Examples include the following. · n-type amorphous silicon carbide or n-type polycrystalline silicon carbide. That is, silicon carbide doped with phosphorus, silicon carbide doped with nitrogen. · n-type amorphous silicon or n-type polycrystalline silicon. That is, amorphous silicon doped with phosphorus, amorphous silicon doped with nitrogen. · n-type amorphous diamond-like carbon or n-type polycrystalline diamond-like carbon. That is, diamond-like carbon doped with nitrogen.

[0036] In any of the above examples, oxygen and hydrogen may be included (n-doped SiC x O y H z [[ID=1(14]]n-doped SiN x O y H z ).

[0037] 64: Electrically inactivated interface layer. The thickness is <10 nm. Because of the thin thickness, there are no conductivity requirements and no absorption limitations. Examples include silicon oxide, silicon nitride, true sex amorphous silicon, true sex polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride.

[0038] 65: n-type crystalline silicon wafer or p-type crystalline silicon wafer. The thickness is in the range of w < 300 um, and the base resistivity is 0.5 Ohm·cm < rho < 20 Ohm·cm for n-type wafers and 0.1 Ohm·cm < rho < 100 Ohm·cm for p-type wafers.

[0039] 66: Electrically inactivated interface layer. The thickness is <10 nm. Because of the thin thickness, there are no conductivity requirements and no absorption limitations. Examples include silicon oxide, silicon nitride, true sex amorphous silicon, true sex polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride.

[0040] 67: Electrically inactivated conductive film. 1E18~5E21 / cm 3 Highly p-doped, with resistivity in the range of rho < 1000 Ohm·cm. Examples include the following. · p-type amorphous silicon carbide or p-type polycrystalline silicon carbide. That is, silicon carbide doped with boron, silicon carbide doped with aluminum, silicon carbide doped with gallium. · p-type amorphous silicon or p-type polycrystalline silicon. That is, silicon doped with boron, silicon doped with aluminum, silicon doped with gallium. · p-type amorphous diamond-like carbon or p-type polycrystalline diamond-like carbon. That is, diamond-like carbon doped with boron, diamond-like carbon doped with aluminum.

[0041] In any of the above examples, oxygen and hydrogen may be included (p-doped SiC x O y H z 、p-doped SiN x O y H z ).

[0042] 68: Permeable and conductive film. The refractive index is in the range of 1.4 < n < 3, and the resistivity is in the range of rho < 1000 ohm cm. Examples include conductive oxides such as indium tin oxide, zinc oxide doped with aluminum, tin oxide doped with fluorine, tantalum oxide, antimony tin oxide, germanium oxide, zirconium oxide, titanium oxide, gallium oxide, cadmium antimony oxide.

[0043] 69: Rear metal electrode.

[0044] FIG. 7 is a partial cross-sectional view of a solar cell 70 having an n-type front portion, an n-type wafer or a p-type wafer, and a p-type rear portion in a double-sided configuration. The cell 70 is similar to the cell 60, but includes a local electrode 79 on the rear portion. This local structure on the rear portion enables photons impinging from the back of the solar cell to be absorbed within the wafer 75, generating electron-hole pairs. This can increase the electrical power output generated by the solar cell under outdoor operating conditions where it is possible to utilize albedo with low additional module manufacturing costs and additional module installation costs.

[0045] FIG. 8 is a partial cross-sectional view of a solar cell 80 having an n-type front portion, an n-type wafer, and a p-type rear portion, including insulation with an antireflection coating. This structure is particularly advantageous in cases where the combination of materials is such that the conductive layer on the front surface of the cell structures 60 and 70 has a high absorption rate. By directly disposing the electrode 81 on the contact layer 83, the conductivity requirements for the layer 82 become unnecessary, and it becomes possible to use a conventional antireflection coating film (which is an insulator). Exemplary layers of the cell 80 include the following.

[0046] 81: Front metal electrode.

[0047] 82: Antireflection film. The refractive index is in the range of 1.4 < n < 3, and the thickness is in the range of 20 nm < thickness < 110 nm. Examples include silicon nitride, silicon carbide, silicon oxide, and transparent conductive oxide.

[0048] 83: Conductive film that is electrically passivated. The thickness is < 110 nm and is highly n-doped at 1e18 cm -3 <N D <5e21 cm -3 and has a resistivity in the range of rho < 1000 Ohm·cm. Examples include the following. · n-type amorphous silicon carbide or n-type polycrystalline silicon carbide. That is, phosphorus-doped silicon carbide, nitrogen-doped silicon carbide. n-type amorphous silicon or n-type polycrystalline silicon. That is, phosphorus-doped amorphous silicon, nitrogen-doped amorphous silicon. n-type amorphous diamond-like carbon or n-type polycrystalline diamond-like carbon; that is, nitrogen-doped diamond-like carbon.

[0049] In any of the above examples, oxygen and hydrogen may be included (n-doped SiC x O y H z , n-doped SiN x O y H z ).

[0050] 84: An electrically inactivating interface layer. Its thickness is <10 nm; due to its thinness, there are no conductivity requirements, and due to its thinness, there are no absorption limitations. Examples include silicon oxide, silicon nitride, and silicon sex Amorphous silicon, true sex This includes polycrystalline silicon, aluminum oxide, aluminum nitride, phosphate nitride, and titanium nitride.

[0051] 85: n-type crystalline silicon wafer. Thickness is in the range w < 300 μm, and base resistivity is 0.5 Ohm·cm for n-type wafers. <rho<20 Ohm·cmである。

[0052] 86: An electrically inactivating interface layer. Its thickness is <10 nm; due to its thinness, there are no conductivity requirements, and due to its thinness, there are no absorption limitations. Examples include silicon oxide, silicon nitride, and silicon sex Amorphous silicon, true sex This includes polycrystalline silicon, aluminum oxide, aluminum nitride, phosphate nitride, and titanium nitride.

[0053] 87: A conductive film that electrically deactivates. 1e18cm -3 <N A <5e21cm -3It is highly p-doped, and the resistivity is in the range of rho < 1000 Ohm·cm. Examples include the following. · p-type amorphous silicon carbide or p-type polycrystalline silicon carbide. That is, boron-doped silicon carbide, aluminum-doped silicon carbide, gallium-doped silicon carbide. · p-type amorphous silicon or p-type polycrystalline silicon. That is, boron-doped silicon, aluminum-doped silicon, gallium-doped silicon. · p-type amorphous diamond-like carbon or p-type polycrystalline diamond-like carbon. That is, boron-doped diamond-like carbon, aluminum-doped diamond-like carbon.

[0054] In any of the above examples, oxygen and hydrogen may be included (p-doped SiC x O y H z , p-doped SiN x O y H z ).

[0055] 88: Permeable and conductive film. The refractive index is in the range of 1.4 < n < 3, and the resistivity is in the range of rho < 1000 Ohm·cm. Examples include permeable conductive oxides such as indium tin oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, tantalum oxide, antimony tin oxide, germanium oxide, zirconium oxide, titanium oxide, gallium oxide, cadmium antimony oxide.

[0056] 89: Rear metal electrode.

[0057] FIG. 9 is a partial cross-sectional view of a solar cell 90 having an n-type front portion, an n-type wafer, a p-type rear portion, and including a highly doped silicon compound layer having multifunctionality, permeability, and conductivity. This aspect of the present invention is an improvement over the other disclosures described above. The reason is that, for example, the functions of layers 62 and 63 of solar cell 60 in FIG. 6 (and any other similar layers in any other embodiment disclosed herein) are consolidated into the multifunctional layer 93a illustrated in FIG. 9. This layer is electrically inactivated, permeable, has sufficient conductivity for vertical carrier flow to the electrodes (back-junction solar cell), forms a junction with the wafer 95, and / or reduces the reflectivity of incident light (e.g., an antireflection coating). At the rear, layer 97a can consolidate the functions of, for example, layers 67 and 68 of solar cell 60 in FIG. 6 (and any other similar layers in any other embodiment disclosed herein). Layer 97a forms a junction with the wafer 95, has a refractive index that provides high reflectivity for photons with wavelengths greater than 900 nm, and has sufficient conductivity for vertical carrier flow from the wafer 95 to the metal electrode 99. Exemplary layers of cell 90 include the following.

[0058] 91: Front metal electrode.

[0059] 93a: Permeable conductive film that is electrically inactivated. The refractive index is in the range of 1.4 < n < 3, the thickness is in the range of 20 nm < thickness < 100 nm, and the resistivity is in the range of rho < 1000 Ohm·cm for an n-type wafer (back-junction solar cell), and is highly n-doped at 1e18 cm -3 <N D <5e21cm -3 and is highly n-doped. Examples include the following. · n-type amorphous silicon carbide or n-type polycrystalline silicon carbide. That is, silicon carbide doped with phosphorus, silicon carbide doped with nitrogen. · n-type amorphous silicon or n-type polycrystalline silicon. That is, amorphous silicon doped with phosphorus, amorphous silicon doped with nitrogen. · n-type amorphous diamond-like carbon or n-type polycrystalline diamond-like carbon. That is, diamond-like carbon doped with nitrogen.

[0060] In any of the above examples, oxygen and hydrogen may be included (n-doped SiC x O y H z , n-doped SiN x O y H z ).

[0061] 94: An electrically-inactivating interface layer. The thickness is <10 nm. Since the thickness is thin, there are no conductivity requirements, and since the thickness is thin, there are no absorption limitations. Examples include silicon oxide, silicon nitride, amorphous silicon, polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride. sex amorphous silicon, sex polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride are included.

[0062] 95: An n-type crystalline silicon wafer or a p-type crystalline silicon wafer. The thickness is in the range of w < 300 μm, and the base resistivity is 0.5 Ohm·cm < ρ < 20 Ohm·cm for n-type wafers and 0.1 Ohm·cm < ρ < 100 Ohm·cm for p-type wafers.

[0063] 96: An electrically-inactivating interface layer. The thickness is <10 nm. Since the thickness is thin, there are no conductivity requirements, and since the thickness is thin, there are no absorption limitations. Examples include silicon oxide, silicon nitride, amorphous silicon, polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride. sex amorphous silicon, sex polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride are included.

[0064] 97a: An electrically-inactivating permeable conductive film. The resistivity is in the range of ρ < 1000 Ohm·cm. Examples include the following. • p-type amorphous silicon carbide or p-type polycrystalline silicon carbide. That is, boron-doped silicon carbide, aluminum-doped silicon carbide, and gallium-doped silicon carbide. • p-type amorphous silicon or p-type polycrystalline silicon. That is, boron-doped silicon, aluminum-doped silicon, gallium-doped silicon. • p-type amorphous diamond-like carbon or p-type polycrystalline diamond-like carbon. That is, boron-doped diamond-like carbon, aluminum-doped diamond-like carbon.

[0065] In any of the above examples, oxygen and hydrogen may be present (p-doped SiC x O y H z p-doped SiN x O y H z ).

[0066] 99: Rear metal electrode.

[0067] Figure 10 is a partial cross-sectional view of a solar cell 100 having an n-type or p-type wafer, an n-type front section having several improvements to the front layer, and a p-type rear section. A back surface structure (omitted for convenience) may be mounted according to any of the other structures described herein.

[0068] This structure is particularly advantageous in the case of a combination of materials such that the upper layers x3 and x4, such as the front surface of the above-described structure, have a high absorption rate exceeding the tolerance. (These notations x3 and x4 represent any of the above-described layers having reference numerals ending with 3, 3a, 4, 4a respectively, which will be further explained below.) In the battery 100, by arranging the layers 103 and 104 only below the contact, their optical properties (refractive index, absorption rate) become unimportant for the efficiency of the battery. The resistive losses are caused only by the vertical carrier flow to the contact 101. Further, the layers 102, 104b, and 105b do not need to shield the contact, so that optimization of the permeability and surface passivation of these layers becomes possible. If these layers actually provide lateral conductivity, the current in the direction of the contact is promoted, and the contact structures can be arranged further apart from each other. This reduces the optical shading loss. This structure functions best in combination with the rear junction since the requirements for lateral conductivity of the layers 102, 104b, and 105b are not applicable. Exemplary layers of the battery 100 include the following.

[0069] 101: Front metal electrode.

[0070] 102: Anti-reflection film. The refractive index is in the range of 1.4 < n < 3, and the thickness is < 150 nm. Examples include silicon nitride, silicon carbide, silicon oxide, titanium oxide, and transparent conductive oxide.

[0071] 103: Conductive film that is electrically passivated. For example, the thickness is < 50 nm, and for example, the resistivity is in the range of ρ < 1000 Ohm·cm. Examples include the following. · n-type amorphous silicon carbide or n-type polycrystalline silicon carbide. That is, phosphorus-doped silicon carbide, nitrogen-doped silicon carbide. · n-type amorphous silicon or n-type polycrystalline silicon. That is, amorphous silicon doped with phosphorus, amorphous silicon doped with nitrogen. · n-type amorphous diamond-like carbon or n-type polycrystalline diamond-like carbon. That is, diamond-like carbon doped with nitrogen.

[0072] In any of the above examples, oxygen and hydrogen may be included (n-doped SiC x O y H z , n-doped SiN x O y H z ).

[0073] 104: Electrically inactivated interface layer. The thickness is <10 nm. Because of the thin thickness, there is no conductivity requirement, and because of the thin thickness, there is no absorption limitation. Examples include silicon oxide, silicon nitride, amorphous silicon, polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride. sex amorphous silicon, sex polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride.

[0074] 104b: Electrically inactivated interface layer. The thickness is <110 nm. Examples include silicon oxide, silicon nitride, amorphous silicon, polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride, silicon carbide, or stacks of two or more of these materials. sex amorphous silicon, sex polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride, silicon carbide, or stacks of two or more of these materials.

[0075] 105: n-type crystalline silicon wafer or p-type crystalline silicon wafer. The thickness is in the range of w < 300 um, and the base resistivity is 0.5 Ohm·cm < rho < 20 Ohm·cm for n-type wafers and 0.1 Ohm·cm < rho < 100 Ohm·cm for p-type wafers.

[0076] 105b: Phosphorus-diffused silicon layer (optional). The sheet resistance is >70 Ohm / square.

[0077] The structures described above are not mutually exclusive, and in accordance with the present invention, any feature of one structure can be applied to any other structure described herein. Exemplary battery structure: p-type front section, n-type wafer or p-type wafer, n-type rear section

[0078] Figure 11 is a partial cross-sectional view of a solar cell 110 having a p-type front portion and an n-type wafer or a p-type wafer and an n-type rear portion.

[0079] In this battery, metal electrodes 111 and 119 are placed on the outer layers 112 and 118, respectively. This has the advantage that the metal does not need to penetrate the underlying layers until it contacts the wafer. Furthermore, the silicon bulk wafer 115 is shielded from these contact interfaces, and therefore carrier recombination at the contact interfaces is minimized. This structure has a p-type front surface. For n-type wafers, this structure concentrates minority carriers (holes) on the front portion. Therefore, a maximum lateral sheet resistivity of 500 Ohm / square meter is permitted for the combined layers 112, 113, and 114. For p-type wafers, this structure concentrates minority carriers (electrons) on the rear portion. Therefore, the current pattern in this solar cell is different, and the requirements regarding the lateral conductivity of layer 112 become relatively less important. Exemplary layers of the battery 110 include the following:

[0080] 111: Front metal electrode.

[0081] 112: Permeable and conductive film. The refractive index is in the range of 1.4 < n < 3, the thickness is < 110 nm, the sheet resistivity is less than 500 Ohm / square for n-type wafers, and the resistivity is in the range of rho < 1000 Ohm·cm for p-type wafers. Examples include permeable conductive oxides such as indium tin oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, tantalum oxide, antimony tin oxide, germanium oxide, zirconium oxide, titanium oxide, gallium oxide, cadmium antimony oxide.

[0082] 113: Conductive film that is electrically inactivated. 1e18cm -3 <N A <5e21cm -3 highly p-doped, and the resistivity is in the range of rho < 1000 Ohm·cm. Examples include the following. · p-type amorphous silicon carbide or p-type polycrystalline silicon carbide. That is, boron-doped silicon carbide, aluminum-doped silicon carbide, gallium-doped silicon carbide. · p-type amorphous silicon or p-type polycrystalline silicon. That is, boron-doped silicon, aluminum-doped silicon, gallium-doped silicon. · p-type amorphous diamond-like carbon or p-type polycrystalline diamond-like carbon. That is, boron-doped diamond-like carbon, aluminum-doped diamond-like carbon.

[0083] In any of the above examples, oxygen and hydrogen may be included (p-doped SiC x O y H z , p-doped SiN x O y H z ).

[0084] 114: An electrically inactivated interfacial layer. It is <10 nm, and due to its thin thickness, there are no conductivity requirements and no absorption limitations. Examples include silicon oxide, silicon nitride, amorphous silicon, polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride. sex amorphous silicon sex polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride are included.

[0085] 115: An n-type crystalline silicon wafer or a p-type crystalline silicon wafer. The thickness is in the range of w < 300 μm, and the base resistivity is 0.5 Ohm·cm < ρ < 20 Ohm·cm for n-type wafers and 0.1 Ohm·cm < ρ < 100 Ohm·cm for p-type wafers.

[0086] 116: An electrically inactivated interfacial layer. The thickness is <10 nm, and due to its thin thickness, there are no conductivity requirements and no absorption limitations. Examples include silicon oxide, silicon nitride, amorphous silicon, polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride. sex amorphous silicon sex polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride are included.

[0087] 117: An electrically inactivated permeable conductive film. It is highly n-doped at 1e18 cm < N < 5e21 cm, for example, the thickness is in the range of 2 nm < thickness < 50 nm or more, and the resistivity is in the range of ρ < 1000 Ohm·cm. Examples include the following. -3 <N D <5e21 cm -3 · n-type amorphous silicon carbide or n-type polycrystalline silicon carbide. That is, phosphorus-doped silicon carbide, nitrogen-doped silicon carbide. · n-type amorphous silicon or n-type polycrystalline silicon. That is, phosphorus-doped amorphous silicon, nitrogen-doped amorphous silicon. · n-type amorphous diamond-like carbon or n-type polycrystalline diamond-like carbon. That is, nitrogen-doped diamond-like carbon. · n-type amorphous diamond-like carbon or n-type polycrystalline diamond-like carbon. That is, nitrogen-doped diamond-like carbon.

[0088] In any of the above examples, oxygen and hydrogen may be included (n-doped SiC x O y H z , p-doped SiN x O y H z ).

[0089] 118: Permeable and conductive films. The refractive index is in the range of 1.4 < n < 3, and the resistivity is in the range of rho < 1000 Ohm·cm. Examples include permeable conductive oxides such as indium tin oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, tantalum oxide, antimony tin oxide, germanium oxide, zirconium oxide, titanium oxide, gallium oxide, cadmium antimony oxide.

[0090] 119: Rear metal electrode.

[0091] FIG. 12 is a partial cross-sectional view of a solar cell 120 having a p-type front portion, an n-type wafer or a p-type wafer, and an n-type rear portion in a double-sided configuration. The cell 120 is similar to the cell 110, but includes a local electrode 129 on the rear portion. This local structure on the rear portion allows photons colliding from the back of the solar cell to be absorbed within the wafer 125, generating electron-hole pairs. This makes it possible to improve the efficiency of the solar cell under outdoor operating conditions where it is possible to utilize albedo at low additional module manufacturing costs and additional module installation costs.

[0092] FIG. 13 is a partial cross-sectional view of a solar cell 130 having a p-type front portion, a p-type wafer, and an n-type rear portion, including insulation of an antireflection coating. This structure is particularly advantageous in the case of a combination of materials such that the conductive layer on the front surface of the cell structures 110 and 120 has a high absorption rate. By arranging the electrode 131 directly on the contact layer 133, the conductivity requirement for the layer 132 becomes unnecessary, and it becomes possible to use a conventional antireflection coating film (which is an insulator). This structure functions best in combination with the rear junction because the lateral conductivity requirements for the layers 133 and 134 become unimportant. Exemplary layers of the cell 130 include the following.

[0093] 131: Front metal electrode.

[0094] 132: Antireflection film. The refractive index is in the range of 1.4 < n < 3 and < 150 nm. Examples include silicon nitride, silicon carbide, silicon oxide, aluminum oxide, titanium oxide, and transparent conductive oxide.

[0095] 133: A transmissive conductive film that is electrically passivated. The thickness is < 110 nm, and the resistivity is in the range of ρ < 1000 Ohm·cm. Examples include the following. · p-type amorphous silicon carbide or p-type polycrystalline silicon carbide. That is, boron-doped silicon carbide, aluminum-doped silicon carbide, gallium-doped silicon carbide. · p-type amorphous silicon or p-type polycrystalline silicon. That is, boron-doped silicon, aluminum-doped silicon, gallium-doped silicon. · p-type amorphous diamond-like carbon or p-type polycrystalline diamond-like carbon. That is, boron-doped diamond-like carbon, aluminum-doped diamond-like carbon.

[0096] In any of the above examples, oxygen and hydrogen may be included (p-doped SiC x Oy H z p-doped SiN x O y H z ).

[0097] 134: An electrically inactivating interface layer. Its thickness is <10 nm; due to its thinness, there are no conductivity requirements, and due to its thinness, there are no absorption limitations. Examples include silicon oxide, silicon nitride, and silicon sex Amorphous silicon, true sex This includes polycrystalline silicon, aluminum oxide, aluminum nitride, phosphate nitride, and titanium nitride.

[0098] 135: p-type crystalline silicon wafer. Thickness is in the range w < 300 μm, and base resistivity is 0.1 Ohm·cm for p-type wafers. <rho<100 Ohm·cmである。

[0099] 136: An electrically inactivating interface layer. Its thickness is <10 nm; due to its thinness, there are no conductivity requirements, and due to its thinness, there are no absorption limitations. Examples include silicon oxide, silicon nitride, and silicon sex Amorphous silicon, true sex This includes polycrystalline silicon, aluminum oxide, aluminum nitride, phosphate nitride, and titanium nitride.

[0100] 137: A permeable conductive film that electrically deactivates. 1e18cm -3 <N D <5e21cm -3 Highly doped with n, the resistivity is in the range of rho < 1000 Ohm·cm. Examples include the following: n-type amorphous silicon carbide or n-type polycrystalline silicon carbide; that is, phosphorus-doped silicon carbide, nitrogen-doped silicon carbide. n-type amorphous silicon or n-type polycrystalline silicon. That is, phosphorus-doped amorphous silicon, nitrogen-doped amorphous silicon. · n-type amorphous diamond-like carbon or n-type polycrystalline diamond-like carbon. That is, diamond-like carbon doped with nitrogen.

[0101] In any of the above examples, oxygen and hydrogen may be included (n-doped SiC x O y H z , n-doped SiN x O y H z ).

[0102] 138: Permeable and conductive film. The refractive index is in the range of 1.4 < n < 3, and the resistivity is in the range of rho < 1000 Ohm·cm. Examples include permeable conductive oxides such as indium tin oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, tantalum oxide, antimony tin oxide, germanium oxide, zirconium oxide, titanium oxide, gallium oxide, cadmium antimony oxide.

[0103] 139: Rear metal electrode.

[0104] FIG. 14 is a partial cross-sectional view of a solar cell 140 having a p-type front portion, a p-type wafer, and an n-type rear portion, and including a highly doped silicon compound layer having multifunctionality, permeability, and conductivity. This aspect of the present invention is an improvement over the other disclosures described above. The reason is that, for example, the functions of layers 112 and 113 of solar cell 110 in FIG. 11 (and any other similar layers in any other embodiment disclosed herein) are consolidated into the multifunctional layer 143a illustrated in FIG. 14. This layer is electrically inactivated, permeable, has sufficient conductivity for vertical carrier flow to the electrodes (back junction solar cell), forms a junction with the wafer 145, and / or reduces the reflectivity of incident light (e.g., an antireflection coating). On the back side, 147a can consolidate the functions of, for example, layers 117 and 118 of solar cell 110 in FIG. 11 (and any other similar layers in any other embodiment disclosed herein). Layer 147a forms a junction with the wafer 145, has a refractive index that provides high reflectivity for photons with wavelengths greater than 900 nm, and has sufficient conductivity for vertical carrier flow from the wafer 145 to the metal electrode 149. Exemplary layers of cell 140 include the following.

[0105] 141: Front metal electrode.

[0106] 143a: Electrically inactivated permeable conductive film. The refractive index is in the range of 1.4 < n < 3, the thickness is < 150 nm, and the resistivity is in the range of rho < 1000 Ohm·cm. Examples include the following. · p-type amorphous silicon carbide or p-type polycrystalline silicon carbide. That is, silicon carbide doped with boron, silicon carbide doped with aluminum, silicon carbide doped with gallium. · p-type amorphous silicon or p-type polycrystalline silicon. That is, silicon doped with boron, silicon doped with aluminum, silicon doped with gallium. · p-type amorphous diamond-like carbon or p-type polycrystalline diamond-like carbon. That is, diamond-like carbon doped with boron, diamond-like carbon doped with aluminum.

[0107] In any of the above examples, oxygen and hydrogen may be included (p-doped SiC x O y H z , n-doped SiN x O y H z ).

[0108] 144: An electrically inactivating interface layer. The thickness is <10 nm. Since the thickness is thin, there is no conductivity requirement, and since the thickness is thin, there is no absorption limitation. Examples include silicon oxide, silicon nitride, amorphous silicon, polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride. sex amorphous silicon, sex polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride are included.

[0109] 145: n-type crystalline silicon wafer or p-type crystalline silicon wafer. The thickness is in the range of w < 300 μm, and the base resistivity is 0.5 Ohm·cm < ρ < 20 Ohm·cm for n-type wafers and 0.1 Ohm·cm < ρ < 100 Ohm·cm for p-type wafers.

[0110] 146: An electrically inactivating interface layer. The thickness is <10 nm. Since the thickness is thin, there is no conductivity requirement, and since the thickness is thin, there is no absorption limitation. Examples include silicon oxide, silicon nitride, amorphous silicon, polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride. sex amorphous silicon, sex polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride are included.

[0111] 147a: An electrically inactivating permeable conductive film. The resistivity is in the range of ρ < 1000 Ohm·cm, 1E18 cm -3 <N D < 5E21 cm -3It is highly doped with n. Examples include the following: n-type amorphous silicon carbide or n-type polycrystalline silicon carbide; that is, phosphorus-doped silicon carbide, nitrogen-doped silicon carbide. n-type amorphous silicon or n-type polycrystalline silicon. That is, phosphorus-doped amorphous silicon, nitrogen-doped amorphous silicon. n-type amorphous diamond-like carbon or n-type polycrystalline diamond-like carbon; that is, nitrogen-doped diamond-like carbon.

[0112] In any of the above examples, oxygen and hydrogen may be included (n-doped SiC x O y H z , n-doped SiN x O y H z ).

[0113] 149: Posterior metal.

[0114] Figure 15 is a partial cross-sectional view of a solar cell 150 having an n-type or p-type wafer, a p-type front section having several improvements to the front layer, and an n-type rear section. A back surface structure (omitted for convenience) may be mounted according to any of the other structures described herein.

[0115] This structure is particularly advantageous in the case of a combination of materials such that the upper layers xx3 and xx4, such as the front surface of the above-described structure, have a high absorption rate exceeding the tolerance. In the battery 150, by arranging the layers 153 and 154 only below the contacts, their optical properties (refractive index, absorption rate) become unimportant for the efficiency of the battery. The resistive loss is caused only by the vertical carrier flow to the contact 151. Further, the layers 152, 154b, and 155b do not need to shield the contacts, so that optimization of the permeability and surface passivation of these layers becomes possible. When these layers actually provide lateral conductivity, the current in the direction of the contacts is promoted, and the contact structures can be arranged further apart from each other. This reduces the optical shadow loss. This structure functions best in combination with the rear junction since the requirements for lateral conductivity of the layers 152, 154b, and 155b become unnecessary. Exemplary layers of the battery 150 include the following.

[0116] 151: Front metal electrode.

[0117] 152: Anti-reflection film. The refractive index is in the range of 1.4 < n < 3, and the thickness is < 110 nm. Examples include silicon nitride, silicon carbide, silicon oxide, and titanium oxide.

[0118] 153: Conductive film for electrically passivating. The thickness is < 110 nm, and the resistivity is in the range of ρ < 1000 Ohm·cm. Examples include the following. · p-type amorphous silicon carbide or p-type polycrystalline silicon carbide. That is, boron-doped silicon carbide, aluminum-doped silicon carbide, gallium-doped silicon carbide. · p-type amorphous silicon or p-type polycrystalline silicon. That is, boron-doped silicon, aluminum-doped silicon, gallium-doped silicon. · p-type amorphous diamond-like carbon or p-type polycrystalline diamond-like carbon. That is, diamond-like carbon doped with boron, diamond-like carbon doped with aluminum.

[0119] In any of the above examples, oxygen and hydrogen may be included (p-doped SiC x O y H z , p-doped SiN x O y H z ).

[0120] 154: Electrically inactivated interface layer. The thickness is <10 nm. Because of the thin thickness, there is no conductivity requirement, and because of the thin thickness, there is no absorption limitation. Examples include silicon oxide, silicon nitride, amorphous silicon, polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride. sex amorphous silicon, sex polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride are included.

[0121] 154b: Electrically inactivated interface layer. The thickness is <10 nm. Examples include silicon oxide, silicon nitride, amorphous silicon, polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride, silicon carbide. sex amorphous silicon, sex polycrystalline silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride, silicon carbide are included.

[0122] 155: n-type crystalline silicon wafer or p-type crystalline silicon wafer. The thickness is in the range of w<300 μm, and the base resistivity is 0.5 Ohm·cm < ρ < 20 Ohm·cm for n-type wafers and 0.1 Ohm·cm < ρ < 100 Ohm·cm for p-type wafers.

[0123] 155b: Phosphorus-diffused silicon layer (optional). The sheet resistance is >70 Ohm / square.

[0124] The structures described above are not mutually exclusive, and in accordance with the present invention, any feature of one structure can be applied to any other structure described herein. Exemplary battery structure: Alternative electrode configuration

[0125] Figure 16 is a partial cross-sectional view of a solar cell 160 having a glass or other permeable film with embedded electrodes that are crimped or bonded to a battery. This alternative configuration can also be applied to any of the structures described above and may comprise an n-type front section or a p-type front section, an n-type wafer or a p-type wafer, and a p-type rear section or an n-type rear section. As an alternative configuration of metal electrodes directly disposed on the battery, metal electrodes 161 and 169 are embedded in the glass or other laminated film 161a and 169a. When the glass or laminated film is crimped or laminated under pressure, the embedded electrodes contact the tops of the outer layers 162 and 168, respectively. This has the advantage that there is no need to directly dispose of the metal in the battery itself, thus eliminating a typical source of film stress that can cause warping of the battery. This is particularly useful when dealing with very large-area wafers, such as thin-film silicon sheets and / or very thin wafers. In many of the embodiments described above, the metal electrodes do not need to penetrate the underlying layers until they contact the battery. Furthermore, it is possible to improve the conductivity between the metal electrodes 161 and 169 and the surfaces of the outer layers 162 and 168 by using various conductive materials. These conductive materials include, but are not limited to, anisotropic conductive films (ACF), conductive epoxy, or spring-like contact probes. Exemplary layers of the battery 160 include the following (which can be formed from any of the materials described above, but are omitted here for simplicity): 161a: A glass plate or permeable film supporting an embedded metal electrode. 161: Front metal electrode. 162: A permeable conductive film. 163: A conductive film that electrically deactivates. 164: An electrically inactivating interface layer. 165: n-type crystalline silicon wafer or p-type crystalline silicon wafer. Thickness is in the range w < 300 nm. 166: An electrically deactivating interface layer. 167: A conductive film that electrically deactivates. 168: A permeable conductive film. 169: Rear metal electrode. 169a: A glass plate or permeable film supporting an embedded metal electrode.

[0126] Figure 17 is a partial cross-sectional view of a solar cell 170 having a glass or other transparent film with embedded electrodes that are crimped or bonded to the battery, and a localized electrode 179 on the rear portion. This localized electrode structure on the rear portion allows photons that collide with the back of the solar cell to be absorbed into the wafer 175, making it possible to generate electron-hole pairs in this double-sided configuration. This makes it possible to increase the efficiency of the solar cell under outdoor operating conditions where albedo can be utilized with low additional module manufacturing and installation costs.

[0127] This alternative configuration can also be applied to any of the above-described structures and may comprise an n-type front section or a p-type front section, an n-type wafer or a p-type wafer, and a p-type rear section or an n-type rear section. As an alternative configuration for metal electrodes directly disposed on the battery, metal electrodes 171 and 179 are embedded in glass or other laminated films 171a and 179a. When the glass or laminated film is pressed or laminated under pressure, the embedded electrodes contact the tops of the outer layers 172 and 178, respectively. This has the advantage that there is no need to directly dispose of the metal on the battery itself, thus eliminating a typical source of film stress that can cause warping of the battery. This is particularly useful when dealing with very large-area wafers, such as thin-film silicon sheets and / or very thin wafers. In many of the embodiments described above, the metal electrodes do not need to penetrate the underlying layers until they contact the battery. Furthermore, it is possible to improve the conductivity between the metal electrodes 171 and 179 and the surfaces of the outer layers 172 and 178 by using various conductive materials. These conductive materials include, but are not limited to, anisotropic conductive films (ACF), conductive epoxy, or spring-like contact probes. An exemplary layer of battery 170 includes the following (which can be formed from any of the materials described above, but are omitted here for simplicity): 171a: A glass plate or permeable film supporting an embedded metal electrode. 171: Front metal electrode. 172: A permeable conductive film. 173: A conductive film that electrically deactivates. 174: An electrically inert interface layer. 175: n-type crystalline silicon wafer or p-type crystalline silicon wafer. Thickness is in the range w < 300 nm. 176: An electrically inert interface layer. 177: A conductive film that electrically deactivates. 178: A permeable conductive film. 179: Rear metal electrode. 179a: A glass plate or permeable film supporting an embedded metal electrode.

[0128] The structures described above are not mutually exclusive, and in accordance with the present invention, any feature of one structure can be applied to any other structure described herein. Manufacturing method

[0129] The following process flow is an example of a method for fabricating the structure disclosed above, but other methods are possible without departing from the scope of the present invention. First, a new wafer is obtained with no surface damage and may be organized or otherwise modified in a manner to have a clean surface. As stated above, and for the sake of simplicity, the geometric surface shape of the layer surface (e.g., it is possible to form a surface structure such as pyramids or other surface structures on the layer surface) is not shown in these drawings, but it will be understood that the geometric shape and / or surface may be organized in any shape that is beneficial for improving the efficiency of the solar cell and is within the scope of the present invention.

[0130] The subsequent processing steps can be as follows (the use of notation such as "xx4" or any other similar directional digit means a similar layer to any of the above structures in Figures 1 to 18, ending in "4" or "4a", such as 4, 14, 134, 4a, 14a, 134a, etc.). • Deposition or growth of interface deactivation layers xx4 and xx6. • Deposition of layers xx3 and xx7. • Heat treatment. • Any deposition of layers xx2 and xx8 (potentially including a low reflective index layer with refractive indices less than 3.0, less than 2.6, less than 2.0, and less than 1.5 for good internal mirroring on the rear section). • Metal coating.

[0131] In any of the structures described above, the layers (e.g., xx2, xx3, xx4, xx6, xx7, and xx8) are conductive, meaning that a metal coating can be directly placed on the outer layer (this is not the case in typical high-efficiency solar cells, because surface deactivation is usually performed by a material that is also an electrical insulator). This enables innovative metal coating techniques, for example, to stack solar cells onto modules with electrodes embedded in glass or laminated sheets. Furthermore, conductive sheets can be applied to mechanically reinforce the cells. Another form of metal coating involves the deposition of thin metal wires. Because the surface is conductive, the requirements for the metal paste are reduced because these surfaces are in direct contact with the outer layer and do not need to penetrate the insulating layer by etching to contact the solar cell. Another example is the direct deposition (evaporation) or sputtering of metal onto a conductive surface.

[0132] Most of the layers within the aforementioned solar cell structures can be deposited or grown using methods such as PECVD, APCVD, LPCVD, PVD, and plating. For some layers and combinations of layers, innovative methods for fabricating the layers and structures may be effective. For example, it is possible to form interface deactivation layers (and multiple interface deactivation layers) using thermal oxidation, plasma deposition, or plasma-based oxidation.

[0133] For example, to achieve highly efficient solar cells using cost-effective manufacturing methods, it is advantageous to deposit films with various characteristics on only one side of the wafer. While this may be difficult (for example, in the case of standard tubular furnace deposition such as LPCVD-deposited polycrystalline silicon), PECVD deposition allows this to be done on one side without deposition on the other side of the wafer. Although PECVD methods are available on an industrial scale, they can only operate under temperature conditions that allow for the deposition of amorphous silicon layers or microcrystalline silicon layers. In the described battery structure, heat treatment can transform the amorphous silicon layer into a polycrystalline silicon layer. Furthermore, this also applies to doped amorphous silicon layers or amorphous silicon carbide compounds, etc. This crystallization negatively affects the deactivation quality of the silicon / amorphous silicon interface layers (if these are present in the battery structure). However, layers xx4 and xx6 have crystallized wafer surfaces. Polysilicon The layers protect the interface. Therefore, the interface remains inactive even after heat treatment, and these layer systems remain stable even at the heat treatment temperature.

[0134] According to the present invention, during this crystallization process, numerous properties of the layer are altered. Specifically, donors or acceptors are activated, optical transmittance increases, and hydrogen is released from the layer. Heat treatment can activate doping atoms in the compound, causing diffusion of dopant atoms into the substrate wafer to form high-low junctions or pn junctions.

[0135] According to the present invention, the good deactivation of layers xx4 and xx6 persists and / or improves even after high-temperature heat treatment. Deactivation may be sufficient after deposition, but its properties can be improved by high-temperature heat treatment. The deactivation has temperature stability (from 500°C, 600°C, or 700°C to 1100°C or above) depending on the composition of these layers. Therefore, heat treatment at 500°C or above constitutes one aspect of the present invention. Other potential advantages of this structure may include the fact that heat treatment makes it possible to avoid alteration of the crystallinity of the silicon substrate, at least at the interface. This is because the first interface layer is amorphous SiO2 and / or the conductive layer is SiC. Therefore, another aspect of the present invention is intended to carry out heat treatment without alteration of the crystallinity of the silicon substrate and / or for the interface deactivation layer to function as a buffer for recrystallization during heat treatment.

[0136] If the layer composition is precisely selected, a layer deposited in a single process separates into two (or more) layers. Oxygen contained within this amorphous deposited layer migrates toward the silicon interface, allowing a thin oxide to grow. When this mechanism is utilized by using oxide-containing films xx3 and xx7, the inactivating interface layers xx4 and xx6 do not need to be fabricated before layers xx3 and xx7, and therefore all the structures described can function without layers xx4 and xx6. Simultaneously, the films can crystallize and the dopants can be activated. This effect can be used to fabricate structures such as the batteries 90 and 140 disclosed above in a very short process flow, but is not limited to this application. For such reasons, if layers xx3 and xx7 contain small amounts of oxygen, this mechanism can be utilized by using layers xx3 and xx7 in any structure, and the list of examples is further extended by the same oxygen-containing layers.

[0137] If the deactivating interface layers xx4 and xx6 and the highly doped layers xx3 and xx7 are deposited or grown with inherent stresses, or if the heat treatment for crystallization described above generates stresses, this may negatively affect the deactivation properties of the wafer surface xx5. To prevent this negative effect, and referring to the partial cross-sectional view of the solar cell 180 in Figure 18, it is possible to deposit thin silicon films 1831 and 1871 on top of the deactivating films 184 and 186 to function as buffer layers. Figure 18 illustrates this concept of silicon buffer layers 1831 and 1871 between the deactivating layers 184 and 186 and the highly doped layers 183a and 187a, respectively. While this concept is particularly advantageous for the batteries 90 and 140 disclosed above, its application is not limited to these structures.

[0138] This silicon buffer layer can be, for example, undoped polysilicon. In this case, a standard tubular furnace can be used because the film can be deposited on both sides. In process sequences where the inactivating layers 184 and 186 are thin thermal oxides, the oxidation process can be carried out immediately after the deposition of polycrystalline silicon in the same furnace but in different tubes (omitting wafer movement), or even in the same tube. The doping required for inactivation can be achieved by moving the dopants contained in films 183a and 187a through the heat treatment used for crystallization, and simultaneously moving the dopants from layers 183a and 187a to layers 1831 and 1871, respectively, thereby inactivating and making them conductive. The allowable thickness of the buffer layer is determined by the doping level of the doped layer deposited on top and by the time / temperature profile used for the crystallization of this doped top layer. The undoped layers are doped during this heat treatment by the doped layers 183a and 187a. The buffer layers 1831 and 1871 can also be composed of multiple silicon layers.

[0139] Another effect of this heat treatment is the reconstruction of the deactivating interface layers 184 and 186. Depending on the thickness of these layers, the heat treatment, and the layers covering them, these layers shrink, via holes open (e.g., perforations occur), allowing adjacent layers 1831 and 1871 to come into direct contact with wafer 185. Very small portions of the interface allow carriers to bypass layers 184 and 186. If the heat treatment is chosen so that via holes do not open completely or completely, layers 184 and 186 need to be thin enough to allow carrier tunneling.

[0140] Other aspects of the present invention include improved methods for manufacturing metal coatings. For example, any of the metal coatings of the structures described above may be formed in accordance with the prior application U.S. Provisional Patent Application No. 61 / 171,187, filed on April 21, 2009, entitled “Method for Forming Structures in a Solar Cell,” and the International Patent Application filed by the same applicant simultaneously under Agent Reference Number 3304.002AWO, entitled “Method for Forming Structures in a Solar Cell.” These applications are each incorporated herein by reference as a whole. According to these applications, a metal coating can be formed by a method for forming a conductive contact / heterocontact pattern on the surface of a solar cell, the method comprising the steps of covering at least one lower layer of the solar cell to form a thin conductive layer, and using a laser beam to remove most of this thin conductive layer, leaving the conductive contact / heterocontact pattern thereafter. A self-aligning metal coating may be formed on top of the conductive contact pattern. This lower layer may include an inert layer and / or a non-reflective layer beneath a thin conductive layer, and this conductive contact pattern forms an electrical contact area to the semiconductor layer of the solar cell via at least one lower layer.

[0141] In another example, a metal coating of any of the structures described above may be formed in accordance with the prior application U.S. Patent Provisional Application No. 61 / 171,491, filed on 22 April 2009 and titled “Localized Metal Contacts By Localized Laser Assisted Reduction Of Metal-Ions In Functional Films, And Solar Cell Applications Thereof,” and the international patent application filed simultaneously by the same applicant under Agent Reference Number 3304.003AWO and titled “Localized Metal Contacts By Localized Laser Assisted Conversion Of Functional Films In Solar Cells.” These applications are each incorporated herein by reference as a whole. According to these applications, a metal coating may be formed by a method for forming at least one electrical contact within a layer of a solar cell, the method comprising the steps of forming a layer in a solar cell containing a material that can be selectively converted into an electrical contact upon laser irradiation, and forming at least one electrical contact within a region of the layer by selectively irradiating at least one region of the layer with a laser. Other areas of this layer may constitute the functional layers of the solar cell, such as a transparent conductive film, an antireflective film, and / or deactivation as described above, and do not need to be removed.

[0142] The present invention generally extends to any one or combination of the solar cell structures disclosed above, comprising a central substrate, a conductive layer (and a plurality of conductive layers), a non-reflective layer (and a plurality of non-reflective layers), a deactivating layer (and a plurality of deactivating layers), and / or electrodes (and a plurality of electrodes). The structures described above are not mutually exclusive, and any feature of one structure can be applied to any other structure herein in accordance with the present invention.

[0143] The present invention includes any method for manufacturing these structures, the manufacturing method comprising the steps of: preparing a wafer as a central substrate; depositing or growing interface deactivating layers xx4 and xx6 over the substrate; depositing conductive layers xx3 and xx7 over the deactivating layers; performing a heat treatment; optionally depositing non-reflective layers xx2 and xx8 (which may include a low-reflectivity layer for a good internal mirror at the rear); and applying a metal coating as an electrode.

[0144] In one embodiment, the present invention includes the step of performing a heat treatment to produce a multifunctional film that is separated into an interface layer that inactivates the surface and a highly permeable, highly doped polycrystalline inactivating layer.

[0145] In one embodiment, the present invention includes the steps of depositing an amorphous silicon-containing compound and initiating crystallization into a polycrystalline film using heat treatment.

[0146] In one embodiment, the present invention includes the steps of depositing an amorphous silicon-containing compound and using heat treatment to induce crystallization of the film and increase its optical transmittance.

[0147] In one embodiment, the present invention includes the steps of depositing an amorphous silicon-containing compound and activating doping atoms in the compound using heat treatment.

[0148] In one embodiment, the present invention includes the steps of depositing an amorphous silicon-containing compound and activating doping atoms in the compound using a heat treatment above 500°C, thereby causing the dopant atoms to diffuse into the substrate wafer and forming a high-low junction or a pn junction.

[0149] One or more of these process control embodiments of the present invention can be incorporated into a product (e.g., one or more computer program products) having, for example, a computer-readable medium. This medium contains, for example, computer-readable program code means for embodying and facilitating the possibilities of the present invention. This product may be included as part of a computer system or sold separately.

[0150] Furthermore, to realize the potential of the present invention, it is possible to provide at least one machine-readable program storage device that embodies at least one machine-executable instruction program.

[0151] The flowcharts and steps shown herein are merely examples. Numerous variations exist to these diagrams or steps (or operations) described herein, which do not depart from the spirit of the invention. For example, these steps may be performed in a different order, or steps may be added, deleted, or modified. All of these variations are considered to be part of the claimed invention.

[0152] While preferred embodiments have been described in detail in this specification, it will be apparent to those skilled in the art that various modifications, additions, and substitutions can be made without departing from the spirit of the invention, and therefore these are considered to fall within the scope of the invention as defined in the following claims.

Claims

1. A method for manufacturing a solar cell, wherein the method is The steps include preparing a silicon wafer as a substrate, A step of depositing or growing an interface deactivating layer on the substrate, wherein the interface deactivating layer is amorphous SiO 2 The step is, A step of depositing a conductive layer on the interface deactivating layer, wherein the conductive layer is an amorphous silicon layer and contains dopant atoms, The steps include: performing heat treatment at a temperature of 500°C or higher to activate the dopant atoms, causing the dopant atoms to diffuse into the substrate, and initiating the crystallization of the amorphous silicon layer into a doped polysilicon layer; The steps include: arranging a permeable conductive film in contact with the doped polysilicon layer; The steps include applying a metal coating as an electrode to the aforementioned permeable conductive film, Methods that include...

2. The method according to claim 1, further comprising the step of depositing at least one anti-reflective layer and / or a low-reflectance layer that forms a good internal reflector at the rear portion of the solar cell.

3. The method according to claim 2, wherein the refractive index of the low reflectance layer is less than 3.

0.

4. The method according to claim 1, wherein the diffusion of the dopant atoms into the substrate forms a high-low junction.

5. The method according to claim 1, wherein the diffusion of the dopant atoms into the substrate forms a p-n junction.

6. The method according to any one of claims 1 to 5, wherein the heat treatment is performed at a temperature in the range of 600°C to 1100°C.

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