Power semiconductor device and method for manufacturing the same

Abstract

A power semiconductor device (20) is identified, comprising: a drift layer (1) of a first conductivity type; at least one well region (2) of a second conductivity type different from the first conductivity type; at least one first doped region (3) of the first conductivity type and at least one second doped region (4) of the second conductivity type, wherein the at least one well region (2), the at least one first doped region (3), and the at least one second doped region (4) are provided on a first side of the power semiconductor device (20), the at least one first doped region (3) and the at least one second doped region (4) are spaced from the drift layer (1) by the at least one well region (2), and an interface between the at least one first doped region (3) and the at least one second doped region (4) is structured. Furthermore, a method for manufacturing such a power semiconductor device (20) is identified.

Description

[Technical Field]

[0001] This disclosure relates to power semiconductor devices and methods for manufacturing the same. [Background technology]

[0002] Some power semiconductor devices are implemented, for example, as metal-oxide-semiconductor field-effect transistors (MOSFETs). MOSFETs may be based on wide-bandgap materials such as silicon carbide (SiC). SiC MOSFETs with 650V and 1200V ratings are currently commercially available. Implemented using either planar cell or trench cell designs, SiC MOSFETs offer competitive static losses, fast dynamic performance, and sufficient reliability. In terms of fault tolerance, SiC MOSFETs still do not meet the typical industry standards shown by their Si counterparts. This is typically associated with a strong trade-off between conduction losses and short-circuit withstand capability (SCWT). Reference US2016 / 005856 A1 describes a method for manufacturing a semiconductor device and a semiconductor device, reference US2007 / 194350 A1 describes a semiconductor device, and reference US2013 / 026559 A1 describes a silicon carbide MOSFET cell structure and a method for forming the same. [Overview of the project] [Problems that the invention aims to solve]

[0003] Embodiments of this disclosure relate to power semiconductor devices with improved efficiency. Further embodiments relate to methods for manufacturing such power semiconductor devices. [Means for solving the problem]

[0004] This is achieved by the subject matter of the independent claim. Further embodiments are evident from the dependent claims and the following description.

[0005] In this specification and hereafter, the term "power" refers to a power semiconductor device adapted to handle voltages greater than 100V, for example, 650V or 1200V, and / or currents greater than 1A.

[0006] Power semiconductor devices include, for example, power metal insulating semiconductor field-effect transistors (MISFETs). The term MISFET also includes MOSFETs, which have an oxide as an insulating material in the gate. Power semiconductor devices may also be insulated-gate bipolar transistors (IGBTs).

[0007] Exemplary, power MISFETs include wide-bandgap materials that can be silicon carbide (SiC). Thus, power semiconductor devices are embodied exemplary as power SiC MISFETs, and in particular as power SiC MOSFETs.

[0008] According to one embodiment, the power semiconductor device comprises a drift layer of a first conductivity type. For example, the drift layer contains or consists of a semiconductor material. Exemplarily, the semiconductor material is SiC. For example, the drift layer contains a first dopant that defines the first conductivity type.

[0009] The drift layer has, for example, a main extending surface. For example, the transverse direction is aligned parallel to the main extending surface, and the longitudinal direction is aligned perpendicular to the main extending surface.

[0010] According to one embodiment, the power semiconductor device includes at least one well region of a second conductivity type different from a first conductivity type.

[0011] Exemplary, a power semiconductor device includes multiple well regions, in particular, at least two well regions. The two well regions are, exemplary, separated from each other in the lateral direction.

[0012] For example, the well regions, and in particular all well regions, extend laterally along the principal extension direction. The principal extension directions of the well regions can be aligned parallel to each other.

[0013] The well region comprises, or consists of, a semiconductor material which is, for example, the same material as the semiconductor material of the drift layer. Exemplarily, the well region contains a second dopant defining a second conductivity type.

[0014] Exemplarily, the first dopant is an n-type dopant such that the first conductivity type is an n-type conductivity type, and the second dopant is a p-type dopant such that the second conductivity type is a p-type conductivity type, or vice versa. For example, the n-type conductivity type is achieved by using phosphorus (P) and / or nitrogen (N) as the first dopant. The p-type conductivity type is achieved by using aluminum (Al) and / or boron (B) as the second dopant.

[0015] According to an embodiment, the semiconductor device for power applications comprises at least one first doped region of a first conductivity type and at least one second doped region of a second conductivity type.

[0016] The first doped region and the second doped region comprise, or consist of, a semiconductor material which is, for example, the same material as the semiconductor material of the drift layer. Exemplarily, the first doped region contains a further first dopant. Exemplarily, the second doped region contains a further second dopant. For example, the further first dopant is an n-type dopant and the further second dopant is a p-type dopant, or vice versa.

[0017] Exemplarily, the further first dopant is the same dopant as the first dopant. Further, the further second dopant is, exemplarily, the same dopant as the second dopant.

[0018] Exemplarily, the drift layer has a uniform doping concentration such that the maximum doping concentration corresponds to the average doping concentration. For example, the maximum doping concentration of the first doped region is higher than the maximum doping concentration of the drift layer. Exemplarily, the maximum doping concentration of the first doped region is at least one order or at least two orders higher than the maximum doping concentration of the drift layer. For example, the maximum doping concentration of the drift layer is at least 1×10 14 cm -3 and at most 1×10 17 cm -3 is.

[0019] For example, the maximum doping concentration of the second doped region is higher than the maximum doping concentration of the well region. Typically, the maximum doping concentration of the second doped region is at least one order or two orders higher than the maximum doping concentration of the well region.

[0020] For example, the maximum doping concentration of the first doped region is at least 1×10 16 cm -3 and at most 1×10 21 cm -3 is. For example, the maximum doping concentration of the second doped region is at least 1×10 17 cm -3 and at most 1×10 21 cm -3 is.

[0021] In particular, at least a part of the first doped region forms the source region of the power semiconductor device. The source region is a region where charge carriers, such as electrons or holes, are injected into the well region.

[0022] According to an embodiment of the power semiconductor device, at least one well region, at least one first doped region, and at least one second doped region are provided on the first side of the power semiconductor device.

[0023] At least one well region, at least one first doped region, and at least one second doped region each extend longitudinally from the first side to a predetermined depth. The well region may have a first depth, the first doped region may have a second depth, and the second doped region may have a third depth.

[0024] Exemplary, the first depth is greater than the second and third depths. For example, the third depth is greater than the second depth, or the second and third depths are equal. For example, the second depth is at least 0.1 μm and at most 0.5 μm. For example, the third depth is at least 0.3 μm and at most 3 μm.

[0025] For example, the first principal surface on the first side of a power semiconductor device is formed flat. The first principal surface extends parallel to the transverse direction. That is, the upper surface of the well region, the upper surface of the first doped region, and the upper surface of the second doped region are part of the first principal surface.

[0026] According to an embodiment of a power semiconductor device, at least one first doped region and at least one second doped region are separated from the drift layer by at least one well region.

[0027] The first doped region and the second doped region are, exemplary, embedded in the well region. That is, the outer surfaces of the first doped region and the second doped region are covered by the well region, except for the top surfaces of the first doped region and the top surfaces of the second doped region. Exemplarily, the top surfaces of the first doped region, the top surfaces of the second doped region, and the top surfaces of the well region terminate flush with each other.

[0028] For example, the upper surfaces of the first doped region and the upper surfaces of the second doped region are at least in areas that can be accessed from the outside in a conductive manner.

[0029] Each well region may, for example, consist of two first doped regions and one second doped region. The second doped region is positioned laterally between the two first doped regions.

[0030] According to an embodiment of a power semiconductor device, the interface between at least one first doped region and at least one second doped region is structured to be non-uniform in the main extending direction of at least one well region. For example, the first doped region and the second doped region are directly adjacent to each other in the lateral direction. This means that the first doped region and the second doped region form an interface.

[0031] Exemplary, an unstructured interface extends uniformly along the main extension direction of the well region. A structured interface is not, in particular, a flat interface. In fact, an unstructured interface is characteristic of a flat interface. Exemplary, a structured interface includes a structure formed by a certain extent in the lateral direction of a first doped region and, therefore, by a certain extent in the lateral direction of a second doped region. In this context, the structure has an extension that is larger than the irregularities resulting from manufacturing tolerances. For example, a non-uniform structure includes a stepped structure. This means that a non-uniform structure is not, in particular, a continuous linear structure.

[0032] At such a structured interface between the first doped region and the second doped region, the on-resistance R on Compared to regions without structured interfaces, it experiences only a slight increase of approximately 7% to 8%. Furthermore, at such structured interfaces, the maximum drain saturation current I Dat_max This represents a reduction of at least 40% compared to conventional MOSFET values. Dat_max Since this is directly related to SCWT, this means that MOSFETs with structured interfaces offer a significantly improved conduction loss advantage over the SCWT tradeoff.

[0033] In other words, power semiconductor devices with structured interfaces have the advantage of providing longer SCWT values ​​and, therefore, improved device durability.

[0034] According to a further embodiment of the power semiconductor device, at least one second doped region comprises a plurality of parts. Exemplarily, all such parts may have equal maximum doping concentrations and / or distributions of the second dopant. Alternatively, at least some of such parts may have different maximum doping concentrations and / or distributions of the second dopant.

[0035] According to a further embodiment of the power semiconductor device, a plurality of parts are arranged adjacent to each other in a continuous manner along the principal extension direction. The principal extension direction extends in particular along the principal extension direction of each well region.

[0036] According to a further embodiment of the power semiconductor device, each of the plurality of parts has a length perpendicular to the principal extending direction. Exemplaryly, the lengths of all such parts may be equal to one another. Alternatively, the lengths of at least some of the parts may differ from one another.

[0037] According to a further embodiment of the power semiconductor device, adjacent portions are in direct contact with each other along the principal extension direction.

[0038] In a further embodiment of the power semiconductor device, adjacent portions are spaced apart from each other along the principal extension direction. In this embodiment, the first doped region is located between adjacent portions in the lateral direction. This means that the portions are spaced apart in the lateral direction by the first doped region.

[0039] According to a further embodiment of the power semiconductor device, the plurality of parts include first parts and second parts that are arranged alternately in a continuous manner along the main extending direction.

[0040] According to a further embodiment of the power semiconductor device, each first portion has a first length perpendicular to the main extending direction, and each second portion has a second length perpendicular to the main extending direction.

[0041] According to a further embodiment of the power semiconductor device, the first length is greater than the second length. Exemplarily, all first parts have the same length, i.e., the first length, and all second parts have the same length, i.e., the second length.

[0042] According to a further embodiment of the power semiconductor device, the maximum doping concentration of the first portion is higher than that of the second portion. Exemplarily, all first portions have the same maximum doping concentration, and all second portions have the same maximum doping concentration.

[0043] According to a further embodiment of the power semiconductor device, at least one first doped region is located between portions of at least one second doped region along the principal extending direction.

[0044] Exemplary, the first doped region is located between the opposing sides of adjacent portions. For example, the first doped region can completely cover the sides of adjacent portions in a transverse direction perpendicular to the main extension direction. Alternatively, the first doped region can cover the sides of adjacent first portions in a transverse region perpendicular to the main extension direction. This means that the first doped region is located between the end regions of adjacent first portions and not in the central region of adjacent first portions where the second portion is located.

[0045] According to a further embodiment of the power semiconductor device, the distance between adjacent portions is at least 0.1 μm and at most 1 μm. Exemplarily, the distance is defined between the opposing sides of adjacent portions. In particular, the distance is defined between the opposing sides of adjacent first portions. Or, further, the distance is defined between the opposing sides of adjacent second portions.

[0046] According to a further embodiment of a power semiconductor device, when adjacent portions are spaced apart from each other along the principal extending direction, at least one first doped region comprises a first doped zone and a second doped zone, wherein the first doped zone is located between adjacent portions of at least one second doped region along the principal extending direction. Exemplarily, the first doped zone is located between the facing sides of adjacent portions, in particular between the side surfaces of the end regions of said portions.

[0047] According to a further embodiment of the power semiconductor device, the maximum doping concentration of the first dope zone is lower than the maximum doping concentration of the second dope zone. Typically, the maximum doping concentration of the first dope zone is at least one order of magnitude smaller or at least two orders of magnitude smaller than the maximum doping concentration of the second dope zone.

[0048] According to a further embodiment of the power semiconductor device, an additional extension extending perpendicular to the length of the portion is located at the end region of the portion. In particular, each portion has two opposing end regions, which are located at the ends of the portion along its length.

[0049] In particular, the portion and the additional extension form a second doped region. For example, the portion and the additional extension are T-shaped in the transverse direction when viewed from above along the longitudinal direction.

[0050] According to a further embodiment of the power semiconductor device, the distance between adjacent additional extensions is at least 0.1 μm and at most 1 μm. In particular, the opposing sides of adjacent additional extensions are spaced apart by that distance in the lateral direction.

[0051] For example, the first dope zone is located between adjacent additional extensions, particularly between the mutually facing sides of adjacent additional extensions. In this case, the second zone can be located between the mutually facing sides of adjacent portions.

[0052] For example, the maximum doping concentration in that portion is the same as the maximum doping concentration in the additional extension. Or, the maximum doping concentration in that portion is higher than the maximum doping concentration in the additional extension.

[0053] According to a further embodiment, the power semiconductor device comprises at least two well regions. Each well region includes, for example, two first doped regions, between which a second doped region is laterally positioned.

[0054] According to further embodiments, the power semiconductor device comprises at least one intermediate region. Exemplarily, the intermediate region includes a further first dopant, for example, an n-type dopant. For example, the maximum doping concentration of the intermediate region is higher than the maximum doping concentration of the drift layer.

[0055] According to a further embodiment of the power semiconductor device, at least two well regions and at least one intermediate region are provided on the first side of the power semiconductor device.

[0056] According to a further embodiment of the power semiconductor device, at least one intermediate region is provided between at least two well regions, particularly in the lateral direction.

[0057] The intermediate region is, exemplary, a junction field-effect transistor (JFET) region or an electron barrier region, which is advantageously introduced into the drift layer to locally increase the resistance of the source region.

[0058] In a further embodiment, the power semiconductor device comprises a semiconductor body having a first principal surface on the first side and a second principal surface on the second side, the semiconductor body comprising a drift layer, at least one well region, at least one first doped region, and at least one second doped region. The second side is on the opposite side of the first side in the longitudinal direction. The semiconductor body may also comprise an intermediate region and / or a substrate layer.

[0059] In a further embodiment, the power semiconductor device comprises an upper metal layer disposed on a first main surface. For example, the upper metal layer is provided on a source region, i.e., on the first side, on a first doped region and a second doped region. For example, the upper metal layer is provided on the first main surface.

[0060] According to a further embodiment of the power semiconductor device, the upper metal layer at least partially overlaps with at least one first doped region and at least one second doped region. Exemplarily, the upper metal layer is in direct contact with the first doped region and the second doped region on their upper surfaces.

[0061] For example, the end region of the first doped area lacks the upper metal layer. Exemplarily, the additional extension also lacks the upper metal layer; that is, the end region of that portion does not overlap with the top metal layer in the lateral direction.

[0062] In a further embodiment, the power semiconductor device comprises a substrate layer. Exemplarily, the substrate layer of a first conductivity type is located on a drift layer on a second side opposite to the first side. For example, the maximum doping concentration of the drift layer is at least two orders of magnitude higher, for example, five times higher, than the maximum doping concentration of the drift layer.

[0063] In a further embodiment, the power semiconductor element comprises a back metal layer disposed on a second main surface. For example, the back metal layer is provided on the second side on the second main surface of the drift layer. For example, the back metal layer completely covers the second main surface.

[0064] The upper metal layer and / or back metal layer may, for example, contain or consist of a metal. For example, the upper metal layer and / or back metal layer may be electrodes that are electrically conductive and accessible from the outside.

[0065] According to a further embodiment of the power semiconductor device, the substrate layer is placed between the second electrode and the drift layer.

[0066] In a further embodiment, the power semiconductor device comprises a gate located on a first principal surface. In particular, the gate does not overlap with the source region in the lateral direction. Exemplarily, the gate is located on at least one intermediate region.

[0067] The gate includes, exemplarily, a gate contact and a gate insulator. The gate contact contains or consists of a metal. The gate insulator includes, for example, an electrical insulating material such as an electrical insulating oxide or a high-k dielectric. SiO2 has a dielectric constant of 3.9, and a "high-k" dielectric material is said to have a dielectric constant k > 3.9.

[0068] For example, the gate contact is located in a region that is accessible from the outside in a conductive manner. Furthermore, the gate contact is, exemplary, embedded in a gate insulator. That is, the gate insulator covers the entire outer surface of the gate contact, except for the region for external contact.

[0069] Further embodiments relate to power semiconductor devices, and more particularly to methods for manufacturing the power semiconductor devices described herein. Thus, the features described in relation to this method are also applicable to power semiconductor devices, and vice versa.

[0070] According to one embodiment of the present method, a first-conductivity drift layer is provided. In particular, the drift layer is an epitaxial semiconductor layer. For example, the substrate for the drift layer is epitaxially grown. The substrate is further doped with a first dopant.

[0071] According to this embodiment of the method, at least one well region of a second conductivity type, different from the first conductivity type, is formed on the first side. Exemplarily, the well region is formed in the drift layer, i.e., within the substrate, by a doping process. For example, a second dopant is introduced into the drift layer. By introducing the second dopant into the drift layer, the well region is exemplary formed.

[0072] According to this embodiment of the method, at least one first doped region of a first conductivity type and at least one second doped region of a second conductivity type are formed on the first side. Exemplarily, the source region including the first doped region and the second doped region is formed within the drift layer by a further doping process.

[0073] For example, the source region is formed by introducing at least one of a further first dopant or a further second dopant into the drift layer. The phrase "at least one of a further first dopant or a further second dopant is introduced" is to include cases where a further first dopant is introduced, where a further second dopant is introduced, or where both a further first dopant and a further second dopant are introduced.

[0074] The first dopant, a further first dopant, a second dopant, and / or a further second dopant are incorporated, for example, into the drift layer by an ion implantation process.

[0075] According to embodiments of this method, a mask is used to form at least one first doped region such that the interface between at least one first doped region and at least one second doped region is structured. In particular, the mask is an injection mask configured to confine an injection region of further first dopants.

[0076] According to further embodiments of the present method, an additional mask is used to form at least one second dope region. In particular, the additional mask is an additional injection mask configured to confine an injection region of an additional second dopant.

[0077] This method, compared to conventional SiC MISFET manufacturing, does not require any changes to the process and, advantageously, does not require an extra mask to create a structured interface between the first and second doped regions. The advantage of forming such a structured interface is that it only requires redrawing the injection masks for the first and second dopants.

[0078] According to a further embodiment of the present method, a self-aligning process is used to form at least one second doped region. Using such a method, the structured interface can be defined particularly simply and accurately.

[0079] The attached drawings are included for further understanding. In the drawings, elements of the same structure and / or function may be referred to by the same reference numerals. Please understand that the embodiments shown in the drawings are illustrative and not necessarily drawn to scale. [Brief explanation of the drawing]

[0080] [Figure 1] A schematic diagram of a power semiconductor device based on prior art is shown as an example and in general terms. [Figure 2] A schematic top view of a power semiconductor device according to an exemplary embodiment is shown. [Figure 3] A schematic top view of a power semiconductor device according to an exemplary embodiment is shown. [Figure 4] A schematic top view of a power semiconductor device according to an exemplary embodiment is shown. [Figure 5] The diagram shows, in particular, exemplary figures of simulated performance data for a power semiconductor device according to an exemplary embodiment. [Figure 6] The diagram shows, in particular, exemplary figures of simulated performance data for a power semiconductor device according to an exemplary embodiment. [Figure 7] The diagram shows, in particular, exemplary figures of simulated performance data for a power semiconductor device according to an exemplary embodiment. [Figure 8] The diagram shows, in particular, exemplary figures of simulated performance data for a power semiconductor device according to an exemplary embodiment. [Modes for carrying out the invention]

[0081] In the power semiconductor device shown in Figure 1, the back metal layer 7, substrate layer 6, and drift layer 1 are stacked on top of each other in the order shown. Adjacent layers are in direct contact with each other. Exemplarily, the drift layer 1 is an epitaxial drift layer 1. That is, the drift layer 1 is formed, for example, by an epitaxial process. The drift layer 1 is of the first conductivity type.

[0082] The maximum doping concentration of substrate layer 6 is higher than the maximum doping concentration of drift layer 1. In other words, drift layer 1 is a low-doping layer, and substrate layer 6 is a high-doping layer.

[0083] The drift layer 1, and in particular the substrate layer 6, include a semiconductor material formed from SiC. For example, a second-conductivity type highly doped collector layer can replace the first-conductivity type substrate layer 6. In this case, the power semiconductor device 20 is an IGBT.

[0084] The power semiconductor device 20 further includes two well regions 2 on the first side of the drift layer 1, each having a second conductivity type different from the first conductivity type. The first side faces away from the back metal layer 7.

[0085] For example, the first conductivity type is n-type conductivity. For example, the second conductivity type is p-type conductivity.

[0086] Well region 2 is formed, for example, within drift layer 1 by a doping process. For example, well region 2 is formed to a first depth by introducing a second dopant into drift layer 1.

[0087] The two well regions 2 are separated from each other in the lateral direction. In other words, the two well regions 2 are arranged within the drift layer 1 with a distance between them in the lateral direction. Each of the two well regions 2 extends along its principal extension direction. Furthermore, the two principal extension directions of the two well regions 2 are aligned parallel to each other.

[0088] Between the two well regions 2 on the first side, an intermediate region 5 is positioned, which also extends along the main extension direction.

[0089] Each well region 2 includes two first doped regions 3 of the first conductivity type and one second doped region 4 of the second conductivity type.

[0090] The two first doped regions 3 are separated from each other in the lateral direction. In other words, the two first doped regions 3 are positioned within their respective well regions 2, maintaining a distance from each other in the lateral direction and extending along the main extending direction of each well region 2. The second doped region 4 is positioned between the two first doped regions 3 and also extends along the main extending direction of each well region 2. The first and second regions extend in the longitudinal direction, perpendicular to the main extending surface of the power semiconductor element 20, to a second and third depth, respectively.

[0091] The upper surfaces of well region 2, the first doped region 3, the second doped region 4, and the intermediate region 5 are all located within a common plane, i.e., the first principal plane.

[0092] In addition, gate 8 is positioned on the intermediate region 5 on the first side. Gate 8 covers the intermediate region 5 and the well region 2, and gate 8 partially covers the first doped region 3, in particular its upper surface. That is, in a top view, gate 8 overlaps the intermediate region 5, the two well regions 2, and the two first doped regions 3 of different well regions 2. Gate 8 includes gate contacts and gate insulators.

[0093] The power semiconductor device 20 according to the exemplary embodiment shown in Figure 2 includes a structured interface between the first doped region 3 and the second doped region 4, compared to the power semiconductor device shown in Figure 1. The second doped region 4 includes a plurality of portions 10, these portions including the first portion 11 and the second portion 12.

[0094] The portions 10, in particular the first portion 11 and the second portion 12, are arranged adjacent to each other in a continuous manner along the main extending direction. The first portion 11 and the second portion 12 are arranged alternately, in particular, along the main extending direction. Adjacent portions 10 are in direct contact with each other along the main extending direction.

[0095] Each first portion 11 has a first length perpendicular to the main extension direction, and each second portion 12 has a second length perpendicular to the main extension direction. The first length is greater than the second length. In particular, the first portion 11 protrudes beyond the second portion 12 in the direction perpendicular to the main extension direction. This means that the end region of the first portion 11 protrudes beyond the second portion 12 in the direction perpendicular to the main extension direction.

[0096] The first doped region 3 is positioned laterally, along the main extension direction, between the end regions of adjacent first portions 11 of the second doped region 4.

[0097] The upper metal layer 9 is positioned on portion 10 of the second doped region 4 and on the first doped region 3, particularly on the first main surface. The upper metal layer 9 completely overlaps the second portion 12 and partially overlaps the first portion 11 in the lateral direction. The upper metal layer 9 is absent at the edges of the edge region of the first portion 11.

[0098] The upper metal layer 9 partially overlaps the first doped region 3 in the lateral direction. In particular, the upper metal layer 9 is positioned on the first doped region 3 between the first portions 11 of the second doped region 4.

[0099] The power semiconductor element 20 according to the exemplary embodiment shown in Figure 3 includes a second doped region 4 portion 10 having the same length as in Figure 2. Adjacent portions 10 are spaced apart from each other along the main extending direction. The first doped region 3 is positioned between adjacent portions 10 in the lateral direction.

[0100] The power semiconductor element 20 according to the exemplary embodiment shown in Figure 4 includes a portion 10 in which an additional extension 13 is located in the end region, compared to Figure 3. The additional extension 13 extends particularly along the main extension direction and extends perpendicularly to the portion 10.

[0101] The first doped region 3 is also positioned laterally between adjacent portions 10, and in particular between adjacent additional extensions 13.

[0102] In a top view, the second doped region 4, having portion 10 and an additional extension 13, is T-shaped in the lateral direction.

[0103] Adjacent additional extensions 13, in particular, the mutually opposing sides of adjacent additional extensions 13, are exemplary, with a distance of at least 0.1 μm and a maximum of 1 μm.

[0104] The first doped region 3 includes a first doped zone 14 and a second doped zone 15, the first doped zone 14 being positioned between adjacent portions 10 of a second doped region 4 along the main extending direction. This means that the first doped zone 14 is positioned between the opposing sides of adjacent additional extending portions 13 that face each other in the lateral direction.

[0105] The maximum doping concentration in the first dope zone 14 is lower than the maximum doping concentration in the second dope zone 15.

[0106] The second doping zone 15 extends in the lateral direction from the side facing the intermediate region 5 to the intermediate region 5.

[0107] current I DSHowever, the unit is amperes (A / cm²). 2 ) is shown on the y-axis of the figure in Figure 5. Furthermore, the drain-source voltage V DS However, the values ​​are shown on the x-axis in volts (V). The uppermost IV curve corresponds to a prior art SiC MOSFET that does not have a structured interface between the first doped region and the second doped region 4.

[0108] For example, the uppermost IV curve is calculated depending on the structure in Figure 1. The central IV curve corresponds to the power semiconductor device 20, which is a SiC MISFET according to the exemplary embodiment in Figure 4, with a distance of 0.3 μm between adjacent additional extensions 13. The bottommost IV curve corresponds to the power semiconductor device 20, which is a SiC MISFET according to the exemplary embodiment in Figure 4, with a distance of 0.6 μm between adjacent additional extensions 13.

[0109] For example, the central and lowest IV curves are calculated depending on the structure in Figure 4. The values ​​in Figure 5 represent a gate-source voltage of 15V V GS And it is simulated at a temperature of 300K.

[0110] In Figure 6, current I DS (Amperes, A / cm) 2 The x-axis is shown on the y-axis of the figure. Furthermore, the x-axis is shown on the x-axis, with time t in seconds (s). Similar to the curves shown in Figure 5, the uppermost It curve corresponds to the prior art SiC MOSFET, and the middle and lowermost It curves correspond to the SiC MISFET according to the exemplary embodiment in Figure 4.

[0111] The values ​​in Figure 6 represent a gate-source voltage of 15V V GS and a drain-source voltage of 600V V DS It is simulated using [this method].

[0112] Figure 7 shows an overview of the results shown in Figures 5 and 6. The B1 design corresponds to the power semiconductor device 20 in Figure 4, which has a distance of 0.3 μm. B1 is A / cm 2 I Dat_max This results in a significant 42% reduction, but mΩcm 2 Eigenvalue R at on The value shows only a modest increase of 7%. This, in turn, results in a longer SCWT value, and consequently, improved device durability.

[0113] The B2 design corresponds to the power semiconductor device 20 in Figure 4, which has a distance of 0.6 μm. The Ref design corresponds to the reference power semiconductor device 20 in Figure 1, which is the conventional technology.

[0114] Figure 8 shows the transfer characteristics of a reference SiC MOSFET Ref and one using the B1 design. The values ​​in Figure 8 are for a drain-source voltage of 1V V DS And it is simulated at a temperature of 300K. Substantially, no changes are observed. [Explanation of Symbols]

[0115] 1. Drift Layer 2 well area 3. First doping area 4. Second doping area 5 Intermediate area 6 Substrate layers 7. Metal layer on the back Gate 8 9 Upper metal layer 10 parts 11 Part 1 12. Part 2 13 Additional extension 14. The First Dope Zone 15. The Second Dope Zone 20 Power Semiconductor Devices

Claims

1. A power semiconductor device (20), - First conductive drift layer (1), - At least one well region (2) of a second conductivity type different from the first conductivity type, - comprising at least one first doped region (3) of the first conductivity type and at least one second doped region (4) of the second conductivity type, - The at least one well region (2), the at least one first doped region (3), and the at least one second doped region (4) are provided on the first side of the power semiconductor element (20), - The at least one first doped region (3) and the at least one second doped region (4) are separated from the drift layer (1) by the at least one well region (2), - The interface between the at least one first doped region (3) and the at least one second doped region (4) is structured to be non-uniform in the main extending direction of the at least one well region (2), - The at least one second doped region (4) includes a plurality of parts (10), - The plurality of parts (10) include first parts (11) and second parts (12) that are arranged alternately and continuously along the main extending direction, The maximum doping concentration of the first portion (11) is higher than the maximum doping concentration of the second portion (12). - The plurality of parts (10) are arranged continuously, adjacent to each other, along the main extending direction. - Each of the plurality of parts (10) has a length perpendicular to the main extending direction, - The adjacent first portion (11) and second portion (12) are in direct contact with each other along the main extending direction, - Each first portion (11) has a first length perpendicular to the main extending direction, and each second portion (12) has a second length perpendicular to the main extending direction. - A power semiconductor element (20) whose first length is greater than the second length.

2. The aforementioned power semiconductor element (20) further comprises - At least two well regions (2), - comprising at least one intermediate region (5), - The at least two well regions (2) and the at least one intermediate region (5) are provided on the first side of the power semiconductor element (20), - The power semiconductor element (20) according to claim 1, wherein the at least one intermediate region (5) is provided between two of the at least two well regions (2).

3. The aforementioned power semiconductor element (20) further comprises - A semiconductor body having a first main surface on the first side and a second main surface on the second side, - The power semiconductor device (20) according to claim 1 or 2, wherein the semiconductor body comprises the drift layer (1), the at least one well region (2), the at least one first doped region (3), and the at least one second doped region (4).

4. The aforementioned power semiconductor element (20) further comprises - comprising an upper metal layer (9) disposed on the first main surface, - The power semiconductor device (20) according to claim 3, wherein the upper metal layer (9) at least partially overlaps the at least one first doped region (3) and the at least one second doped region (4).

5. The aforementioned power semiconductor element (20) further comprises - Substrate layer (6), - comprising a back metal layer (7) arranged on the second main surface, - The power semiconductor element (20) according to claim 3, wherein the substrate layer (6) is disposed between the arranged back metal layer (7) and the drift layer (1).

6. The power semiconductor element (20) according to claim 3, further comprising a gate (8) disposed on the first main surface.

7. A method for manufacturing a power semiconductor device (20), - To provide a first conductive drift layer (1), - To form at least one well region (2) of a second conductivity type different from the first conductivity type on the first side, - Including forming at least one first doped region (3) of the first conductivity type and at least one second doped region (4) of the second conductivity type on the first side, - A mask is used to form the at least one first doped region (3) such that the interface between the at least one first doped region (3) and the at least one second doped region (4) is structured to be non-uniform in the main extending direction of the at least one well region (2). - The at least one second doped region (4) includes a plurality of parts (10), - The plurality of parts (10) include first parts (11) and second parts (12) that are arranged alternately and continuously along the main extending direction, The maximum doping concentration of the first portion (11) is higher than the maximum doping concentration of the second portion (12). - The plurality of parts (10) are arranged continuously, adjacent to each other, along the main extending direction. - Each of the plurality of parts (10) has a length perpendicular to the main extending direction, - The adjacent first portion (11) and second portion (12) are in direct contact with each other along the main extending direction, - Each first portion (11) has a first length perpendicular to the main extending direction, and each second portion (12) has a second length perpendicular to the main extending direction. A method for manufacturing a power semiconductor element (20), wherein the first length is greater than the second length.

8. - To form the at least one second doped region (4), an additional mask may be used, or A method for manufacturing a power semiconductor device (20) according to claim 7, wherein a self-alignment process is used to form the at least one second doped region (4) so ​​as to structure the interface between the at least one first doped region (3) and the at least one second doped region (4).

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