I / O circuits, semiconductor devices, cell libraries, and semiconductor device circuit design methods.

Abstract

For example, an I / O circuit 140 is formed by combining a plurality of types of standard cells included in a cell library 10, as desired. The plurality of types of standard cells include at least first standard cells 11X and 11Y and a second standard cell 12A. The first standard cells 11X and 11Y comprise first protection elements 11Xa and 11Ya, and a first power supply line L11 formed in a region over the first protection elements 11Xa and 11Ya so as to be in electrical communication with the first protection elements 11Xa and 11Ya. The second standard cell 12A comprises: a second protection element 12a formed in the same layout as the first protection elements 11Xa and 11Ya; and a second power supply line L21 formed in a region over the second protection element 12a so as to be in electrical communication with the second protection element 12a while being separated from the first power supply line L11.

Claims

1. An I / O circuit formed by arbitrarily combining multiple types of standard cells included in a cell library, The aforementioned multiple types of standard cells include at least a first standard cell and a second standard cell, The first standard cell includes a first protective element and a first power line formed in the upper region of the first protective element so as to be electrically connected to the first protective element. The second standard cell is an I / O circuit comprising a second protection element formed in the same layout as the first protection element, and a second power line formed in the upper region of the second protection element so as to be disconnected from the first power line while being electrically connected to the second protection element.

2. The I / O circuit according to claim 1, wherein the plurality of standard cells are arranged along a first direction, and the first power line is laid along the first direction.

3. The I / O circuit according to claim 1, further comprising a third power line formed to be conductive with the first power line across the second power line, wherein the second standard cell further includes the second power line.

4. The first standard cell further includes a first buffer or first resistor formed to connect to the first protection element, and a fourth power line formed in the upper region of the first buffer or first resistor. The I / O circuit according to claim 3, further comprising a second buffer or second resistor formed to connect to the second protection element in the same layout as the first buffer or first resistor, wherein the second standard cell further comprises a second buffer or second resistor.

5. The I / O circuit according to claim 4, wherein the upper region of the second buffer or the second resistor is provided with a fifth power line formed to be disconnected from the fourth power line while being conductive to the second power line, or a non-wiring region for forming the fifth power line.

6. The I / O circuit according to claim 4, wherein the first buffer and the second buffer are, respectively, an input buffer, an output buffer, or an input / output buffer.

7. An I / O circuit according to any one of claims 1 to 6, A first internal circuit connected to the first standard cell and configured to receive power from the first power line, A second internal circuit connected to the second standard cell and configured to receive power from the second power line, A semiconductor device having

8. The semiconductor device according to claim 7, further comprising a pad configured such that the first standard cell and the second standard cell are commonly connected.

9. A cell library containing multiple types of standard cells that can be read from a circuit design program executed on a computer and arbitrarily combined to form an I / O circuit of a semiconductor device, The aforementioned multiple types of standard cells include at least a first standard cell and a second standard cell, The first standard cell includes a first protective element and a first power line formed in the upper region of the first protective element so as to be electrically connected to the first protective element. The cell library includes a second standard cell, a second protection element formed in the same layout as the first protection element, and a second power line formed in the upper region of the second protection element so as to be disconnected from the first power line while being electrically connected to the second protection element.

10. A method for designing a semiconductor device circuit using the cell library of claim 9, The steps include selecting and arranging the multiple types of standard cells included in the cell library and combining them as desired, The steps include laying power lines and signal lines to connect the arbitrarily combined multiple types of standard cells and other circuit blocks, A circuit design method for semiconductor devices, comprising the characteristics of a semiconductor device.

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