Semiconductor device and method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device that suppresses a proof pressure from reducing, and provide a manufacturing method of the semiconductor device.SOLUTION: An IGBT region 10 comprises: an n-type carrier accumulation layer 2 which is provided on a first main surface 1a side of an n-type drift layer 1 so as to be contacted, and has an n-type impurity concentration higher than that of the n-type drift layer 1; a p-type base layer 15 provided between the n-type carrier accumulation layer 2 and the first main surface 1a; an n+type emitter layer 13 selectively provided to a front surface part of the p-type base layer 15; and a gate electrode 11a provided oppositely to the n+type emitter layer 13 and the p-type base layer 15 via an insulation film. A diode region 20 comprises a p-type anode layer 25 which is provided between the n-type drift layer 1 and the first main surface 1a, and is provided up to a position where a depth from the first main surface 1a is deeper than a boundary between the n-type carrier accumulation layer 2 and the n-type drift layer 1.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] A semiconductor device known as an RC-IGBT (Reverse Conducting Insulated Gate Bipolar Transistor) has both an IGBT region and a diode region within a single semiconductor device. Furthermore, a semiconductor device is known in which a carrier storage layer with a higher impurity concentration of the first conductivity type than the drift layer is provided between the first conductivity type drift layer and the second conductivity type base layer of the IGBT region.

[0003] In conventional semiconductor devices, a carrier storage layer was not provided in the diode region, but a carrier storage layer was provided in the IGBT region, and a second carrier storage layer was formed shallower than the first carrier storage layer, which was the central carrier storage layer of the IGBT region, on the boundary side between the IGBT region and the diode region. This made it easier for the field plate effect at the boundary between the IGBT region and the diode region to occur, thereby improving the breakdown voltage (see, for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] International Publication No. 2017 / 141998 [Overview of the project] [Problems that the invention aims to solve]

[0005] However, in conventional semiconductor devices, the electric field acts to concentrate on the second carrier storage layer, which is formed shallower than the first carrier storage layer. This concentration of the electric field in a part of the carrier storage layer leads to a problem where the breakdown voltage decreases.

[0006] This disclosure was made to solve the problems described above, and aims to provide a semiconductor device and a method for manufacturing a semiconductor device that suppress the concentration of electric fields in the carrier storage layer and suppress the decrease in breakdown voltage. [Means for solving the problem]

[0007] The semiconductor device according to this disclosure comprises an IGBT region and a diode region arranged in a first direction along the first main surface on a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface facing the first main surface, the IGBT region having a collector layer of a second conductivity type provided between the drift layer and the second main surface, a carrier storage layer of a first conductivity type provided in contact with the drift layer on the first main surface side of the drift layer and having a higher impurity concentration of the first conductivity type than the drift layer, a base layer of a second conductivity type provided between the carrier storage layer and the first main surface, and the base layer The diode region comprises an emitter layer of a first conductivity type selectively provided on the surface and having a portion of the first main surface, and a gate electrode provided opposite to the emitter layer and the base layer via an insulating film, wherein the diode region comprises a cathode layer of a first conductivity type provided between the drift layer and the second main surface, and an anode layer of a second conductivity type provided between the drift layer and the first main surface and provided at a depth greater from the first main surface than the boundary between the carrier storage layer and the drift layer, wherein the impurity concentration of the second conductivity type in the anode layer is higher than the impurity concentration of the first conductivity type in the carrier storage layer.

[0008] Furthermore, the method for manufacturing a semiconductor device according to the present disclosure includes the steps of: preparing a semiconductor substrate of a first conductivity type having a first main surface and a first region where IGBT regions are formed and a second region where diode regions are formed, arranged in a first direction along the first main surface; forming a first resist mask having a first opening on the first main surface of the first region; forming a carrier storage layer of a first conductivity type by implanting impurity ions of a first conductivity type from the first opening; forming a base layer of a second conductivity type between the first main surface and the carrier storage layer by implanting impurity ions of a second conductivity type from the first opening; forming a second resist mask having a second opening on the first main surface of the second region; and forming an anode layer of a second conductivity type from a position deeper from the first main surface than the depth to which the carrier storage layer is formed, up to the first main surface, by implanting impurity ions of a second conductivity type from the second opening. [Effects of the Invention]

[0009] The semiconductor device described herein can provide a semiconductor device that suppresses the concentration of electric fields in the carrier storage layer and suppresses the decrease in breakdown voltage.

[0010] Furthermore, the semiconductor device manufacturing method described herein provides a method for manufacturing a semiconductor device that suppresses the concentration of electric fields in the carrier storage layer and suppresses the decrease in breakdown voltage. [Brief explanation of the drawing]

[0011] [Figure 1] This is a plan view showing the semiconductor device in Embodiment 1. [Figure 2] This is a plan view showing a semiconductor device with a different configuration in Embodiment 1. [Figure 3] This is a partially enlarged plan view showing the configuration of the IGBT region of the semiconductor device in Embodiment 1. [Figure 4] This is a cross-sectional view showing the configuration of the IGBT region of the semiconductor device in Embodiment 1. [Figure 5] This is a cross-sectional view showing the configuration of the IGBT region of the semiconductor device in Embodiment 1. [Figure 6]This is a partially enlarged plan view showing the configuration of the diode region of the semiconductor device in Embodiment 1. [Figure 7] This is a cross-sectional view showing the configuration of the diode region of the semiconductor device in Embodiment 1. [Figure 8] This is a cross-sectional view showing the configuration of the diode region of the semiconductor device in Embodiment 1. [Figure 9] This is a cross-sectional view showing the configuration of the boundary between the IGBT region and the diode region of the semiconductor device in Embodiment 1. [Figure 10] This is a cross-sectional view showing the configuration of the boundary between the IGBT region and the diode region of another semiconductor device in Embodiment 1. [Figure 11] This is a cross-sectional view showing the configuration of the terminal region of the semiconductor device in Embodiment 1. [Figure 12] This figure shows the method for manufacturing a semiconductor device according to Embodiment 1. [Figure 13] This figure shows the method for manufacturing a semiconductor device according to Embodiment 1. [Figure 14] This figure shows the method for manufacturing a semiconductor device according to Embodiment 1. [Figure 15] This figure shows the method for manufacturing a semiconductor device according to Embodiment 1. [Figure 16] This figure shows the method for manufacturing a semiconductor device according to Embodiment 1. [Figure 17] This figure shows the method for manufacturing a semiconductor device according to Embodiment 1. [Figure 18] This figure shows the method for manufacturing a semiconductor device according to Embodiment 1. [Figure 19] This figure shows the method for manufacturing a semiconductor device according to Embodiment 1. [Figure 20] This is a partially enlarged plan view showing the configuration of the boundary between the IGBT region and the diode region of the semiconductor device in Embodiment 2. [Figure 21] This is a cross-sectional view showing the configuration of the IGBT region, boundary region, and diode region of the semiconductor device in Embodiment 2. [Figure 22]This is a cross-sectional view showing the configuration of the IGBT region, boundary region, and diode region of the semiconductor device in Embodiment 2. [Figure 23] This is a cross-sectional view showing the configuration of the IGBT region, boundary region, and diode region of the semiconductor device in Embodiment 2. [Figure 24] This is a cross-sectional view showing the configuration of the IGBT region, boundary region, and diode region of the semiconductor device in Embodiment 2. [Figure 25] This is a cross-sectional view showing the configuration of the boundary between the IGBT region and the diode region of the semiconductor device in Embodiment 3. [Modes for carrying out the invention]

[0012] Embodiment 1. First, the configuration of the semiconductor device in Embodiment 1 will be described. Figure 1 is a plan view showing the semiconductor device in Embodiment 1.

[0013] In the following description, n and p represent the conductivity types of semiconductors, and in this invention, the first conductivity type is described as n-type and the second conductivity type as p-type. - This indicates that the impurity concentration is lower than n, and n + This indicates that the impurity concentration is higher than n. Similarly, p - This indicates that the impurity concentration is lower than p, and p + This indicates that the impurity concentration is higher than p.

[0014] The semiconductor device 100 shown in Figure 1 is an RC-IGBT in which the IGBT region 10 and the diode region 20 are arranged in a stripe pattern, and can simply be called a "striped" RC-IGBT.

[0015] In Figure 1, the semiconductor device 100 includes IGBT regions 10 and diode regions 20 within a single semiconductor device. The IGBT regions 10 and diode regions 20 are arranged side by side in a first direction (up and down direction on the paper) along the first main surface of the semiconductor substrate constituting the semiconductor device 100. The IGBT regions 10 and diode regions 20 extend from one end to the other end of the semiconductor device 100 and are arranged alternately in a stripe pattern in a direction perpendicular to the extending direction of the IGBT regions 10 and diode regions 20. In Figure 1, three IGBT regions 10 and two diode regions are shown, and all diode regions 20 are shown sandwiched between IGBT regions 10. However, the number of IGBT regions 10 and diode regions 20 is not limited to this; the number of IGBT regions 10 may be three or more, or three or less, and the number of diode regions 20 may be two or more, or two or less. Furthermore, the configuration may be one in which the locations of the IGBT region 10 and the diode region 20 in Figure 1 are swapped, or all IGBT regions 10 may be sandwiched between diode regions 20. Alternatively, one IGBT region 10 and one diode region 20 may be provided adjacent to each other.

[0016] As shown in Figure 1, a pad region 40 is provided adjacent to the IGBT region 10 on the lower side of the paper. The pad region 40 is the region where control pads 41 for controlling the semiconductor device 100 are provided. The IGBT region 10 and the diode region 20 together are called the cell region. A termination region 30 is provided around the combined region of the cell region and the pad region 40 to maintain the breakdown voltage of the semiconductor device 100. A well-known breakdown voltage maintenance structure can be appropriately selected and provided in the termination region 30. For example, the breakdown voltage maintenance structure may be configured by providing an FLR (Field Limiting Ring) on ​​the first main surface side, which is the front side of the semiconductor device 100, where the cell region is surrounded by a p-type termination well layer of a p-type semiconductor, or a VLD (Variation of Lateral Doping) where the cell region is surrounded by a p-type termination well layer with a concentration gradient. The number of ring-shaped p-type termination well layers used in the FLR and the concentration distribution used in the VLD may be appropriately selected according to the breakdown voltage design of the semiconductor device 100. Furthermore, a p-type termination well layer may be provided over almost the entire area of ​​the pad region 40, and IGBT cells or diode cells may be provided in the pad region 40.

[0017] The control pads 41 may be, for example, a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, and temperature sense diode pads 41d and 41e. The current sense pad 41a is a control pad for detecting the current flowing in the cell region of the semiconductor device 100, and is electrically connected to a portion of the IGBT cells or diode cells in the cell region such that when current flows in the cell region of the semiconductor device 100, a current of one-several-thousandth to one-tens-thousandth of the current flowing in the entire cell region flows.

[0018] The Kelvin emitter pad 41b and gate pad 41c are control pads to which a gate drive voltage is applied for on / off control of the semiconductor device 100. The Kelvin emitter pad 41b is electrically connected to the p-type base layer of the IGBT cell, and the gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer are p +They may be electrically connected via a contact layer. The temperature sense diode pads 41d and 41e are control pads electrically connected to the anode and cathode of a temperature sense diode provided on the semiconductor device 100. The temperature of the semiconductor device 100 is measured by measuring the voltage between the anode and cathode of a temperature sense diode (not shown) provided in the cell region.

[0019] Figure 2 is a plan view showing a semiconductor device with a different configuration from Embodiment 1. The semiconductor device 101 shown in Figure 2 is an RC-IGBT in which multiple diode regions 20 are provided in the vertical and horizontal directions, and an IGBT region 10 is provided around the diode regions 20, and can simply be called an "island type" RC-IGBT.

[0020] In Figure 2, the semiconductor device 101 includes an IGBT region 10 and a diode region 20 within a single semiconductor device. The IGBT region 10 and the diode region 20 are arranged side by side in a first direction (up and down direction of the paper) along the first main surface of the semiconductor substrate constituting the semiconductor device 101. Multiple diode regions 20 are arranged side by side in the vertical and horizontal directions within the semiconductor device, and each diode region 20 is surrounded by the IGBT region 10. In other words, multiple diode regions 20 are arranged in an island-like manner within the IGBT region 10. In Figure 2, the diode regions 20 are shown arranged in a matrix with 4 columns in the left-right direction of the paper and 2 rows in the upper-up direction of the paper, but the number and arrangement of diode regions 20 are not limited to this, and it is sufficient for one or more diode regions 20 to be scattered within the IGBT region 10, with each diode region 20 being surrounded by the IGBT region 10.

[0021] Similar to the semiconductor device 100 shown in Figure 1, the semiconductor device 101 has a cell region which is a combination of the IGBT region 10 and the diode region 20. A termination region 30, which has the same configuration as the semiconductor device 100 shown in Figure 1, is provided around the area which is a combination of the cell region and the pad region 40.

[0022] Figure 3 is a partially enlarged plan view showing the configuration of the IGBT region of a semiconductor device that is an RC-IGBT. Figures 4 and 5 are cross-sectional views showing the configuration of the IGBT region of a semiconductor device that is an RC-IGBT. Figure 3 is an enlarged view of the region enclosed by the dashed line 82 in the semiconductor device 100 shown in Figure 1 or the semiconductor device 101 shown in Figure 2. Figure 4 is a cross-sectional view of the semiconductor device 100 or semiconductor device 101 shown in Figure 3 along the dashed line AA, and Figure 5 is a cross-sectional view of the semiconductor device 100 or semiconductor device 101 shown in Figure 3 along the dashed line BB.

[0023] As shown in Figure 3, the IGBT region 10 is provided with active trench gates 11 and dummy trench gates 12 arranged in a stripe pattern. In semiconductor devices 100 and 101, the active trench gates 11 and dummy trench gates 12 extend in a second direction (left-right direction on the plane of the paper) that is perpendicular to the first direction in which the IGBT region 10 and the diode region 20 are aligned.

[0024] The active trench gate 11 is configured with a gate trench electrode 11a provided in a trench formed in a semiconductor substrate via a gate trench insulating film 11b. The dummy trench gate 12 is configured with a dummy trench electrode 12a provided in a trench formed in a semiconductor substrate via a dummy trench insulating film 12b. The gate trench electrode 11a and the dummy trench electrode 12a are IGBT trench electrodes provided in the IGBT region 10. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c and is a gate electrode that switches the ON state and OFF state of the IGBT cell in the IGBT region 10. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode provided on the first main surface of the semiconductor device 100 or semiconductor device 101.

[0025] n + The type emitter layer 13 is provided on both sides of the width direction of the active trench gate 11, in contact with the gate trench insulating film 11b. +The n-type emitter layer 13 is a semiconductor layer having, for example, arsenic (As) or phosphorus (P) as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 17 / cm 3 ~1.0×10 20 / cm 3 . The n + -type emitter layer 13 is provided alternately with the p + -type contact layer 14 along the extending direction of the active trench gate 11. The p + -type contact layer 14 is also provided between two adjacent dummy trench gates 12. The p + -type contact layer 14 is a semiconductor layer having, for example, boron (B) or aluminum (Al) as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 15 / cm 3 ~1.0×10 20 / cm 3 .

[0026] The p + -type contact layer 14 is a semiconductor layer formed by increasing the p-type impurity concentration higher than that of the p-type base layer in the surface layer portion of the p-type base layer in order to make the electrical connection between the emitter electrode and the p-type base layer good. In the present disclosure, the p + -type contact layer 14 is described as a part of the p-type base layer. The p + -type contact layer 14 is not necessarily required, and a configuration in which a p-type base layer is provided instead of the p + -type contact layer 14 in the plan view of FIG. 3 may be adopted.

[0027] As shown in Figure 3, in the IGBT region 10 of semiconductor device 100 or semiconductor device 101, three active trench gates 11 are arranged in a row, followed by three dummy trench gates 12, and then three active trench gates 11 are arranged in a row next to three dummy trench gates 12. The IGBT region 10 is thus configured with alternating sets of active trench gates 11 and dummy trench gates 12. In Figure 3, the number of active trench gates 11 in one set of active trench gates 11 is set to 3, but it is acceptable to have 1 or more. Also, the number of dummy trench gates 12 in one set of dummy trench gates 12 may be 1 or more, and the number of dummy trench gates 12 may be 0. In other words, all trenches provided in the IGBT region 10 may be active trench gates 11. To put it another way, all IGBT trench electrodes may be gate trench electrodes 11a of active trench gates 11.

[0028] Figure 4 is a cross-sectional view of semiconductor device 100 or semiconductor device 101 along the dashed line AA in Figure 3, and is a cross-sectional view of the IGBT region 10. Semiconductor device 100 or semiconductor device 101 is made of an n semiconductor substrate. - It has a type drift layer 1. - The n-type drift layer 1 is a semiconductor layer having, for example, arsenic (As) or phosphorus (p) as an n-type impurity, and the concentration of the n-type impurity is 1.0 × 10⁻⁶. 12 / cm 3 ~1.0×10 15 / cm 3 In Figure 4, the semiconductor substrate is n + Type emitter layer 13 and p + This range extends from the p-type contact layer 14 to the p-type collector layer 16. In Figure 4, n + Type emitter layer 13 and p +The upper edge of the paper of the p-type contact layer 14 is called the first main surface 1a of the semiconductor substrate, and the lower edge of the paper of the p-type collector layer 16 is called the second main surface 1b of the semiconductor substrate. The first main surface 1a of the semiconductor substrate is the main surface on the front side of the semiconductor device 100, and the second main surface 1b of the semiconductor substrate is the main surface on the back side of the semiconductor device 100. In the IGBT region 10, which is the cell region, the semiconductor device 100 has n between the first main surface 1a and the second main surface 1b facing the first main surface 1a. - It has a type drift layer 1.

[0029] As shown in Figure 4, in the IGBT region 10, n - On the first main surface 1a side of the drift layer 1, n - n-type carrier storage layer 2 has a higher concentration of n-type impurities than n-type drift layer 1. - It is provided in contact with the n-type drift layer 1. The n-type carrier storage layer 2 is a semiconductor layer having, for example, arsenic (As) or phosphorus (P) as n-type impurities, and the concentration of n-type impurities is 1.0 × 10⁻⁶ 13 / cm 3 ~1.0×10 17 / cm 3 Therefore, by providing the n-type carrier storage layer 2, the current loss when current flows through the IGBT region 10 can be reduced.

[0030] n-type carrier storage layer 2 is n - n-type impurities are ion-implanted into the semiconductor substrate constituting the n-type drift layer 1, and then the implanted n-type impurities are removed by annealing. - It is formed by diffusion into the semiconductor substrate, which is the drift layer 1. Therefore, n - Near the boundary from the n-type drift layer 1 to the n-type carrier storage layer 2, the concentration distribution shows a gradual increase in n-type impurity concentration. In this disclosure, n - The n-type impurity concentration from the n-type drift layer 1 to the n-type carrier storage layer 2 was measured using the spreading resistance method (SR method). - The n-type impurity concentration in the direction from n-type drift layer 1 to n-type carrier storage layer 2 is n - The position where the average impurity concentration of the drift layer 1 is 2% or more higher is n -This is defined as the boundary between the n-type drift layer 1 and the n-type carrier storage layer 2.

[0031] A p-type base layer 15 is provided on the first main surface 1a side of the n-type carrier storage layer 2. The p-type base layer 15 is a semiconductor layer having, for example, boron (B) or aluminum (Al) as a p-type impurity, and the concentration of the p-type impurity is 1.0 × 10⁻⁶. 12 / cm 3 ~1.0×10 19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11. On the first main surface side of the p-type base layer 15, in contact with the gate trench insulating film 11b of the active trench gate 11, is n + A type emitter layer 13 is provided, and the remaining region is p + A type contact layer 14 is provided. + Type emitter layer 13 and p + The type contact layer 14 constitutes the first main surface 1a of the semiconductor substrate. + As described above, the p-type contact layer 14 is a region of the p-type base layer where the concentration of p-type impurities is higher than that of the p-type base layer 15, and in this disclosure, p + Unless otherwise specified, the p-type contact layer 14 and the p-type base layer 15 are not considered to be the same. + The p-type contact layer 14 and the p-type base layer 15 together are called the p-type base layer.

[0032] Furthermore, the semiconductor device 100 or semiconductor device 101 is n - On the second main surface 1b side of the drift layer 1, n - An n-type buffer layer 3 is provided, in which the concentration of n-type impurities is higher than that of the p-type drift layer 1. The n-type buffer layer 3 is provided to suppress punch-through of the depletion layer extending from the p-type base layer 15 toward the second main surface when the semiconductor device 100 is in the off state. The n-type buffer layer 3 contains, for example, phosphorus (P) or protons (H). + The layer may be formed by injecting ) or by injecting both phosphorus and protons. The concentration of n-type impurities in the n-type buffer layer 3 is 1.0 × 10⁻⁶ 12 / cm 3 ~1.0×1018 / cm 3 Furthermore, semiconductor device 100 or semiconductor device 101 does not have an n-type buffer layer 3, and the region of the n-type buffer layer 3 shown in Figure 4 also contains n - A configuration may also be provided with an n-type drift layer 1. - The drift layer 1 and this layer together can be called the drift layer.

[0033] The semiconductor device 100 or semiconductor device 101 has a p-type collector layer 16 on the second main surface 1b side of the n-type buffer layer 3. - A p-type collector layer 16 is provided between the p-type drift layer 1 and the second main surface 1b. The p-type collector layer 16 is a semiconductor layer having, for example, boron (B) or aluminum (Al) as a p-type impurity, and the concentration of the p-type impurity is 1.0 × 10⁻⁶ 16 / cm 3 ~1.0×10 20 / cm 3 The p-type collector layer 16 constitutes the second main surface 1b of the semiconductor substrate. The p-type collector layer 16 is provided not only in the IGBT region 10 but also in the termination region 30, and the portion of the p-type collector layer 16 provided in the termination region 30 constitutes the p-type termination collector layer. Furthermore, a portion of the p-type collector layer 16 may extend from the IGBT region 10 into the diode region 20.

[0034] As shown in Figure 4, the semiconductor device 100 or semiconductor device 101 penetrates the first main surface 1a of the semiconductor substrate through the p-type base layer 15 and the n-type carrier storage layer 2, - A trench is formed that reaches the drift layer 1. An active trench gate 11 is formed by providing a gate trench electrode 11a in the trench via a gate trench insulating film 11b. The gate trench electrode 11a is connected to the gate trench insulating film 11b via n -It faces the drift layer 1. Furthermore, the dummy trench gate 12 is formed by providing a dummy trench electrode 12a in the trench via a dummy trench insulating film 12b. The dummy trench electrode 12a is connected to the dummy trench insulating film 12b via n - It faces the type drift layer 1. The gate trench insulating film 11b of the active trench gate 11 is made of p-type base layer 15 and n + It is in contact with the p-type emitter layer 13. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 that is in contact with the gate trench insulating film 11b of the active trench gate 11.

[0035] As shown in Figure 4, an interlayer insulating film 4 is provided on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is formed on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not provided, and on the interlayer insulating film 4. The barrier metal 5 may be, for example, a conductor containing titanium (Ti), for example, titanium nitride, or TiSi, which is an alloy of titanium and silicon (Si). As shown in Figure 4, the barrier metal 5 is n + Type emitter layer 13, p + The contact layer 14 and the dummy trench electrode 12a make ohmic contact, n + Type emitter layer 13, p + It is electrically connected to the type contact layer 14 and the dummy trench electrode 12a.

[0036] An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 may be formed from an aluminum alloy such as an aluminum-silicon alloy (Al-Si alloy), or it may be an electrode consisting of multiple layers of metal films formed by electroless plating or electrolytic plating on an electrode made of an aluminum alloy. The plating film formed by electroless plating or electrolytic plating may be, for example, a nickel (Ni) plating film or a copper (CU) plating film. Furthermore, if there are fine regions such as between adjacent interlayer insulating films 4 where good embedding cannot be obtained with the emitter electrode 6, tungsten, which has better embedding properties than the emitter electrode 6, may be placed in the fine regions, and the emitter electrode 6 may be provided on top of the tungsten.

[0037] Furthermore, without providing barrier metal 5, n + Type emitter layer 13, p + An emitter electrode 6 may be provided on the type contact layer 14 and the dummy trench electrode 12a. + The barrier metal 5 may be provided only on the n-type semiconductor layer, such as the n-type emitter layer 13. The barrier metal 5 and the emitter electrode 6 together may be called the emitter electrode. In Figure 4, a configuration is shown in which the interlayer insulating film 4 is not provided on the dummy trench electrode 12a of the dummy trench gate 12, but the interlayer insulating film 4 may be formed on the dummy trench electrode 12a of the dummy trench gate 12. If the interlayer insulating film 4 is formed on the dummy trench electrode 12a of the dummy trench gate 12, the emitter electrode 6 and the dummy trench electrode 12a may be electrically connected in a cross-section different from the cross-section shown in Figure 4.

[0038] A collector electrode 7 is provided on the second main surface 1b side of the p-type collector layer 16. The collector electrode 7 may be made of an aluminum alloy or an aluminum alloy with a plating film, similar to the emitter electrode 6. Alternatively, the collector electrode 7 may have a different configuration from the emitter electrode 6. The collector electrode 7 makes ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0039] FIG. 5 is a cross-sectional view taken along the dashed line B-B in FIG. 3 of the semiconductor device 100 or 101, and is a cross-sectional view of the IGBT region 10. Different from the cross-sectional view taken along the dashed line A-A shown in FIG. 4, an n + -type emitter layer 13 provided on the first main surface side of the semiconductor substrate is not seen in the cross-section taken along the dashed line B-B in FIG. 5. That is, as shown in FIG. 3, the n + -type emitter layer 13 is selectively provided on the first main surface 1a side of the p-type base layer. Here, the p-type base layer mentioned here refers to the p-type base layer formed by combining the p-type base layer 15 and the p + -type contact layer 14.

[0040] FIG. 6 is a partially enlarged plan view showing the configuration of the diode region of the semiconductor device which is an RC-IGBT. FIGS. 7 and 8 are cross-sectional views showing the configuration of the diode region of the semiconductor device which is an RC-IGBT. FIG. 6 is an enlarged view of the region surrounded by the dashed line 83 in the semiconductor device 100 or 101 shown in FIG. 1. FIG. 7 is a cross-sectional view taken along the dashed line C-C of the semiconductor device 100 shown in FIG. 6. FIG. 8 is a cross-sectional view taken along the dashed line D-D of the semiconductor device 100 shown in FIG. 6.

[0041] The diode trench gate 21 extends along the first main surface 1a of the semiconductor device 100 or 101 in a second direction (horizontal direction on the paper) orthogonal to the first direction in which the IGBT region 10 and the diode region 20 are arranged side by side. The diode trench gate 21 is composed of a diode trench electrode 21a provided in a trench formed in the semiconductor substrate of the diode region 20 via a diode trench insulating film 21b. The diode trench electrode 21a faces the n - -type drift layer 1 through the diode trench insulating film 21b.

[0042] A p + -type contact layer 24 and a p-type anode layer 25 are provided between two adjacent diode trench gates 21. The p +The p-type contact layer 24 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 15 / cm 3 ~1.0×10 20 / cm 3 The p-type anode layer 25 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 12 / cm 3 ~1.0×10 19 / cm 3 The p + -type contact layer 24 and the p-type anode layer 25 are alternately provided in the second direction which is the longitudinal direction of the diode trench gate 21.

[0043] FIG. 7 is a cross-sectional view taken along the dashed line C-C in FIG. 6 of the semiconductor device 100 or the semiconductor device 101, and is a cross-sectional view of the diode region 20. The semiconductor device 100 or the semiconductor device 101 has an n - -type drift layer 1 made of a semiconductor substrate also in the diode region 20. The n - -type drift layer 1 of the diode region 20 and the n - -type drift layer 1 of the IGBT region 10 are continuously and integrally formed, and are formed of the same semiconductor substrate. In FIG. 7, the semiconductor substrate is in the range from the p + -type contact layer 24 to the n + -type cathode layer 26. In FIG. 7, the upper end of the p + -type contact layer 24 on the paper surface is called the first main surface 1a of the semiconductor substrate, and the lower end of the n + -type cathode layer 26 on the paper surface is called the second main surface 1b of the semiconductor substrate. The first main surface 1a of the diode region 20 and the first main surface 1a of the IGBT region are the same surface, and the second main surface 1b of the diode region 20 and the second main surface 1b of the IGBT region are the same surface.

[0044] As shown in FIG. 7, different from the IGBT region 10, the diode region 20 has a p-type anode layer 25 provided on the first main surface 1a side of the n - -type drift layer 1. The p-type anode layer 25 is n- It is provided between the type drift layer 1 and the first main surface 1a. The p-type anode layer 25 is located between the n-type carrier storage layer 2 of the IGBT region 10 and n - It is provided at a depth greater than the boundary with the p-type drift layer 1 from the first main surface 1a. That is, the p-type anode layer 25 and n - The depth from the first main surface 1a where the boundary with the n-type drift layer 1 is located is the distance between the n-type carrier storage layer 2 and n - The boundary with the p-type drift layer 1 is located at a depth greater than the first main surface 1a. By forming the p-type anode layer 25 at a depth greater than the n-type carrier storage layer 2 in this way, the electric field concentration on the n-type carrier storage layer 2 is suppressed in the semiconductor device 100 or semiconductor device 101, and the decrease in breakdown voltage can be suppressed.

[0045] The p-type anode layer 25 is a semiconductor layer having p-type impurities such as boron (B) or aluminum (Al), and the concentration of the p-type impurities is 1.0 × 10⁻⁶. 12 / cm 3 ~1.0×10 19 / cm 3 Therefore, the p-type impurity concentration in the p-type anode layer is higher than the n-type impurity concentration in the n-type carrier storage layer 2 of the IGBT region 10. The p-type anode layer 25 may have the same concentration of p-type impurities as the p-type base layer 15 of the IGBT region 10. Alternatively, the concentration of p-type impurities in the p-type anode layer 25 may be lower than that of the p-type impurities in the p-type base layer 15 of the IGBT region 10 to reduce the amount of holes injected into the diode region 20 during diode operation. Reducing the amount of holes injected during diode operation can reduce recovery losses during diode operation.

[0046] On the first main surface 1a side of the p-type anode layer 25, + A type contact layer 24 is provided. + The concentration of p-type impurities in the type contact layer 24 is the same as the p-type impurity in the IGBT region 10. + The concentration of the p-type impurities in the type contact layer 14 may be the same as, or it may be a different concentration. + The type contact layer 24 constitutes the first main surface 1a of the semiconductor substrate.+ The p-type contact layer 24 is a region where the concentration of p-type impurities is higher than that of the p-type anode layer 25. + When it is necessary to distinguish between the type contact layer 2414 and the p-type anode layer 25, they may be referred to individually. + The p-type contact layer 24 and the p-type anode layer 25 together may be referred to as the p-type anode layer.

[0047] Furthermore, as shown in Figure 7, in the diode region 20 of semiconductor device 100 or semiconductor device 101, similar to the IGBT region 10, n - An n-type buffer layer 3 is provided on the second main surface 1b side of the type drift layer 1. The n-type buffer layer 3 of the diode region 20 may be continuously and integrally formed with the n-type buffer layer 3 of the IGBT region 10. - The n-type drift layer 1 and the n-type buffer layer 3 together can be called the drift layer.

[0048] In the diode region 20, on the second main surface 1b side of the n-type buffer layer 3, n + A type cathode layer 26 is provided. + The type cathode layer 26 is n - It is provided between the mold drift layer 1 and the second main surface 1b. + The n-type cathode layer 26 is a semiconductor layer having, for example, arsenic (As) or phosphorus (P) as an n-type impurity, and the concentration of the n-type impurity is 1.0 × 10⁻⁶. 16 / cm 3 ~1.0×10 21 / cm 3 n + The cathode layer 26 is provided in part or all of the diode region 20. + The cathode layer 26 constitutes the second main surface 1b of the semiconductor substrate. Although not shown in the figure, as described above, n + In the region where the type cathode layer 26 is formed, p-type impurities are further selectively injected, + A portion of the region where the type cathode layer 26 is formed is used as a p-type semiconductor. + A type cathode layer may be provided. For example, n + Type cathode layer and p +The cathode layer and other elements may be arranged alternately along the second main surface 1b of the semiconductor substrate, and diodes with such a configuration are known as RFC (Relaxed Field of Cathode) diodes.

[0049] As shown in Figure 7, the diode region 20 of the semiconductor device 100 or semiconductor device 101 has a first main surface 1a of the semiconductor substrate that penetrates the p-type anode layer 25, and n - A trench is formed that reaches the drift layer 1. The diode trench gate 21 is formed by providing a diode trench electrode 21a within the trench of the diode region 20 via a diode trench insulating film 21b. The diode trench electrode 21a is via the diode trench insulating film 21b - It is facing the drift layer 1.

[0050] As shown in Figure 7, the diode trench electrode 21a and p + A barrier metal 5 is provided on the type contact layer 24. The barrier metal 5 is provided on the diode trench electrodes 21a and p + The type contact layer 24 makes ohmic contact with the diode trench electrode and p + It is electrically connected to the type contact layer 24. The barrier metal 5 may have the same configuration as the barrier metal 5 of the IGBT region 10. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 provided in the diode region 20 is formed continuously with the emitter electrode 6 provided in the IGBT region 10. In addition, as in the case of the IGBT region 10, the diode trench electrodes 21a and p + The p-type contact layer 24 and the emitter electrode 6 may be in ohmic contact. Alternatively, a barrier metal 5 may be provided in the IGBT region 10, but not in the diode region 20. In this case, the p-type impurity concentration in the p-type anode layer of the diode region 20 may be lower than the p-type impurity concentration in the p-type base layer of the IGBT region 10.

[0051] Although Figure 7 shows a configuration in which the interlayer insulating film 4 is not provided on the diode trench electrode 21a of the diode trench gate 21, the interlayer insulating film 4 may be formed on the diode trench electrode 21a of the diode trench gate 21. If the interlayer insulating film 4 is formed on the diode trench electrode 21a of the diode trench gate 21, the emitter electrode 6 and the diode trench electrode 21a can be electrically connected in a cross-section different from the cross-section shown in Figure 7.

[0052] n + A collector electrode 7 is provided on the second main surface side of the cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 of the diode region 20 is formed continuously with the collector electrode 7 provided in the IGBT region 10. The collector electrode 7 is n + Ohmic contact is made with the type cathode layer 26, n + It is electrically connected to the cathode layer 26.

[0053] Figure 8 is a cross-sectional view of semiconductor device 100 or semiconductor device 101 along the dashed line DD in Figure 6, and is a cross-sectional view of the diode region 20. Compared to the cross-sectional view along the dashed line CC shown in Figure 7, a p-type anode layer 25 and a barrier metal 5 are separated by a p-type anode layer 25. + The difference is that there is no p-type contact layer 24, and the p-type anode layer 25 constitutes the first main surface of the semiconductor substrate. In other words, as shown in Figure 7, p + The type contact layer 24 is selectively provided on the first main surface side of the p-type anode layer 25.

[0054] Figure 9 is a cross-sectional view showing the boundary configuration between the IGBT region and the diode region of a semiconductor device that is an RC-IGBT. Figure 9 is a cross-sectional view along the dashed line GG in the semiconductor device 100 shown in Figure 1 or the semiconductor device 101 shown in Figure 2.

[0055] As shown in Figure 9, the semiconductor device 100 or 101 has a boundary region 50 between the IGBT region 10 and the diode region 20. The boundary region 50 is provided between the IGBT trench electrode closest to the diode region 20 among the IGBT trench electrodes, which are a collective term for the gate trench electrode 11a and dummy trench electrode 12a of the IGBT region 10, and the diode trench electrode closest to the IGBT region 10 among the diode trench electrodes 21a of the diode region 20.

[0056] In this disclosure, an IGBT trench electrode penetrates the p-type base layer 15 from the first main surface 1a of the semiconductor substrate. - The IGBT trench electrode is provided in a trench reaching the type drift layer 1, with an insulating film in between. The IGBT trench electrode has two opposing sides facing each other, with the insulating film in between, facing the p-type base layer 15. The IGBT trench electrode is either a gate trench electrode 11a or a dummy trench electrode 12a. In this disclosure, the gate trench electrode 11a and the dummy trench electrode 12a are referred to as IGBT trench electrodes without distinction.

[0057] Furthermore, in this disclosure, the diode trench electrode 21a penetrates the p-type anode layer 25 from the first main surface 1a of the semiconductor substrate and n - The trench electrode is provided in a trench reaching the p-type drift layer 1, with an insulating film in between. The diode trench electrode 21a has two opposing sides facing the p-type anode layer 25 via the insulating film. Also, as shown in Figure 9, the diode trench electrode 21a has an n on the second main surface 1b side of the p-type anode layer 25, which faces it via the insulating film. + This is the diode trench electrode where the cathode layer 26 is located.

[0058] As shown in Figure 9, the boundary region 50 is n - A p-type collector layer 16 is provided between the type drift layer 1 and the second main surface 1b. The boundary between the boundary region 50 and the diode region 20 is the p-type collector layer 16 provided on the second main surface 1b side. +It can be defined as the boundary with the p-type cathode layer 26. In this way, by providing the p-type collector layer 16 in the boundary region 50 between the IGBT region 10 and the diode region 20, the n of the diode region 20 + The distance between the cathode layer 26 and the active trench gate 11 of the IGBT region 10 can be increased, and even when a gate drive voltage is applied to the gate trench electrode 11a during freewheeling diode operation, the channel formed adjacent to the active trench gate 11 of the IGBT region 10 can be increased. + This makes it possible to suppress the flow of current through the cathode layer 26.

[0059] Figure 10 is a cross-sectional view showing the boundary configuration between the IGBT region and the diode region of another RC-IGBT semiconductor device. Similar to Figure 9, Figure 10 is a cross-sectional view along the dashed line GG in the semiconductor device 100 shown in Figure 1 or the semiconductor device 101 shown in Figure 2. In Figure 9, no trench electrodes are provided in the boundary region 50, but as shown in Figure 10, from the first main surface 1a to n - One or more boundary trench electrodes 51a, provided in trenches that reach the mold drift layer via an insulating film, may be provided in the boundary region 50. The width U1 of the boundary region 50 may be, for example, 100 μm. Depending on the application of the semiconductor device 100 or semiconductor device 101, which is an RC-IGBT, the width U1 of the boundary region 50 may be less than 100 μm, and may be the same width as the distance between adjacent trenches.

[0060] As shown in Figures 9 and 10, in the semiconductor device 100 or semiconductor device 101, the n-type carrier storage layer 2 and the p-type anode layer 25 are in contact at the boundary region 50. - The boundary with the n-type drift layer 1 is between the n-type carrier storage layer 2 and n -The p-type anode layer 25 is located at a depth greater from the first main surface 1a than the boundary with the n-type drift layer 1. In the semiconductor device 100 or semiconductor device 101 of this disclosure, the p-type anode layer 25 is located at a depth greater than the n-type carrier storage layer 2, thereby suppressing electric field concentration on the n-type carrier storage layer 2 and thus suppressing a decrease in breakdown voltage. In Figure 10, the contact point between the n-type carrier storage layer 2 and the p-type anode layer 25 is located between the dummy trench electrode 12a, which is the IGBT trench electrode closest to the diode region 20, and the boundary trench electrode 50a. However, the contact point between the n-type carrier storage layer 2 and the p-type anode layer 25 is not particularly limited as long as it is within the boundary region 50.

[0061] In Figures 9 and 10, the IGBT trench electrode closest to the diode region 20 is shown as a dummy trench electrode 12a electrically connected to the emitter electrode 6. However, the IGBT trench electrode closest to the diode region 20 may also be a gate trench electrode 11a electrically connected to the gate pad 41c. As shown in Figures 9 and 10, using a dummy trench electrode 12a electrically connected to the emitter electrode 6 as the IGBT trench electrode closest to the diode region 20 prevents the boundary region 50 from contributing to the switching operation. This suppresses the impact of the boundary region 50 on the switching operation while also suppressing a decrease in breakdown voltage.

[0062] Figure 11 is a cross-sectional view showing the configuration of the termination region of a semiconductor device that is an RC-IGBT. Figure 11(a) is a cross-sectional view along the dashed line EE in Figure 1 or Figure 2, showing the cross-section from the IGBT region 10 to the termination region 30. Figure 11(b) is a cross-sectional view along the dashed line FF in Figure 1, showing the cross-sectional view from the diode region 20 to the termination region 30.

[0063] As shown in Figures 11(a) and 11(b), the termination region 30 of the semiconductor device 100 is between the first main surface 1a and the second main surface 1b of the semiconductor substrate n -It has a type drift layer 1. The first main surface 1a and the second main surface 1b of the termination region 30 are the same surface as the first main surface 1a and the second main surface 1b of the IGBT region 10 and the diode region 20, respectively. - The drift layer 1 consists of n of the IGBT region 10 and the diode region 20, respectively. - It has the same configuration as the drift layer 1 and is formed continuously and integrally.

[0064] n - The first main surface 1a side of the drift layer 1, that is, the first main surface 1a of the semiconductor substrate and n - A p-type termination well layer 31 is provided between the p-type drift layer 1 and the other layer. The p-type termination well layer 31 is a semiconductor layer having, for example, boron (B) or aluminum (Al) as a p-type impurity, and the concentration of the p-type impurity is 1.0 × 10⁻¹⁶. 14 / cm 3 ~1.0×10 19 / cm 3 The p-type termination well layer 31 is provided surrounding the cell region which includes the IGBT region 10 and the diode region 20. The p-type termination well layer 31 is formed to a depth greater than the n-type carrier storage layer and to a depth greater than the trenches formed in the IGBT region 10 and the diode region 20. Multiple p-type termination well layers 31 are provided in a ring shape, and the number of p-type termination well layers 31 is appropriately selected according to the breakdown voltage design of the semiconductor device 100 or semiconductor device 101. Furthermore, on the outer edge of the p-type termination well layer 31 there is an n + A channel stopper layer 32 is provided, n + The p-type channel stopper layer 32 surrounds the p-type termination well layer 31.

[0065] n -A p-type termination collector layer 16a is provided between the p-type drift layer 1 and the second main surface 1b of the semiconductor substrate. The p-type termination collector layer 16a is formed integrally with the p-type collector layer 16 provided in the cell region. Therefore, the p-type termination collector layer 16a may also be included in the term p-type collector layer 16. Furthermore, in a configuration that can accommodate the diode region 20 being adjacent to the termination region 30, as shown in Figure 11(b), the end of the p-type termination collector layer 16a on the diode region 20 side extends into the diode region 20 by a distance U2. By providing the p-type termination collector layer 16a extending into the diode region 20 in this way, the n of the diode region 20 can be + The distance between the p-type cathode layer 26 and the p-type termination well layer 31 can be increased, thereby suppressing the p-type termination well layer 31 from acting as the anode of the diode. The distance U2 may be, for example, 100 μm.

[0066] A collector electrode 7 is provided on the second main surface 1b of the semiconductor substrate. The collector electrode 7 is formed integrally and continuously from the cell region, which includes the IGBT region 10 and the diode region 20, to the termination region 30. On the other hand, on the first main surface of the semiconductor substrate in the termination region 30, an emitter electrode 6 that is continuous with the cell region and a termination electrode 6a that is separated from the emitter electrode 6 are provided.

[0067] The emitter electrode 6 and the termination electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 may be, for example, sinSiN (semi-insulating silicon nitride). The termination electrode 6a and the p-type termination well layer 31 and n + The channel stopper layer 32 is electrically connected to the terminal region 30 via a contact hole formed in the interlayer insulating film 4 provided on the first main surface of the terminal region 30. Furthermore, a terminal protective film 34 is provided in the terminal region 30, covering the emitter electrode 6, the terminal electrode 6a, and the semi-insulating film 33. The terminal protective film 34 may be formed from, for example, polyimide.

[0068] Next, a method for manufacturing the semiconductor device 100 or semiconductor device 101 of this disclosure will be described.

[0069] Figures 12 to 19 show the manufacturing method for a semiconductor device that is an RC-IGBT. Figures 12 to 17 show the process of forming the front side of the semiconductor device 100 or semiconductor device 101, and Figures 18 and 19 show the process of forming the back side of the semiconductor device 100 or semiconductor device 101.

[0070] First, as shown in Figure 12(a), n - Prepare the semiconductor substrate that constitutes the n-type drift layer 1. The semiconductor substrate may be, for example, a so-called FZ wafer fabricated by the FZ (Floating Zone) method, or a so-called MCZ wafer fabricated by the MCZ (Magnetic applied CZochralki) method, and may be an n-type wafer containing n-type impurities. The concentration of n-type impurities contained in the semiconductor substrate is appropriately selected according to the breakdown voltage of the semiconductor device to be fabricated. For example, in a semiconductor device with a breakdown voltage of 1200V, the n-type impurities constituting the semiconductor substrate are used. - The concentration of n-type impurities is adjusted so that the resistivity of the n-type drift layer 1 is approximately 40 to 120 Ω·cm. As shown in Figure 12(a), in the process of preparing the semiconductor substrate, the entire semiconductor substrate is n - Although it is a type drift layer 1, p-type or n-type impurity ions are implanted from the first main surface 1a side or the second main surface 1b side of such a semiconductor substrate, and then diffused into the semiconductor substrate by heat treatment or the like to form a p-type or n-type semiconductor layer, thereby manufacturing the semiconductor device 100 or semiconductor device 101.

[0071] As shown in Figure 12(a), n -The semiconductor substrate constituting the p-type drift layer 1 includes regions that will become an IGBT region 10, a diode region 20, and a boundary region 50. Although not shown in the figures, the area surrounding the regions that will become the IGBT region 10, the diode region 20, and the boundary region 50 also includes a region that will become a termination region 30. The following description will mainly focus on the manufacturing method of the IGBT region 10, the diode region 20, and the boundary region 50 of the semiconductor device 100 or semiconductor device 101, but the termination region 30 of the semiconductor device 100 or semiconductor device 101 may be manufactured by a well-known manufacturing method. For example, when forming an FLR having a p-type termination well layer 31 as a voltage-resistant holding structure in the termination region 30, the p-type impurity ions may be implanted before processing the IGBT region 10 and the diode region 20 of the semiconductor device 100 or semiconductor device 101, or the p-type impurity ions may be implanted simultaneously when ion-implanting p-type impurities into the IGBT region 10 or the diode region 20 of the semiconductor device 100.

[0072] Next, as shown in Figure 12(b), a first resist mask, a resist mask 60, is formed on the first main surface 1a of the semiconductor substrate in the region that will become the diode region 20, and a masking process is performed. In this disclosure, masking refers to the process of forming a mask on the semiconductor substrate in order to apply a resist to the semiconductor substrate, form an opening in a predetermined region of the resist using photolithography technology, and then perform ion implantation or etching on a predetermined region of the semiconductor substrate through the opening. As shown in Figure 12(b), the resist mask 60 has an opening 60a, which is the first opening, in the region that will become the IGBT region 10. The resist mask 60 is provided so that its edges extend from the region that will become the diode region 20 to the region that will become the boundary region 50 on the first main surface 1a of the semiconductor substrate. In other words, the resist mask 60 has openings 60a in the region that will become the IGBT region 10 and a part of the region that will become the boundary region 50 on the first main surface 1a of the semiconductor substrate, and the ends of the openings 60a of the resist mask 60 are located at a distance a from the boundary between the region that will become the IGBT region 10 and the region that will become the boundary region 50 toward the diode region 20.

[0073] After forming a resist mask 60 on the first main surface 1a of the semiconductor substrate, n-type impurities such as phosphorus (P) are injected from the first main surface 1a side of the semiconductor substrate to form an n-type carrier storage layer 2 in the IGBT region 10 and a part of the boundary region 50, as shown in Figure 12(b). The n-type carrier storage layer 2 consists of a p-type anode layer 25 and n - It is formed at a shallower position than the boundary of the n-type drift layer 1. As shown in Figure 12(b), at the edge of the n-type carrier storage layer 2 on the diode region 20 side, it is formed at a shallower depth from the first main surface 1a than the n-type carrier storage layer 2 of the IGBT region 10.

[0074] Next, as shown in Figure 13(a), p-type impurities such as boron (B) are implanted from the first main surface 1a side of the semiconductor substrate to form a p-type base layer 15. Since the p-type base layer 15 is formed by a masking process using the resist mask 60 used when forming the n-type carrier storage layer 2, the p-type base layer 15 is formed in the IGBT region 10 and a part of the boundary region 50. After implanting impurity ions into the IGBT region 10 and a part of the boundary region 50 of the semiconductor substrate to form the n-type carrier storage layer 2 and the p-type base layer 15, the semiconductor substrate is heat-treated to diffuse the impurity ions implanted in the n-type carrier storage layer 2 and the p-type base layer 15 into the semiconductor substrate.

[0075] Next, as shown in Figure 13(b), a second resist mask, a resist mask 61, is formed on the first main surface 1a of the semiconductor substrate in the region that will become the IGBT region 10, and a masking process is performed. Then, p-type impurity ions are implanted from the first main surface 1a side of the semiconductor substrate to form a p-type anode layer 25. As shown in Figure 13(b), the resist mask 61 has a second opening, an opening 61a, in the region that will become the diode region 20. The end of the resist mask 61 extends by a distance b from the region that will become the IGBT region 10 on the first main surface 1a of the semiconductor substrate to the region that will become the boundary region 50. That is, the resist mask 61 has an opening 61a in the region that will become the diode region 20 and a part of the region that will become the boundary region 50 on the first main surface 1a of the semiconductor substrate, and the end of the opening 61a of the resist mask 61 is located at a distance b from the boundary between the region that will become the IGBT region 10 and the region that will become the boundary region 50 towards the diode region 20 side.

[0076] The distance b shown in Figure 13(b) is smaller than the distance a shown in Figure 13(a), and is set so that the portion of the n-type carrier storage layer 2 at the diode region 20 side end that is shallower from the first main surface 1a is located at the opening 61a of the resist mask 61. That is, the opening 60a of the resist mask 60 and the opening 61a of the resist mask 61 are formed to partially overlap in the boundary region 50. Therefore, the end of the p-type anode layer 25 on the IGBT region 10 side is formed superimposed on the region where the n-type carrier storage layer 2 and the diode region 20 side end of the p-type base layer 15 are formed. By making the p-type impurity concentration of the p-type anode layer 25 higher than the n-type impurity concentration of the n-type carrier storage layer 2, the region where the region in which n-type impurity ions were implanted to form the n-type carrier storage layer 2 and the region in which p-type impurity ions were implanted to form the p-type anode layer 25 overlap becomes a p-type semiconductor layer and becomes part of the p-type anode layer 25. As a result, a configuration can be achieved in which the n-type carrier storage layer 2 and the p-type anode layer 25 are in contact at the boundary region 50. Furthermore, since the portion of the n-type carrier storage layer 2 at the diode region 20 side where the depth from the first main surface 1a is shallow is canceled out with p-type impurities at a higher concentration than the n-type impurities in the n-type carrier storage layer 2 to form the p-type anode layer 25, the concentration of the electric field at the edge of the n-type carrier storage layer 2 can be suppressed, and the breakdown voltage reduction can be suppressed.

[0077] After forming a p-type anode layer 25 by implanting p-type impurity ions into the diode region 20 and a portion of the boundary region 50 of the semiconductor substrate, the semiconductor substrate is heat-treated to diffuse the impurity ions implanted in the p-type anode layer 25 into the semiconductor substrate. Note that the heat treatment for diffusing impurity ions in the n-type carrier storage layer 2 and the p-type base layer 15, and the heat treatment for diffusing impurity ions in the p-type anode layer 25 may be performed simultaneously. By simultaneously performing the heat treatment for diffusing impurity ions in the n-type carrier storage layer 2, the p-type base layer 15, and the p-type anode layer 25, the number of diffusion cycles for impurity ions in the n-type carrier storage layer 2, which has a lower impurity concentration than the p-type base layer 15 and the p-type anode layer 25, can be reduced, making it easier to form an n-type carrier storage layer 2 of a predetermined thickness.

[0078] Another method for forming the n-type carrier storage layer 2 and the p-type anode layer 25 is to form the p-type anode layer 25 before the n-type carrier storage layer 2. Figure 14 shows a manufacturing method when the p-type anode layer 25 is formed before the n-type carrier storage layer 2. The steps shown in Figures 14(a) and 14(b) can be applied in place of the steps shown in Figures 12(b), 13(a), and 13(b).

[0079] As shown in Figure 12(a), n - After preparing the semiconductor substrate constituting the p-type drift layer 1, a resist mask 61 is formed on the first main surface 1a of the semiconductor substrate in the region that will become the IGBT region 10, as shown in Figure 14(a), and a masking process is performed. Then, p-type impurity ions are implanted from the first main surface 1a side of the semiconductor substrate to form the p-type anode layer 25. Similar to Figure 13(b), the resist mask 61 is provided with its edges extending by a distance b from the region that will become the IGBT region 10 to the region that will become the boundary region 50. After implanting p-type impurity ions into the diode region 20 and a part of the boundary region 50 of the semiconductor substrate to form the p-type anode layer 25, the semiconductor substrate is heat-treated to diffuse the impurity ions implanted in the p-type anode layer 25 into the semiconductor substrate.

[0080] Next, as shown in Figure 14(b), a resist mask 60 is formed on the first main surface 1a of the semiconductor substrate in the region that will become the diode region 20, and a masking process is performed. As shown in Figure 12(b), the resist mask 60 is provided with an opening so that the end of the p-type anode layer 25 on the IGBT region 10 side is exposed on the first main surface 1a. The resist mask 60 has openings in the region that will become the IGBT region 10 and a part of the region that will become the boundary region 50 on the first main surface 1a of the semiconductor substrate, and the end of the opening of the resist mask 60 is located at a distance a from the boundary between the region that will become the IGBT region 10 and the region that will become the boundary region 50 toward the diode region 20. The distance a shown in Figure 14(a) is greater than the distance b shown in Figure 14(a).

[0081] After forming a resist mask 60 on the first main surface 1a of the semiconductor substrate, n-type impurity ions are implanted from the first main surface 1a side of the semiconductor substrate to form an n-type carrier storage layer 2, and p-type impurity ions are implanted to form a p-type base layer 15. The n-type carrier storage layer 2 consists of a p-type anode layer 25 and n - The n-type carrier storage layer 2 is formed at a position shallower than the boundary with the n-type drift layer 1. Ion implantation for forming the n-type carrier storage layer 2 and ion implantation for forming the p-type base layer 15 can be performed in either order. Although n-type impurity ions for forming the n-type carrier storage layer 2 are also implanted at the edges of the p-type anode layer 25 located at the opening of the resist mask 60, the p-type impurity concentration of the p-type anode layer 25 is higher than that of the n-type carrier storage layer 2. Therefore, even if n-type impurity ions are implanted at the edges of the p-type anode layer 25, the edges of the p-type anode layer 25 maintain their p-type semiconductor layer structure. As a result, a configuration can be achieved in which the n-type carrier storage layer 2 and the p-type anode layer 25 are in contact at the boundary region 50. Furthermore, since the n-type impurities are injected only to a depth shallower than the n-type carrier storage layer 2 in the IGBT region 10, the end of the n-type carrier storage layer 2 on the diode region 20 side can be embedded in the p-type anode layer 25. This suppresses the formation of shallow portions in the n-type carrier storage layer 2 from the first main surface 1a, thereby suppressing the concentration of the electric field at the end of the n-type carrier storage layer 2 and suppressing a decrease in breakdown voltage.

[0082] After forming the n-type carrier storage layer 2 and the p-type base layer 15, the semiconductor substrate is heat-treated to diffuse the impurity ions implanted in the n-type carrier storage layer 2 and the p-type base layer 15 into the semiconductor substrate. In this way, by implanting impurity ions for forming the p-type anode layer 25 before implanting impurity ions for forming the n-type carrier storage layer, only the p-type anode layer 25 can have its impurity ions diffused into the semiconductor substrate by heat treatment. This reduces the number of times impurity ions need to be diffused by heat treatment of the n-type carrier storage layer 2, making it easier to form the n-type carrier storage layer 2 as designed.

[0083] Furthermore, the p-type termination well layer 31 formed in the termination region 30 of the semiconductor device 100 or semiconductor device 101 may be formed by implanting p-type impurity ions simultaneously with the p-type anode layer 25. In this case, the depth and p-type impurity concentration of the p-type termination well layer 31 and the p-type anode layer 25 will be the same. Also, in the masking process when forming the p-type termination well layer 31 and the p-type anode layer 25, by using a mesh-like mask for the mask formed in the region where the p-type termination well layer 31 is formed or the region where the p-type anode layer 25 is formed, and changing the aperture ratio, the p-type impurity concentrations of the p-type termination well layer 31 and the p-type anode layer 25 can be made different even if p-type impurity ions are implanted into the p-type termination well layer 31 and the p-type anode layer 25 simultaneously. Alternatively, by implanting p-type impurity ions into the p-type termination well layer 31 and the p-type anode layer 25 separately through masking, the depths of the p-type termination well layer 31 and the p-type anode layer 25 may be made different, and the p-type impurity concentrations may be made different.

[0084] Next, as shown in Figure 15(a), n-type impurities are selectively injected into the first main surface 1a side of the p-type base layer 15 of the IGBT region 10 by masking. + A type emitter layer 13 is formed. The n-type impurity to be implanted may be, for example, arsenic (As) or phosphorus (P). Alternatively, by masking, p-type impurities can be selectively implanted into the first main surface 1a side of the p-type base layer 15 of the IGBT region 10. + A type contact layer 14 is formed, and p-type impurities are selectively injected into the first main surface 1a side of the p-type anode layer 25 of the diode region 20. + A p-type contact layer 24 is formed. The p-type impurity to be injected may be, for example, boron (B) or aluminum (Al).

[0085] Next, as shown in Figure 15(b), the p-type base layer 15 and the p-type anode layer 25 are penetrated from the first main surface 1a side of the semiconductor substrate, n - A trench 8 is formed that reaches the drift layer 1. In Figure 15(b), no trench 8 is formed in the boundary region 50, but one or more trenches 8 may be formed in the boundary region 50. In the IGBT region 10, n+ The trench 8 that penetrates the type emitter layer 13 has side walls n + It constitutes a part of the type emitter layer 13. The trenches 8 may be formed by depositing an oxide film such as SiO2 on a semiconductor substrate, then creating openings in the oxide film in the area where the trenches 8 will be formed by a masking process, and finally etching the semiconductor substrate using the oxide film with the openings as a mask. In Figure 15(b), the pitch of the trenches 8 is the same in the IGBT region 10 and the diode region 20, but the pitch of the trenches 8 may be different in the IGBT region 10 and the diode region 20. The pattern of the trenches 8 in a plan view can be appropriately changed by the mask pattern of the masking process.

[0086] Next, as shown in Figure 16(a), the semiconductor substrate is heated in an oxygen-containing atmosphere to form an oxide film 9 on the inner walls of the trenches 8 and on the first main surface 1a of the semiconductor substrate. Of the oxide film 9 formed on the inner walls of the trenches 8, the oxide film 9 formed in the trenches 8 of the IGBT region 10 is the gate trench insulating film 11b of the active trench gate 11 and the dummy trench insulating film 12b of the dummy trench gate 12. The oxide film 9 formed in the trenches 8 of the diode region 20 is the diode trench insulating film 21b. The oxide film 9 formed on the first main surface 1a of the semiconductor substrate is removed in a later process.

[0087] Next, as shown in Figure 16(b), polysilicon doped with n-type or p-type impurities is deposited in the trench 8, on which an oxide film 9 is formed on the inner wall, by CVD (Chemical Vapor Deposition) or the like, to form a gate trench electrode 11a, a dummy trench electrode 12a, and a diode trench electrode 21a.

[0088] Next, as shown in Figure 17(a), an interlayer insulating film 4 is formed on the gate trench electrode 11a of the active trench gate 11 of the IGBT region 10, and then the oxide film 9 formed on the first main surface 1a of the semiconductor substrate is removed. The interlayer insulating film 4 may be, for example, SiO2. Then, contact holes are formed in the deposited interlayer insulating film 4 by masking. The contact holes are n + On type emitter layer 13, p + On the type contact layer 14, p + It is formed on the mold contact layer 24, on the dummy trench electrode 12a, and on the diode trench electrode 21a.

[0089] Next, as shown in Figure 17(b), a barrier metal 5 is formed on the first main surface 1a and the interlayer insulating film 4 of the semiconductor substrate, and then an emitter electrode 6 is formed on the barrier metal 5. The barrier metal 5 is formed by depositing titanium nitride using PDV (Physical Vapor Deposition) or CVD.

[0090] The emitter electrode 6 may be formed by depositing an aluminum-silicon alloy (Al-Si alloy) onto the barrier metal 5, for example, by PVD such as sputtering or vapor deposition. Alternatively, a nickel alloy (Ni alloy) or copper alloy (Cu alloy) may be further formed on the formed aluminum-silicon alloy by electroless plating or electrolytic plating to form the emitter electrode 6. Forming the emitter electrode 6 by plating allows for the easy formation of a thick metal film, thereby increasing the heat capacity of the emitter electrode 6 and improving its heat resistance. When forming the emitter electrode 6 from an aluminum-silicon alloy by PVD and then further forming a nickel alloy or copper alloy by plating, the plating process for forming the nickel alloy or copper alloy may be performed after processing the second main surface side of the semiconductor substrate.

[0091] Next, as shown in Figure 18(a), the second main surface 1b side of the semiconductor substrate is ground to thin the semiconductor substrate to the predetermined thickness designed. The thickness of the semiconductor substrate after grinding may be, for example, 80 μm to 200 μm.

[0092] Next, as shown in Figure 18(b), n-type impurities are injected from the second main surface 1b side of the semiconductor substrate to form an n-type buffer layer 3. Furthermore, p-type impurities are injected from the second main surface 1b side of the semiconductor substrate to form a p-type collector layer 16. The n-type buffer layer 3 may be formed in the IGBT region 10, the diode region 20, the boundary region 50, and the termination region 30, or it may be formed only in the IGBT region 10 or the diode region 20.

[0093] The n-type buffer layer 3 may be formed, for example, by implanting phosphorus (P) ions. + The layer may be formed by injecting protons and phosphorus. Furthermore, it may be formed by injecting both protons and phosphorus. Protons can be injected to a deep position from the second main surface 1b of the semiconductor substrate with relatively low acceleration energy. Also, the depth to which protons are injected can be changed relatively easily by changing the acceleration energy. For this reason, when forming the n-type buffer layer 3 with protons, if multiple injections are performed while changing the acceleration energy, it is possible to form an n-type buffer layer 3 that is wider in the thickness direction of the semiconductor substrate than when formed with phosphorus.

[0094] Furthermore, since phosphorus can have a higher activation rate as an n-type impurity compared to protons, forming an n-type buffer layer 3 with phosphorus can more reliably suppress punch-through of the depletion layer even in a thinned semiconductor substrate. To further thin the semiconductor substrate, it is preferable to form the n-type buffer layer 3 by implanting both protons and phosphorus, in which case the protons are implanted at a deeper position from the second main surface 1b than the phosphorus.

[0095] The p-type collector layer 16 may be formed, for example, by implanting boron (B). The p-type collector layer 16 is also formed in the termination region 30, and the p-type collector layer 16 in the termination region 30 becomes the p-type termination collector layer 16a. After ion implantation from the second main surface 1b side of the semiconductor substrate, the second main surface 1b is irradiated with a laser and laser annealed, which activates the implanted boron and forms the p-type collector layer 16. At this time, phosphorus for the n-type buffer layer 3, which is implanted at a relatively shallow position from the second main surface 1b of the semiconductor substrate, is also activated. On the other hand, since protons are activated at relatively low annealing temperatures of 350°C to 500°C, care must be taken to ensure that the entire semiconductor substrate does not exceed 350°C to 500°C after proton implantation, except for the proton activation process. Laser annealing can raise the temperature only near the second main surface 1b of the semiconductor substrate, so it can be used to activate n-type and p-type impurities even after proton implantation.

[0096] Next, as shown in Figure 18(a), n is added to the diode region 20. + A type cathode layer 26 is formed. + The p-type cathode layer 26 may be formed, for example, by injecting phosphorus (P). As shown in Figure 18(a), a p-type collector layer 16 and n-type cathode layer 26 are formed at a distance U1 from the boundary between the IGBT region 10 and the boundary region 50 toward the diode region 20. + Phosphorus is selectively injected from the second main surface side by masking so that the boundary with the type cathode layer 26 is located. + The amount of n-type impurities injected to form the n-type cathode layer 26 is greater than the amount of p-type impurities injected to form the p-type collector layer 16. In Figure 18(a), the p-type collector layer 16 and n-type impurities from the second main surface 1b are shown. + The depth of the type cathode layer 26 is shown to be the same, n + The depth of the p-type cathode layer 26 is greater than or equal to the depth of the p-type collector layer 16. + The region where the p-type cathode layer 26 is formed requires the injection of n-type impurities into the region where p-type impurities have been implanted to create an n-type semiconductor, therefore, n + In all regions where the type cathode layer 26 is formed, the concentration of implanted p-type impurities is made higher than the concentration of n-type impurities.

[0097] Next, as shown in Figure 18(b), a collector electrode 7 is formed on the second main surface 1b of the semiconductor substrate. The collector electrode 7 is formed over the entire surface of the IGBT region 10, boundary region 50, diode region 20, and termination region 30 of the second main surface 1b. Alternatively, the collector electrode 7 may be formed over the entire surface of the second main surface 1b of the n-type wafer, which is the semiconductor substrate. The collector electrode 7 may be formed by depositing aluminum-silicon alloy (Ai-Si alloy) or titanium (Ti) by PVD such as sputtering or vapor deposition, or by layering multiple metals such as aluminum-silicon alloy, titanium, nickel, or gold. Furthermore, a metal film may be formed on the metal film formed by PVD by electroless plating or electrolytic plating to form the collector electrode 7.

[0098] The semiconductor device 100 or semiconductor device 101 is manufactured through the process described above. Since multiple semiconductor devices 100 or semiconductor device 101 are manufactured in a matrix on a single n-type wafer, the semiconductor device 100 or semiconductor device 101 is completed by cutting them into individual semiconductor devices 100 or semiconductor device 101 using laser dicing or blade dicing.

[0099] As described above, in the semiconductor device 100 or semiconductor device 101 of this disclosure, the depth of the p-type anode layer 25 of the diode region 20 from the first main surface 1a of the semiconductor substrate is made deeper than the depth of the n-type carrier storage layer 2 provided in the IGBT region 10 from the first main surface 1a. Therefore, electric field concentration on the n-type carrier storage layer 2 is suppressed, and thus a decrease in the breakdown voltage of the semiconductor device 100 or semiconductor device 101 can be suppressed.

[0100] Furthermore, by making the p-type impurity concentration of the p-type anode layer 25 higher than the n-type impurity concentration of the n-type carrier storage layer 2, and by superimposing the p-type anode layer 25 on the portion of the n-type carrier storage layer 2 formed in the IGBT region 10 where the depth from the first main surface 1a at the diode region 20 side is shallow, it is possible to eliminate the portion of the n-type carrier storage layer 2 where the depth from the first main surface 1a is shallow at the edge, thereby suppressing electric field concentration on the n-type carrier storage layer 2 and suppressing a decrease in breakdown voltage.

[0101] Furthermore, since a boundary region 50 is provided between the IGBT region 10 and the diode region 20, and the n-type carrier storage layer 2 and the p-type anode layer 25 are in contact at the boundary region 50, the boundary between the n-type carrier storage layer 2 and the p-type anode layer 25 can be set away from the trench electrode where electric fields tend to concentrate. This suppresses electric field concentration at the end of the n-type carrier storage layer 2 on the diode region 20 side, thereby suppressing a decrease in breakdown voltage.

[0102] Furthermore, since the boundary between the n-type carrier storage layer 2 and the p-type anode layer 25 is located between two trench electrodes electrically connected to the emitter electrode 6, the boundary between the n-type carrier storage layer 2 and the p-type anode layer 25 can suppress its influence on the switching operation of the semiconductor device 100 or semiconductor device 101, thereby suppressing a decrease in breakdown voltage.

[0103] Furthermore, by providing one or more boundary trench electrodes 51a in the boundary region 50, and by providing a boundary between the n-type carrier storage layer 2 and the p-type anode layer 25 in the boundary region 50, the width of the boundary region 50, which does not contribute to the switching operation of the semiconductor device 100 or semiconductor device 101, can be increased, thereby further suppressing the influence of the boundary between the n-type carrier storage layer 2 and the p-type anode layer 25 on the switching operation and suppressing a decrease in withstand voltage.

[0104] Embodiment 2. Next, the configuration of the semiconductor device in Embodiment 2 will be described. Figure 20 is a partially enlarged plan view showing the configuration of the boundary between the IGBT region and the diode region of the semiconductor device which is an RC-IGBT in Embodiment 2. Figure 20 is an enlarged view of other configurations of the region enclosed by the dashed line 84 in the semiconductor device with the configuration shown in Figure 1 or Figure 2. In Embodiment 2, the same or corresponding components as those of the semiconductor device 100 or semiconductor device 101 described in Embodiment 1 are denoted by the same reference numerals as in Embodiment 1 and their descriptions are omitted.

[0105] As shown in Figure 20, the semiconductor device of Embodiment 2 has a boundary region 50 between the IGBT region 10 and the diode region 20, and a plurality of boundary trench electrodes 51a are provided in the boundary region 50. The boundary region 50 is provided between the dummy trench electrode 12a, which is the IGBT electrode on the diode region 20 side of the IGBT region 10, and the diode trench electrode 21a on the IGBT region 10 side of the diode region 20.

[0106] p provided on the first main surface 1a side of the IGBT region 10 + Unlike the semiconductor device 100 or 101 of Embodiment 1, the type contact layer 14 is sandwiched between the IGBT electrodes consisting of a gate trench electrode 11a or a dummy trench electrode 12a, and is sandwiched between the p-type base layer 15. Also, the n-type contact layer is the one on the diode region 20 side of the IGBT region 10. + The type emitter layer 13 is not in contact with the IGBT trench electrode via an insulating film at its edge on the diode region 20 side, n + A p-type base layer 15 is provided between the p-type emitter layer 13 and the dummy trench electrode 12a, which is an IGBT trench electrode. + Unlike the semiconductor device 100 or semiconductor device 101 of Embodiment 1, the type contact layer 24 is sandwiched between the diode trench electrode 21a and the p-type anode layer 25.

[0107] Note that in the IGBT region 10 and diode region 20 shown in Figure 20, p+ Type contact layer 14, p-type base layer 15, p + The arrangement of the type contact layer 24 and the p-type anode layer 25 is not limited to this, and may be the arrangement shown in Figure 3 or Figure 6 of Embodiment 1, and in the semiconductor device 100 or semiconductor device 101 of Embodiment 1, the p in the IGBT region 10 and the diode region 20 + Type contact layer 14, p-type base layer 15, p + The arrangement of the type contact layer 24 and the p-type anode layer 25 may be as shown in Figure 20.

[0108] As shown in Figure 20, in the boundary region 50, the p-type base layer 15 or the p-type anode layer 25 faces the boundary trench electrode 51a via an insulating film. Figure 20 shows a configuration in which the boundary trench electrode 51a closest to the IGBT region 10 faces the p-type base layer 15 via an insulating film, and the boundary trench electrode 51a closest to the diode region 20 faces the p-type anode layer 25 via an insulating film, with the boundary between the p-type base layer 15 and the p-type anode layer 25 located in the boundary region 50 (not shown). - Since there is an n-type carrier storage layer 2 between the n-type drift layer 1 and the p-type anode layer 25, the boundary between the n-type carrier storage layer 2 and the p-type anode layer 25 is also located in the boundary region 50 (not shown).

[0109] As shown in Figure 20, the semiconductor device of Embodiment 2 has a surface layer of the p-type base layer 15 or p-type anode layer 25 included in the boundary region 50, with an n-type impurity concentration higher than that of the n-type carrier storage layer 2. + A carrier injection suppression layer 53 is selectively provided. + The n-type impurity concentration in the carrier injection suppression layer 53 is the n-type impurity concentration in the IGBT region 10. + The n-type impurity concentration may be the same as that of the n-type emitter layer 13. + The n-type impurity concentration in the emitter layer 13 may be higher or lower than the n-type impurity concentration in the emitter layer 13. Also, in Figure 20, in the direction in which the IGBT region 10 and the diode region 20 are aligned (up and down direction on the paper), n + Type emitter layer 13 and n +Although it is provided so as to face the carrier injection suppression layer 53, + The carrier injection suppression layer 53 is n + It may be provided regardless of the arrangement of the type emitter layer 13. That is, in Figure 20, n is provided in the longitudinal direction (left-right direction of the paper) of the gate trench electrode 11a and boundary trench electrode 51a. + The number of type emitter layers 13 and n + The number of carrier injection suppression layers 53 is the same as the number of n + The number of type emitter layers 13 and n + The number of carrier injection suppression layers 53 may be different from the number of carrier injection suppression layers 53.

[0110] As shown in Figure 20, n is provided in the boundary region 50 + The type carrier injection suppression layer 53 is positioned between the p-type base layer 15 or the p-type anode layer 25 in the direction in which the IGBT region 10 and the diode region 20 are aligned (up and down direction on the paper). That is, n + The p-type carrier injection suppression layer 53 is not in contact with the insulating film provided in contact with the boundary trench electrode 51a, but faces the trench where the boundary trench electrode 51a is provided via the p-type base layer 15 or the p-type anode layer 25.

[0111] In the semiconductor device of Embodiment 2 shown in Figure 20, adjacent n in the extension direction of the boundary trench electrode 51a + Between the type carrier injection suppression layer 53, p + Type contact layer 14 or p + Although a type contact layer 24 was provided, p + Type contact layer 14 or p + The type contact layer 24 does not necessarily have to be provided, p + Type contact layer 14 or p + A p-type base layer 15 or a p-type anode layer 25 may be provided instead of the p-type contact layer 24. + A p-type base layer 15 or a p-type anode layer 25 is provided between the p-type carrier injection suppression layer 53 and the trench where the boundary trench electrode 51a is provided, but instead of the p-type base layer 15 or p-type anode layer 25, +Type contact layer 14 or p + A contact layer 24 may be provided.

[0112] Figures 21 to 24 are cross-sectional views showing the configuration of the IGBT region, boundary region, and diode region of a semiconductor device which is an RC-IGBT according to Embodiment 2. Figure 21 is a cross-sectional view of the IGBT region 10 along the dashed line HH shown in Figure 20. Figure 22 is a cross-sectional view of the boundary region 50 along the dashed line II shown in Figure 20. Figure 23 is a cross-sectional view of the boundary region 50 along the dashed line JJ shown in Figure 20. Figure 24 is a cross-sectional view of the diode region 20 along the dashed line KK shown in Figure 20. All of Figures 21 to 24 are cross-sectional views in a direction perpendicular to the direction in which the IGBT region 10 and the diode region 20 are aligned (up and down direction on the paper), and are cross-sectional views in a direction perpendicular to the extension direction of the gate trench electrode 11a, dummy trench electrode 12a, and boundary trench electrode 51a.

[0113] As shown in Figure 21, in the IGBT region 10, a p-type base layer 15 is provided on the first main surface 1a side of the semiconductor substrate, and n + Type emitter layer 13 and p + A type contact layer 14 is selectively provided. + The contact layer 14 is n + The p-type base layer 15 and n - An n-type carrier storage layer 2 is provided between the n-type drift layer 1 and the n-type carrier storage layer 2. - An n-type buffer layer 3 is provided on the second main surface 1b side of the n-type drift layer 1, and a p-type collector layer 16 is provided between the n-type buffer layer 3 and the second main surface 1b.

[0114] As shown in Figures 22 and 23, in the boundary region 50, a p-type base layer 15 is provided on the first main surface 1a side of the semiconductor substrate in the region close to the IGBT region 10, and a p-type anode layer 25 is provided on the first main surface 1a side of the semiconductor substrate in the region close to the diode region 20. Furthermore, in the boundary region 50 where the p-type base layer 15 is provided, the p-type base layer 15 and n -An n-type carrier storage layer 2 is provided between the n-type drift layer 1 and the n-type carrier storage layer 2.

[0115] As described in Embodiment 1, the p-type base layer 15 of the boundary region 50 is a p-type semiconductor layer continuous with the p-type base layer 15 of the IGBT region 10, the n-type carrier storage layer 2 of the boundary region 50 is an n-type semiconductor layer continuous with the n-type carrier storage layer 2 of the IGBT region 10, and the p-type anode layer 25 of the boundary region 50 is a p-type semiconductor layer continuous with the p-type anode layer 25 of the diode region 20. The n-type carrier storage layer 2 provided in the IGBT region 10 and the boundary region 50 is continuous with the p-type anode layer 25 provided in the diode region 20 and the boundary region 50. - It is located at a depth from the first main surface 1a of the semiconductor substrate that is shallower than the boundary with the n-type drift layer 1. Although not shown in Figures 22 and 23, as described in Embodiment 1, the n-type carrier storage layer 2 and the p-type anode layer 25 are in contact at the boundary region 50.

[0116] As shown in Figures 22 and 23, in the boundary region 50, the surface layer of the p-type base layer 15 or p-type anode layer 25 has a higher n-type impurity concentration than the n-type carrier storage layer 2. + A carrier injection suppression layer 53 is selectively provided. + Between the type carrier injection suppression layers 53, p + Type contact layer 14 or p + A type contact layer 24 is provided. + Type contact layer 14 or p + The contact layer 24 is n + The carrier accumulation layer 53 may be provided at a depth greater than that from the first main surface 1a. + Type contact layer 14 or p + The type contact layer 24 does not necessarily need to be provided, p + Type contact layer 14 or p +A p-type base layer 15 or a p-type anode layer 25 may be provided instead of the p-type contact layer 24. In the boundary region 50, an n-type buffer layer 3 is provided on the second main surface 1b side of the semiconductor substrate, and a p-type collector layer 16 is provided between the n-type buffer layer 3 and the second main surface 1b.

[0117] As shown in Figure 24, in the diode region 20, a p-type anode layer 25 is provided on the first main surface 1a side of the semiconductor substrate, and the surface layer of the p-type anode layer 25 is p + A type contact layer 24 is provided. + The type contact layer 24 may be selectively provided on the surface of the p-type anode layer 25. The p-type anode layer 25 is n - It is in contact with the p-type drift layer 1, and the p-type anode layer 25 and n - The boundary with the n-type drift layer 1 is located at a depth greater than the depth at which the n-type carrier storage layer 2 is provided. - An n-type buffer layer 3 is provided on the second main surface 1b side of the n-type drift layer 1, and an n-type buffer layer 3 is provided between the n-type buffer layer 3 and the second main surface 1b. + A type cathode layer 26 is provided.

[0118] The semiconductor device of Embodiment 2 is configured as described above. In the semiconductor device of Embodiment 2, n is present in the surface layer portion of the p-type base layer 15 or p-type anode layer 25 of the boundary region 50. + Because a type carrier injection suppression layer 53 is provided, the amount of holes supplied from the first main surface 1a side of the boundary region 50 decreases, thus reducing the hole injection efficiency into the diode region 20. Therefore, it is possible to reduce recovery losses during diode operation while suppressing a decrease in the breakdown voltage of the semiconductor device.

[0119] Embodiment 3. Figure 25 is a cross-sectional view showing the boundary configuration between the IGBT region and the diode region of a semiconductor device which is an RC-IGBT according to Embodiment 3. Figure 25 is a cross-sectional view along the dashed line GG in the semiconductor device 100 shown in Figure 1 or the semiconductor device 101 shown in Figure 2, and unlike the cross-sectional views shown in Figure 9 or Figure 10 described in Embodiment 1, it is a cross-sectional view of a semiconductor device which does not have a boundary region 50 between the IGBT region 10 and the diode region 20.

[0120] As shown in Figure 25, the semiconductor device of Embodiment 3 has an IGBT region 10 and a diode region 20 adjacent to each other, and a gate trench electrode 11a, which is an IGBT trench electrode, is provided at the boundary between the IGBT region 10 and the diode region 20. In Figure 25, the IGBT trench electrode provided at the boundary between the IGBT region 10 and the diode region 20 is shown as the gate trench electrode 11a, but it may also be a dummy trench electrode 12a.

[0121] The semiconductor device of Embodiment 3, similar to the semiconductor device 100 or semiconductor device 101 described in Embodiment 1, has an n-type carrier storage layer 2 provided in the IGBT region 10, and the n-type carrier storage layer 2 is provided in the p-type anode layer 25 provided in the diode region 20 and n - It is located at a position shallower from the first main surface 1a than the boundary with the n-type drift layer 1. That is, the n-type carrier storage layer 2 provided in the IGBT region 10 and n - The p-type anode layer 25 is provided at a depth greater than the boundary with the p-type drift layer 1 from the first main surface 1a of the semiconductor substrate.

[0122] In the semiconductor device of Embodiment 3, similar to the semiconductor device described in Embodiment 1, the depth of the p-type anode layer 25 of the diode region 20 from the first main surface 1a of the semiconductor substrate is made deeper than the depth of the n-type carrier storage layer 2 provided in the IGBT region 10 from the first main surface 1a. As a result, electric field concentration on the n-type carrier storage layer 2 is suppressed, and thus a decrease in the breakdown voltage of the semiconductor device can be suppressed.

[0123] In the embodiments 1 to 3 described above, a trench-type semiconductor device was described in which trenches are formed in the IGBT region 10 and the diode region 20 of the semiconductor device, and electrodes are provided in the trenches via an insulating film. However, the semiconductor device of this disclosure may be a planar-type semiconductor device in which electrodes are provided on the first main surface 1a of the semiconductor substrate via an insulating film without the formation of trenches. Furthermore, a semiconductor device may be one in which trenches are formed only in the IGBT region 10, and trenches are not formed in the diode region 20 or the boundary region 50.

[0124] Furthermore, combining, modifying, or omitting each embodiment as appropriate is also included within the scope of this disclosure. [Explanation of Symbols]

[0125] 1 n - Type drift layer, 1a first principal surface, 1b second principal surface 2 n-type carrier storage layer 6. Emitter electrode 10 IGBT area 11 Active trench gate, 11a Gate trench electrode (IGBT trench electrode), 11b Gate trench insulating film 12 Dummy trench gate, 12a Dummy trench electrode (IGBT trench electrode), 12b Dummy trench insulating film 13 n + Type emitter layer, 15 p-type base layer 16p-type collector layer, 16a-p-type termination collector layer 20 Diode region 21 Diode trench gate, 21a Diode trench electrode, 21b Diode trench insulating film 25 p-type anode layer 26 n + Type cathode layer 30 Termination area 31 p-type terminal well layer 50 Boundary Area 51a Boundary trench electrode 53 n + Type carrier injection suppression layer 60, 61 Resist Mask 100, 101 Semiconductor Machine

Claims

1. A semiconductor substrate having a first conductivity type drift layer between a first main surface and a second main surface facing the first main surface comprises an IGBT region and a diode region arranged in a first direction along the first main surface. The aforementioned IGBT area is, A second conductive collector layer is provided between the drift layer and the second main surface, A carrier accumulation layer of a first conductivity type is provided on the first main surface side of the drift layer in contact with the drift layer, and has a higher concentration of first conductivity type impurities than the drift layer. A second conductive base layer is provided between the carrier storage layer and the first main surface, A first conductivity type emitter layer is selectively provided on the surface portion of the base layer and has a part of the first main surface, The emitter layer and the base layer are provided opposite each other via an insulating film, and the gate electrode is provided opposite each other. The diode region is A first conductive cathode layer is provided between the drift layer and the second main surface, The system comprises a second conductive anode layer provided between the drift layer and the first main surface, and extending to a depth greater from the first main surface than the boundary between the carrier accumulation layer and the drift layer, The IGBT region extends along the first main surface in a second direction perpendicular to the first direction, and has an IGBT trench electrode provided via an insulating film in a trench that penetrates the base layer from the first main surface to the drift layer. The diode region extends in the second direction and has a diode trench electrode provided in a trench extending from the first main surface to the anode layer via an insulating film. A termination region is provided around the cell region, which is a combination of the IGBT region and the diode region. The aforementioned termination region is A second conductivity type termination well layer is provided between the drift layer and the first main surface, and at least a portion of the anode layer is provided to the same depth as the termination well layer. The diode trench electrode is provided at a depth from the first main surface that is shallower than the termination well layer in the semiconductor device.

2. The semiconductor device according to claim 1, wherein the termination well layer and the anode layer have the same impurity concentration.

3. The semiconductor device according to claim 1, wherein a plurality of diode trench electrodes are provided.

4. A semiconductor substrate having a first conductivity type drift layer between a first main surface and a second main surface facing the first main surface comprises an IGBT region and a diode region arranged in a first direction along the first main surface. The aforementioned IGBT area is, A second conductive collector layer is provided between the drift layer and the second main surface, A carrier accumulation layer of a first conductivity type is provided on the first main surface side of the drift layer in contact with the drift layer, and has a higher concentration of first conductivity type impurities than the drift layer. A second conductive base layer is provided between the carrier storage layer and the first main surface, A first conductivity type emitter layer is selectively provided on the surface portion of the base layer and has a part of the first main surface, The emitter layer and the base layer are provided opposite each other via an insulating film, and the gate electrode is provided opposite each other. The diode region is A first conductive cathode layer is provided between the drift layer and the second main surface, The system comprises a second conductive anode layer provided between the drift layer and the first main surface, and extending to a depth greater from the first main surface than the boundary between the carrier accumulation layer and the drift layer, The IGBT region extends along the first main surface in a second direction perpendicular to the first direction, and has an IGBT trench electrode provided via an insulating film in a trench that penetrates the base layer from the first main surface to the drift layer. The diode region extends in the second direction and has a diode trench electrode provided in a trench extending from the first main surface to the anode layer via an insulating film. The IGBT region and the diode region are provided adjacent to each other. A semiconductor device wherein the IGBT trench electrode is provided at the boundary between the IGBT region and the diode region so as to be in contact with both the carrier storage layer and the anode layer.

5. A step of preparing a semiconductor substrate comprising a first conductivity type drift layer having a first main surface, a first region where IGBT regions are formed in a first direction along the first main surface, a second region where diode regions are formed, and a third region where termination regions are formed around the first and second regions, A step of forming a first resist mask having a first opening on the first main surface of the first region, A step of implanting impurity ions of a first conductivity type from the first opening to form a carrier accumulation layer of a first conductivity type, A step of forming a second resist mask having a second opening on the first main surface of the second region and a third opening on the first main surface of the third region, The process involves simultaneously implanting impurity ions of a second conductivity type from the second and third openings to form an anode layer of a second conductivity type in the second region and a terminal well layer in the third region, from a position deeper than the depth at which the carrier accumulation layer is formed to the first main surface, and at least a portion of the anode layer is provided at the same depth as the terminal well layer. A step of forming an IGBT trench electrode, which is provided in a trench with an insulating film between the first main surface and the first main surface of the first region, extending in a second direction perpendicular to the first direction and reaching the drift layer, The process includes the step of forming a diode trench electrode, which is provided in a trench extending in a second direction perpendicular to the first direction along the first main surface of the second region and reaching the anode layer via an insulating film, A method for manufacturing a semiconductor device, wherein the diode trench electrode is formed at a depth from the first main surface that is shallower than the termination well layer.

6. The method for manufacturing a semiconductor device according to claim 5, wherein the second resist mask is a mesh-like mask in the region where the anode layer is formed.

7. The method for manufacturing a semiconductor device according to claim 5, wherein the termination well layer and the anode layer have the same impurity concentration.

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