Method for manufacturing a semiconductor device and a semiconductor device.

Abstract

In at least one embodiment, the method is for manufacturing a semiconductor device (1) and includes, in the order listed, the following steps: A) providing a semiconductor body (2) having a top surface (20), the semiconductor body (2) being based on SiC; B) producing a first layer (21) of the semiconductor body (2) adjacent the top surface (20) by doping with a dopant (4); C) applying a carbon-containing layer (3) to the top surface (20); D) implanting C into the first layer (21) through the carbon-containing layer (3); and E) performing a temperature treatment of the semiconductor body (2) while the carbon-containing layer (3) is still present on the top surface (20).

Description

[Technical Field]

[0001] A method for manufacturing a semiconductor device is provided. A corresponding semiconductor device is also provided. [Background technology]

[0002] Reference: HMAyedh et al., "Carbon Vacancy control in p + The paper "n silicon carbide diodes for high voltage bipolar applications," J.Phys.D:Appl.Phys.54(2001)455106(5pp), https: / / doi.org / 10.1088 / 1361-6463 / ac19df, argues that controlling carbon vacancies (Vc) in silicon carbide (SiC) is one of the remaining major bottlenecks in the fabrication of high-voltage SiC bipolar devices. This is because Vc causes recombination levels in the bandgap, significantly shortening the lifetime of charge carriers. The literature shows that significant Vc changes have been measured by capacitance spectroscopy using Schottky diodes, but p + -n diodes have not received much attention. Applying a similar methodology, Vc is p + -By annealing at 1800°C required for activation of the injected acceptor in component n, 2 × 10 13 Vc public -3 It is shown that it is regenerated to an unacceptably high equilibrium level. Nevertheless, Vc removed by thermodynamic equilibrium annealing at 1500°C using a carbon cap is p + - It can be easily integrated into the production of component n, 10 11 Vc public -3 The following results demonstrate that this could potentially pave the way for the realization of high-voltage SiC bipolar devices. The paper, S. Chowdhury et al., "Effect of Carrier Lifetime Enhancement on the Performance of Ultra-High Voltage 4H-SiC PiN Diodes," 2016 LESTER EASTMAN FONFERENCE (LEC), IEEE, August 2, 2016, pp. 23-26, https: / / doi.org / 10.1109 / LEC.2016.7578925, argues that a long minority carrier lifetime is desirable to improve the on-state performance of ultra-high voltage 4H-SiC bipolar devices. A study of a lifetime enhancement process applied to low-concentration doped, self-supporting 4H-SiC substrates is provided. An optimized carbon implantation and annealing process was developed, resulting in a lifetime of 9.7 ps (an increase from 2.1 ps on as-received wafers). PiN diodes were fabricated on these wafers, exhibiting improved on-state performance compared to diodes fabricated on as-received wafers. The paper by L. Storasta et al., "Reduction of traps and improvement of carrier lifetime in 4H-SiC," Appl. Phys. Lett. 90, 062116 (2007); https: / / doi.org / 10.1063 / 1.2472530, mentions the reduction of deep-level defects.

[0003] The paper HMAyedh et al., "Elimination of carbon vacancies in 4H-SiC epi-layers by near-surface ion implantation: Influence of the species," Journal of Applied Physics 118, 175701 (2015); https: / / doi.org / 10.1063 / 1.4934947, discusses methods for addressing carbon vacancies.

[0004] The document K. Hamada et al., U.S. Patent Application Publication No. 2016 / 0247894, describes a method for manufacturing a semiconductor device that can reduce on-resistance, comprising forming a drift layer on a substrate and forming an ion implantation layer on the surface of the drift layer. An excess carbon region is formed in the drift layer. The drift layer is heated.

[0005] The paper by B. Zippelius et al., "High Temperature annealing of n-type 4H-SiC: Impact on intrinsic defects and carrier lifetime," J.Appl.Phys.111, 033515(2012); http: / / dx.doi.org / 10.1063 / 1.3681806, mentions the carrier lifetime of SiC. [Overview of the project] [Problems that the invention aims to solve]

[0006] The objective is to provide a semiconductor device with improved electrical behavior. [Means for solving the problem]

[0007] This objective is achieved, in particular, by power semiconductor devices and by methods defined in the independent claims. Exemplary further developments constitute the subject matter of the dependent claims.

[0008] In at least one embodiment, a method for manufacturing a semiconductor device can be performed in the following steps in the order described: A) To provide a semiconductor body having an upper surface, which is made of SiC. B) By doping with a dopant, for example, the first layer of the semiconductor body is manufactured adjacent to the top surface. C) Applying a carbon-containing layer to the upper surface, D) Injecting C into the first layer through the carbon-containing layer, E) When the carbon-containing layer still exists on the upper surface, performing a temperature treatment of the semiconductor body.

[0009] By this method, it is possible to efficiently achieve carbon vacancy removal by low-dose C implantation using a carbon-containing layer, also called a C cap. Therefore, it becomes possible to remove carbon vacancies during device processing.

[0010] Carbon vacancy (V C :carbon vacancy) is one of the most important point defects in n-type 4H silicon carbide 4H-SiC. V C generates two electrically active levels in the bandgap labeled as Z C :conduction band edge) located at 0.65 eV and 1.6 eV below the conduction band edge, respectively. In particular, Z 1 / 2 is a recombination center, which affects the lifetime of charge carriers in bipolar devices and increases the leakage current in unipolar devices. 6 / 7 1 / 2 C C

[0011] V C A method for reducing the concentration [V C was presented by Storasta et al. (see the above citation). This consists of performing C ion implantation with a shallow 100 nm - 2000 nm depth box profile in the SiC epi layer at an implantation energy of 10 keV - 10 MeV, followed by annealing at a high temperature of 1200 °C - 2200 °C. In this way, the C-interstitial atoms (C i :C-interstitial) formed by ion implantation diffuse into the epi layer and recombine with V C resulting in a decrease in [V C . Another method based on annealing using a C cap at low temperature, i.e., below 1500 °C, was proposed by Ayedh et al. (see the above citation). Both methods ultimately result in the recombination of C i +V C →φ with V C in the drift layer. iThis is based on diffusion and therefore extends the lifetime of minority carriers. The term "epitaxial layer" refers to the epitaxially grown layer. For example, the epitaxial layer is grown on a substrate that may be the same substrate, such as SiC.

[0012] However, p + When manufacturing an in diode, by using an epitaxial layer processed according to one of the two methods described above, Al implantation for anode formation and subsequent annealing are performed. C It brings about regeneration.

[0013] Referring to the above quote, Hamada et al. 10 13 cm -2 This suggests using high injection volumes exceeding [a certain value] to perform deep C injection into the epitaxial layer within 500 nm of the Al box profile. During activation, C i These deeply injected regions diffuse into the epitaxial layer. However, such high injection levels can lead to amorphous formation of the epitaxial layer's crystalline structure. i It is also an acceptor for n-type 4H-SiC, and has a high concentration of C i This can result in n-type doping compensation. Similarly, if a high injection volume of C is injected into the anode layer, i.e., the first layer, p + The formation of injection-related defects occurs that can compensate for doping. In the method described herein, because the amount of C injected is low, the p + Doping compensation is avoided or its effect is significantly reduced. Low C injection volume also prevents a decrease in hole injection efficiency from the anode, but this is p + This is because it may decrease due to the presence of defects within the region.

[0014] In the methods described herein, p + After injecting C into the injection region, i.e., the anode, annealing is performed using a C cap. This uses lower injection volumes and energies than, for example, Hamada et al., and unlike the case of Ayedh et al., p + V in diode CIt has the advantage of removing V by C-cap annealing, and in the latter case, V C It has been shown that the concentration of decreases, but some still remains. The method described herein involves injecting a low volume of C into the anode layer to introduce additional C i Therefore, C derived from the C cap is supplied. i and C derived from injected C i These C are present in the anode layer. i All of them, for example, V C Remove it completely or substantially completely from the drift layer.

[0015] Therefore, the methods described herein include, in particular, injecting a low volume of C into, for example, an Al box profile, followed by annealing using a C cap.

[0016] According to at least one embodiment, the concentration of the dopant provided and activated in step B) is at least 3 times or at least 6 times the concentration of C injected in step D). Alternatively or additionally, the concentration of the dopant ultimately activated is up to 30 times or up to 15 times the concentration of C injected. That is, the concentration of the activated dopant in the finished semiconductor device is about 10 times the concentration of C injected in step B).

[0017] It should be noted that not all injected dopants are activated; that is, some are available for, for example, charge carrier conduction within the finished device. For example, when Al is used as a dopant, about 2% of the injected Al is actually activated. That is, for example, 1 × 10⁻⁶ 20 cm -3 The Al injection concentration is 2 × 10 18 cm -3 This results in a certain level of activated Al concentration.

[0018] According to at least one embodiment, in step E), the temperature treatment includes applying a first temperature. For example, the first temperature is at least 1400°C or at least 1500°C. Alternatively or additionally, the first temperature is up to 1800°C, up to 1700°C, or up to 1650°C. At such a first temperature, in step E), the pre-implanted C can diffuse from the carbon-containing layer, i.e., the C cap, into the first layer, and optionally into a second layer of the semiconductor body, such as a uniquely doped layer.

[0019] According to at least one embodiment, the method further includes step B2). For example, step B2) is performed after step B) and before step D). In step B2), the dopant is activated by applying a second temperature. For example, the second temperature is at least 1400°C, or at least 1500°C, or at least 1600°C. Alternatively or additionally, the first temperature is up to 1900°C, or up to 1800°C, or up to 1750°C. The second temperature can be 50°C to 150°C higher than the first temperature.

[0020] For example, both temperature treatments at the first and second temperatures are performed in this method. According to at least one embodiment, in step E), C diffuses from the carbon-containing layer to the first and / or second layer, and the dopant is activated. For example, in step E), the temperature treatment includes applying a third temperature. For example, the third temperature is at least 1400°C, or at least 1500°C, or at least 1550°C. Alternatively or additionally, the third temperature is up to 1900°C, or up to 1800°C, or up to 1750°C, or up to 1650°C. If a third temperature is applied, the temperature treatment by the first or second temperature may not be present.

[0021] According to at least one embodiment, between step A) and step E), the temperature of the semiconductor body (2) is maintained at less than 800°C, less than 500°C, less than 300°C, or less than 100°C. This applies, for example, when temperature treatment is performed at a third temperature. In other words, in this case, C diffusion and dopant activation can be performed in the same temperature treatment step without requiring an intermediate temperature step.

[0022] According to at least one embodiment, the dopant is aluminum (Al). Alternatively, the dopant may be B, Ga, or In. In the case of the n-doped first layer, other dopants such as P, As, Sb, and / or Bi may also be used. It is also possible that co-doping is used, i.e., at least two different dopants are used. Thus, in step B), at least one dopant is introduced into the first layer of the semiconductor body by either injection, thermal diffusion, or epitaxial growth, or any combination thereof.

[0023] According to at least one embodiment, in step B), doping is provided by ion implantation. For example, different ion implantation energies are used to achieve the box profile of at least one dopant. The ion implantation energies are, for example, 10 keV to 10 MeV, and may be, for example, 30 keV to 300 keV.

[0024] According to at least one embodiment, the first layer is p-doped. According to at least one embodiment, at least one dopant comprises at least 1 × 10 13 cm -2 or at least 1 × 10 14 cm -2 or at least 2 × 10 14 cm -2 The injection volume is provided by ion implantation. Alternatively or additionally, the injection volume may be up to 1 × 10⁻⁶ 16 cm -2 or up to 1 x 10 15 cm-2 or up to 6 x 10 14 cm -2 Or up to 4 x 10 14 cm -2 That is the case.

[0025] According to at least one embodiment, C is at least 5 × 10 8 cm -2 or at least 1 × 10 9 cm -2 or at least 2 × 10 9 cm -2 It is injected at an injection volume of . Alternatively or additionally, the injection volume may be up to 1 × 10 12 cm -2 or up to 1 x 10 11 cm -2 Or up to 5 x 10 10 cm -2 or up to 1 x 10 10 cm -2 That is the case.

[0026] According to at least one embodiment, the first layer is fabricated adjacent to the top surface by doping with at least one dopant. Thus, the first layer can be placed directly on the top surface such that the top surface is partially or completely formed by the first layer. Alternatively, the first layer may be at least partially embedded within the semiconductor body such that the top layer can be partially or completely separated from the top surface.

[0027] According to at least one embodiment, the carbon-containing layer is applied directly to the top surface, for example, directly to the first layer. Otherwise, at least one intermediate layer may exist between the carbon-containing layer and the top surface and / or between the carbon-containing layer and the first layer.

[0028] For example, the carbon-containing layer is a continuous, non-porous layer. The carbon-containing layer may extend throughout the entire semiconductor body. The carbon-containing layer can be used in the applicable method steps D) and E), i.e., without any material removal or structuring of the carbon-containing layer in between. Therefore, the carbon-containing layer can be used in steps D) and E) with the coverage of the semiconductor body as it was when it was first placed on the semiconductor body.

[0029] According to at least one embodiment, in step D), the first injection energy is at least 10 keV and / or up to 300 keV.

[0030] According to at least one embodiment, at least one dopant and / or C is applied in a box profile. The term “box profile” may also be called a multi-energy injection profile, that is, the concentration of each dopant and / or C is substantially constant along the depth direction.

[0031] According to at least one embodiment, after step D) or after step E), the first box profile depth of at least one dopant is greater than the second box profile depth of C. For example, each depth refers to the depth to which the concentration has decreased to 1 / e of the maximum concentration of each dopant or C, where e ≈ 2.7183 is Euler's number. For example, the second box profile depth is at least 30% or at least 45% and / or up to 80% or up to 60% of the first box profile depth.

[0032] According to at least one embodiment, the first box profile depth is at least 0.1 μm, or at least 0.2 μm, or at least 0.3 μm. Alternatively or additionally, the first box profile depth is up to 1.5 μm, or up to 1.2 μm, or up to 0.7 μm.

[0033] According to at least one embodiment, the method further includes step B1). For example, step B1 is performed after step B) and before step C). In step B1), the semiconductor body is etched. This etching forms, for example, a mesa. A mesa is a raised portion of the semiconductor body, and the semiconductor body adjacent to the mesa portion is removed. Step B1) can be performed between step B) and step B2).

[0034] According to at least one embodiment, the etching depth in step B1) is greater than the thickness of the first layer, i.e., the depth of the first box profile. For example, the etching depth is at least 1.2 times and / or up to 3 times greater than the depth of the first box profile.

[0035] According to at least one embodiment, in step C), the carbon-containing layer is applied to the entire semiconductor body or to only a portion of the semiconductor body. If a mesa is present, the carbon-containing layer may completely cover the top surface and side walls of the mesa.

[0036] According to at least one embodiment, the carbon-containing layer comprises or consists of at least one of graphite, graphite material, and diamond-like carbon (DLC). That is, the carbon-containing layer may consist of C, or may consist essentially of C.

[0037] According to at least one embodiment, the carbon-containing layer comprises or consists of a photoresist. For example, the photoresist is developed and / or fired to become a carbon-containing layer. That is, the carbon-containing layer may contain further elements such as H and / or O and / or N in addition to C.

[0038] According to at least one embodiment, the thickness of the carbon-containing layer is at least 0.1 μm or at least 0.2 μm. Alternatively or additionally, the thickness is up to 1.5 μm, up to 0.9 μm, or up to 0.6 μm.

[0039] According to at least one embodiment, in a completed semiconductor device, the semiconductor body further comprises a second layer. For example, the second layer is directly on the side furthest from the top surface of the first layer. If mesas are present, the second layer may be partially exposed and / or etching may terminate at the second layer.

[0040] According to at least one embodiment, the second layer is doped with a lower doping concentration than the first layer, or is not doped at all. Thus, the second layer can be an essentially doped layer. For example, the doping concentration of the second layer may be up to 1 × 10⁻⁶ 15 cm -3 Or up to 5 x 10 14 cm -3 or up to 1 x 10 14 cm -3 Or up to 5 x 10 13 cm -3 That is the case.

[0041] According to at least one embodiment, the thickness of the second layer is at least 10 μm. Alternatively or additionally, the thickness is up to 100 μm or up to 50 μm.

[0042] According to at least one embodiment, the first layer or the entire semiconductor body is 4H-SiC. According to at least one embodiment, in the completed semiconductor device, the first layer is an anode layer. For example, the first layer is in direct contact with a semiconductor contact layer, such as a plug, and the semiconductor contact layer may be in direct contact with an electrode, such as a metal electrode or a poly-Si electrode. The semiconductor contact layer may have a higher doping concentration than the rest of the first layer, but due to having the same conductivity type, such as p-conductivity, the semiconductor contact layer can be considered as part of the first layer.

[0043] Further semiconductor devices are provided. Semiconductor devices can be manufactured by the methods shown in connection with at least one of the embodiments described above. Thus, features of semiconductor devices are disclosed in this method, and vice versa.

[0044] In at least one embodiment, the semiconductor device comprises a semiconductor body. The semiconductor body has a first layer of 4H-SiC directly on its upper surface. The first layer comprises at least 2 × 10 17 cm -3 and / or up to 8 x 10 18 cm -3 It contains a dopant having an activated dopant concentration of . The concentration of carbon vacancies in the first layer adjacent to the top surface is up to 2 × 10 11 cm -3 That is the case.

[0045] According to at least one embodiment, the semiconductor device is a pin diode, or an insulated-gate bipolar transistor (IGBT), or a reverse-conducting insulated-gate bipolar transistor (RC-IGBT), or a metal-insulator-semiconducor field-effect transistor (MISFET), or a metal-oxide-semiconducor field-effect transistor (MOSFET).

[0046] Semiconductor devices are power devices or parts of power devices used to convert direct current from a battery into alternating current for an electric motor, for example, in vehicles such as hybrid cars and plug-in electric vehicles, or in railway vehicles such as commuter trains.

[0047] For example, a semiconductor device is configured such that the maximum voltage between its two electrodes, or between the source or emitter electrode and the drain or collector electrode, is at least 0.2kV, or at least 0.6kV, or at least 1.2kV. Alternatively or additionally, a semiconductor device is configured for currents of at least 0.01kA, or at least 0.1kA, or at least 1kA, and / or up to 100kA, or up to 10kA, between its two electrodes, or between the source or emitter electrode and the drain or collector electrode.

[0048] The methods and semiconductor devices described herein are described in more detail below by exemplary embodiments with reference to the drawings. In the individual drawings, the same elements are indicated by the same reference numerals. However, the relationships between elements are not shown to scale, and individual elements may be shown in an exaggerated manner to aid understanding. [Brief explanation of the drawing]

[0049] [Figure 1] This is a schematic block diagram of an exemplary embodiment of a method for manufacturing a semiconductor device as described herein. [Figure 2] This is a schematic block diagram of an exemplary embodiment of a method for manufacturing a semiconductor device as described herein. [Figure 3] This is a schematic diagram of the doping profile provided by the method described herein. [Figure 4] This is a schematic cross-sectional view of a method step of an exemplary embodiment of the method for manufacturing a semiconductor device described herein. [Figure 5] This is a schematic cross-sectional view of a method step of an exemplary embodiment of the method for manufacturing a semiconductor device described herein. [Figure 6] This is a schematic cross-sectional view of a method step of an exemplary embodiment of the method for manufacturing a semiconductor device described herein. [Figure 7] This is a schematic cross-sectional view of a method step of an exemplary embodiment of the method for manufacturing a semiconductor device described herein. [Figure 8] This is a schematic cross-sectional view of a method step of an exemplary embodiment of the method for manufacturing a semiconductor device described herein. [Figure 9] This is a schematic cross-sectional view of a method step of an exemplary embodiment of the method for manufacturing a semiconductor device described herein. [Figure 10] This is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 11] This is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 12] This is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 13] These figures show deep-level transient spectral data of exemplary embodiments of the semiconductor devices described herein, and comparative examples. [Modes for carrying out the invention]

[0050] Figures 1 and 2 are schematic diagrams of a method for manufacturing a semiconductor device 1. In step S1 of the method, a semiconductor body 2 is provided. See also the descriptions of Figures 4 to 9 below. For example, the semiconductor body is SiC.

[0051] Next, in step S2, the first layer 21 of the semiconductor body 2 is fabricated by doping each region of the semiconductor body 2 with dopant 4. For example, the first layer 21 is p-doped in step S2. This can be achieved, for example, by ion implantation of dopant 4. Dopant 4 is, for example, Al.

[0052] Next, in step S3, a carbon-containing layer 3 is applied to the upper surface 20 of the semiconductor body 2. The upper surface 20 may be partially or completely formed by the first layer 21.

[0053] In the subsequent step S4, C is injected into the first layer at a lower concentration than dopant 4. According to Figure 1, in step S5, the temperature treatment is performed at a third temperature. In this step, both dopants are activated, and C can diffuse from the carbon-containing layer 3 into the semiconductor body 2, for example, into and / or through the first layer 21. Therefore, in the method shown in Figure 1 in the related method step, there is only one temperature treatment of the semiconductor body 2 at a high temperature, for example, above 1000°C.

[0054] In contrast, Figure 2 shows the existence of step S31. In step S31, a temperature treatment is performed at a second temperature. During this temperature treatment, dopant 4 is activated. After step S4, there is also step S5, in which C diffusion occurs at a first temperature. Therefore, in the method shown in Figure 2, activation and diffusion can be performed separately from each other. The first temperature can be lower than the second temperature.

[0055] Figure 3 shows the obtained doping profiles for dopant 4, such as Al, and injected C. Both profiles are box profiles. Note that Figure 3 shows the injection concentration c of dopant 4, but not the concentration of activated dopant 4. The concentration of activated dopant 4 is about two orders of magnitude lower than the actual injection concentration c of dopant 4. Therefore, the maximum injection concentration c of dopant 4 is about three orders of magnitude higher than the maximum injection concentration c of C.

[0056] As can be seen from Figure 3, the box profile of dopant 4 has a depth T of approximately 0.3 μm to 0.4 μm. The box profile depth T of injected C is approximately 0.2 μm. Following the upper surface 20, the doping concentration c is relatively low in both cases compared to the maximum injection concentration.

[0057] For example, the methods shown in Figures 1 and 2 can be carried out as follows. First, an anode, i.e., the first layer 21, is formed by Al ion implantation. For example, the energies are set to 30 keV, 60 keV, 110 keV, and 180 keV, and the total implantation amount is 10 15cm -2 When Al implantation is performed at a temperature of at least 100 °C, the Al concentration [Al] is about 10 20 cm -3 becomes a plateau, and the box profile depth becomes 0.4 μm. After that, Al activation is performed at a temperature of 1700 °C for 30 minutes.

[0058] Next, p + region, that is, a part of the first layer 21, C implantation is performed through the previously applied C cap, that is, a carbon-containing layer 3 with a thickness of about 0.15 μm, for example. The C implantation energy should be selected so that the C implantation profile is within 0.1 μm from the Al box profile tail region where T ≈ 0.4 μm. The implantation amount of implanted C i should be selected so that the concentration is lower than the implanted [Al] after activation. Assuming the activation rate of the dopant 4 is 2%, the implanted [C i is, for example, 10 17 cm -3 or less, corresponding to [Al] / [C i > 10. For example, in the profile of FIG. 3, C is implanted at an implantation amount of 5 × 10 9 cm -2 .

[0059] Finally, annealing is performed at a maximum of 1600 °C to diffuse C i . The C i coming from the C cap is also implanted into the second layer of the semiconductor body 2 such as the drift layer. Their concentrations are not sufficient to reduce [Z 10 cm -3 below the detection limit, for example, about 10 1 / 2 . Therefore, the implanted C i compensates for them.

[0060] Alternatively, referring to FIG. 2, C implantation can be performed before Al activation. In this case, the activation temperature also enables C i diffusion.

[0061] For example, a longer annealing time of at least 30 minutes is used to anneal a thicker second layer 22 having a thickness of approximately 100 μm. i It is possible to choose to spread it.

[0062] As a result, [V C ] drops below the detection limit. Two other levels, called ON1 and ON2, may be detected, but please compare them with B. Zippelius et al. above. These levels do not affect device performance. For example, standard p + In an in diode, p + Upon activation, a certain amount of V C Please note that this will always be detected.

[0063] For example, p that has not been treated as described herein by deep-level transient spectroscopy (DLTS). + V in n diode C (Z 1 / 2 The existence of p can be demonstrated, and p processed by the method described can be demonstrated. + V in n diode C The absence of ON1 and the appearance of ON2 can also be demonstrated.

[0064] Figures 4 to 9 show examples for fabricating a semiconductor device 1 which is a PIN diode. According to Figure 4, a semiconductor body 2 is provided. The semiconductor body 2 has a third layer 23 on a second layer 22. The second layer 22 is, for example, intrinsically doped or only very weakly n-doped. The third layer 23 is, for example, n-doped. The top surface 20 is on the second layer 22. The third layer 23 and / or the second layer 22 may be provided by epitaxy.

[0065] Figure 5 shows that the first layer 21 is formed by doping the semiconductor body 2 adjacent to the upper surface 20 with a dopant 4, for example, Al. The thickness of the first layer 21 is, for example, about 0.4 μm.

[0066] Subsequently, mesa 5 is formed by etching (see Figure 6). Etching is terminated at the second layer 22 so that the first layer 21 is completely removed in places.

[0067] As shown in Figure 7, for electric field protection, or to form a junction termination extension (JTE) as the fourth layer 24 of the semiconductor body, another injection, for example, is performed, again with Al. The carbon-containing layer 3 is applied to the entire upper surface 20, i.e., the mesa 5, as well as to the second layer 22 and the fourth layer 24. The fourth layer 24 may not completely span the second layer 22, but may be terminated laterally near the mesa 5. Otherwise, the same can be applied to the fourth layer 24 as to the first layer 21.

[0068] The injection region is activated, for example, at 1700°C, after which carbon is injected through the carbon-containing layer 3 (see Figure 8). The carbon-containing layer 3 may be a continuous, non-porous, and therefore uninterrupted layer. For example, the thickness of the carbon-containing layer 3 is constant.

[0069] Figure 8 also shows that the first layer 21 may optionally consist of two regions substantially separated from each other by horizontal lines within the first layer 21 in Figure 8. In the upper region adjacent to the top surface 20, a higher maximum p-doping concentration may exist than in the lower region. Therefore, the upper region is p + It may be doped, may function as a contact layer, and the lower region may be p-doped. This can be applied similarly to all other examples of semiconductor device 1.

[0070] Next, referring to Figure 9, C i To diffuse it, for example, low-temperature annealing is performed at a temperature below 1600°C. As a result, for example, the second layer 22, which is the drift layer, V C The amount decreases.

[0071] After temperature treatment, the carbon-containing layer 3 can be completely removed before applying, for example, electrodes or an electrical insulating layer.

[0072] An example of the completed semiconductor device 1 is shown in Figure 10. The semiconductor device 1 is a SiC-p with a mesa 5. + It is an in diode. Inside Mesa 5, for example, p + A fifth layer 25 of the semiconductor body 2, which is a contact layer, may exist. Also, the first layer 21 is located within the mesa 5. Starting from the first layer 21, the fourth layer 24 may extend laterally adjacent to the mesa 5 so that a JTE is formed. Layers 24 and 25 can be considered as special parts of the first layer 21, or as separate layers.

[0073] Below Mesa 5, for example, there is approximately 1 × 10⁻⁶ 15 cm -3 At a concentration of slightly n - There is a second layer 22 that is doped and can have a thickness of approximately 70 μm. The third layer 23 is made of, for example, SiC and has a doping concentration of 5 × 10⁻¹⁶ 18 cm -3 degree n + This is a doped substrate. The thickness of the third layer 23 is, for example, about 0.25 mm. The sides of the mesa, as well as the exposed areas of the second layer 22 and the fourth layer 24, are covered with an electrical insulating layer 6, which is, for example, silicon dioxide.

[0074] The fifth layer 25 above mesa 5 has a first electrode 71, which acts as an anode, and the third layer 23 has a second electrode 72, which acts as a cathode. Optionally, for example, n + A sixth circumferential layer 26 may exist in the semiconductor body 2, which is doped and functions as a channel stop. In a top view, the mesa 5 may be surrounded all around by the fourth layer 24 and the sixth layer 26, for example, in a rotationally symmetric manner.

[0075] Otherwise, the same thing that applies to Figures 1 through 9 also applies to Figure 10, and vice versa.

[0076] The semiconductor device 1 in Figure 11 is also a 4H-SiC based pin diode, but in contrast to the semiconductor device 1 in Figure 10, it is planar so that there is a flat top surface 20 without a mesa. In the design of Figure 11, the first electrode 71 is located on the side edge of the device 1. The first layer 21 is well-shaped and is located within the second layer 22. The thickness of the second layer 22 is, for example, about 10 μm. For example, the second layer 22 and the third layer 23 are each about 9 × 10 15 cm -3 and 1 × 10 19 cm -3 It is doped with n at a concentration of [value].

[0077] Otherwise, the same thing that applies to Figures 1 through 10 also applies to Figure 11, and vice versa.

[0078] Figure 12 shows that the semiconductor device 1 is an insulated-gate bipolar transistor (IGBT). Therefore, the first layer 21 is a well region. In the well region, for example, the first electrode 71, which is the emitter electrode, is, for example, p + A fifth layer, which is a plug, exists. Also, in the well region, there is a seventh layer of the semiconductor body 2, which is configured as the emitter region. Therefore, the second layer 22 is n - This is the drift region. For example, the second layer 22 is a substrate having a thickness between 50 μm and 200 μm. The doping concentration of the drift layer is, for example, 2 × 10 14 cm -3 It is to that extent.

[0079] The second layer 22 extends to the upper surface 20 between the two well regions when viewed in cross-section. An insulating layer 6 is present on the upper surface 20 above the well regions and the central portion of the second layer 22, separating the third electrode 73 from the semiconductor body 2. The third electrode 73 is the gate electrode.

[0080] Optionally, below the second layer 22, there are eight layers 28 of the semiconductor body 2 that can serve as buffer layers. For example, the buffer layers are approximately 1 × 10⁻⁶.18 cm -3 It is doped with n at the maximum doping concentration. The thickness of the buffer layer may be between 2 μm and 10 μm.

[0081] The third layer 23 is located on the side furthest from the top surface 20 of the second layer 22, or on the side furthest from the top surface 20 of the eighth layer 28. The third layer 23 is the collector region. The third layer 23 is, for example, 1 × 10 19 cm -3 It has a doping concentration of a certain degree. The thickness of the third layer 23 is, for example, 2 μm to 10 μm. The second electrode 72 of the third layer 23 is a collector electrode.

[0082] Similarly, the semiconductor device 1 may be a metal-insulator-semiconductor field-effect transistor (MISFET) or a metal-oxide-semiconductor field-effect transistor (MOSFET). In this case, the eighth layer 28 may be omitted, and the third layer 23 may be, for example, at least 1 × 10 18 cm -3 Or at least 5 × 10 18 cm -3 or at least 1 × 10 19 cm -3 and / or up to 5 × 10 20 cm -3 or up to 2 x 10 20 cm -3 or up to 1 x 10 20 cm -3 This is the n-doped drain region having the maximum doping concentration. In this case, the seventh layer 27 is the source region, and the first electrode 71 and the second electrode 72 are the source electrode and drain electrode, respectively.

[0083] Aside from those shown, the IGBT, MISFET, or MOSFET does not need to be a planar design, and may be a trench design in which the gate electrode 73 is housed in a trench not shown.

[0084] Otherwise, the same thing that applies to Figures 1 through 11 also applies to Figure 12, and vice versa.

[0085] The data in Figure 13 for Comparative Example 9 and Semiconductor Device 1 described herein were obtained by Deep Level Transient Spectroscopy (DLTS). The measurements were performed under a reverse bias of -5V. r and a pulse voltage of 5V V p The procedure was performed as follows. The filling pulse length was 1 ms with a period width of 0.2 seconds. The semiconductor device 1 was processed as described in relation to Figures 4 to 9, but in the case of Comparative Example 9, there was no low-injection C ion implantation via the carbon-containing layer. In Comparative Example 9, Z 1 / 2 As shown by the peak, V C It can be seen that there is a strong presence of Z. In contrast, in the example of semiconductor device 1, Z 1 / 2 There are no peaks; instead, there are peaks corresponding to states ON1 and ON2.

[0086] Typically, V in n-type 4H-SiC as grown. C The concentration is 10 11 cm -3 ~10 12 cm -3 At such concentrations, the lifetime of minority carriers is approximately 1 μs. This value is quite low and unsuitable for SiC bipolar devices. Allowable [V] C ] is, for example, 10 11 cm -3 It is less than. High-voltage SiC bipolar devices have low doping concentrations, i.e., 10 14 cm -3 Since it depends on the domain, [V C The threshold for detecting ] is approximately 10 10 cm -3 It is possible. Therefore, V C The detection threshold limit is approximately four orders of magnitude lower than the doping concentration. Therefore, 10 14 cm -3 doping concentration and 5 × 10 10 cm-3 ~8×10 10 cm -3 or even lower [V C SiC bipolar devices having [ ] function well.

[0087] The methods described herein have, for example, the following advantages: -C i Since it is supplied by the C cap and injected C, by performing C injection into the anode via the C cap, effective V C Removal becomes possible.

[0088] Unlike Hamada et al., C injection can be performed with a low injection volume, thus avoiding amorphous formation of the drift layer.

[0089] -Unlike Hamada et al., C i Since it is an acceptor for n-type SiC, carbon injection is performed at the anode rather than the drift layer, thus avoiding doping compensation.

[0090] Unlike Storasta et al., structuring such as etching of the C-containing layer is not necessary. -Unlike Ayedh et al., C i Since it is supplied not only from the C-cap but also from the injection process, residual V C It won't remain.

[0091] - Low injection volume C injection avoids excessive defect formation in the anode layer, i.e., the first layer, and thus maintains injection efficiency.

[0092] 7) To detect carbon in the anode layer, reverse engineering of the final product is possible, for example, by secondary-ion mass spectrometry (SIMS).

[0093] - To detect ON1 and ON2 states, reverse engineering is possible even in the final product, for example, using DLTS.

[0094] - An anode layer of any thickness can be formed. Unless otherwise indicated, the components shown in the diagram are, illustratively, arranged directly on top of each other in the specified order. Components that are not in contact in the diagram are, illustratively, spaced apart from each other. Where lines are drawn parallel to each other, the corresponding surfaces may be oriented parallel to each other. Similarly, unless otherwise indicated, the relative positions of the depicted components are accurately reproduced in the diagram.

[0095] The invention described herein is not limited by the description based on exemplary embodiments. Rather, the invention also encompasses any new features, and in particular any combination of features including any combination of features in the claims, even if these features or combinations themselves are not expressly specified in the claims or exemplary embodiments. [Explanation of Symbols]

[0096] List of reference symbols 1 Semiconductor device 2. Semiconductor body 20 Top surface of the semiconductor main unit 21. The first layer of the semiconductor body 22 The second layer of the semiconductor body 23. The third layer of the semiconductor body 24. The fourth layer of the semiconductor body 25. The fifth layer of the semiconductor body 26. The sixth layer of the semiconductor body 27. The seventh layer of the semiconductor body 28. The eighth layer of the semiconductor body 3. Carbon-containing layer 4 Dopant 5 Mesa 6. Insulating layer 71 First electrode 72 Second electrode 9 Comparative Examples A. Absolute temperature (K) Al Aluminum Ion Implantation c cm -3 concentration C carbon ion implantation DLTS pF deep-level transient spectroscopy data First other level in the ON1 band structure Second other level in the ON2 band structure S.. Method Step T Depth from the top surface to the inside of the semiconductor body Z 1 / 2 Activity level within the band gap

Claims

1. A method for manufacturing a semiconductor device (1), comprising the following steps: A) To provide a semiconductor body (2) having an upper surface (20), which is made of SiC, B) Manufacturing the first layer (21) of the semiconductor body (2) adjacent to the upper surface (20) by doping with dopant (4), C) Applying a carbon-containing layer (3) to the upper surface (20), D) The first layer (21) via the carbon-containing layer (3) contains a maximum of 1 × 10 １２ cm －２ Inject C in the following amount, E) The semiconductor body (2) is subjected to temperature treatment while the carbon-containing layer (3) is still present on the upper surface (20), It includes the items listed in the order they are described. A method wherein the concentration of the dopant (4) provided and activated in step B) is at least 3 times and up to 30 times the concentration of C injected in step D).

2. The concentration of the dopant (4) provided and activated in step B) is at least 6 times and up to 15 times the concentration of C injected in step D). The method according to claim 1.

3. In step E), the temperature treatment includes applying a first temperature, The first temperature is between 1400°C and 1800°C. In step E), C diffuses from the carbon-containing layer (3) to the first layer (21). The method according to claim 1 or 2.

4. The process B2) is further included between process B) and process D), B2) Activating the dopant (4) by applying a second temperature, The second temperature is 1400°C or higher and 1800°C or lower, further comprising activation. The method according to claim 1 or 2.

5. In step E), C diffuses from the carbon-containing layer (3) to the first layer (21), and the dopant (4) is activated. In step E), the temperature treatment includes applying a third temperature, In step E), the third temperature is 1400°C or higher and 1800°C or lower. Between process A) and process E), the temperature of the semiconductor body (2) is maintained below 800°C. The method according to claim 1 or 2.

6. In step B), the doping is provided by ion implantation. The method according to claim 1 or 2.

7. The dopant (4) is Al, The dopant (4) is 10 １３ cm －２ ~10 １６ cm －２ Provided in injection volumes between, The method according to claim 1 or 2.

8. In step D), the first injection energy is at least 10 keV and at most 300 keV. The method according to claim 1 or 2.

9. After step D), the first box profile depth of the dopant (4) is greater than the second box profile depth of C. The first box profile depth is 0.1 μm or more and 1.2 μm or less. The method according to claim 1 or 2.

10. Between process B) and process C) is process B1), B1) Etching the semiconductor body (2) such that a mesa (5) is formed, further comprising etching to a depth greater than the thickness of the first layer (21), The method according to claim 1 or 2.

11. In step C), the carbon-containing layer (3) is applied to the entire semiconductor body (2), The carbon-containing layer (3) comprises at least one of graphite and photoresist, and the thickness of the carbon-containing layer (3) is at least 0.1 μm and at most 0.9 μm. The method according to claim 1 or 2.

12. In the completed semiconductor device (1), the semiconductor body (2) further comprises a second layer (22) directly on the side of the first layer (21) that is farther from the upper surface (20), The second layer (22) is doped with a lower doping concentration than the first layer (21). The thickness of the second layer (22) is 10 μm to 100 μm. The method according to claim 1 or 2.

13. The first layer (21) is 4H-SiC, In the completed semiconductor device (1), the first layer (21) is an anode layer. The method according to claim 1 or 2.

14. The completed semiconductor device (1) is either a pin diode, an insulated-gate bipolar transistor (IGBT), or a reverse-conducting insulated-gate bipolar transistor (RC-IGBT). The method according to claim 1.

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