Zero-crossing detection system and method for DC-DC converters

Abstract

To provide a zero-crossing detector (ZCD) for a direct current to direct current (DC-DC) converter.SOLUTION: A ZCD 900 is provided with a ZCD integrator for receiving a switch voltage VSW and an output voltage of a power stage of a DC-DC converter, and generating a zero-crossing detect signal 928 based, at least in part, on the received switch voltage and output voltage Vout. The zero-crossing detect signal indicates an output current in an output inductor of the power stage of the DC-DC converter is approximately zero. The ZCD may also include a ZCD offset calibrator that receives the switch voltage and generate a ZCD calibration offset based, at least in part, on the received switch voltage, where the ZCD integrator generates the zero-crossing detect signal based, at least in part, on the ZCD calibration offset.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] This application generally relates to a direct current to direct current (DC-DC) converter, and more particularly, to a system and method for zero-crossing detection and associated timing acquisition in, for example, a discontinuous conduction mode DC-DC converter.

Background Art

[0002] Power converters including direct current to direct current (DC-DC) converters are used to supply power to many electronic devices. The amount of load drawn by these electronic devices varies from device to device and may also vary over time for each device. Some electronic devices, and / or modules within an electronic device, may be lightly loaded and draw minimal current, while other electronic devices / modules may be heavily loaded and draw a relatively large amount of current. Such loads can vary within the same device or between interconnected devices depending on usage and mode. When a particular load varies, conventional switched-mode DC-DC converters often produce voltage ripple and / or radio frequency interference, which can negatively impact the performance of the device. Additionally, conventional switched-mode DC-DC converters are often negatively affected by various inefficient operating modes. Therefore, there is a need in the art for improvements to DC-DC converters that reduce these and other negative effects.

Summary of the Invention

[0003] This disclosure describes an improved direct current to direct current (DC-DC) converter that includes an improved system and method for adjusting the output of a DC-DC converter. A circuit is described in accordance with one embodiment of the disclosure.

[0004] In one embodiment, the DC-DC converter may include a DC-DC converter controller configured to receive the output voltage of the DC-DC converter and adjust the switching frequency of the DC-DC converter in response to the output load state of the DC-DC converter. An output load sensor may be configured to determine the output load state and supply a peak current target value to the DC-DC controller. The output load sensor includes a first timer configured to supply a delayed first signal to the peak current controller in response to a heavy output load, a second timer configured to supply a delayed second signal to the peak current controller in response to a light output load, and a peak current control configured to adjust the peak current target value based at least in part on the received first and second signals and supply the peak current target value to the DC-DC converter control.

[0005] In other embodiments, the method may include measuring the timing between a first switching cycle of the DC-DC converter and a second switching cycle of the DC-DC converter; determining whether the second switching cycle begins before the end of a predetermined first time; and incrementing a peak current target value when the second switching cycle begins before the end of the predetermined first time.

[0006] In one embodiment, a zero-crossing detector (ZCD) for a DC-DC converter comprises a ZCD integrator configured to receive a switch voltage and the output voltage of the power stage of the DC-DC converter, and generate a zero-crossing detection signal based at least partially on the received switch voltage and output voltage. Here, the zero-crossing detection signal is configured to indicate that the output current in the output inductor of the power stage of the DC-DC converter is approximately zero. In various embodiments, the ZCD may further comprise a ZCD offset calibrator configured to receive a switch voltage and generate a ZCD calibration offset based at least partially on the received switch voltage. Here, the ZCD integrator is configured to generate a zero-crossing detection signal based at least partially on the ZCD calibration offset. The ZCD may further comprise an idle release generator configured to receive a switch voltage and the input voltage to the power stage of the DC-DC converter, and generate an idle release signal based at least partially on the received switch voltage and input voltage. Here, the idle release signal is configured to indicate that the DC-DC converter is ready to exit its idle mode.

[0007] In other embodiments, a method for operating a ZCD for a DC-DC converter may include: receiving a switch voltage and the output voltage of the power stage of the DC-DC converter by the ZCD integrator of the ZCD; and generating a zero-crossing detection signal based at least partially on the received switch voltage and output voltage. Here, the zero-crossing detection signal is configured to indicate that the output current at the output inductor of the power stage of the DC-DC converter is approximately zero. In various embodiments, the method may include: receiving a switch voltage and generating a ZCD calibration offset based at least partially on the received switch voltage by the ZCD offset calibrator of the ZCD; here, generating the zero-crossing detection signal is based at least partially on the ZCD calibration offset. The method may further include: receiving a switch voltage and the input voltage to the power stage of the DC-DC converter by an idle release generator; and generating an idle release signal based at least partially on the received switch voltage and input voltage. Here, the idle release signal is configured to indicate that the DC-DC converter is ready to exit its idle mode.

[0008] The scope of this disclosure is defined by the claims incorporated into this chapter by reference. A more complete understanding of the embodiments of this disclosure, along with the realization of their additional advantages, can be obtained by considering the following detailed descriptions of one or more embodiments. An appendix of drawings, briefly described first, will be referenced. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a block diagram of a DC-DC converter according to one embodiment of the present disclosure.

[0010] [Figure 2] Figure 2 is a block diagram of a DC-DC converter showing the interconnections between various modules according to one embodiment of the present disclosure.

[0011] [Figure 3] Figure 3 is a circuit diagram of a load sensing circuit and a control circuit for a DC-DC converter according to one embodiment of the present disclosure.

[0012] [Figure 4] Figure 4 is a timing diagram showing various waveforms representing the transition of a DC-DC converter from a good load state to a heavy load state, according to one embodiment of the present disclosure.

[0013] [Figure 5] Figure 5 is a timing diagram showing various waveforms representing the transition of a DC-DC converter from a well-loaded state to a light-loaded state, according to one embodiment of the present disclosure.

[0014] [Figure 6] Figure 6 is a timing diagram showing various waveforms representing the transition of a DC-DC converter from a heavy load state to a light load state, according to one embodiment of the present disclosure.

[0015] [Figure 7] Figure 7 is a timing diagram showing various waveforms representing the transition of a DC-DC converter from a good-load state to a good-load state, according to one embodiment of the present disclosure.

[0016] [Figure 8] Figure 8 shows a waveform of adaptive peak current control for adjusting the switching frequency according to one embodiment of the present disclosure.

[0017] [Figure 9] Figure 9 is a circuit diagram of a zero-crossing detector (ZCD) for a DC-DC converter according to one embodiment of the present disclosure.

[0018] [Figure 10] Figure 10 is a flowchart illustrating the process of realizing a state machine for operating a ZCD for a DC-DC converter, according to one embodiment of the present disclosure.

[0019] [Figure 11] FIG. 11 is a flowchart showing a process for operating a ZCD for a DC-DC converter according to an embodiment of the present disclosure.

[0020] [Figure 12] FIG. 12 is a flowchart showing a process for operating a ZCD for a DC-DC converter according to an embodiment of the present disclosure.

[0021] Embodiments of the present disclosure and their advantages are best understood by referring to the following detailed description. Unless otherwise indicated, like reference numerals throughout the accompanying drawings and written description indicate like elements. Accordingly, their description will not be repeated here. For clarity, the relative sizes of elements, layers, and regions may be emphasized in the drawings.

Mode for Carrying Out the Invention

[0022] A direct current-to-direction (DC-DC) power converter ("converter") generally receives an input voltage at a first voltage level and converts this input voltage to an output voltage at a second voltage level. For example, a "step-down" converter may receive an input voltage of 5V and provide a lower, or stepped-down, output voltage of 1.5V, while a "step-up" converter may receive an input voltage of 5V and provide a higher, or boosted, output voltage of 7V. The output of a DC-DC converter may be coupled to a load that may include various components of electronic devices, such as electronic devices and / or components of other electronic devices or multiple devices. Embodiments of this disclosure provide systems and techniques for monitoring the output load condition (e.g., heavy load, light load, or good / medium load) and adjusting the output voltage and switching frequency of the DC-DC converter according to the appropriate load condition. Embodiments of the present disclosure further provide systems and techniques for improving the overall efficiency of a DC-DC converter through the use of a reliable, accurate, and relatively low-power zero-cross detector (ZDC) configured to help control the timing of various modes, cycles, and switching of the DC-DC converter, as described herein.

[0023] Figure 1 is a block diagram of a DC-DC converter 100 according to one embodiment of the present disclosure. In Figure 1, the DC-DC converter 100 includes a power stage 110, a controller 120, and an output load sensor 130. The power stage 110 may be configured to receive an input voltage (e.g., 5V DC) and convert it to another voltage (e.g., 1.5V DC) supplied as the output voltage from the DC-DC converter 100. The power stage 110 may be implemented as a boost converter, a buck converter, a buck-boost converter, a synchronous or asynchronous discontinuous conduction mode (DCM) DC-DC converter, and / or other types of DC-DC converters, such as other types of power converters, as described herein. The output load sensor 130 may be configured to determine the load state of the DC-DC converter 100 and to supply this load state and / or related information to the controller 120. The controller 120 may be configured to coordinate the power conversion by generating feedback supplied to the power stage 110 as various control signals, as described herein. Each of the power stage 110, the controller 120, and the output load sensor 130 may be implemented, for example, as one or more logic devices (e.g., microcontrollers, field-programmable gate arrays, and / or other logic devices), analog or digital circuit elements, and / or other circuits, and may be coupled together and / or configured to implement any of the various power converters, for example, including any of the power converters described herein.

[0024] The operation of the DC-DC converter 100 in Figure 1 will be described in further detail here in relation to the block diagram in Figure 2. The block diagram in Figure 2 shows additional and / or alternative interconnections between various elements of the DC-DC converter 100 according to one embodiment of the present disclosure. For example, the output load sensor 130 determines the output load status of the DC-DC converter 100 and / or the power stage 110, and the Heavy_load_status and / or logic signal Ipeak_control <a:0>The power stage may be configured to supply the controller 120 with values ​​corresponding to the output load state via one or more load state signals, such as the above. The controller 120 may then be configured to control the power stage 110 based on such load state signals in the form of one or more control signals supplied to the power stage 110 (for example, logic / control signals hs_on or ls_on configured to enable / disable the high and low FETs of the power stage 110, as described herein). The power stage 110 may be configured to receive and utilize such control signals to supply and / or regulate the peak current of the power stage 110, and in this way to regulate the power conversion of the DC-DC converter 100.

[0025] Figure 3 shows a circuit diagram of an output load sensor 330 and a controller 320 of a DC-DC converter 300 according to one embodiment of the present disclosure. The output load sensor 330 and the controller 320 may be configured to monitor the output load state of the DC-DC converter 300 (DC-DC step-down converter) using the continuous timer of the output load sensor 330. The controller 320 (e.g., a DC-DC converter control circuit of an asynchronous DCM) may be configured to control the adaptive peak current using the output load state so that the DC-DC converter 300 can reduce switch noise interference by adjusting the switching frequency of the DC-DC converter 300 between audible and radio frequencies across different output loads to reduce switch noise interference by supplying a higher output load capacitance when the output load is heavy and a smaller output voltage ripple when the output load is light. In addition, the controller 320 may be configured to adaptively change the power mode of the DC-DC converter 300 to power-save mode under relatively light output load conditions (for example, by disabling the zero-cross detector 322 and peak current detector 324 and reducing the quiescent currents specific to the operation of detectors 322 and 324) and to power burst mode under relatively heavy output load conditions to support higher output load capacities (for example, by forcibly enabling the zero-cross detector 322 and peak current detector 324 and increasing the cycle speed of the DC-DC converter 300).

[0026] Adaptive peak current control, as described herein, can provide higher output load capacity by incrementing the peak current, lower output voltage ripple by decrementing the peak current, and control the switching frequency of the DC-DC converter 300 by varying the peak current. For example, in audio and wireless applications, varying the switching frequency of the DC-DC converter 300 between audible and radio frequencies may be desirable to reduce interference from switching noise coupled with the operating frequency of the voice or wireless device. While pulse density modulation techniques can be used for peak current control, pulse density modulation uses a relatively high-frequency oscillator (e.g., oscillator frequency ≥ maximum DC-DC switching frequency). This can be difficult to implement in relatively low-power asynchronous DC-DC converters. Therefore, embodiments of the present disclosure present a technique for performing adaptive peak current control using two continuous timers and asynchronous DC-DC converter control configured for applications to DC-DC converters with low quiescent current, as described herein. In some embodiments, more than two timers, for example three or more timers, may be used to control the adaptive peak current at a higher granularity.

[0027] In some embodiments, such as the DC-DC converter of an asynchronous DCM, the peak current detector 324 and zero-cross detector 322 may consume the largest quiescent current in the controller 320 while enabled. Therefore, the controller 320 may be configured to disable such detectors when the output load is light (e.g., power-save mode), such that the quiescent current is comparable to the current of a light output load. However, when the detectors are disabled, the controller 320 generally needs to wait for the detectors to be re-enabled before proceeding to the next switching cycle. The accompanying enable settling delay may reduce the maximum achievable output load capacity by limiting the highest achievable switching frequency. On the other hand, when the output load is relatively heavy, the quiescent current of the detectors is typically negligible compared to the output load current, and therefore the peak current detector 324 and zero-cross detector 322 may be kept enabled to support heavier output load capacities (e.g., power-burst mode) without significantly reducing conversion efficiency. Accordingly, the embodiments described provide adaptive power mode control in a DC-DC converter of an asynchronous DCM by using continuous timers (e.g., Heavy_delay_cell332 and Light_delay_cell334) in an adaptive peak current control methodology.

[0028] As shown in Figure 3, the DC-DC converter controller 320 of the asynchronous DCM may be configured to initiate a switching cycle (e.g., one cycle in this case: hs_on=high, ls_on=low; hs_on=low, ls_on=high; hs_on=low, ls_on=low, -idle mode proceeds) when the output comparator (comp1) senses that the output voltage (Vout) generated by the power stage 110 is lower than a threshold voltage (e.g., VREF, which is the desired output voltage of the DC-DC converter 300) and the output comparator (comp1) transitions the vout_islow signal to logic high. The vout_islow signal is supplied to a reset-priority SR latch (sr1) (e.g., via the AND gate DCM_and, which gates vout_islow with an idle release signal release_idle_time, configured to indicate that the DC-DC converter 300 is ready to exit idle mode and initiate the next switching cycle while maintaining the operation of the DCM, as described herein). The SR latch (sr1) latches the vout_islow_latch signal. When the vout_islow_latch signal is logic high, the enable signals supplied to each detection block (e.g., zero-cross detector 322 and peak current detector 324) also go high when the output load is light (e.g., heavy_load_status = low).

[0029] When the enable signal goes high, the controller 320 waits for an enable settling delay (en_delay) to ensure that detectors 322 and 324 are operational before turning on the high-side field-effect transistor (FET) (hs_on=high) of the power stage 110. When the high-side FET is turned on, the output current of the inductor output of the power stage 110 increases and is monitored by the peak current detector 324. The peak current detector 324 checks if the inductor current is Ipeak_control <a:0>If it detects that the value is greater than the value set by the zero-cross detector, the Ipeak signal goes high. This then turns off the high-side FET and on the low-side FET of the power stage 110 (hs_on=low, ls_on=high), thereby reducing the inductor current. As the inductor current approaches zero, the zero-cross detector 322 goes high, turns off the low-side FET (ls_on=low), and enters idle mode (both the high-side and low-side FETs are off). After a minimum idle delay (idle_delay), the DC-DC converter 300 is ready for the next switching cycle when vout again falls below VREF.

[0030] In Figure 3, the output load sensor 330 comprises two continuous timers (heavy_delay_cell 322 and light_delay_cell 334) and a peak current controller 336 (Ipeak_control). In some embodiments, the peak current controller 336 (Ipeak_control) may be implemented as a 4-bit digital logic device / controller configured to output various levels of the peak current target value in 16 different increments. In other embodiments, the peak current controller 336 (Ipeak_control) may be implemented as, for example, a 3-bit or 5-bit controller, or as a controller of different bit widths, to provide, for example, a wider or narrower dynamic range and / or peak current resolution. At the end of the switching cycle, the DC-DC converter 300 enters idle mode, the vout_islow_latch signal transitions to logic low by reset-priority SR latch (sr1) reset=high, and the heavy_delay_cell begins an X falling-fall delay. During the X falling-fall delay, the heavy_load signal remains high (indicating a "heavy" load state), and after the X delay, heavy_load transitions to a logical low.

[0031] When the heavy_load signal goes low, the light_delay_cell starts a Y rising edge delay. During the Y rising edge delay, both the heavy_load and light_load signals are low (indicating that the load is in a state between heavy and light load; referred to herein as "good" or "medium" load). After the Y rising edge delay, the light_load signal goes logically high (indicating a "light" load). The light_load and heavy_load signals are sampled by the peak current controller 336 (Ipeak_control) and the D flip-flop (dff1) respectively using the rising edge of the vout_islow_latch signal. If heavy_load=high and light_load=low when sampled, the load state of the DC-DC converter 300 is a "heavy" load, and the time between switching cycles is shorter than the X delay (as set, for example, by detectors 322 and 324). If heavy_load=low and light_load=low when sampled, the load state of the DC-DC converter 300 is a "good" load state, and the time between switching cycles is between X and X+Y (including X and X+Y). If heavy_load=low and light_load=high when sampled, the load state of the DC-DC converter 300 is a "light" load state, and the time between switching cycles is longer than the time between X+Y.

[0032] In various embodiments, as shown in the figures, based on the sampled heavy_load signal and light_load signal, the peak current controller 336 (Ipeak_control) controls the Ipeak_control <a:0>Incrementing this variable increases the peak current under heavy load conditions, and Ipeak_control <a:0>The configuration may be configured to decrement the peak current under light load conditions while maintaining the same peak current under good load conditions. In some embodiments, dff1 samples the heavy_load signal to enable power burst mode (heavy_load_status=high). If heavy_load_status=high, the enable and en_settle signals are held logic high by an OR gate (or1) for the next switching cycle. Power burst mode (heavy_load_status=high) bypasses the enable settling delay (en_delay) by holding a logic high signal at the input of (en_delay), turning on the high-side FET as soon as the shortest idle time (idle_delay) ends.

[0033] In various embodiments, heavy_delay_cell332 may be implemented with an additional 10 nanosecond rise time to reduce or avoid sampling of incorrect heavy_load=high. For example, when the vout_islow_latch signal transitions to logical high, the heavy_load signal will transition to logical high 10 nanoseconds later. Therefore, if the heavy_load signal is logical low at the rising edge of the vout_islow_latch signal, heavy_load=low will be sampled. Furthermore, this 10 nanosecond rise delay keeps the light_load signal high in order to sample light_load=high. Therefore, if the light_load signal is high at the rising edge of the vout_islow_latch signal, light_load=high will be sampled. To avoid sampling of incorrect heavy_load=high and to correctly sample light_load=high, a 10 nanosecond delay and / or other shorter or longer delays may be selected. Accordingly, in some embodiments, the 10ns delay may be longer or shorter. In some embodiments, heavy_delay_cell332 and light_delay_cell334 may be implemented using a resistor-capacitor delay or a bias current-capacitor delay to achieve a substantially zero quiescent current. More generally, heavy_delay_cell332 and light_delay_cell334 may be implemented using any combination of digital and / or analog circuits configured to supply the heavy_load and light_load signals described herein.

[0034] Figure 4 is a timing diagram showing various waveforms when a DC-DC converter transitions from a good load state to a heavy load state according to one embodiment of the present disclosure. As shown, when vout_islow_latch transitions to high, both the heavy_load signal and the light_load signal are initially low. This indicates that the previous switching cycle was a good load state. Since heavy_load=low and light_load=low are sampled according to the vout_islow_latch signal, Ipeak_control <x:0>The same peak current target value is maintained. Also, the heavy_load_status signal is low (e.g., power save mode). At the end of the first switching cycle, when the zero-cross detection goes high, the reset signal remains high for the shortest idle time and the vout_islow_latch signal goes low. When the vout_islow_latch signal goes low, heavy_delay_cell332 starts an X falling delay. Before the X falling delay ends, vout_islow is set high and the second switching cycle begins. Then, when the vout_islow_latch signal goes high, it samples heavy_load=high and light_load=low, indicating a heavy load condition. Accordingly, for example, to support a higher load capacity, the peak current controller 336 sets the peak current target value Ipeak_control <a:0>This is incremented from 4 to 5. Then, ddf1 samples heavy_load, sets heavy_load_status=high, and enables power burst mode.

[0035] Because the first switching cycle was under a "good" load condition, all detectors 322 and 324 were initially disabled to reduce the flow of quiescent current. When the vout_islow_latch signal goes high for the second switching cycle, it enables 322 and 324 and waits only an enable set delay (en_delay) before turning on the high-side FET of power stage 110. At the end of the second switching cycle, an X falling delay begins, and before the X falling delay ends, the vout_islow_latch signal goes high and the third switching cycle begins. heavy_load=high and light_load=low are sampled (e.g., a "heavy" load condition), and therefore, for example, to support even larger load capacities, the peak current control block Ipeak_control <a:0>The value is incremented from 5 to 6. Because the previous switching cycle (second cycle) was under heavy load (heavy_load_status=high), detectors 322 and 324 remained active. Therefore, the DC-DC asynchronous controller 320 bypasses the enable settling delay (en_delay) and immediately starts turning on the high-side FET (e.g., power burst mode). Peak current target value Ipeak_control <a:0>By incrementing the value and bypassing the enable settling time, the DC-DC converter 300 can increase its maximum output load capacity.

[0036] Figure 5 is a timing diagram showing various waveforms when a DC-DC converter 300 transitions from a good load state to a light load state according to one embodiment of the present disclosure. As shown, the DC-DC converter 300 starts in a "good" load state (e.g., sampled heavy_load=low and light_load=low). At the end of the first switching cycle, zero-cross detection goes high and the vout_islow_latch signal goes low due to the reset signal.

[0037] Under light load conditions, vout remains higher than VREF for a longer period, and therefore vout_islow and vout_islow_latch remain low for a longer period than the X+Y delay. After the X delay, heavy_load transitions to low due to the X falling-edge delay of heavy_delay_cell332, and the Y rising-edge delay of light_delay_cell334 begins. After the Y delay, light_load transitions to high (light load condition), and when the vout_islow_latch signal also transitions to high, light_load=high is sampled. Finally, to reduce output voltage ripple and increase the switching frequency, Ipeak_control is used. <a:0>This value is decremented. Due to power-saving mode, heavy_load_status also goes to low.

[0038] Figure 6 is a timing diagram showing various waveforms when a DC-DC converter transitions from a heavy load state to a light load state according to one embodiment of the present disclosure. As shown, heavy_load is initially high, and therefore when the vout_islow signal transitions, heavy_load=high is sampled, and heavy_load=high sets heavy_load_status to high. Because heavy_load_status is high, the enable signals for detectors 322, 324 are held high. However, after an X+Y delay from the end of the first switching cycle, light_load transitions to high. The inverted light_load signal gates heavy_load_status to low via an AND gate (and1). Therefore, as described herein, when light_load transitions to high, the enable signal transitions to low, disabling detectors 322, 324 and entering power-saving mode.

[0039] Figure 7 is a timing diagram showing various waveforms when the load of a DC-DC converter is in a steady state, according to one embodiment of the present disclosure. In the steady state, the switching frequency is already in a good load state and remains in a good load state. For example, Figure 4-6 shows a procedure in which the load changes abruptly, for example, from heavy load to light load, medium load, or any combination thereof. In these procedures, the peak current is adaptively adjusted to a good load state by the peak current controller 336 for the new output load value. Thus, after the abrupt load change, the output load becomes steady, the adaptive peak current loop is completed, and the DC-DC converter 300 converges to a good load state regardless of the updated output load value. Therefore, as shown in Figure 7, when the load does not change, the DC-DC converter 300 remains in a good load state (e.g., sampled heavy_load=low and light_load=low). Since all switching cycles start during the Y delay, when the output load is in a steady state, the converted good load state causes the switching period to be between X and X+Y.

[0040] Figure 8 shows a waveform of adaptive peak current control for adjusting the switching frequency according to one embodiment of the present disclosure. For example, adaptive peak current control adjusts the switching frequency between the audible frequency and the radio frequency. If the switching frequency is too high and interferes with the radio frequency (block 810), the peak current may be incremented to lower the switching frequency in the next cycle, thereby bringing the peak current within a good switching frequency range. If the switching frequency is too low (block 820) and interferes with the audible frequency, the peak current may be decremented to raise the switching frequency in the next pulse, thereby bringing the peak current within a good switching frequency range. When the output load is in a steady state, the switching frequency may be adjusted between 1 / X and 1 / (X+Y), as shown. By setting the X delay to be longer than the period of the radio frequency (e.g., longer than 415 nanoseconds corresponding to a 2.4 MHz Bluetooth® application) and the X+Y delay to be shorter than the period of the audible frequency (e.g., longer than 25 microseconds corresponding to a maximum audible frequency of 40 kHz), the DC-DC converter of the asynchronous DCM (e.g., DC-DC converter 300) can reduce interference to audible and radio frequencies by pushing and holding the peak current within a good switching frequency range. In some embodiments, a Z delay (or additional delay) may be added for further adjustment and peak current control.

[0041] In some embodiments, the described technique may be implemented for a synchronous DC-DC converter. However, a synchronous DC-DC converter may consume more quiescent current for the oscillator. In further embodiments, more than two timers may be implemented to check more than three output load states. For example, four sequential timers may check the following five output load states: for example, 1) a "heavy load state" incrementing the peak current target value by 2 LSB, 2) a "heavy load state" incrementing the peak current target value by 1 LSB, 3) a "good load state" maintaining the same peak current target value, 4) a "light load state" decrementing the peak current target value by 1 LSB, and 5) a "heavy light load state" decrementing the peak current target value by 2 LSB. The switching frequency may then converge to the good load state more quickly.

[0042] As described above, embodiments described herein may incorporate a zero-crossing detector (ZCD) design using an integrator circuit that simulates a relatively power-efficient profile of the output inductor current of the DC-DC converter of the DCM for initiating the on-time of the low-side FET that crosses the zero output current in the output inductor of the power stage 110. Embodiments may be robust to power-ground noise, as described herein, and the inherent ZCD timing errors may be calibrated and corrected using an inductor current direction detector and calibration controller (e.g., by implementing a calibration process) to achieve relatively high and / or optimal DC-DC converter efficiency.

[0043] The previous ZCD design senses when the switch voltage is equal to the power ground voltage (pvss) to detect the zero-crossing point of the output current in the output inductor of the power stage for the DC-DC converter. This is sensitive to ground noise. Due to the sharp current transition from the sudden transition from the high-side FET ON (hs_on) to the low-side FET ON (ls_on), and the parasitic inductance in pvss, a large spike in the pvss voltage is expected. Therefore, the previous methodology may generate an incorrect ZCD transition that can lead to functional problems (overheating, Vout drop, reduced operating efficiency, buck failure, and / or damage to the DC-DC converter). In the embodiments described herein, the ZCD comprises a ZCD integrator configured to detect the zero-crossing point by charging / discharging an integrator capacitor (Cint) according to the difference (e.g., current of (VSW-Vout) / Rint) between the switch voltage VSW supplied through the input resistor (Rint) and the output voltage Vout, between hs_on and ls_on. This ZCD integrator is robust against PVSS noise.

[0044] Furthermore, the above method requires sensing relatively small voltage changes (e.g., close to pvss) that are roughly proportional to the Ron* inductor current of the low-side FET. Therefore, such methods require comparators with extremely small offsets. Such comparators are often implemented using offset cancellation techniques, which are typically sensitive to noise during the offset sampling phase. In contrast, the ZCD embodiments described herein sense voltage changes at relatively high voltage levels (e.g., the output voltage of the ZCD integrator). Therefore, these embodiments do not require high-performance comparators.

[0045] Furthermore, the above-described ZCD designs suffered from errors due to offset and delay. The embodiments of the ZCD described herein implement an automatic ZCD calibration technique using an inductor current direction detector and a calibration controller to compensate for ZCD errors caused by non-idealism. The calibration controller automatically calibrates the ZCD error to the minimum ZCD error that allows for optimal efficiency. Pre-emptive or delayed zero-crossing detections within the ZCD error can significantly reduce the efficiency of the DC-DC converter.

[0046] Figure 9 shows a schematic of a ZCD900 for DC-DC converters (e.g., DC-DC converter 100, DC-DC converter 200, and / or DC-DC converter 300) according to one or more embodiments of the present disclosure. For example, as shown in the embodiment of Figure 9, the ZCD900 comprises a ZCD integrator 920, a ZCD offset calibrator 930, and an idle release generator 940. The idle release generator 940 is configured to receive / monitor the switch voltage VSW and the output voltage Vout of the power stage 910, in addition to various switch control signals (e.g., signal hs_on on the high side, signal ls_on on the low side) generated by the controllers 120 / 320 as described herein, and to generate a zero-cross detection signal 928 based at least in part on such monitored voltage and switch control signals. In various embodiments, the ZCD900 (e.g., ZCD integrator 920, ZCD offset calibrator 930, and / or idle release generator 940) may be integrated with a DC-DC converter controller, such as the ZCD322 integrated with the DC-DC converter controller 320 of the DC-DC converter 300.

[0047] As shown in Figure 9, the power stage 910 may be implemented as a step-down DC-DC converter comprising a high-side FET / switch 911 and a low-side FET / switch 912. The high-side FET / switch 911 is coupled, for example, between the input voltage Vin of DC-DC converter 100, DC-DC converter 200, and / or DC-DC converter 300 and the switch voltage VSW at the input of the output inductor 916 of the power stage 910. The low-side FET / switch 912 is coupled between the switch voltage VSW at the input of the output inductor 916 and the power ground (pvss) for DC-DC converter 100, DC-DC converter 200, and / or DC-DC converter 300. Generally, the switch voltage VSW is measured, for example, between the input side of the output inductor 916 and the power ground (pvss) for DC-DC converter 300, and / or at the input side of the output inductor 916 (compared to, for example, an absolute ground reference for DC-DC converter 300). The switches 911 / 912 may be controlled by a high-side control signal hs_on and a low-side control signal ls_on (e.g., gate control signals generated and / or supplied by the controller 320 of the DC-DC converter 300). The high-side FET 911 and the low-side FET 912 may each have effective body diode structures 913 and 914, respectively, which provide a conductive path for current flowing through the output inductor 916 when the switches 911 / 912 are closed (such as when the high-side control signal hs_on and the low-side control signal ls_on are logic low). In various embodiments, as shown, each control signal may be buffered in a buffer 915 before reaching the switches 911 / 912. The output side of the output inductor 916 may be coupled to ground via a shunt capacitor 917 (e.g., to help isolate relatively high-frequency noise to ground and isolate the switch noise generated by the DC-DC converter 300 from the electronic device or multiple electronic devices powered by the DC-DC converter 300).

[0048] The ZCD integrator 920 may be configured to receive the switch power VSW and the output voltage Vout of the power stage 910, and to generate a zero-crossing detection signal 928 based at least partially on the received switch voltage VSW and output voltage Vout. In various embodiments, the zero-crossing detection signal 928 may be configured to indicate that the output current at the output inductor 916 of the power stage 910 (e.g., of the DC-DC converter 300) is approximately zero and / or crosses zero. As shown in Figure 9, the ZCD integrator 920 may include a differential voltage integrator 929 configured to receive the switch voltage VSW and output voltage Vout (e.g., through an input resistor 923 (Rint)) and to generate an integrator output that is subsequently fed to an output comparator 927. The output comparator 927 of the ZCD integrator 920 may be configured to receive the integrator output generated by the differential voltage integrator 929, as shown, and to generate a zero-crossing signal based at least partially on the integrator output and output voltage Vout.

[0049] In some embodiments, the ZCD integrator 920 may include an integrator reset switch 925 configured to reset the differential voltage integrator 929 during the idle mode of the DC-DC converter 300 (e.g., both the high-side FET 911 and the low-side FET 912 are off; hs_on=low, ls_on=low). For example, as shown in Figure 9, when hs_on=low, ls_on=low, the hsls_on_b generated by the NOR gate 924 becomes high. This closes the integrator reset switch 925 and completely discharges the integrator capacitor 922 (Cint). The ZCD integrator 920 has an output voltage Vout and a ZCD calibration offset 935 (e.g., a digital offset such as a programmable voltage zcd_offset <a:0>The system may further include a ZCD offset calibration assigner 926 configured to receive a ZCD calibration offset (or analog offset) and a corresponding calibrated output voltage, and to supply a corresponding calibrated output voltage to the output comparator 927. Here, the calibrated offset voltage is configured to compensate for operational non-idealities in the operation of the DC-DC converter 300, as described herein. In some embodiments, the ZCD offset calibration assigner 926 may be implemented as a programmable voltage generator (e.g., a digital-to-analog converter) configured to receive a ZCD calibration offset 935, combine it with the output voltage Vout, and supply the combined result to the output comparator 927 as a calibrated output voltage. The output comparator 927 is configured to generate a zero-crossing detection signal 928 (e.g., zero-crossing detection in Figure 3) when the integrator output crosses the calibrated output voltage.

[0050] The ZCD offset calibrator 930 may be configured to receive a switch voltage VSW and generate a ZCD calibration offset 935 based at least partially on the received switch voltage VSW. Here, the ZCD integrator 920 is configured to generate a zero-cross detection signal 928 based at least partially on the ZCD calibration offset 935, so that a zero-cross detection signal 928 is applied to the output voltage Vout using a ZCD offset calibration assigner 926, as shown in the figure. In some embodiments, the ZCD offset calibrator 930 includes a current direction detector 933 configured to receive a switch voltage VSW and compare the switch voltage VSW to a reference voltage Vref for the DC-DC converter 300 (e.g., Vref is substantially the same as the desired output voltage of the power stage 910 and / or the DC-DC converter 300) at approximately the time when the low-side switch 912 of the power stage 910 transitions to the off state (e.g., when ls_on transitions from high to low), and generate a current direction signal curr_dir based at least partially on the result of the comparison between the switch voltage VSW and the reference voltage Vref. The ZCD offset calibrator 930 may further comprise a logic device / calibration controller 934 configured to receive a current direction signal cur_dir and generate a ZCD calibration offset 935 based at least partially on the current direction signal cur_dir. Here, the ZCD calibration offset 935 is set to adjust the timing of the zero-cross detection signal 928 (for example, by adjusting the comparison voltage supplied to the output comparator 927) in order to compensate for operational non-idealities in the operation of the DC-DC converter 300.

[0051] In some embodiments, the ZCD offset calibrator 930 may include a low-side FET offset detector 931 configured to monitor the low-side control signal ls_on and / or the gate voltage of the low-side FET 912 and generate a low-side offset detection signal ls_off_detect. The low-side offset detection signal ls_off_detect may be used to trigger the operation of the current direction detector 933 and the calibration controller 934 (for example, delayed 932 to ensure that the operation of the current direction detector 933 is completed before the calibration controller 934 operates to generate the ZCD calibration offset 935 based at least partially on the current direction signal cur_dir). In various embodiments, the calibration controller 934 may be configured to increment the ZCD calibration offset 935 by the least significant bit (1 LSB) for each switching cycle of the DC-DC converter 300 when the switch voltage VSW is lower than the reference voltage Vref (e.g., the current direction is negative), or to decrement the ZCD calibration offset 935 by 1 least significant bit (1 LSB) when the switch voltage VSW is higher than or equal to the reference voltage Vref (e.g., the current direction is non-negative). In alternative or additional embodiments, the calibration controller 934 may be configured to implement a state machine such as the state machine 1000 in Figure 10. This state machine is configured to average the current direction signal cur_dir and / or lock the ZCD calibration offset 935 for a predetermined number of switching cycles of the DC-DC converter 300 to provide a more stable ZCD calibration offset 935.

[0052] In yet another embodiment, the calibration controller 934 may be configured to iteratively increment and / or decrement the ZCD calibration offset 935 based at least partially on the current direction (e.g., as indicated by the current direction signal cur_dir) of the output current in the output inductor, which is determined approximately when the low-side switch 912 of the power stage 910 transitions to the off state, to determine the transition of the current direction from negative to positive after incrementing the ZCD calibration offset 935, and to lock the ZCD calibration offset 935 for a predetermined number of switching cycles of the power stage 910 of the DC-DC converter 300.

[0053] The idle release generator 940 may be configured to receive a switch voltage VSW and an input voltage VIN of the power stage 910 of the DC-DC converter 300, and to generate an idle release signal 947 (release_idle_time) based at least in part on the received switch voltage VSW and input voltage VIN. Here, the idle release signal 947 may be configured to indicate that the DC-DC converter 300 is ready to exit idle mode. In particular, the DC-DC converter 300 may be ready to exit idle mode when, while operating as the DC-DC converter of the DCM, any output voltage remaining in the output inductor 916 after the DC-DC converter has entered idle mode has discharged through one or both of the body diodes 913 / 914. In some embodiments, the idle release generator 940 may include a first low-side comparator 941 configured to receive a switch voltage VSW and generate a first comparator output indicating that the switch voltage VSW is higher than a pre-selected idle mode threshold voltage Vx, which is between ground (pvss) and the output voltage Vout. In such embodiments, the idle release generator 940 may further include a second high-side comparator 944, which is coupled to the comparator output and configured to generate a second comparator output indicating that the switch voltage VSW is lower than the input voltage VIN, after the low-side comparator 941 has generated a first comparator output. The idle release generator 940 may also include a logic device (e.g., an AND gate 945) configured to generate an idle release signal 947 based at least in part on the first and second comparator outputs, as shown in the figure.

[0054] The idle release generator 940 may additionally include various circuit elements to facilitate the operation of the idle release generator 940, such as a delay 942 (e.g., approximately 10-50 nanoseconds, typically ~20 nanoseconds) to allow the switch voltage VSW to settle before the high-side comparator 944 is triggered, and to eliminate any transients through the idle release generator 940; a latch 943 configured to latch the first comparator output (e.g., when both switch control signals transition to high or low); and a latch 946 configured to latch the second comparator output (e.g., when ls_on transitions to high or low). Generally, the idle release signal 947 may be supplied to the controller 320 to maintain idle time (e.g., to potentially extend Idle_delay) until the output current discharges through the body diodes 913 / 914.

[0055] For example, in a DC-DC converter of a DCM implemented with a power stage 910, during the idle mode, both the high-side FET 911 and the low-side FET 912 are turned off (hs_on=low, ls_on=low), causing hsls_on_b to become high, which in turn shorts the integrator capacitor 922 (Cint) using the integrator reset switch 925. Therefore, the ZCD integrator 920 behaves as a unity-gain buffer, and if the inductor current is completely discharged to zero amperes in the idle mode steady state, the switch voltage VSW~=Vout during the idle mode, thus setting the initial integrator output voltage to the Vout voltage. This is ensured by the idle release generator 940, as described herein. When the high-side FET 911 is switched on, the integrator reset switch 925 is off, and the switch voltage VSW rises to VIN (more precisely, VIN - (hsFET - Ron * (inductor current of output inductor 916)), but for simplicity, hsFET - Ron = 0 is assumed). A current of (VIN - Vout) / Rint discharges the integrator output from the initial voltage = Vout with a slope of (VIN - Vout) / (Rint * Cint). This slope replicates the slope of the inductor current while hs_on ((VIN - Vout) / (inductance value)). This is the same slope as when a constant inductor value is replaced by a constant Rint * Cint. When the low-side FET 912 is switched on, the switch voltage VSW drops to 0V (more precisely, pvss - (lsFET - Ron * inductor current), but for simplicity, lsFET - Ron = 0 is assumed). Therefore, the integrator output is charged with a current of Vout / Rint, with a slope of (Vout / (Rint*Cint)). This slope also replicates the slope of the inductor current during ls_on = (Vout / inductance value). In DCM, the inductor current must start at 0A and end at 0A, as determined by ZCD900.Then, during ls_on, as the integrator output voltage returns to the initial integrator output = Vout, the ZCD900 (more specifically the ZCD integrator 920) indicates the zero-crossing point by generating a zero-crossing detection signal 928. The output comparator 927 is configured to detect and indicate when the integrator output crosses Vout for the zero-crossing point.

[0056] In some embodiments, the ZCD integrator 920 is configured to operate only in DCM mode, and the output current in the output inductor 916 must start at 0A and end at 0A to complete the entire switching cycle. In such embodiments, an idle release generator 940 is used to ensure the operation of such DCM. For example, when the low-side FET 912 is turned off, the positive residual output current (e.g., flowing from VSW to Vout) is discharged by the body diode 914 of the low-side FET 912, and the switch voltage VSW becomes equal to the (-) body diode voltage. If the output voltage is negative (e.g., flowing from Vout to VSW), this is discharged by the body diode 913 of the high-side FET 911, and the switch voltage VSW becomes equal to the body diode voltage +VIN. Thus, when the switch voltage VSW is between the idle-mode threshold voltage Vx and VIN, the residual output current is completely discharged by the body diode 913 or body diode 914, and the power stage 910 is ready for the next DCM switching cycle. In various embodiments, the DC-DC converter controller 120 / 320 may be configured to maintain or keep the idle mode (e.g., both the high-side FET 911 and the low-side FET 912 are off) until the release_idle_time signal reports that the switch voltage VSW is between Vx and VIN, in order to ensure the operation of the DCM. Generally, the idle mode threshold voltage Vx is between ground and Vout, but in some embodiments, the idle mode threshold voltage Vx may be higher than Vth (e.g., the body diode threshold voltage, approximately 700mV).

[0057] The output current in the output inductor 916 (e.g., ZCD error current) when the low-side FET 912 is turned off may vary due to non-idealities (op-amp offset, comparator offset and delay, pre-driver delay, transfer delay, thermal drift, and / or other non-idealities). Therefore, the ZCD offset calibrator 930 is configured to generate a ZCD calibration offset 935. The ZCD calibration offset 935 is then applied to the Vout side of the output comparator 927 to minimize the ZCD error current as much as possible for optimal DC-DC converter efficiency. When the low-side FET 912 is turned off, the ls_off_detect signal transitions to high, and the current direction detector 933 is triggered to sample the VSW and determine if the sampled VSW is higher than Vref. When VSW is lower than Vref (cur_dir = high), the ZCD error current is positive (e.g., flows from VSW to Vout) because it is discharged through / by the body diode 914 of the low-side FET 912. When VSW is higher than Vref (cur_dir = low), the ZCD error current is negative (e.g., flows from Vout to VSW) because it is discharged through / by the body diode 913 of the high-side FET 911. The positive / negative ZCD error current direction signal (cur_dir) is sampled by the calibration controller 934, triggered by the zcd_cal_clk signal. The zcd_cal_clk signal can be a delayed logic signal based on the ls_off_detect signal, as illustrated. The calibration controller 934 uses the sampled output current direction (e.g., the cur_dir signal) to perform a ZCD calibration offset 935 (zcd_offset <a:0>The calibration controller 934 may be configured to update the ZCD calibration offset 935. The ZCD calibration offset 935 is provided to the ZCD integrator 920 to gradually / actually reduce the ZCD error current in the next switching cycle. The calibration controller 934 may be configured to generate and / or update the ZCD calibration offset 935 by performing various different processes. One such process for updating the ZCD calibration offset 935 is illustrated as pseudocode in the block depicting the calibration controller 934 in Figure 9. Another process for updating the ZCD calibration offset 935, implemented as a state machine performed by the calibration controller 934, is shown in Figure 10.

[0058] Figure 10 is a flowchart showing a process 1000 that realizes a state machine (e.g., blocks 1010, 1020, 1030, 1040) for operating the ZCD 900 for DC-DC converters 100, 200, and / or 300, according to one or more embodiments of the present disclosure. A defect in the cur_dir signal is the ZCD calibration offset 935 (zcd_offset <a:0>To prevent uncertain updates of the ZCD calibration offset 935 (zcd_offset), the calibration controller 934 samples the number of cycles of "avg_cycle" in the cur_dir cycles and performs the ZCD calibration offset 935 (zcd_offset <a:0>) may be configured to average the samples before updating. If, over the cycles of "avg_cycle", more samples with cur_dir=high are detected than samples with cur_dir=low, the calibration controller 934 will set zcd_offset <a:0>The zcd_offset may be decremented to lower the level of the ZCD error current in the next switching cycle. If, over the "avg_cycle" cycles, more cur_dir=low samples are detected than cur_dir=high samples, the calibration controller 934 decrements the zcd_offset. <a:0>The value may be incremented to increase the level of ZCD error current in the next switching cycle. Ultimately, the ZCD calibration offset 935 may oscillate between a positive minimum ZCD error current zcd_offset value and a negative minimum ZCD error current zcd_offset value. Transient fluctuations to negative ZCD error current reduce the efficiency of the DC-DC converter compared to transient fluctuations to positive ZCD error current. Therefore, the calibration controller 934 determines the zcd_offset value for ZCD error currents crossing from negative to positive, and the zcd_offset value for positive minimum ZCD error current <a:0>The value may be configured to lock for a number of cycles of "lock_cycle". After the "lock_cycle" cycles, the calibration controller 934 resamples cur_dir to compensate for any temperature changes, voltage changes, and / or other non-idealities that may occur, and sets zcd_offset <a:0>It may be configured to update.

[0059] More specifically, process 1000 represents a state machine used to generate the ZCD calibration offset 935. In block 1010, the calibration controller 934 initializes and / or resets various state variables to their initial values, which are set to ensure proper operation of the state machine 1000. These state variables include disabling the execution of the state machine 1000 (dcdc_enable=0) (for example, to block the state variable from being modified by the state machine 1000), setting the ZCD calibration offset 935 to an initial, pre-stored, or desired value (for example, zcd_offset=ctrl_zcd_force_offset), and setting various other state variables to their initial values ​​in preparation for enabling the state machine 1000. After receiving or detecting an enable signal (dcdc_enable=1), the state machine 1000 advances its state to the initial state smState="00" shown as block 1020.

[0060] In block 1020, the calibration controller 934 may be configured to receive the current direction (e.g., cur_dir) of the output current in the output inductor 916 and to increment or decrement a current direction counter (offset_updown) based on the current direction. When the current direction is positive, the calibration controller 934 loops through loop 1022 within block 1020 to (effectively) average the current direction counter (e.g., over avg_cycle cycles). After averaging is complete, the calibration controller 934 increments or decrements the ZCD calibration offset 935 and either advances the state to block 1030 (e.g., if the ZCD calibration offset 935 is incremented) or starts a new averaging loop through block 1020 (e.g., if the ZCD calibration offset 935 is decremented). If the received current direction (cur_dir) is negative, the calibration controller 934 advances the state to block 1030 along state transition 1024, as shown in the figure.

[0061] In block 1030, the calibration controller 934, similar to block 1020, may be configured to receive the current direction of the output current in the output inductor 916 and increment or decrement a current direction counter (offset_updown) based on that current direction. If the current direction is positive, the calibration controller 934 advances the state to block 1040 along state transition 1034. If the current direction is negative, the calibration controller 934 loops through block 1030 via loop 1032 (for example, over avg_cycle cycles) to complete the averaging of the current direction counter. After averaging is complete, the calibration controller 934 either increments the ZCD configuration offset 935 and starts a new averaging loop through block 1030 (for example, if the current direction counter indicates that the current direction is still negative), or advances the state to block 1040. When the direction of the received current (cur_dir) is positive, the calibration controller 934 advances to block 1040, as shown in the diagram.

[0062] In block 1040, the calibration controller 934 may be configured to lock the ZCD calibration offset 935 over (lock_cycle) switching cycles via loop 1042 to stabilize the ZCD calibration offset 935 when the current direction is detected as the smallest positive value (e.g., compared to the available resolution of the ZCD calibration offset 935) after the ZCD calibration offset 935 has become negative in the previous increment (e.g., via the processing of blocks 1020 and 1030). The calibration controller 934 may be configured to loop through block 1040 over (lock_cycle) switching cycles, as shown, and then advance through the state along state transition 1044 to return to block 1020. In addition, the calibration controller 934 may be configured to advance the state and reset block 1010 via state transitions 1028, 1038, and / or 1048 when it detects the execution of disabling the state machine 1000 (dcdc_enable=0). In various embodiments, the state machine 1000 may be implemented without the reset block 1010, and various state variables may be initialized and / or reset within block 1020 and / or block 1040, as illustrated.

[0063] Figure 11 is a flowchart illustrating the process for operating a ZCD for a DC-DC converter according to one or more embodiments of the present disclosure. In particular, process 1100 illustrates the process of the ZCD 900 in the DC-DC converter 100, DC-DC converter 200, and / or DC-DC converter 300. In various embodiments, the operation of Figure 11 may be implemented as software instructions executed by one or more logic devices or controllers relating to the corresponding methods, electronic devices, sensors, and / or structures shown in Figures 1-10. More generally, the operation of Figure 11 may be implemented using any combination of software instructions, mechanical elements, and / or electronic hardware (e.g., inductors, capacitors, amplifiers, actuators, or other analog and / or digital components). Any step, substep, subprocess, or block of process 1100 may be executed in a different order or sequence than in the embodiments shown in Figure 11. Furthermore, process 1100 may be implemented as a control loop configured to repeat one or more steps, substeps, subprocesses, or blocks of process 1100, and return to the previous step, substep, subprocess, or block of process 1100, in order to repeat process 1100 one or more additional times. For example, in other embodiments, one or more blocks may be omitted or added to process 1100. In addition, block inputs, block outputs, various sensor signals, sensor information, calibration parameters, and / or other operating parameters may be stored in one or more memories before proceeding to the corresponding parts of the following processes. Process 1100 is described with reference to the systems and methods described in Figure 1-10, but process 1100 may be performed by other systems, which differ from those systems, and may include different choices of electronic devices, sensors, assemblies, mechanisms, systems, and / or system attributes.

[0064] In block 1102, the ZCD900 receives the switch voltage VSW and the output voltage Vout. For example, any one or a combination of the ZCD integrator 920, the ZCD offset calibrator 930, and / or the idle release generator 940 may be configured to receive the switch voltage VSW and / or the output voltage Vout from the power stage 910 of the DC-DC converter 100, DC-DC converter 200, and / or DC-DC converter 300. In some embodiments, before the operation of the ZCD900, the DC-DC converter controller 120 or the DC-DC converter controller 320 may be configured to selectively enable the ZCD900 based at least in part on the output voltage Vout and / or the output load status of the DC-DC converter 100, DC-DC converter 200, and / or DC-DC converter 300, as shown in the vout_islow_latch and / or processing via the Heavy_load_status and OR gate (or1) in Figure 3. Such activation may be configured to power / dispower various elements of the ZCD900, such as the 929 of the ZCD integrator 920, the calibration controller 934 of the ZCD offset calibrator 930, and / or other logic and / or comparator elements of the ZCD900, as shown in Figure 9.

[0065] In block 1104, the ZCD 900 generates the ZCD calibration offset 935. For example, the ZCD offset calibrator 930 may be configured to generate the ZCD calibration offset 935 based at least in part on the switch voltage VSW received in block 1102. In various embodiments, the ZCD offset calibrator 930 may be configured to implement, for example, the state machine 1000 in Figure 10, or to execute pseudocode presented in the block showing the calibration controller 934 in Figure 9, and / or to execute any alternative process described herein. In certain embodiments, such as when the ZCD offset calibrator 930 is initially initialized and before the DC-DC converters 100, 200, and / or 300 complete their first switching cycle (e.g., idle -> hs_on=high, ls_on=low -> hs_on=low, ls_on=high -> idle), the ZCD offset calibrator 930 may be configured to generate a ZCD calibration offset 935 based on an initial value and / or a predetermined value (e.g., ctrl_zcd_force_offset, or a value stored and / or acquired by the calibration controller 934 during a previous operation of the ZCD offset calibrator 930), as described herein.

[0066] In block 1106, the ZCD 900 generates a zero-crossing detection signal 928. For example, the ZCD integrator 920 may be configured to generate the zero-crossing detection signal 928 based at least partially on the switch voltage VSW, the output voltage Vout received in block 1102, and the ZCD calibration offset 935 generated in block 1104. In some embodiments, the DC-DC converter controller 120 or the DC-DC converter controller 320 may be configured to receive the zero-crossing detection signal 928 (e.g., “Zero-crossing detection” in Figure 3) and generate switch control signals (e.g., ls_on, hs_on) based at least partially on the peak current target value (e.g., provided to the output load sensor 330) and / or the zero-crossing detection signal 928 generated by the ZCD integrator 920 of the ZCD 900 to adjust the switching frequency of the power stage 910.

[0067] In certain embodiments, such as when the ZCD offset calibrator 930 is initially initialized and before the DC-DC converters 100, 200, and / or 300 complete their first switching cycle, the ZCD integrator 920 may be configured, at least partially, to generate a zero-cross detection signal 928 based on the switch voltage VSW and / or the output voltage Vout received in block 1102, and / or the ZCD calibration offset 935 initialized in block 1104 and / or set to a predetermined value. In subsequent switching cycles, as described herein, the ZCD integrator 920 may be configured, at least partially, to generate a zero-cross detection signal 928 based on the switch voltage VSW and / or the output voltage Vout received in the current switching cycle [n] of the DC-DC converter, and / or the ZCD error current sampled by the calibration controller 934, and the ZCD calibration offset 935 generated by the ZCD offset calibrator 930 at the end of the previous switching cycle [n-1].

[0068] For example, the flowchart in Figure 12 illustrates the process for operating a ZCD for a DC-DC converter according to one or more embodiments of the present disclosure. In particular, process 1200 illustrates the operation of the ZCD 900 in DC-DC converters 100, 200, and / or 300, with added sequence and timing details to those shown in Figure 11. In various embodiments, the operation in Figure 12 may be implemented as software instructions executed by one or more logic devices or controllers related to the corresponding methods, electronic devices, sensors, and / or structures shown in Figures 1-11. More generally, the operation in Figure 12 may be implemented using any combination of software instructions, mechanical elements, and / or electronic hardware (e.g., inductors, capacitors, amplifiers, actuators, or other analog and / or digital components). Any step, substep, subprocess, or block of process 1200 may be executed in a different order or sequence than in the embodiments shown in Figure 12. Furthermore, process 1200 may be implemented as a control loop configured to repeat one or more steps, substeps, subprocesses, or blocks of process 1200, and return to the previous step, substep, subprocess, or block of process 1200, in order to repeat process 1200 one or more additional times. For example, in other embodiments, one or more blocks may be omitted or added to process 1200. In addition, block inputs, block outputs, various sensor signals, sensor information, calibration parameters, and / or other operating parameters may be stored in one or more memories before proceeding to the corresponding parts of the following processes. Process 1200 is described with reference to the systems and methods described in Figure 1-11, but process 1200 may be performed by other systems, which differ from those systems, and may include different choices of electronic devices, sensors, assemblies, mechanisms, systems, and / or system attributes.

[0069] In block 1202, the DC-DC converter controller 120 or the DC-DC converter controller 320 initiates the first switching cycle. For example, the DC-DC converter controller 320 may be configured to detect that Vout is less than Vref, thereby switching comp1 high and setting the high-side control signal hs_on=high to turn on the high-side FET / switch 911. Prior to the start of block 1202, the ZCD 900 may be configured to initialize the ZCD calibration offset 935 to an initial value and / or a predetermined value (e.g., ctrl_zcd_forse_offset, or a value stored and / or acquired by the calibration controller 934 during a previous operation of the ZCD offset calibrator 930), as described herein.

[0070] In block 1204, the ZCD900 receives a first switch voltage VSW and a first output voltage Vout. For example, one or any combination of the ZCD integrator 920, the ZCD offset calibrator 930, and / or the idle release generator 940 may be configured to receive the first switch voltage VSW and / or the first output voltage Vout from the power stage 910 of the DC-DC converter 100, DC-DC converter 200, and / or the DC-DC converter 300. In some embodiments, the DC-DC converter controller 120 or the DC-DC converter controller 320 may be configured to selectively enable the ZCD900 prior to the operation of the ZCD900, based at least in part on the output voltage Vout and / or the output load status of the DC-DC converter 100, DC-DC converter 200, or DC-DC converter 300, such as the vout_islow_latch and / or processing via the Heavy_load_status and OR gate (or1) in Figure 3. Such activation may be configured to power / dispower various elements of the ZCD900, such as the 929 of the ZCD integrator 920, the calibration controller 934 of the ZCD offset calibrator 930, and / or other logic and / or comparator elements of the ZCD900, as shown in Figure 9.

[0071] When the high-side control signal hs_on is set to high, the ZCD integrator 920 exits the reset state. In the reset state, as described herein, the integrator output is initially set to Vout and the integrator capacitor 922 begins to discharge. Next, when the current flowing through the output inductor 916 reaches the peak current, the peak current detector 324 goes high, and the DC-DC converter controller 320 sets the high-side control signal hs_on = low and the low-side control signal ls_on = high, turning off the high-side FET / switch 911 and turning on the low-side FET / switch 912. The ZCD integrator 920 then begins charging the integrator capacitor 922 as described herein, and the integrator output approaches Vout.

[0072] In block 1206, the ZCD 900 generates a first zero-crossing detection signal 928. For example, the ZCD integrator 920 may be configured to generate the first zero-crossing detection signal 928 at least in part based on a first switch voltage VSW and / or a first output voltage Vout initially received in block 1204, and / or based on a ZCD calibration offset 935 initialized in block 1202. In particular, the ZCD output comparator 927 may turn the zero-crossing detection signal 928 high when the integrator output = Vout + ZCD calibration offset 935 (combined by the ZCD offset calibration assigner 926). In some embodiments, the DC-DC converter controller 120 or DC-DC converter controller 320 may be configured to receive a first zero-crossing detection signal 928 (e.g., “Zero-crossing detection” in Figure 3) and generate switch control signals (e.g., ls_on, hs_on) to adjust the switching frequency of the power stage 910 based at least in part on a peak current target value (e.g., provided by the output load sensor 330) and / or the first zero-crossing detection signal 928 generated by the ZCD integrator 920 of the ZCD 900. When the first zero-crossing detection signal 928 is generated, the DC-DC converter controller 320 sets the low-side control signal ls_on = low to turn off the low-side FET / switch 912 and put the DC-DC converter 300 into idle mode.

[0073] In block 1208, the ZCD 900 receives the idle mode switch voltage VSW. For example, the ZCD offset calibrator 930 may be configured to receive the switch voltage VSW approximately when the low-side FET / switch 912 turns off (e.g., before VSW reaches a steady state during idle mode). In certain embodiments, the ZCD offset calibrator 930 may be configured to determine, approximately when idle mode begins (e.g., during idle mode resulting from the low-side FET / switch 912 being turned off), that the low-side control signal ls_on = low, and / or that the low-side FET / switch 912 is off via the low-side FET offset detector 931, and to sample the switch voltage VSW using the current direction detector 933. Thus, the ZCD offset calibrator 930 receives the initial idle mode switch voltage VSW and determines whether the corresponding ZCD error current is positive or negative (which is represented by the current direction signal cur_dir generated by the current direction detector 933).

[0074] In block 1210, ZCD 900 generates an updated ZCD calibration offset 935. For example, ZCD offset calibrator 930 may be configured to generate and update the updated ZCD calibration offset 935 based at least in part on the idle initial switch voltage VSW received in block 1208. In various embodiments, ZCD offset calibrator 930 may be configured to, for example, realize state machine 1000 in Figure 10, or to realize pseudocode shown in the block showing calibration controller 934 in Figure 9, and / or to perform any alternative processing described herein. In some embodiments, calibration controller 934 may be configured to receive a current direction signal cur_dir and generate a ZCD calibration offset 935 based at least in part on the current direction signal cur_dir. Here, as described herein, the ZCD calibration offset 935 is iteratively driven to a value set to reduce the magnitude of the ZCD error current, and ultimately to a value that realizes the minimum positive ZCD error current for optimal DC-DC converter efficiency. In various embodiments, as also described herein, the DC-DC converter controller 320 may be configured to maintain idle mode until an idle release generator 940 generates an idle release signal 947 (e.g., release_idle_time=high) and provides it to the input of the AND gate (DCM_and in Figure 3) of the DC-DC converter controller 320, in order to ensure the operation of the DCM of the DC-DC converter 300.

[0075] In block 1212, the DC-DC converter controller 120 or the DC-DC converter controller 320 starts the second switching cycle. For example, the DC-DC converter controller 320 may be configured to detect that Vout is less than Vref, thereby switching comp1 high, setting the high-side control signal hs_on=high, and turning the high-side FET / switch 911 on again.

[0076] In block 1214, the ZCD900 receives a second switch voltage VSW and a second output voltage Vout. For example, one or any combination of the ZCD integrator 920, the ZCD offset calibrator 930, and / or the idle release generator 940 may be configured to receive the second switch voltage VSW and / or the second output voltage Vout from the power stage 910 of the DC-DC converter 100, DC-DC converter 200, and / or the DC-DC converter 300. In some embodiments, the DC-DC converter controller 120 or the DC-DC converter controller 320 may be configured to selectively enable the ZCD900 prior to the operation of the ZCD900, based at least in part on the output voltage Vout and / or the output load status of the DC-DC converter 100, DC-DC converter 200, or DC-DC converter 300, such as the vout_islow_latch and / or processing via the Heavy_load_status and OR gate (or1) in Figure 3. When the high-side control signal hs_on is set to high, the ZCD integrator 920 exits the reset state. In the reset state, as described herein, the integrator output is initially set to Vout and the integrator capacitor 922 begins to discharge. Next, when the current flowing through the output inductor 916 reaches the peak current, the peak current detector 324 goes high, and the DC-DC converter controller 320 sets the high-side control signal hs_on = low and the low-side control signal ls_on = high, turning off the high-side FET / switch 911 and turning on the low-side FET / switch 912. Then, the ZCD integrator 920 begins charging the integrator capacitor 922, as described herein, in exactly the same way as the process described for block 1204, and the integrator output approaches Vout.

[0077] In block 1216, the ZCD 900 generates a second zero-crossing detection signal 928. For example, the ZCD integrator 920 may be configured to generate the second zero-crossing detection signal 928 at least in part based on the second switch voltage VSW and / or the second output voltage Vout initially received in block 1214, and / or based on the updated ZCD calibration offset 935 generated in block 1210. In particular, the ZCD output comparator 927 may turn the zero-crossing detection signal 928 high when the integrator output = Vout + ZCD calibration offset 935 (combined by the ZCD offset calibration assigner 926). In some embodiments, the DC-DC converter controller 120 or DC-DC converter controller 320 may be configured to receive a second zero-crossing detection signal 928 (e.g., “Zero-crossing detection” in Figure 3) and generate switch control signals (e.g., ls_on, hs_on) to adjust the switching frequency of the power stage 910 based at least in part on a peak current target value (e.g., provided by the output load sensor 330) and / or the second zero-crossing detection signal 928 generated by the ZCD integrator 920 of the ZCD 900. When the second zero-crossing detection signal 928 is generated, the DC-DC converter controller 320 sets the low-side control signal ls_on = low to turn off the low-side FET / switch 912 and put the DC-DC converter 300 into idle mode. Process 1200 loops back to block 1210, as described herein, to update the ZCD calibration offset 935 for the next switching cycle.

[0078] Accordingly, embodiments can improve the overall efficiency of a DC-DC converter by using a reliable, accurate, and relatively low-power ZCD configured to assist in controlling various modes, cycles, and switching timings in the DC-DC converter, as described herein. Furthermore, embodiments can do so while adaptively providing higher load currents, reducing the risk of output voltage ripple at relatively low load currents, and reducing the risk of switching interference in downstream devices powered by the DC-DC converter.

[0079] The electronic or electrical devices and / or other related devices or components according to embodiments of the present invention described herein may be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and / or hardware. For example, the various components of these devices may be formed separately on one integrated circuit (IC) chip or on multiple IC chips. Furthermore, the various components of these devices may be formed on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or a single substrate. Furthermore, the various components of these devices may be processes or threads that execute instructions of a computer program to perform the various functions described herein, running on one or more processors in one or more computing devices, and interacting with other system components. The computer program instructions are stored in memory which may be implemented in the computing device using standard memory devices such as random-access memory (RAM). Instructions for computer programs may also be stored on other non-temporary computer-readable media, such as CD-ROMs or flash drives. Furthermore, those skilled in the art should recognize, without departing from the spirit and scope of the exemplary embodiments of the present invention, that the functions of various computing devices may be combined or integrated into a single computing device, or that the functions of a particular computing device may be distributed across one or more other computing devices.

[0080] The foregoing disclosure is not intended to limit the disclosure to the exact form or specific field of use disclosed. Therefore, it is reasonable to assume that various alternative embodiments and / or modifications to the disclosure are possible, whether expressly described or implied herein. Since embodiments of the disclosure have been described in this manner, those skilled in the art will recognize that the form and details may be modified without departing from the scope of the disclosure. Accordingly, the disclosure is limited only by the claims.

Claims

1. This is a zero-crossing detector (ZCD) for a DC-DC converter. Equipped with a ZCD integrator, The ZCD integrator, A differential voltage integrator configured to receive a switch voltage and the output voltage of the power stage of the DC-DC converter, and to generate an integrator output based on the switch voltage and the output voltage of the power stage, An output comparator configured to generate a zero-crossing detection signal based at least partially on the integrator output and the output voltage of the power stage, Equipped with, The zero-crossing detection signal indicates whether the output current in the output inductor of the power stage of the DC-DC converter is approximately zero. ZCD.

2. The ZCD integrator, An integrator reset switch configured to reset the differential voltage integrator while the DC-DC converter is idle, A ZCD offset calibration assigner configured to receive the output voltage and the ZCD calibration offset and to supply the corresponding calibrated output voltage to the output comparator, Furthermore, The calibrated output voltage is set to compensate for operational non-idealities in the operation of the DC-DC converter. ZCD according to claim 1.

3. A ZCD offset calibrator configured to receive the switch voltage and generate a ZCD calibration offset based at least partially on the received switch voltage, Furthermore, The ZCD integrator is configured to generate the zero-crossing detection signal based at least partially on the ZCD calibration offset. ZCD according to claim 1.

4. The ZCD offset calibrator, A current direction detector is configured to receive the aforementioned switch voltage, and approximately at the time the low-side switch of the power stage transitions to the off state, compare the switch voltage with a reference voltage for the DC-DC converter, and generate a current direction signal based at least partially on the comparison result between the switch voltage and the reference voltage. A logic device configured to receive the current direction signal and generate the ZCD calibration offset based at least partially on the current direction signal, Equipped with, The ZCD calibration offset is set to adjust the timing of the zero-cross detection signal in order to compensate for operational non-idealities in the operation of the DC-DC converter. ZCD according to claim 3.

5. To generate the aforementioned ZCD calibration offset, The ZCD calibration offset is iteratively incremented and / or decremented based at least partially on the current direction of the output current in the output inductor, which is determined approximately at the time the low-side switch of the power stage transitions to the off state. After incrementing the ZCD calibration offset, the transition from negative to positive in the current direction is determined. The ZCD calibration offset is locked for a predetermined number of cycles in the power stage. including, ZCD according to claim 4.

6. It is an idle release generator, The switch voltage and the input voltage of the DC-DC converter to the power stage are received, An idle release signal is generated based at least partially on the received switch voltage and the input voltage. It further includes an idle release generator configured as follows: The idle release signal is configured to indicate that the DC-DC converter is ready to exit its idle mode. ZCD according to claim 1.

7. The aforementioned idle release generator, A first comparator configured to receive the switch voltage and generate a first comparator output indicating that the switch voltage is higher than an idle mode threshold voltage that is pre-selected to be between ground and the output voltage, A second comparator is coupled to the first comparator output and configured to generate a second comparator output indicating that the switch voltage is lower than the input voltage after the first comparator has generated the first comparator output, A logic device configured to generate the idle release signal based at least partially on the first comparator output and the second comparator output, Equipped with, ZCD according to claim 6.

8. The DC-DC converter comprises a discontinuous conduction mode (DCM) DC-DC converter, The power stage of the DC-DC converter of the DCM is A high-side field-effect transistor (FET) is coupled between the input voltage of the DC-DC converter and the input side of the output inductor. A low-side FET coupled between the input side of the output inductor and the ground for the DC-DC converter, Equipped with, The switch voltage is measured on the input side of the output inductor. The high-side FET and the low-side FET are controlled by the high-side control signal and the low-side control signal supplied by the DC-DC converter's controller, respectively. ZCD according to claim 1.

9. A DC-DC converter comprising the ZCD of claim 1, wherein the DC-DC converter is A DC-DC converter controller configured to receive the output voltage of the power stage of the DC-DC converter, generate a switch control signal, and control the switching frequency of the power stage, An output load sensor configured to determine the output load state of the DC-DC converter, determine a peak current target value for the DC-DC converter based at least partially on the determined output load state, and supply the output load state and / or the peak current target value to the DC-DC converter controller, Equipped with, The DC-DC converter controller, Based at least partially on the output voltage and / or the output load state of the DC-DC converter supplied by the output load sensor, the ZCD is selectively enabled. The switch control signal is generated to adjust the switching frequency of the power stage, at least partially based on the peak current target value supplied by the output load sensor and / or the zero-crossing detection signal generated by the ZCD integrator. DC-DC converter.

10. This is a method for operating a zero-crossing detector (ZCD) for a DC-DC converter. The ZCD integrator receives the switch voltage and the output voltage of the power stage of the DC-DC converter. The ZCD integrator generates an integrator output based on the switch voltage and the output voltage of the power stage, The output comparator generates a zero-crossing detection signal based at least partially on the integrator output and the output voltage of the power stage, Includes, The zero-crossing detection signal indicates whether the output current in the output inductor of the power stage of the DC-DC converter is approximately zero. method.

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