Power semiconductor devices with a shallow conduction region

Abstract

The power transistor device includes a drift layer having a first conductivity type and a mesa on the drift layer. The mesa includes a channel region on the drift layer, a source layer on the channel region, and a gate region in the mesa adjacent to the channel region. The channel region and the source layer have the first conductivity type, and the gate region has a second conductivity type opposite the first conductivity type. The channel region includes a deep conduction region and a shallow conduction region between the deep conduction region and the gate region. The deep conduction region has a first doping concentration, and the shallow conduction region has a second doping concentration greater than the first doping concentration.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices. In particular, the disclosure relates to junction field effect transistor (JFET) power semiconductor devices.

Background Art

[0002] A conventional n-channel vertical JFET structure 10 is shown in FIG. 1A. The vertical JFET structure 10 includes an n+ drain layer 26, on which an n-drift layer 15 is formed. The n-type channel region 24 is on the drift layer 15, and the n+ source layer 16 is on the channel region 14. The n++ source contact layer 38 is on the n+ source layer. The drain resistance contact 28 is on the drain layer 26, and the source resistance contact 40 is on the source contact layer 38. The channel region 24, the source layer 16, and the source contact layer 38 are provided as part of a mesa 12 above the drift layer 15. The p+ gate region 18 is provided as part of the mesa 12 adjacent to the channel region 24. The p++ shield region 32 is provided adjacent to the gate region 18, and the gate resistance contact 36 is formed on the shield region 32. The passivation layer 42 is on the gate resistance contact 36 and the shield region 32.

[0003] FIG. 1A shows half of the vertical JFET unit cell structure 10. The overall structure is symmetric about the axis 30 and includes two gate regions 18 as part of the mesa 12 on the opposite side of the channel region 24. That is, only a half cross-section of the JFET device is shown in FIG. 1A. The shown portion can be mirrored along the vertical axis 30 to obtain the full pitch of the device's unit cell. The complete JFET device includes many such unit cells. For clarity, FIG. 1C shows the entire JFET unit cell 10 including half-cells 10A, 10B sharing the same mesa 12.

[0004] Referring again to Figure 1A, the channel of the vertical JFET structure 10 is formed within the mesa 12. The channel width in the n-type region is in the horizontal direction, away from the pn junction between the gate region 18 and the channel region 24. The channel width is in the plane of Figure 1A, and the channel length is in the vertical direction. Such a vertical JFET structure with a short channel length may be called a static-induction transistor (SIT). In an SIT, the channel length is selected based on a trade-off between low on-resistance in the on-state (short channel) and resistance to drain-induced barrier lowering (DIBL) in the off-state. Conventional p-channel JFETs may have a similar structure, but their conductivity type is the opposite of that shown in Figure 1A.

[0005] During operation, conduction between the source layer 16 and the drain layer 26 is adjusted by applying a reverse bias to the gate region 18 relative to the source layer 16. To switch off an n-channel device such as the JFET structure 10, a negative gate-source voltage, or simply the gate voltage (V) is applied. GSA reverse bias (Gate-to-Source Voltage) is applied to the gate region 18. When no voltage is applied to the gate region 18, the charge carrier can flow freely from the source layer 16 through the channel region 24 and the drift layer 15 to the drain layer 26. Conversely, referring to Figure 1B, when a reverse bias is applied to the gate region 18, a depletion region 33 is formed at the interface between the gate region 18 and the surrounding n-type region, i.e., the channel region 24, and the source layer 16. The depletion region 33 may extend into the drift layer 15. As its name suggests, the depletion region 33 is depleted of charge carriers. When the magnitude of the reverse bias applied to the gate region 18 is sufficiently large, the depletion region extends to cover the entire width of the channel region 24, pinching off the channel region 24 and hindering or blocking the flow of charge carriers between the source layer 16 and the drift layer 15. As shown in Figure 1A, in the mesa JFET structure 10, the "width" of the channel region 24 is in the same direction as the width of the mesa 12. Therefore, the lateral width of the mesa 12 defines the width of the channel region 24.

[0006] The threshold voltage of a JFET device refers to the gate voltage at which the device begins to conduct. The threshold voltage of the device is highly sensitive to the width of the channel region 24, because pinch-off of the channel region 24 occurs when the gate voltage is large enough for the depletion region 33 to extend across the entire channel layer 24. As described above, in the conventional vertical JFET structure 10 shown in Figures 1A and 1B, the width of the channel region 24 is determined by the width of the mesa 12. The width of the mesa 12 is determined by the manufacturing process used to form the mesa 12, namely the masking and etching process. Such manufacturing processes introduce various tolerances. Manufacturing variations within these tolerances can lead to significant variations in threshold voltage from device to device, even within the same manufacturing run. [Overview of the project]

[0007] Power transistor devices according to some embodiments include a drift layer having a first conductivity type and a mesa on the drift layer. The mesa includes a channel region on the drift layer, a source layer on the channel region, and a gate region in the mesa adjacent to the channel region. The channel region and the source layer have the first conductivity type, and the gate region has a second conductivity type opposite to the first conductivity type. The channel region includes a deep conduction region and a shallow conduction region between the deep conduction region and the gate region. The deep conduction region has a first doping concentration, and the shallow conduction region has a second doping concentration greater than the first doping concentration.

[0008] In some embodiments, the shallow conduction region extends vertically between the drift layer and the source layer, and the deep conduction region extends vertically between the drift layer and the source layer.

[0009] The channel region may include silicon carbide, the shallow conduction region may have a doping concentration greater than about 1E17 cm -3 and the deep conduction region may have a doping concentration lower than about 1E17 cm -3 The channel region may include silicon carbide, the shallow conduction region may have a doping concentration of about 3E17 cm

[0010] ~ about 5E18 cm -3 and the deep conduction region may have a doping concentration of about 1E16 cm -3 ~ about 5E16 cm -3 In some embodiments, the shallow conduction region may have a doping concentration of about 1E18 cm -3 and the deep conduction region may have a doping concentration of about 1.5E16 cm -3 -3 The shallow conduction region may have a doping concentration at least about 10 times greater than the doping concentration of the deep conduction region. [[ID=二十九]]

[0011] ​The shallow conduction region may have a gradient doping profile, which is gradient in the transverse direction perpendicular to the direction of carrier flow through the channel region when the vertical junction field-effect device is ON.

[0012] The shallow conduction region may have a width of approximately 0.1 to 0.3 microns in the transverse direction perpendicular to the direction of carrier flow through the channel region when the vertical junction field-effect device is in the ON state.

[0013] The shallow conduction region may have a width in the transverse direction perpendicular to the direction of carrier flow through the channel region when the vertical junction field-effect device is ON, and may be about one-third of half the width of the mesa. The shallow conduction region may include a region injected into the mesa.

[0014] The power transistor device may further include a breakdown adjustment region between the shallow conduction region and the gate region. The breakdown adjustment region may have a first conductivity type and a third doping concentration lower than the second doping concentration of the shallow conduction region.

[0015] The vertical junction field-effect device exhibits a threshold voltage change with respect to the mesa width of less than 20 V / micron, less than 10 V / micron in some embodiments, and less than 5 V / micron in some embodiments.

[0016] The power transistor device may be a junction field-effect transistor (JFET). The drift layer, channel region, and gate region may contain silicon carbide.

[0017] The width of the lateral shallow channel region, which can be perpendicular to the direction of current when the device may be in an ON state, may be independent of the lateral mesa width.

[0018] The width of the deep channel region in the lateral direction perpendicular to the direction of current when the device is ON may be directly proportional to the width of the mesa in the lateral direction.

[0019] The gate region may include a first gate region, the shallow conduction region may include a first shallow conduction region, the power transistor device may further include a second gate region in a mesa opposite to the first gate region, and the channel region is located between the first and second gate regions. The device may include a second shallow conduction region in the channel region between the deep conduction region and the second gate region. The second shallow conduction region may have a third doping concentration greater than the first doping concentration of the deep conduction region.

[0020] The first gate region may be surrounded by a breakdown adjustment region in the mesa, so that the breakdown region is located above, below, and to the side of the gate region adjacent to the channel region in the mesa. The breakdown adjustment region may have a first conductivity type and a third doping concentration which may be lower than the second doping concentration of the shallow conduction region.

[0021] The deep conduction region and channel region may be located opposite the shallow conduction region in a transverse direction perpendicular to the direction of current in the power transistor device.

[0022] A power transistor device according to several embodiments includes a drift layer having a first conductivity type, a mesa on the drift layer comprising a channel region on the drift layer and a source layer on the channel region, and a gate region in the mesa on the channel region side. The channel region and the source layer have a first conductivity type. The gate region has a second conductivity type opposite to the first conductivity type. The vertical junction field-effect device exhibits a threshold voltage change corresponding to a mesa width of less than 20 V / micron.

[0023] A method for forming a power transistor device includes providing a drift layer having a first conductivity type, forming a source layer having the first conductivity type on the drift layer, and forming a mesa by selectively etching a portion of the source layer and the drift layer to form a trench that extends into the drift layer and defines a mesa adjacent to the trench, wherein the mesa has a mesa sidewall adjacent to the trench, forming a shallow conduction region in the mesa extending between the drift layer and the source layer, and forming a gate region having a second conductivity type in the mesa, wherein the gate region may be adjacent to a channel region in the mesa. The channel region includes a deep conduction region adjacent to the shallow conduction region, the shallow conduction region may be between the deep conduction region and the gate region, and the shallow conduction region may have a higher doping concentration than the deep conduction region.

[0024] Forming a shallow conduction region may involve performing angled ion implantation of a first conductivity type dopant ion into the mesa sidewall with a first implantation energy to form a shallow conduction region in the mesa, such that a portion of the drift layer in the mesa forms a deep conduction region adjacent to the shallow conduction region.

[0025] Forming a gate region may involve implanting a second conductivity type dopant ion into the mesa sidewall at a second injection energy which may be lower than the first injection energy used to form a gate region in the mesa, the shallow conduction region may be located between the gate region and the deep conduction region, and the second conductivity type is the opposite of the first conductivity type.

[0026] Forming a mesa may include forming an etch mask on the source layer and etching the source and drift layers in the region below the etch mask to form a mesa. Forming a shallow conductive region may include implanting a first conductive type of dopant ion into the mesa sidewall using the etch mask as an implantation mask.

[0027] The etch mask may include an SiO2 etch mask on the source layer and a silicon nitride mask on the SiO2 mask, and the method may further include forming a second etch mask on a mesa and trenches, patterning the second etch mask to expose the floors of the mesa and trenches adjacent to the mesa and to expose one or more surface regions in the edge regions of the device, and implanting dopant ions of a second conductivity type into the mesa sidewalls and junction termination regions at a second injection energy lower than the first injection energy to form a gate region in the mesa and an edge termination region in the edge region. The shallow conduction region is located between the gate region and the deep conduction region, and the second conductivity type is the opposite of the first conductivity type.

[0028] The second etch mask may contain SiO2, and patterning the second etch mask may involve selectively etching the second etch mask using a silicon nitride mask as an etch stop layer.

[0029] A power transistor device according to some embodiments includes a drift layer having a first conductivity type; a mesa on the drift layer, comprising a channel region on the drift layer and a source layer on the channel region, wherein the channel region and source layer have the first conductivity type; and a gate region in the mesa adjacent to the channel region, wherein the gate region has a second conductivity type opposite to the first conductivity type. A breakdown adjustment region may be provided in the mesa between the channel region and the gate region, and the breakdown adjustment region has the first conductivity type. The channel region has a first doping concentration, and the breakdown adjustment region may have a second doping concentration which may be lower than the first doping concentration.

[0030] The channel region may include a deep conduction region and a shallow conduction region between the deep conduction region and the breakdown adjustment region. The shallow conduction region may have a first doping concentration, and the deep conduction region may have a third doping concentration which may be lower than the first doping concentration. The breakdown adjustment region surrounds the gate region in the mesa.

[0031] The accompanying drawings, included to provide a further understanding of the disclosure and incorporated into and constituting part of this Specified Version, illustrate aspects of the disclosure and, together with a detailed description, are useful in illustrating the principles of the disclosure. There is no intention to show structural details of the disclosure in more detail than may be necessary for a basic understanding of the disclosure and the various ways in which it may be implemented. [Brief explanation of the drawing]

[0032] [Figure 1A] This figure shows a conventional JFET device structure. [Figure 1B] This figure shows a conventional JFET device structure. [Figure 1C] This figure shows a conventional JFET device structure. [Figure 2A] This figure shows the structure of a JFET device according to several embodiments. [Figure 2B] This figure shows the structure of a JFET device according to several embodiments. [Figure 2C] This figure shows channel doping profiles for JFET device structures according to several examples. [Figure 3] This figure shows channel doping profiles and associated electric field strength and electron energy for JFET device structures according to several embodiments. [Figure 4A] This figure shows the process for manufacturing a JFET device structure according to several examples. [Figure 4B] This figure shows the process for manufacturing a JFET device structure according to several examples. [Figure 4C]This figure shows the process for manufacturing a JFET device structure according to several examples. [Figure 4D] This figure shows the process for manufacturing a JFET device structure according to several examples. [Figure 4E] This figure shows the process for manufacturing a JFET device structure according to several examples. [Figure 4F] This figure shows the process for manufacturing a JFET device structure according to several examples. [Figure 4G] This figure shows the process for manufacturing a JFET device structure according to several examples. [Figure 4H] This figure shows the process for manufacturing a JFET device structure according to several examples. [Figure 4I] This figure shows the process for manufacturing a JFET device structure according to several examples. [Figure 5A] This figure shows the process for manufacturing a JFET device structure according to further embodiments. [Figure 5B] This figure shows a JFET device structure according to a further embodiment. [Figure 5C] Figure 5B shows several possible channel doping profiles for the JFET device structure. [Figure 5D] Figure 5B shows several possible channel doping profiles for the JFET device structure. [Figure 5E] Figure 5B shows several possible channel doping profiles for the JFET device structure. [Figure 6] This figure shows an exemplary circuit including a JFET device according to several embodiments. [Figure 7] This flowchart shows the process for manufacturing a JFET device according to several examples. [Modes for carrying out the invention]

[0033] Embodiments of the concept of the invention are described more fully with reference to non-limiting embodiments and examples described and / or illustrated in the accompanying drawings and detailed in the following description. It should be noted that features shown in the drawings are not necessarily drawn to scale, and that features of some embodiments may be used in conjunction with other embodiments recognized by those skilled in the art, even if not explicitly stated herein. Descriptions of well-known components and manufacturing techniques may be omitted to avoid unnecessarily obscuring the embodiments of the disclosure. The examples used herein are intended solely to facilitate understanding of the methods by which the disclosure may be carried out and to enable those skilled in the art to further implement the embodiments of the disclosure. Therefore, the examples and embodiments herein should not be construed as limiting the scope of the disclosure as defined solely by the accompanying claims and applicable law. Furthermore, it should be noted that the same reference numerals represent similar parts across multiple drawings.

[0034] While terms such as "first," "second," etc., may be used herein to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of disclosure, the first element may be called the second element, and similarly, the second element may be called the first element. Where used herein, the term "and / or" includes any and all combinations of one or more of the relevant enumerated items.

[0035] When an element such as a layer, region, or substrate is described as "on top of" or "extending onto" another element, it will be understood that the element may be directly on or extend directly onto the other element, or there may be an intervening element. In contrast, when an element is described as "directly on" or "extending directly onto" another element, there is no intervening element. Similarly, when an element such as a layer, region, or substrate is described as "spanning" or "extending" another element, it will be understood that the element may be directly on or extend directly onto the other element, or there may be an intervening element. In contrast, when an element is described as "spanning" or "extending directly onto" another element, there is no intervening element. When it is stated that one element is “connected” or “joined” to another element, it will be understood that the element may be directly connected or joined to the other element, or that there may be an intermediary element. In contrast, when it is stated that one element is “directly connected” or “directly joined” to another element, there is no intermediary element.

[0036] Relative terms such as “down,” “up,” “above,” “downward,” “horizontal,” or “vertical” may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the drawings. These terms and those described above are intended to include different orientations of the device in addition to the orientation shown in the drawings.

[0037] The terms used herein are intended to describe only specific aspects and are not intended to be limitations on disclosure. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless the context clearly indicates otherwise. Furthermore, where used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” indicate the presence of the described features, integers, steps, processes, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, processes, elements, components, and / or groups thereof.

[0038] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as those generally understood by those skilled in the art to which this disclosure pertains. It will be further understood that terms used herein should be interpreted in a manner consistent with their meanings relating to this specification and related technologies.

[0039] JFET devices are sometimes called electrostatic induction transistors, but the term JFET will be used in the following description. However, it will be recognized that the embodiments described herein may be applicable to any device that uses a depletion region to adjust the conductivity of the channel in a mesa.

[0040] Power electronic devices manufactured using silicon carbide (SiC) can achieve high blocking voltages. For power devices with blocking voltages in the 600V to 1000V range, SiC JFETs have a chip area 2 to 3 times smaller than SiC MOSFETs. SiC JFETs can also be manufactured using simpler manufacturing processes than MOSFETs, which can lead to lower manufacturing costs. Furthermore, SiC JFET devices do not have an SiO2-SiC interface. This can improve device reliability because the oxide layer can break down under high-voltage operation. JFET devices have the disadvantage of being normally-on devices. However, their advantages can outweigh these disadvantages in power applications such as high-reliability Si-SiC heterogeneous integrated circuits.

[0041] In vertical SiC JFETs optimized for low resistance, it is desirable that the device has a predictable threshold voltage for circuit performance. However, as described above, the threshold voltage of a vertical JFET is highly sensitive to the mesa width of the device. Several embodiments described herein are based on the understanding that the sensitivity of the threshold voltage to mesa width in a vertical JFET device is related to the conductivity of the channel portion whose width changes with the mesa width. Several embodiments described herein can reduce the sensitivity of the threshold voltage to changes in mesa width by providing a stepped or gradient doping profile in the channel region.

[0042] For example, in some embodiments, the channel is divided into a shallow channel region with high conductivity near the gate region and a deeper channel region with lower conductivity. In some embodiments, the shallow channel may be self-aligned with respect to the mesa edge, so that only the width of the deeper channel region with lower conductivity is sensitive to the mesa width. This can reduce the sensitivity of the device's threshold voltage to the mesa width. The total central conductivity of the channel itself can be kept constant or nearly constant because the channel conductivity is dominated by the shallow channel region with high conductivity. In some embodiments, appropriate selection of doping concentrations in the shallow and deep channel regions can provide a reduction of an order of magnitude or more in the sensitivity of the threshold voltage to the mesa width.

[0043] Therefore, some embodiments can avoid the conventional trade-off between the conductivity of the JFET channel and the sensitivity of the threshold voltage to changes in mesa width. That is, in conventional structures, the higher the conductivity of the channel, the more sensitive it becomes to changes in mesa width. Therefore, some embodiments can narrow the mesa width and dope the channel region more densely to increase conductivity while reducing the sensitivity of the threshold voltage to the mesa width.

[0044] As shown in Figures 1A and 1B, conventional JFET channels have substantially constant doping to ensure uniform conductivity regardless of channel width. According to some embodiments described herein, JFET channel doping is gradient such that deeper portions of the JFET channel, closer to the center of the mesa, are doped to a lower concentration, while shallower portions of the JFET channel (closer to the gate junction) are doped to a higher concentration. In addition, in some embodiments, the doping of the shallower portions of the JFET channel may be self-aligned with respect to the mesa edge. These embodiments are combined to desensitize the threshold voltage of the JFET device to changes in mesa width without incurring trade-offs in channel conductivity.

[0045] Figure 2A shows an n-channel vertical JFET structure 100 according to several embodiments. The vertical JFET structure 100 includes an n+ drain layer 26 on which an n-drift layer 15 is formed. The n-type channel region 114 is on the drift layer 15, and the n+ source layer 16 is on the channel region 114. The n++ source contact layer 38 is on the n+ source layer. The drain resistance contact 28 is on the drain layer 26, and the source resistance contact 40 is on the source contact layer 38. The channel region 114, source layer 16, and source contact layer 38 are provided to the mesa 12 on the drift layer 15. The p+ gate region 18 is provided adjacent to the channel region 24 as part of the mesa 12. The p++ shield region 32 is provided adjacent to the gate region 18, and the gate resistance contact 36 is on the shield region 32. The passivation layer 42 covers the gate resistance contact 36 and the shield region 32. The selective sidewall protection layer 61 is located on the exposed sidewall of the mesa 12. The sidewall protection layer 61 may have a thickness of, for example, 20-30 nm, 23-27 nm in some embodiments, and 25 nm in some embodiments.

[0046] In some embodiments, the doping concentration in the channel region 114 may be gradient along the width of the mesa 12 (corresponding to the width of the channel region 114), so that the channel region 114 has a lower doping concentration near the center of the mesa 12 and a higher doping concentration near the gate region 18.

[0047] For example, in the embodiment shown in Figure 2A, the channel region 114 has a two-stage gradient profile, thereby dividing the channel region 114 into a deep conduction region 122 and a shallow conduction region 124 between the deep conduction region 122 and the gate region 18. The channel region 114 includes both the shallow conduction region 124 and the deep conduction region 122 adjacent to the gate region 18, and both the shallow conduction region 124 and the deep conduction region 122 may extend perpendicularly between the drift layer 15 and the source layer 16. The shallow conduction region 124 extends perpendicularly between the drift layer 15 and the source layer 16 (for example, in the y-direction or in the direction of carrier flow, as shown in Figure 2A), and the deep conduction region 122 extends perpendicularly between the drift layer 15 and the source layer 16. Therefore, the deep conduction region 122 and the channel region 18 are located opposite the shallow conduction region 124 in the transverse direction (e.g., the x-direction) perpendicular to the direction of current in the device 100.

[0048] The deep conduction region 122 is located near the center of the mesa 12 and has a lower doping concentration than the shallow conduction region 124. For example, the shallow conduction region 124 may have a doping concentration at least about 10 times higher than the doping concentration of the deep conduction region 122. In some cases, the shallow conduction region 124 may have a doping concentration at least about 20 times higher, and in some cases at least about 100 times higher, than the doping concentration of the deep conduction region 122.

[0049] In some embodiments, the shallow conduction region 124 is approximately 1E17cm. -3 For example, approximately 1E17cm -3 ~1E19cm -3 It has a doping concentration of . In some examples, the shallow conduction region 124 is approximately 3E17cm. -3 ~5E 18cm -3 It has a doping concentration of . In some examples, the shallow conduction region 124 is approximately 1E18cm -3 It has a doping concentration of [value].

[0050] In some embodiments, the deep conduction region 122 is approximately 5E15cm -3 ~1E17cm -3 It has a doping concentration of . In some examples, the deep conduction region 122 is approximately 5E16cm -3 For example, approximately 5E15cm -3 ~5E 16cm -3 It has a doping concentration of . In some examples, the deep conduction region 122 is approximately 1.5E16cm -3 It has a doping concentration of [value].

[0051] In some embodiments, the shallow conduction region has a doping concentration that is at least about 10 times greater, and in some cases at least about 100 times greater, than the doping concentration in the deep conduction region.

[0052] In some embodiments, the deep conduction region 122 may have the same doping concentration as the drift layer 15, because the shallow conduction region 124 can be formed by ion implantation into a portion of the epitaxial layer that forms the drift layer 15.

[0053] In some embodiments, the shallow conduction region 124 may have a width of approximately 0.1 to 0.3 microns in the transverse direction (x direction shown in Figure 2A) perpendicular to the direction of carrier flow through the channel region 114 when the vertical JFET 100 is ON (y direction shown in Figure 2A). In some embodiments, the shallow conduction region has a width in the transverse direction perpendicular to the direction of carrier flow through the channel region when the vertical junction field-effect device is ON, which is approximately one-third of half the width of the mesa.

[0054] Although it is presented as an n-channel device, it can be seen that the JFET device structure 100 can be formed as a p-channel device by switching the n-type layer to a p-type layer, and vice versa.

[0055] In some embodiments, the vertical JFET 100 may exhibit a threshold voltage change depending on the mesa width of less than 20V / micron. In some embodiments, the vertical JFET 100 may exhibit a threshold voltage change depending on the mesa width of less than 10V / micron, and in some embodiments, less than 5V / micron.

[0056] A two-stage gradient doping profile is shown in Figure 2A, but channel regions 114 may have other doping profiles. For example, various possible doping profiles are shown in Figure 2C, which includes graphs of various channel doping profiles across the entire mesa width according to several embodiments. In Figure 2C, the total channel width is 2W. Thus, each channel region 114 in half of the mesa has a width of W.

[0057] Figure 2C(a) shows a two-stage doping profile in which each half of the mesa includes a shallow conduction region 124 that is more highly doped and a deep conduction region 122 that is less highly doped. Figure 2C(b) shows a three-stage doping profile in the channel region 114. Figure 2C(c) shows a doping profile in which the interface between the shallow conduction region 124 and the deep conduction region 122 is gradient from higher doping concentrations to lower doping concentrations. The doping profiles shown in Figure 2C are illustrative, and many other doping profiles are possible within the scope of the concept of the invention.

[0058] As shown in Figure 2A, the shallow conduction region 124 extends perpendicularly between the drift layer 15 and the source layer 16, and the deep conduction region 122 extends perpendicularly between the drift layer 15 and the source layer 16.

[0059] In some embodiments, the shallow conduction region has a gradient doping profile, which is gradient in the transverse direction perpendicular to the direction of carrier flow through the channel region when the vertical junction field-effect device is ON.

[0060] Figure 3(a) is a graph of doping concentration with respect to the horizontal position of the channel for a conventional JFET structure 10, Figure 3(b) is a graph of electric field strength, and Figure 3(c) is a graph of electron energy. Similarly, Figure 3(d) is a graph of doping concentration with respect to the horizontal position of the channel for a JFET structure 100 according to several embodiments, Figure 3(e) is a graph of electric field strength, and Figure 3(f) is a graph of electron energy.

[0061] As shown in Figure 3(a), in the conventional structure, the channel region is at a constant doping concentration N ch It has. In contrast, as shown in Figure 3(d), in the structures according to some embodiments, the channel region is a p-type gate region (with a doping concentration N of the opposite type to that in the channel region). g Low doping concentration N in deep conduction regions away from (having) d and high doping concentration N in the shallow conduction region near the p-type gate region. h It has a stepped doping profile that includes [a specific component]. The shallow conduction region may have a width δ of about 0.2 microns in some embodiments.

[0062] As shown in Figures 3(b) and 3(e), the peak electric field (E m The gate-source breakdown voltage is higher in the JFET structure 100 because the junction is formed by a more doped n-channel region than in the conventional structure 10, while the built-in voltage is the same in both cases. The gate-source breakdown voltage is determined by the junction between the gate region 18 and the source layer 16, as long as the n+ doping of Nh, i.e., the shallower conduction region 124, is lower than the n+ doping of the source layer 16. Therefore, the JFET structure 100 should not have a lower gate-source breakdown voltage than the conventional JFET structure 10.

[0063] Solving Poisson's equation for electrostatics yields the threshold voltage (V) for both the conventional constant-doped structure and the two-stage wide-gradient structure shown in Figure 2A. T ) and V for mesa width T Sensitivity can be obtained. In the examples described herein, N d (Doping in the middle of the channel) is N ch Because it is lower than (channel doping in conventional structures), V T The sensitivity can be reduced.

[0064] N ch For a certain doped channel having V T It is calculated as follows:

number

[0065] V according to mesa width W T The change is calculated as follows:

number

[0066] N h and N d For a two-stage doped channel having V T It is calculated as follows:

number

[0067] V according to mesa width W T The change is calculated as follows:

number

[0068] V in conventional structures T is N ch Although sensitive to V in some embodiments T This is a significantly lower value Nd They are sensitive to this.

[0069] Simulations were performed to compare the performance of conventional structures with structures from several embodiments. The simulations used a gate voltage (V) that generates a potential barrier in the channel against electron flow from a 1.5V source. barrier ) as V T The simulation used a mesa width of 1.2 microns, a mesa width variation of ±0.2 microns, a p+ injection depth of 0.2 microns into the mesa on each side, an n+ injection depth of 0.2 microns into the channel for the new structure, and 8E16cm. -3 N ch , 1E16cm -3 N d , and 3E17cm -3 N h The above analysis model was used. Under these conditions, the V shown in Table 1 T Results and V T This brings about a change in the conventional structure. As shown in Table 1, the V T The voltage changed from -5.0V to -16.6V when the mesa width was varied by ±0.2 μm. In contrast, for structures formed as described herein, V T When the mesa width was changed by ±0.2 microns, the voltage only changed from -9.3V to -10.4V.

[0070] Therefore, V with respect to mesa width T The change is shown to be reduced to less than one-tenth when a structure as described herein is used. [Table 1]

[0071] In some embodiments, vertical junction field-effect devices may exhibit a change in threshold voltage depending on the mesa width of less than 20 V / micron. In some embodiments, vertical junction field-effect devices exhibit a change in threshold voltage depending on the mesa width of less than 10 V / micron, and in some embodiments, less than 5 V / micron. In some embodiments, vertical junction field-effect devices exhibit a change in threshold voltage depending on the mesa width of 5 V / micron to 20 V / micron.

[0072] Process flows for forming JFET structures according to several embodiments are shown in Figures 4A to 4I. In Figures 4A to 4I, the relative sizes of various layers and regions are exaggerated for clarity and are not drawn to scale. The process flows shown in Figures 4A to 4I are for manufacturing n-channel JFET devices. In the case of p-channel JFET devices, the conductivity type of the device layers / regions is reversed from n-type to p-type, or vice versa.

[0073] Referring to Figure 4A, an n+SiC substrate 26 having a thickness of approximately 350 microns is provided. The substrate 26 may have a 2H, 4H, 6H, or 3C polytype and may be on-axial or off-axial orientation. The n+ substrate 26 forms the drain layer 26 of the completed JFET device.

[0074] An n-epitaxial layer 15 with a thickness of approximately 8 microns is formed on the substrate 26. Such an epitaxial layer thickness is suitable for devices with blocking voltages of 600-800V. For higher voltage ratings, the n-epitaxial layer 15 becomes thicker. The n-epitaxial layer 15 is approximately 5E15cm². -3 ~1E17cm -3 In some embodiments, approximately 1E16cm -3 ~5E 16cm -3 It may have a doping concentration of . In a particular example, the n-epitaxial layer 15 is approximately 1.5E16cm -3The doping concentration may be such that the n-epitaxial layer 15 forming the drift layer of the device is selected to provide the desired on-state resistance and / or off-state voltage blocking capability for the device.

[0075] Referring to Figure 4B, the n+ source layer 16 and the n++ source-contact layer are formed by implanting n-type ions such as silicon into the epitaxial layer 15 in terms of capacity and implantation energy. The n+ source layer 16 has a thickness of approximately 0.5 microns and approximately 1E18 cm². -3 The doping concentration may be such that the n+ source contact layer 38 has a thickness of about 0.5 microns and may be regressively doped to enable the formation of a source resistance contact thereto.

[0076] Referring to Figure 4C, a mask 46 is formed on the upper surface of the structure. The mask 46 is formed to have a thickness of approximately 1 micron and is created by depositing a layer 46A of SiO2 by plasma-enhanced chemical vapor deposition (PECVD), followed by a layer 46B of silicon nitride. The structure is then etched to form trenches 48 that define the mesa 12. As shown in Figures 2A and 2B, the right half of the structure to the right of axis 30 is shown for ease of understanding. The trenches 48 have a width of approximately 1.2 microns, and the mesa has a total width of approximately 1.2 microns. The trenches 48 may be etched to a depth of approximately 2 microns into the n-epitaxial layer 15.

[0077] After the trench formation process, the mask 46 may have a residual thickness of approximately 0.7 microns. Referring to Figure 4D, with the mask 46 in place, gradient ion implantation 50 is performed to implant an n+ shallow channel region 124 into the sidewall of the mesa 12. The n+ shallow channel region 124 is approximately 1E17 cm -3 ~1E19cm -3 In some cases, approximately 3E17cm -3 ~5E 18cm -3A sufficient dose is injected to obtain the doping concentration. The n+ shallow channel region 124 may be injected with a maximum injection energy of approximately 700-800 keV to obtain the desired injection depth. The injection may be performed at high temperatures multiple times, at an inclination angle of 35-40 degrees from the vertical to ensure that the bottom of the trench sidewall is not screened. The injection may be performed at four twist angles spaced 90 degrees apart from each other.

[0078] Referring to Figure 4E, a second SiO2 layer 48 is deposited on the structure and patterned to form an opening 49 in the edge termination region 57 of the structure. The pattern etch conditions are selected to use the underlying silicon nitride layer 46B as an etch stop so that the mask 46 is not removed when the second SiO2 layer 48 is patterned. Gradient ion implantation 52 is performed to implant a p+ gate region 18 into the sidewall of the mesa 12 and simultaneously implant an edge termination region 55 into the edge termination region 57. The p+ gate 18 is approximately 1E18cm -3 ~1E19cm -3 A sufficient dose is injected to obtain the doping concentration. The p+ gate region 18 may be injected with a maximum injection energy of approximately 300–400 keV to obtain the desired injection depth. The injection may be performed at high temperatures multiple times, at an inclination angle of 35–40 degrees from the vertical to ensure that the bottom of the trench sidewall is not screened. The injection may be performed at four twist angles spaced 90 degrees apart from each other.

[0079] Referring to Figure 4F, ion implantation step 54 is performed to implant a p++ shield region 32 onto the surface of the trench 48. In ion implantation step 54, p-type ions may be implanted onto the trench surface at a maximum implantation energy of approximately 350 keV. After ion implantation step 54, a junction termination extension (JTE) region (not shown) may be formed on the edge termination region 57 by ion implantation. All implanted dopants may then be activated by annealing at 1550°C for 30 minutes using a carbon cap.

[0080] Referring to Figure 4G, SiO 2 The layer is deposited on the structure using PECVD to form a sidewall protective layer 61 on the exposed sidewall of the mesa 12 adjacent to the trench 48, and may be isotropically etched, for example, using inductively coupled plasma (ICP) etch. The sidewall protective layer 61 may have a thickness of, for example, 20-30 nm, 23-27 nm in some embodiments, and 25 nm in some embodiments.

[0081] Referring to Figure 4H, a layer of Ni 63 having a thickness of 100 nm is deposited on the structure to form a silicide at the bottom of the trench 48 and may be annealed at 750°C. The unreacted Ni may then be etched, and the structure is annealed at 1000°C or less to form a gate resistance contact 36 on the p+ shield region 32 in the gate pad region and a source resistance contact 40 on the source contact layer 38. Additional conventional fabrication processes such as trench filling 72, planarization, metallization 74, backside metallization 76 and laser annealing may then be performed to complete the device fabrication as shown in Figure 4I.

[0082] Figure 5A shows the process for manufacturing a JFET device structure according to a further embodiment. As shown in Figure 5A, in some embodiments, the injection energy and capacitance of the n-type injection 50 (Figure 4D) for forming the shallow conduction region 124 and the p-type injection 52 (Figure 4E) for forming the gate region 18 may be selected such that, after injection and annealing, an n-breakdown adjustment region 202 remains around the gate region 18, including between the shallow conduction region 124 and the gate region 18, and between the source region 16 and the gate region 18. The shallow conduction region 124 is located between the deep conduction region 122 and the breakdown adjustment region 202. The breakdown adjustment region 202 is approximately 5E15cm -3 ~About 1E17cm -3 In some examples, approximately 1E16cm -3~About 5E16cm -3 In certain examples, approximately 1.5E16cm -3 The breakdown adjustment region 202 may have a net n-type doping concentration. The breakdown adjustment region 202 may have a doping concentration similar to that of the deep conduction region 122, but it does not need to be equal to that of the deep conduction region 122.

[0083] The breakdown adjustment region 202 is provided so that the gate-source PN junction is formed by the p+ gate region 18 and the n- region. This can increase the gate-source breakdown voltage. The n-breakdown adjustment region 202 surrounding the p+ gate region 18 is also self-aligned with respect to the edge of the mesa 12 and, in some embodiments, can be formed using gradient injection by adding lower energy n-injections.

[0084] Figure 5B shows a JFET device structure 200 including an n-breakdown adjustment region 202 between the shallow conduction region 124 and the gate region 18, and Figures 5C, 5D, and 5E show several possible channel doping profiles for the JFET device structure of Figure 5B. As seen in Figure 5C, the breakdown adjustment region 202 has a doping concentration of n in the shallow conduction region 124. h Lower doping concentration N b It holds.

[0085] Doping concentration N b This refers to the doping concentration N in the deep conduction region 122. d It may be larger, smaller, or equal to. For example, in Figure 5C, the breakdown adjustment region 202 has a doping concentration N of the deep conduction region 122. d doping concentration N is approximately equivalent to b It has. Figure 5D shows the doping concentration N in the breakdown adjustment region 202. b However, the doping concentration N in the deep conduction region 122 d Figure 5E shows a higher doping profile, and the doping concentration N in breakdown adjustment region 202 is shown. bHowever, the doping concentration N in the deep conduction region 122 d It shows a lower doping profile.

[0086] Although it is shown as an n-channel device, it will be recognized that the JFET device structure 200 can be formed as a p-channel device by switching the n-type layer to a p-type layer, and vice versa.

[0087] In some embodiments, SiC JFET devices may offer improved yield due to reduced sensitivity of the threshold voltage to mesa width. Alternatively or additionally, such devices can maintain yield while enabling tighter designs (e.g., narrower mesas) that improve performance.

[0088] Figure 6 shows an exemplary circuit including a JFET device according to several embodiments. As shown in Figure 6, the vertical SiC JFET 100 according to some embodiments can be connected to a silicon MOSFET 150 in a modified cascode topology, where the SiC JFET is driven directly and it is desirable that the change in the SiC JFET threshold voltage is very low.

[0089] The JFET devices described herein may, advantageously, be used for other SiC JFET applications, such as in solid-state circuit breakers, as normally-on SiC JFET switches.

[0090] More broadly, some of the embodiments described herein can be used in any vertical channel junction field-effect device having a mesa / trench feature, where a key characteristic of the device is sensitive to the mesa width and it is important to reduce the sensitivity of that characteristic to the mesa width.

[0091] Figure 7 shows a method for forming a vertical junction field-effect transistor. The method includes providing a drift layer having a first conductivity type (block 702), forming a source layer having the first conductivity type on the drift layer (block 704), and forming a mesa by selectively etching a portion of the source layer and the drift layer to form a trench that extends into the drift layer and defines the mesa adjacent to the trench (block 706). This trench has a mesa sidewall adjacent to the trench. The method further includes forming a shallow conduction region in the mesa extending between the drift layer and the source layer (block 708), and forming a gate region having a second conductivity type in the mesa (block 710). The gate region is adjacent to a channel region in the mesa, and the channel region includes a deep conduction region adjacent to the shallow conduction region, so that the shallow conduction region is between the deep conduction region and the gate region. The shallow conduction region has a higher doping concentration than the deep conduction region.

[0092] Forming a shallow conduction region may involve performing a gradient ion implantation of a first conductivity type dopant ion into the mesa sidewall at a first implantation energy to form a shallow conduction region in the mesa, such that a portion of the drift layer in the mesa forms a deep conduction region adjacent to the shallow conduction region.

[0093] Forming a gate region may involve implanting a second conductivity type dopant ion into the mesa sidewall at a second injection energy lower than a first injection energy in order to form a gate region in the mesa, where the shallow conduction region lies between the gate region and the deep conduction region, and the second conductivity type is the opposite of the first conductivity type.

[0094] In some embodiments, forming a mesa involves forming an etch mask on a source layer and etching the source and drift layers to form a mesa in the region beneath the etch mask. Forming a shallow conductive region may involve implanting a first conductive type of dopant ion into the mesa sidewall using the etch mask as an implantation mask.

[0095] The etch mask may include an SiO2 etch mask on the source layer and a silicon nitride mask on the SiO2 mask, and the method further includes forming a second etch mask on a mesa and trenches, patterning the second etch mask to expose the floors of the mesa and trenches adjacent to the mesa, and injecting dopant ions of a second conductivity type into the mesa sidewalls and junction termination regions at a second injection energy lower than the first injection energy to expose one or more surface regions in the edge regions of the device, thereby forming gate regions in the mesa and edge termination regions in the edge regions. The shallow conduction region is located between the gate region and the deep conduction region, and the second conductivity type is the opposite of the first conductivity type.

[0096] The second etch mask may contain SiO2, and patterning the second etch mask involves selectively etching the second etch mask using a silicon nitride mask as an etch stop layer.

[0097] While embodiments of the concept of the invention have been described in considerable detail with reference to a particular configuration, other embodiments are possible. The field plate and gate can have many different shapes and can be connected to the source contact in many different ways. Therefore, the spirit and scope of the invention should not be limited to the specific embodiments described above.

Claims

1. A drift layer (15) having a first conductivity type, A mesa (12) on the drift layer, comprising a channel region (114) on the drift layer and a source layer (16) on the channel region, wherein the channel region and the source layer have the first conductivity type, The gate region (18) in the mesa adjacent to the channel region is a gate region (18) having a second conductivity type opposite to the first conductivity type, The channel region includes a deep conduction region (122), a shallow conduction region (124) between the deep conduction region and the gate region, and an intermediate conduction region between the deep conduction region and the shallow conduction region. The deep conduction region has a first doping concentration of a first conductivity type dopant ion, the shallow conduction region has a second doping concentration of a first conductivity type dopant ion greater than the first doping concentration, the intermediate conduction region has a third doping concentration of a first conductivity type dopant ion between the first doping concentration and the second doping concentration, and the shallow conduction region, the intermediate conduction region, and the deep conduction region form a multi-stage doping profile in the channel region. A power transistor device in which the shallow conduction region, the intermediate conduction region, and the deep conduction region are arranged perpendicular to the direction of current passing through the channel region from the source layer to the drift layer.

2. The power transistor device according to claim 1, wherein the shallow conduction region extends vertically between the drift layer and the source layer, and the deep conduction region extends vertically between the drift layer and the source layer.

3. The power transistor device according to claim 1, wherein the shallow conduction region has a doping concentration at least 10 times greater than the doping concentration of the deep conduction region.

4. The power transistor device according to claim 1, wherein the shallow conduction region has a gradient doping profile, which is gradient in a transverse direction perpendicular to the direction of carrier flow through the channel region when the vertical junction field-effect device is ON.

5. The power transistor device according to claim 1, wherein the shallow conduction region has a width in the transverse direction perpendicular to the direction of carrier flow through the channel region when the vertical junction field-effect device is ON, which is one-third of half the width of the mesa.

6. The power transistor device according to claim 1, further comprising a breakdown adjustment region between the shallow conduction region and the gate region, wherein the breakdown adjustment region has the first conductivity type and a third doping concentration lower than the second doping concentration of the shallow conduction region.

7. The power transistor device according to claim 1, wherein the channel region contains silicon carbide, and the vertical direct combined field-effect device exhibits a change in threshold voltage corresponding to a mesa width of less than 20 V / micron.

8. The power transistor device according to claim 1, wherein the width of the shallow channel region in the transverse direction perpendicular to the direction of current when the device is ON is independent of the width of the mesa in the transverse direction.

9. The power transistor device according to claim 1, wherein the width of the deep channel region in the transverse direction perpendicular to the direction of current when the device is in the ON state is directly proportional to the width of the mesa in the transverse direction.

10. The gate region includes a first gate region, the shallow conduction region includes a first shallow conduction region, and the power transistor device is A second gate region in the mesa opposite to the first gate region, wherein the channel region is located between the first gate region and the second gate region, The channel region further comprises a second shallow conduction region between the deep conduction region and the second gate region, The power transistor device according to claim 1, wherein the second shallow conduction region has a third doping concentration greater than the first doping concentration in the deep conduction region.

11. To provide a drift layer having a first conductivity type (702), Forming a source layer having the first conductivity type on the drift layer (704), To form a trench that extends into the drift layer and defines a mesa adjacent to the trench, a mesa is formed by selectively etching the source layer and a portion of the drift layer (706), wherein the mesa has a mesa side wall adjacent to the trench (706), In the mesa, a shallow conductive region is formed between the drift layer and the source layer (708), The method includes forming a gate region having a second conductivity type in the mesa (710), wherein the gate region is adjacent to a channel region in the mesa, the channel region includes a deep conduction region adjacent to the shallow conduction region, and the shallow conduction region forms a gate region located between the deep conduction region and the gate region (710), A method for forming a power transistor device in which the shallow conduction region has a higher doping concentration than the deep conduction region.

12. The method according to claim 11, wherein forming the shallow conduction region involves performing angled ion implantation of a first conductivity type dopant ion into the mesa sidewall with a first implantation energy to form the shallow conduction region in the mesa, and a portion of the drift layer in the mesa forms the deep conduction region adjacent to the shallow conduction region.

13. The method according to claim 12, wherein forming the gate region involves implanting a second conductivity type dopant ion into the mesa sidewall at a second injection energy lower than the first injection energy in order to form the gate region in the mesa, the shallow conduction region being located between the gate region and the deep conduction region, and the second conductivity type being the opposite of the first conductivity type.

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