Nanosheet-based semiconductor structures with dielectric pillars

Abstract

The semiconductor structure includes a substrate, a first device disposed on the substrate, and a second device disposed on the substrate. The first device includes a first plurality of nanosheets including a p-type material. The second device includes a second plurality of nanosheets including an n-type material. A dielectric isolation pillar is disposed between the first device and the second device.

Description

Technical Field

[0001] The present invention relates to the manufacture of semiconductor integrated circuits, and more particularly to the formation of field effect transistor (FET) devices within integrated circuits.

Background Art

[0002] Ongoing technological innovations in semiconductor process technology have enabled higher integration levels and associated device scaling. As the semiconductor industry moves towards even more limits of the spacing architecture, FET devices must be scaled to smaller dimensions in order to increase the effective channel width per footprint area. In some cases, such scaling is achieved using nanosheet FET devices. A given nanosheet FET device includes a channel that includes a number of nanosheet layers arranged in a stacked configuration, each nanosheet layer having a vertical thickness that is significantly smaller than the width of the nanosheet layer. A common gate structure is formed in the upper and lower areas of the stacked configuration of nanosheet layers, thereby increasing the effective channel width of the resulting device, and thus the drive current supported thereby, for a given footprint area. Nanosheet technology is considered to be a viable option for the continued scaling of metal oxide semiconductor (MOS) devices such as complementary MOS (CMOS) devices that each include an n-type FET region (n-type semiconductor device) and a p-type FET region (p-type semiconductor device).

[0003] However, due to scaling limitations associated with nanosheet device architectures, electrostatic problems and reduced mobility can occur. Therefore, to address the nanosheet scaling problems, a variation of the nanosheet device architecture called the fork-sheet has been proposed. Generally, fork-sheet semiconductor devices offer superior area and performance scalability by allowing for denser spacing between p-type and n-type semiconductor devices or regions, thereby significantly reducing the separation distance between p-type and n-type regions. [Overview of the Initiative]

[0004] The exemplary embodiments relate to the fabrication of nanosheet semiconductor structures and devices, particularly forksheet semiconductor structures and devices.

[0005] In one exemplary embodiment, the semiconductor structure includes a substrate, a first device disposed on the substrate, and a second device disposed on the substrate. The first device includes a plurality of first nanosheets comprising a p-type material. The second device includes a plurality of second nanosheets comprising an n-type material. A dielectric isolation pillar is disposed between the first and second devices.

[0006] In another exemplary embodiment, the semiconductor structure includes a substrate, a dielectric isolation pillar extending perpendicularly from the substrate, a pFET device comprising a plurality of channel nanosheets in contact with the dielectric isolation pillar, disposed on a first side of the dielectric isolation pillar, and an nFET device comprising a plurality of channel nanosheets in contact with the dielectric isolation pillar, disposed on a second side of the dielectric isolation pillar.

[0007] In another exemplary embodiment, the method includes forming a first device on a semiconductor substrate and forming a second device on the semiconductor substrate. The first device includes a plurality of first nanosheets comprising a p-type material. The second device includes a plurality of second nanosheets comprising an n-type material. The method further includes forming a dielectric isolation pillar extending perpendicularly from the semiconductor substrate between the first device and the second device.

[0008] These purposes, features, and advantages of the Disclosure, as well as other purposes, features, and advantages, will become apparent from the following detailed description of exemplary embodiments of the Disclosure. The following description should be read with reference to the accompanying drawings. [Brief explanation of the drawing]

[0009] [Figure 1] This is a top view of a semiconductor structure in a first intermediate manufacturing stage, according to one or more exemplary embodiments. [Figure 2] This is a cross-sectional view of the semiconductor structure at the first intermediate stage, cut along line 2-2 in Figure 1. [Figure 3] This is a top view of the semiconductor structure in the second intermediate manufacturing stage. [Figure 4] This is a cross-sectional view of the semiconductor structure at the second intermediate stage, cut along line 4-4 in Figure 3. [Figure 5] This is a cross-sectional view of the semiconductor structure at the third intermediate manufacturing stage. [Figure 6] This is a cross-sectional view of the semiconductor structure at the fourth intermediate manufacturing stage. [Figure 7] This is a cross-sectional view of the semiconductor structure at the fifth intermediate manufacturing stage. [Figure 8] This is a top view of the semiconductor structure in the sixth intermediate manufacturing stage. [Figure 9] This is a cross-sectional view of the semiconductor structure at the sixth intermediate stage, cut along line 9-9 in Figure 8. [Figure 10] This is a cross-sectional view of the semiconductor structure at the sixth intermediate stage, cut along line 10-10 in Figure 8. [Figure 11] This is a cross-sectional view of the semiconductor structure at the sixth intermediate stage, cut along line 11-11 in Figure 8. [Figure 12] This is a top view of the semiconductor structure in the seventh intermediate manufacturing stage. [Figure 13] This is a cross-sectional view of the semiconductor structure at the seventh intermediate stage, cut along line 13-13 in Figure 12. [Figure 14] This is a cross-sectional view of the semiconductor structure at the seventh intermediate stage, cut along line 14-14 in Figure 12. [Figure 15] This is a cross-sectional view of the semiconductor structure at the seventh intermediate stage, cut along line 15-15 in Figure 12. [Figure 16] This is a top view of the semiconductor structure in the eighth intermediate manufacturing stage. [Figure 17] This is a cross-sectional view of the semiconductor structure at the eighth intermediate stage, cut along line 17-17 in Figure 16. [Figure 18] This is a cross-sectional view of the semiconductor structure at the eighth intermediate stage, cut along line 18-18 in Figure 16. [Figure 19] This is a cross-sectional view of the semiconductor structure at the eighth intermediate stage, cut along line 19-19 in Figure 16. [Modes for carrying out the invention]

[0010] The processes disclosed herein provide isolation structures within semiconductor structures such as nanosheet FET transistor devices, particularly forksheet CMOS devices. These vertical isolation pillars separate n-type semiconductor regions or devices from p-type semiconductor regions or devices, extending from within the semiconductor substrate base to the vertical limits of the CMOS device. The n-type and p-type semiconductor regions utilize channel nanosheets of different materials, which enhances the operability of the CMOS device, particularly the performance of the p-type semiconductor region, and mitigates the patterning challenges in forming work function metal (WFM) in the n-type and p-type semiconductor regions.

[0011] While this description includes a detailed description of exemplary nanosheet FET architectures, such as fork-sheet CMOS devices having channel nanosheets in n-type and p-type semiconductor regions, it should be understood that embodiments of the teachings described herein are not limited to the specific FET architectures described herein. Rather, exemplary embodiments can be implemented with any other type of FET device, including, for example, any p-type or n-type nanosheet FET architecture and transistor structure.

[0012] Generally, the various processes used to form microchips for ICs are classified into four common categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that involves growing material on a semiconductor device, coating a semiconductor device with material, or otherwise moving material onto a semiconductor device. Available techniques include, in particular, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Removal / etching is any process that removes material from a semiconductor structure. Examples include etching processes (wet or dry) and chemical mechanical planarization (CMP). Semiconductor doping is the modification of electrical properties by doping, for example, the source and drain of a transistor, and is generally performed by diffusion, ion implantation, or both. After these doping processes, furnace annealing or fast thermal annealing (RTA) is performed. Annealing serves to activate the implanted dopants. Films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of different regions of a semiconductor substrate allows the conductivity of the substrate to be changed by applying a voltage. By fabricating structures of these various components, millions of transistors can be built and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the process of forming a three-dimensional relief image or pattern on a semiconductor substrate, which is later transferred to the substrate beneath it. In semiconductor lithography, this pattern is formed by a photosensitive polymer called photoresist. The lithography and etching pattern transfer steps are repeated many times to build the complex structures that make up the transistors and the many wires that connect the millions of transistors in the circuit.Each pattern printed on a substrate, such as a wafer, is aligned with a previously formed pattern, and conductors, insulators, and selectively doped areas are gradually built up to form the final device.

[0013] The various layers, structures, and regions shown in the attached drawings are schematic diagrams not drawn to a specific scale. Furthermore, for the sake of clarity, one or more layers, structures, and regions of types commonly used to form semiconductor devices or structures may not be explicitly shown in the given drawings. This does not mean that any of the unshown layers, structures, and regions are omitted from actual semiconductor structures. Moreover, the embodiments discussed herein are not limited to the specific materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it should be emphasized that the descriptions provided herein are not intended to include all processing steps that may be necessary to form a functional semiconductor integrated circuit device. Rather, for the sake of efficiency in the description, certain processing steps commonly used in forming semiconductor devices, such as film deposition, removal / etching, semiconductor doping, patterning / lithography, and annealing steps, are intentionally not described in great detail herein.

[0014] Furthermore, throughout the drawings, the same reference numerals or similar reference numerals are used to indicate the same or similar features, elements or structures, and thus, for each drawing, detailed descriptions of the same or similar features, elements or structures will not be repeated. The terms "about" or "substantially" used herein with respect to thickness, width, percentage, range, etc. mean that although not exact, they indicate being close or approximate. For example, the terms "about" or "substantially" used herein mean that there is a small error. Further, the terms "vertical" or "vertical direction" or "vertical height" used herein represent the Z direction of the Cartesian coordinates shown in the drawings, and the terms "horizontal" or "horizontal direction" or "lateral direction" used herein represent the X direction or the Y direction or both of the Cartesian coordinates shown in the drawings.

[0015] Furthermore, as used herein, the term "exemplary" means "serving as an example, instance or illustration". The embodiments or designs described herein are intended to be "exemplary" and should not necessarily be construed as being more preferable or advantageous than other embodiments or designs. The term "connected" can include both indirect "connection" and direct "connection". The terms "on" or "onto" with respect to the arrangement of components with respect to a semiconductor structure should not be construed as requiring direct contact of the components. This is because, unless otherwise specified, there may be a possibility of arranging one or more intermediate components, layers or coatings between the selected components. More specifically, unless otherwise specified, the positional relationship can be direct or indirect, and the present disclosure is not intended to limit in this regard.

[0016] As described above in this specification, for the sake of brevity, in this specification, the prior art related to semiconductor devices and integrated circuit (IC) manufacturing may or may not be described in detail. Certain manufacturing operations used when implementing one or more embodiments of the present disclosure may be individually known, but the described combinations of the operations of the present disclosure, the resulting structures, or both are without precedent. Therefore, the unprecedented combination of operations described with respect to the manufacture of a semiconductor structure including a nanosheet FET transistor structure or device according to an exemplary embodiment utilizes various physical and chemical processes known individually that are performed on a semiconductor (e.g., silicon) substrate. Some of those processes are described in the paragraphs immediately following.

[0017] In the following discussion, throughout various manufacturing stages, a semiconductor device including a nanosheet FET transistor structure, region, or device is referred to as "semiconductor structure 100," which is shown in all of the accompanying drawings. Further, the following discussion identifies various intermediate manufacturing stages of semiconductor structure 100. It should be understood that those intermediate stages are merely examples. When processing semiconductor structure 100, more or fewer intermediate stages may be implemented, and the disclosed stages may be implemented in a different order or sequence. Further, one or more processes may be incorporated into the various intermediate stages described herein, and one or more processes may be performed at intermediate stages described elsewhere herein.

[0018] Figures 1 - 19 show various top views and cross-sectional views of at least a portion of semiconductor structure 100 when undergoing sequential processing operations as part of the process of forming the semiconductor structure.

[0019] Figure 1 is a top view of the semiconductor structure in the first intermediate manufacturing stage, and Figure 2 is a cross-sectional view taken along line 2-2 in Figure 1. The semiconductor structure 100 includes a substrate or wafer 102 and a nanosheet stack 104 formed on the substrate 102. The substrate 102 defines the longitudinal x-axis, the horizontal y-axis, and the vertical z-axis. The substrate 102 may include an oxide layer (not specifically shown) on which the nanosheet stack 104 is formed. In exemplary embodiments, a sacrificial layer 106 is formed on the substrate 102. The sacrificial layer 106 may be an active layer and may include a silicon-germanium layer containing at least 50 percent (50%) germanium in its composition. Other germanium compositions are also conceivable. The material of the sacrificial layer 106 is selective to other materials forming the nanosheet stack 104 for removal during one or more subsequent etching processes. The substrate 102 may include a silicon (Si) material or another dielectric material, such as silicon oxide or silicon nitride. In exemplary embodiments, the substrate 102 may have a thickness of approximately 500 to 1000 micrometers (μm). The substrate 102 itself may contain multiple layers, but again, for clarity and simplicity of illustration, the substrate 102 is shown as a single layer in these figures.

[0020] The nanosheet stack 104 is formed as a series of interlayers of stacked semiconductor materials. In an exemplary embodiment, the nanosheet stack 104 includes an alternating arrangement of p-type semiconductor region channel nanosheets 108 and n-type semiconductor region channel nanosheets 110 placed on a sacrificial layer 106. The p-type semiconductor region channel nanosheets contain silicon germanium (SiGe) with a germanium composition of 25 percent (25%). Other germanium concentrations are conceivable, insofar as the germanium concentration differs from that of the sacrificial layer 106. The n-type semiconductor region channel nanosheets 110 contain silicon (Si). Generally, these alternatingly stacked p-type semiconductor region channel nanosheets 108 and n-type semiconductor region channel nanosheets 110 should be made of semiconductor materials that may selectively etch each other. The thicknesses of the p-type semiconductor region channel nanosheets 108 and n-type semiconductor region channel nanosheets 110 can vary depending on the individual application. In one exemplary embodiment, the silicon germanium p-type semiconductor region channel nanosheet 108 can have a thickness of approximately 5 to 30 nm, and the silicon n-type semiconductor region channel nanosheet can have a thickness of approximately 5 to 15 nm. Naturally, not all p-type semiconductor region channel nanosheets 108 and all n-type semiconductor region channel nanosheets 110 need to have the same thickness, but they may be made to the same thickness depending on the application.

[0021] This alternating arrangement of p-type semiconductor region channel nanosheets 108 and n-type semiconductor region channel nanosheets 110 is deposited or grown on a semiconductor substrate 102, more specifically on a sacrificial layer 106. The p-type semiconductor region channel nanosheets 108 and n-type semiconductor region channel nanosheets 110 can be formed by a CVD deposition process or by alternate epitaxial growth according to conventional methods. For example, this alternating continuum of silicon germanium (SiGe) p-type semiconductor region channel nanosheets 108 and n-type semiconductor region channel nanosheets 110 containing silicon (Si) nanosheets can be formed by epitaxially growing one layer at a time until a desired number and thickness of p-type semiconductor region channel nanosheets 108 and n-type semiconductor region channel nanosheets 110 are achieved. Epitaxial materials can be grown from gaseous or liquid precursors and can be grown using gas-phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable processes. Doping can be carried out during deposition to epitaxial silicon (Si), silicon germanium (SiGe), or carbon-doped silicon (Si:C), or a combination thereof, by adding dopants, i.e., n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), depending on the type of transistor. In exemplary embodiments, p-type dopants are added to produce p-type semiconductor regions or transistor structures, and n-type dopants are added to produce n-type semiconductor regions or transistor structures.

[0022] A hard mask layer 112 can be formed on top of the nanosheet stack 104. The hard mask layer 112 can be formed from any suitable material, such as silicon nitride (SiN) hard mask material, which has etching resistance greater than the etching resistance of the substrate 102 and the etching resistance of at least some of the insulating materials used in the subsequent processing of the semiconductor structure 100. The hard mask material 112 is used to cover / protect the nanosheet stack 104 during the subsequent etching process.

[0023] Next, refer to Figures 3 and 4, which illustrate an exemplary second intermediate manufacturing stage. Conventional lithography and anisotropic etching processes are used to form a vertical isolation channel that penetrates the hard mask layer 112 and the nanosheet stack 104 and extends a predetermined distance into the interior of the semiconductor substrate 102, running through approximately the center of the semiconductor structure 100. Dielectric materials, including but not limited to silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), carbon-doped silicon oxide (SiOC), silicon carbonitride (SiCN), boron nitride (BN), silicon boron nitride (SiBN), silicon boron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), silicon oxide, and combinations thereof, to form a vertical dielectric isolation pillar 114. The vertical dielectric separation pillar 114 divides the nanosheet stack 104, separating the p-type semiconductor region and the n-type semiconductor region of the semiconductor structure 100, represented by reference numerals 116 and 118, respectively. The vertical separation pillar 114 extends into the semiconductor substrate 102 by a predetermined distance "d". "d" is >0 and is not limited, but for example, "d" is in the range of approximately 10 to 30 nm. As shown in Figure 4, in exemplary embodiments, the edges of the p-type semiconductor region channel nanosheet 108 and the n-type semiconductor region Chanel nanosheet 110 may be in contact with the vertical separation pillar 114. The vertical separation pillar 114 acts as an anchor to stably hold the nanosheets in subsequent processing, such as the processes related to the processes shown in Figures 4 and 5.

[0024] Furthermore, shallow trench isolation (STI) regions 120-1 and 120-2 are formed at least partially on each side of the nanosheet stack 104 within the substrate 102. The shallow trench isolation (STI) regions 120-1 and 120-2 electrically isolate the longitudinally spaced semiconductor structures 100. In one exemplary embodiment, the STI regions 120-1 and 120-2 can be formed in conjunction with the lithography and anisotropic etching processes described above or subsequent processes that form the corresponding trenches in the substrate 102. The formed trenches are filled with isolation or STI dielectric fillers, including, for example, a dielectric material such as silicon oxide and a silicon nitride liner, to form the STI (shallow trench isolation) regions 120-1 and 120-2. The STI regions 120-1 and 120-2 can be subjected to a chemical mechanical polishing (CMP) process to flatten the STI dielectric fillers 120-1 and 120-2 so that they are coplanar with the upper surface of the semiconductor substrate 102.

[0025] Next, refer to Figure 5, which illustrates an exemplary third intermediate manufacturing step. A lithography mask, represented by reference numeral 122, is deposited on the p-type semiconductor region 116, surrounding the perpendicular dielectric pillar 114 and the STI region 120-2 adjacent to the p-type semiconductor region 116. One or more etching processes selective to the silicon (Si) material of the n-type semiconductor region channel nanosheet 110 remove the portion of the p-type semiconductor region channel nanosheet 108 containing silicon germanium (SiGe) that lies within the n-type semiconductor region 118, thereby leaving the n-type semiconductor region channel nanosheet 110 in a suspended relation and forming a suspended channel structure within the n-type semiconductor region 118. "Suspended channel" means that the n-type semiconductor region channel nanosheet 110 lies on the substrate 102 in a separated relationship. In exemplary embodiments, the edges of the n-type semiconductor region channel nanosheet 112 can be supported by vertical separation pillars 114, for example, fixed or bonded to the vertical separation pillars 114. One or more etching processes also remove the sacrificial layer 106. Once the sacrificial layer 106 is removed, a large void or gap is created between the bottom silicon channel nanosheet 110 and the silicon substrate 102 (compared to the voids between the remaining vertically adjacent channel nanosheets 110). Subsequently, the lithography mask 122 on the p-type semiconductor region 116 is removed by a conventional process.

[0026] Next, refer to Figure 6, which illustrates an exemplary fourth intermediate manufacturing step. In this process, a lithography mask 124 is subsequently deposited on the n-type semiconductor region 118, surrounding the n-type semiconductor region 118, the vertical separation pillars 114, and the STI region 120-1 adjacent to the n-type semiconductor region 118. A conventional etching process selective for the silicon germanium (SiGe) material of the p-type semiconductor region channel nanosheet 108 removes the portion of the n-type semiconductor region channel nanosheet 110 containing silicon (Si) material that lies within the p-type semiconductor region 116, thereby leaving four p-type semiconductor region channel nanosheets 108 suspended relative to the semiconductor substrate 102. In exemplary embodiments, the edges of the p-type semiconductor region channel nanosheet 108 can be supported by the vertical separation pillars 114, for example, fixed or bonded to the vertical separation pillars 114. The sacrificial layer 106, made from silicon germanium (SiGe 50%), also remains and is not removed during the etching process described above. More specifically, the selected etching process is also selective for silicon germanium (SiGe 50%). Subsequently, the lithography mask 124 on the n-type semiconductor region 118 is removed by a conventional process.

[0027] Next, refer to Figure 7, which illustrates an exemplary fifth intermediate manufacturing step. The semiconductor structure 100 is subjected to a deposition process, thereby depositing a sacrificial material containing silicon germanium (SiGe), but not limited to (e.g., 50% germanium), onto the semiconductor structure 100 to fill the spaces or voids formed by the removal of portions of the n-type semiconductor region 118 of the p-type semiconductor region channel nanosheet 108 and portions of the p-type semiconductor region 116 of the n-type semiconductor region channel nanosheet 110. This sacrificial material forms a sacrificial layer 126 between vertically adjacent p-type semiconductor region channel nanosheets 108 and vertically adjacent n-type semiconductor region channel nanosheets 110. This additional sacrificial material or layer 126 is intended to protect the remaining p-type semiconductor region channel nanosheets 108 and n-type semiconductor region channel nanosheets 110 during the subsequent manufacturing process. Other materials, including other silicon germanium materials with different germanium concentrations, can also be used as sacrificial materials. Optional silicon dioxide (SiO2) can also be used along with this sacrificial material.

[0028] Next, refer to Figures 8-11, which illustrate an exemplary sixth intermediate manufacturing step. One or more sacrificial gates 128 are formed on the nanosheet stack 104 by one or more conventional lithography and etching processes, positioned perpendicular to the vertical separation pillars 114. In one exemplary embodiment, three sacrificial gates 128 are formed on the nanosheet stack 104, but four or more or two or fewer sacrificial gates 128 are also conceivable. These one or more sacrificial gates 128 act as placeholders and are later removed and replaced with suitable gate materials to form a functional gate structure. The sacrificial gates 128 can include any material that can be selectively etched more than the materials of the p-type semiconductor region channel nanosheet 108 and the n-type semiconductor region channel nanosheet 110. One suitable material for the sacrificial gates 128 includes silicon materials such as polysilicon and amorphous silicon, or dielectric materials such as oxides, nitrides, or oxynitrides. The sacrificial gate 128 can be formed using deposition (e.g., chemical vapor deposition), planarization (e.g., chemical mechanical polishing (CMP)), photolithography, and etching processes (e.g., reactive ion etching). A hard mask layer (not specifically shown, but incorporated as part of the structure of the sacrificial gate 128) can be formed on top of the sacrificial gate 128. This hard mask layer can be formed from a suitable material, such as silicon nitride (SiN) hard mask material, having etching resistance greater than the etching resistance of the substrate 102 and the etching resistance of at least some of the insulating materials used in the remaining processing of the semiconductor structure 100. The hard mask material is used to cover / protect the nanosheet stack 104 during the subsequent etching process. The hard mask 112 placed on the nanosheet stack 104 is removed during these processes.

[0029] Furthermore, gate spacers 130 are formed around each sacrificial gate 128 (and around the hard mask layer). The gate spacers 130 can include dielectric materials such as silicon boron nitride carbide (SiBCN), silicon oxycarbonite (SiOCN), carbon-doped silicon oxide (SiOC), silicon carbonitride (SiCN), boron nitride (BN), silicon boron nitride (SiBN), oxides, nitrides, silicon nitride (SiN), silicon oxide (SO2), or other materials including low-k materials. In an exemplary embodiment, the gate spacer 130 includes SiBCN. The gate spacers 130 can be formed using deposition processes such as chemical vapor deposition (CVD) and reactive ion etching (RIE) processes. The gate spacers 130 are positioned on the sidewalls of the sacrificial gates 128 and can have wall thicknesses ranging from about 3 nanometers (nm) to about 15 nanometers (nm).

[0030] Refer to Figures 8-11. An internal spacer 132 is formed within each nanosheet stack 104, aligned with the gate spacer 130. In exemplary embodiments, one or more selective etching processes are used for the materials of the p-type semiconductor region channel nanosheet 108 (silicon germanium (SiGe 25%)) and the n-type semiconductor region nanosheet channel 110 (silicon (Si)) to deform the sacrificial material or the periphery or edges of layer 126, along with one or more lithography processes. A suitable etching process includes an anisotropic etching process. The term “anisotropic etching process” means a material removal process in which the etching rate in the direction perpendicular to the surface being etched is greater than the etching rate in the direction parallel to the surface being etched. This anisotropic etching may include reactive ion etching (RIE). Other examples of anisotropic etching that can be used at this point in the present disclosure include ion beam etching, plasma etching, or laser ablation.

[0031] Subsequently, the void formed by the removed sacrificial layer portion 126 is filled with the material for the internal spacer 132 by one or more deposition processes. The material for the internal spacer 132 may include any of the materials identified above with respect to the gate spacer 130. In exemplary embodiments, the gate spacer 130 and the internal spacer 132 can be formed simultaneously using the same etching and deposition processes. In other exemplary embodiments, the gate spacer 130 and the internal spacer 132 can be formed by separate processes.

[0032] In exemplary embodiments, forming the sacrificial gate 128, gate spacer 130, and internal spacer 132 may further include recessing the peripheral portions of the p-type semiconductor region channel nanosheet 108 and n-type semiconductor region channel nanosheet 110 that extend beyond the outer wall of the sacrificial gate 128. In exemplary embodiments, this etching process that removes the portion of the nanosheet stack 104 that extends beyond the outer wall of the gate spacer 130 may be a selective etching process. For example, in one embodiment, selective etching may include etching chemistry that selectively removes the first material more than the second material in a ratio of 10:1 or greater, for example, 1000:1. For example, one or more etching processes can selectively remove the exposed silicon-germanium (SiGe) material of the p-type semiconductor region channel nanosheet 108 and the exposed silicon (Si) material of the n-type semiconductor region channel nanosheet 110 from at least one of the materials of the sacrificial gate 128, gate spacer 130, internal spacer 132, and substrate 102. In some embodiments, an etching-blocking mask, such as a photoresist or hard mask, e.g., a silicon nitride (SiN) mask, can be formed on the sacrificial gate 128 during the etching process to remove the exposed portion of the nanosheet stack 104.

[0033] Refer to Figures 8-11 next. This process then forms source and drain (S / D) regions 134 between adjacent internal spacers 132 around each sacrificial gate 128. The S / D regions 134 are formed using an epitaxial layer growth process. In exemplary embodiments, forming the S / D regions 134 in a p-type semiconductor region 116 involves epitaxially growing a silicon germanium (SiGe) material that can be similar to the material of the p-type semiconductor region channel nanosheet 108, and forming the S / D regions 134 in an n-type semiconductor region 118 involves epitaxially growing a silicon (Si) material that can be similar to the material of the n-type semiconductor region channel nanosheet 110. As used herein, the term “drain” means a doped region within a semiconductor structure located at the edge of a channel region through which carriers flow out of the semiconductor structure 100, e.g., a nanosheet transistor structure. The term "source" refers to a doped region within a semiconductor structure into which majority carriers flow into the channel region. The S / D region 134 can be formed by in situ doping (doping in epitaxy) or ex situ doping, or a combination of in situ and ex situ doping. Doping techniques may include, but are not limited to, ion implantation, gas-phase doping, plasma doping, plasma immersion ion implantation, cluster doping, infusion doping, liquid-phase doping, solid-phase doping, or any suitable combination of these techniques. In some embodiments, the dopant is activated by thermal annealing such as laser annealing, flash annealing, fast thermal annealing (RTA), or any suitable combination of these techniques.

[0034] The epitaxial growth or deposition of the S / D region 134 can be carried out in a chemical deposition apparatus such as a metal-organic chemical vapor deposition (MOCVD) apparatus or a plasma-accelerated chemical vapor deposition (PECVD) apparatus. The epitaxial semiconductor S / D region 134 can be doped in situ to make it p-type or n-type conductive. The term "in situ" means that a dopant, such as a p-type or n-type dopant, is introduced into the base material during the formation of the base semiconductor material, such as silicon (Si) or silicon germanium (SiGe). In one exemplary embodiment, a boron p-type dopant is introduced into a silicon germanium (SiGe) epitaxial growth to make it p-type conductive, and a phosphorus n-type dopant is introduced into a silicon (Si) epitaxial growth to make it n-type conductive.

[0035] An inter-layer dielectric (ILD) 136 is deposited on the semiconductor structure 100 so as to at least partially surround the nanosheet stack 104 and the sacrificial gate 128. In exemplary embodiments, the inter-layer dielectric (ILD) 136 is an oxide layer. In various embodiments, the height of the inter-layer dielectric (ILD) 136 can be reduced by chemical mechanical polishing (CMP) or etching or both to expose the sacrificial gate 128. Other dielectric materials suitable for forming the inter-layer dielectric (ILD) 136 include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, SiCO, SiCON, or any suitable combination of such materials.

[0036] Next, referring to Figures 12-15, which illustrate an exemplary seventh intermediate manufacturing step, the sacrificial gate 128 has been removed. In exemplary embodiments, the removal of the sacrificial gate 128 can be achieved using one or more wet or dry etching processes. More specifically, the sacrificial gate 128 can be removed by at least one of an anisotropic etching process, such as reactive ion etching (RIE), and an isotropic etching process, such as wet chemical etching. In one example, this etching process for removing the sacrificial gate 128 may include etching chemistry that is selective for the silicon germanium (SiGe) material layer of the p-type semiconductor region channel nanosheet 108 and the silicon (Si) material layer of the n-type semiconductor region channel nanosheet 110. After the removal of the sacrificial gate 128, an opening or replacement gate cavity is formed that exposes the suspended channels beneath the p-type semiconductor region channel nanosheet 108 and the n-type semiconductor region channel nanosheet 110, respectively.

[0037] Following the removal of the sacrificial gate 128, the sacrificial layer 126 and the remaining portion of the sacrificial layer 106 within the p-type semiconductor region 116 are removed by one or more selective etching processes for silicon germanium (SiGe) in the p-type semiconductor region channel nanosheet 108 and silicon in the n-type semiconductor region channel nanosheet 110. After the removal of the sacrificial layers 106 and 126, suspended channel structures are formed in the p-type and n-type semiconductor regions 116 and 118, respectively. "Suspended channels" means that the p-type semiconductor region channel nanosheet 108 and the n-type semiconductor region channel nanosheet 110 lie on the substrate 102 and exist in a separated relationship supported, bonded, or fixed to the internal spacer 132. As described above, the p-type semiconductor region channel nanosheet 108 and the n-type semiconductor region channel nanosheet 110 are further in contact with the vertical separation pillar 114, engaged with the vertical separation pillar 114, partially embedded in the vertical separation pillar 114, or a combination thereof. The space around the suspended structure can be formed with gate structure material, conductive material, or semiconductor material, or a combination thereof.

[0038] Next, refer to Figures 16-19, which illustrate an exemplary eighth intermediate manufacturing step. This process subsequently involves forming a substitutional high-k / metal gate structure 138 around the n-type semiconductor region channel nanosheet 110 within the n-type semiconductor region 118, and forming a substitutional high-k / metal gate structure 140 around the p-type semiconductor region channel nanosheet 108 within the p-type semiconductor region 116. For example, a conformal high-k gate liner and a work function metal can be deposited on the semiconductor structure 100. This gate liner can be formed over the entire outer surface of the suspended p-type semiconductor region channel nanosheet 108 and n-type semiconductor region channel nanosheet 110. Examples of gate dielectric materials include, but are not limited to, any suitable dielectric material, including silicon oxide, silicon nitride, silicon oxynitride, high-k materials, or combinations thereof. Examples of high-k materials include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. This high-k dielectric may further contain dopants such as lanthanum, aluminum, and magnesium. This gate dielectric material can be formed by any suitable process or any suitable combination of many processes, but is not limited to, thermal oxidation, chemical oxidation, thermal nitriding, plasma oxidation, plasma nitriding, atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. In some embodiments, this gate dielectric has a thickness ranging from 1 nm to 5 nm, but thinner and thicker thicknesses are also conceivable.

[0039] Work function metals can be deposited on the semiconductor structure 100, i.e., in or on top of a high-k liner, to form a functional gate structure. Work function metals can be formed by depositing conductive materials, including, but not limited to, titanium nitride (TiN), titanium aluminum nitride (TiAlN), or combinations thereof. Other suitable materials include doped polycrystalline or amorphous silicon, germanium, silicon germanium, metals (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold), conductive metal compound materials (tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium aluminum carbide, tungsten silide, tungsten nitride, ruthenium oxide, cobalt silide, nickel silide), carbon nanotubes, conductive carbon, graphene, or any suitable combination of such conductive materials. In embodiments, the work function metal includes one or more of TiN and TiAlN. The work function metal may further include dopants incorporated during or after deposition. The work function metal is deposited using a suitable deposition process, such as CVD, plasma-accelerated chemical deposition (PECVD), PVD, plating, thermal or e-beam deposition, sputtering, etc. In exemplary embodiments, the p-type semiconductor region includes a gate structure of a first material, and the n-type semiconductor region includes a gate structure of a second material different from the first material, where these materials include, but are not limited to, TiAlC for the n-type semiconductor region and TiN for the p-type semiconductor region.

[0040] Therefore, the above process provides a semiconductor structure 100 having at least the following characteristics. In an exemplary embodiment, the semiconductor structure 100 is a fork-sheet device including a central vertical separation pillar 114 that separates a p-type semiconductor region 116 from an n-type semiconductor region 118. This semiconductor structure may include one or more gates on the substrate 102, including, but not limited to, a number of gates such as three gates, and these gates extend over the p-type semiconductor region or device 116 and over the n-type semiconductor region or device 118. The p-type semiconductor region 116 includes a first number of p-type semiconductor region channel nanosheets 108 on a first side of the vertical separation pillar 114, and these first number of p-type semiconductor region channel nanosheets 108 may be in contact with the first side of the vertical separation pillar 114 or bonded to the first side of the vertical separation pillar 114. The p-type semiconductor region channel nanosheets 108 may be fabricated from silicon germanium (SiGe) and may be surrounded by a gate structure of the first material. Silicon germanium material provides excellent hole mobility. The n-type semiconductor region 118 includes a second number of n-type semiconductor region channel nanosheets 110 on the second side surface of the vertical separation pillar 114, the second number of n-type semiconductor region channel nanosheets 110 which may be in contact with the second side surface of the vertical separation pillar 114 or bonded to the second side surface of the vertical separation pillar 114. The n-type semiconductor region channel nanosheets 110 can be manufactured from silicon (Si) and may be surrounded by a gate structure of the second material. In exemplary embodiments, the second material is different from the first material. Silicon (Si) is a good conductor and provides high electron mobility. The first number of p-type semiconductor region channel nanosheets 108 and the second number of n-type semiconductor region channel nanosheets 110 may be the same or different. In exemplary embodiments, the first and second numbers are different. In an exemplary additional embodiment, the first number of p-type semiconductor region channel nanosheets 108 is greater than the second number of n-type semiconductor region channel nanosheets 110.The thicknesses of the p-type semiconductor region channel nanosheet 108 and the n-type semiconductor region channel nanosheet 110 may be the same or different. In another exemplary embodiment, the p-type semiconductor region channel nanosheet 108 is offset perpendicularly along the z-axis from the n-type semiconductor region channel nanosheet 110 in a staggered or alternating arrangement. In another exemplary embodiment, the p-type semiconductor region channel nanosheet 108 and the n-type semiconductor region channel nanosheet 110 are aligned perpendicularly.

[0041] In exemplary embodiments, the suspended p-type semiconductor region channel nanosheets 108 and n-type semiconductor region channel nanosheets 110 can be further processed to provide nanowire geometry. The term “nanosheet” refers to a substantially two-dimensional structure having a thickness in the range of 1 to 100 nm. The width and length dimensions of a nanosheet may be greater than the width dimension. As used herein, the term “nanowire” refers to a structure having a cross-section with a perimeter defined by curvature and a cross-sectional diameter of less than 1 micron. Nanowires may have an aspect ratio of about 1, e.g., a height-to-width ratio. In some examples, the cross-section of a nanowire may have a diameter in the range of 1 nm to 40 nm. Nanowire geometry can be produced from the suspended p-type semiconductor region channel nanosheets 108 and n-type semiconductor region channel nanosheets 110 using etching processes such as isotropic etching.

[0042] The semiconductor devices and methods for forming semiconductor devices according to the above-described techniques can be used in a variety of applications, hardware, or electronic systems, or combinations thereof, including, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., mobile phones and smartphones), solid-state media storage devices, and functional circuits. Given the teachings described herein, those skilled in the art will be able to envision other embodiments and applications of the exemplary embodiments.

[0043] Accordingly, one or at least one of the semiconductor structures described herein can be mounted on an integrated circuit. The manufacturer may distribute the resulting integrated circuit chip in the form of a raw wafer (i.e., as a single wafer with a number of unpackaged chips), as a bare die, or in a packaged form. When distributed in a packaged form, the chip is mounted in a single-chip package (such as a plastic carrier with lead wires attached to a motherboard or other higher-order carrier) or in a multi-chip package (such as a ceramic carrier with single-sided or double-sided interconnects or embedded interconnects). In either case, the chip is then integrated with other chips, separate circuit elements, or other signal processing devices or combinations thereof as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product may be any product containing an integrated circuit chip, ranging from toys and other low-cost applications to high-end computer products with displays, keyboards or other input devices and central processing units.

[0044] In some embodiments, this suspended nanosheet channel structure can be further processed to provide nanowires. For example, nanowire geometry can be generated from the suspended channel structure using an etching process, such as isotropic etching. The above description of various embodiments of the present invention is illustrative and is not intended to be exhaustive or to limit the above description to the disclosed embodiments only. Many changes and modifications will become apparent to those skilled in the art that do not depart from the scope of the embodiments described. The terms used herein have been chosen to best describe the principles, practical applications, or technical improvements not found in commercially available art, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. circuit board and A first device disposed on the substrate, wherein the first device comprises a first plurality of nanosheets, and the first plurality of nanosheets comprises a first material that is p-type doped, A second device disposed on the substrate, wherein the second device comprises a second plurality of nanosheets, and the second plurality of nanosheets comprises a second material doped in the n-type, A dielectric isolation pillar disposed between the first device and the second device, A first shallow trench isolation region is formed at least partially within the substrate along the first side surface of the first plurality of nanosheets, A second shallow trench isolation region is formed at least partially within the substrate along the first side surface of the second plurality of nanosheets. Includes, The second surfaces of the first plurality of nanosheets extend from the first surfaces of the dielectric isolation pillar, and the second surfaces of the second plurality of nanosheets extend from the second surfaces of the dielectric isolation pillar, A semiconductor structure in which the first plurality of nanosheets are offset in a direction perpendicular to the second plurality of nanosheets.

2. The semiconductor structure according to claim 1, wherein the first plurality of nanosheets and the second plurality of nanosheets are in contact with, or engaged with, the dielectric isolation pillar, or partially embedded in the dielectric isolation pillar.

3. The semiconductor structure according to claim 1, wherein the first material contains silicon germanium and the second material contains silicon.

4. The semiconductor structure according to claim 1, wherein the first device comprises a given first number of the first nanosheets, and the second device comprises a given second number of the second nanosheets, wherein the given first number is different from the given second number.

5. The semiconductor structure according to claim 4, wherein the given first number of the first plurality of nanosheets is greater than the given second number of the second plurality of nanosheets.

6. The first device includes one or more gate structures, each having a first work function metal, and source and drain regions. The semiconductor structure according to claim 1, wherein the second device includes one or more gate structures, each having a second work function metal, and source and drain regions.

7. The semiconductor structure according to claim 6, wherein the second work function metal is different from the first work function metal.

8. The semiconductor structure according to claim 1, comprising three gates arranged on the substrate.

9. The semiconductor structure according to claim 1, wherein the dielectric isolation pillar extends into the substrate by a predetermined distance.

10. circuit board and A dielectric isolation pillar extending vertically from within the substrate, A pFET device comprising a first plurality of channel nanosheets arranged on the first side surface of the dielectric isolation pillar and in contact with the dielectric isolation pillar, An nFET device comprising a second plurality of channel nanosheets arranged on the second side surface of the dielectric isolation pillar and in contact with the dielectric isolation pillar, A first shallow trench isolation region is formed at least partially within the substrate along the first side surface of the first plurality of channel nanosheets, A second shallow trench isolation region is formed at least partially within the substrate along the first side surface of the second plurality of channel nanosheets and Includes, The second side surface of the first plurality of channel nanosheets extends from the first side surface of the dielectric isolation pillar, and the second side surface of the second plurality of channel nanosheets extends from the second side surface of the dielectric isolation pillar, A semiconductor structure in which the first plurality of channel nanosheets of the pFET device are offset perpendicularly to the second plurality of channel nanosheets of the nFET device.

11. The semiconductor structure according to claim 10, wherein the channel nanosheet of the pFET device comprises a first material, and the channel nanosheet of the nFET device comprises a second material different from the first material.

12. The semiconductor structure according to claim 11, wherein the first material comprises silicon germanium and the second material comprises silicon.

13. The semiconductor structure according to claim 10, wherein the pFET device comprises a first number of channel nanosheets, and the nFET device comprises a second number of channel nanosheets different from the first number.

14. The semiconductor structure according to claim 13, wherein the first number of channel nanosheets of the pFET device is greater than the second number of channel nanosheets of the nFET device.

15. The first device is formed on a semiconductor substrate, wherein the first device comprises a first plurality of nanosheets, and the first plurality of nanosheets comprises a first material that is p-type doped. The process involves forming a second device on the substrate, wherein the second device comprises a second plurality of nanosheets, and the second plurality of nanosheets comprises a second material that is n-type doped. A dielectric isolation pillar extending perpendicularly from the semiconductor substrate is formed between the first device and the second device. To form at least partially first shallow trench isolation regions within the substrate along the first side surfaces of the first plurality of nanosheets, and To form at least partially second shallow trench isolation regions within the substrate along the first side surfaces of the second plurality of nanosheets, Includes, The second surfaces of the first plurality of nanosheets extend from the first surfaces of the dielectric isolation pillar, and the second surfaces of the second plurality of nanosheets extend from the second surfaces of the dielectric isolation pillar, A method comprising arranging the first plurality of nanosheets in a positional displacement perpendicular to the second plurality of nanosheets.

16. The method according to claim 15, wherein the first material of the first plurality of nanosheets contains silicon germanium, and the second material of the second plurality of nanosheets contains silicon.

17. The method according to claim 15, comprising bringing each of the first plurality of nanosheets and the second plurality of nanosheets into contact with the dielectric isolation pillar, engaging with the dielectric isolation pillar, or partially embedding each of the dielectric isolation pillar.

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