Stacked structure, qubit device, method for manufacturing a stacked structure, and method for manufacturing a qubit device

Abstract

The layered structure is constructed by layering a sapphire substrate, an s-wave superconductor film, and a higher order topological insulator film. The sapphire substrate has, at a main surface, a step-and-terrace periodic structure in parallel to the [-12-10] direction. The s-wave superconductor film is a layered transition metal dichalcogenide film that is disposed on a surface of the sapphire substrate. The higher order topological insulator film is a layered transition metal dichalcogenide film that is disposed on the s-wave superconductor multilayer film.

Description

[Technical Field]

[0001] The disclosed technology relates to stacked structures and qubit devices. [Background technology]

[0002] The following technologies are known as technologies related to qubit devices. Patent document 1 describes a qubit circuit that includes a Majorana support containing a topological insulator layer and an s-wave superconductor layer in contact with the Majorana support.

[0003] Patent Document 2 describes a semiconductor device comprising a sapphire substrate whose main surface is inclined from the (0001) plane, a (0001) plane region partially provided on the sapphire substrate whose surface is the (0001) plane, and a layered chalcogenide film formed on the (0001) plane region. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] WO2022 / 137421 issue [Patent Document 2] Japanese Patent Publication No. 2017-128461 [Overview of the project] [Problems that the invention aims to solve]

[0005] Topological quantum computers have attracted attention in recent years. Topological quantum computers utilize Majorana quasiparticles, which follow non-Abelian statistics, as qubits. In quantum computers using Majorana quasiparticles, calculations are performed by the physical exchange of Majorana quasiparticle positions, a process called braiding. As a result, they have excellent noise immunity, and it is expected that practical quantum computing can be realized with minimal resources, even with the inclusion of redundant bits for error correction.

[0006] A hybrid structure combining a two-dimensional topological insulator and an s-wave superconductor has been proposed as a system in which Majorana quasiparticles are expected to appear (J. Alicea, Rep. Prog. Phys. 75, 076501 (2012)), and is being studied both theoretically and experimentally. A two-dimensional topological insulator has an insulator interior in a two-dimensional plane and a gapless helical channel encircling its edge. The helical channel is a one-dimensional conduction channel formed by up-spin electrons with positive momentum and down-spin electrons with negative momentum. By inducing a proximity effect in the helical channel with an s-wave superconductor and providing a ferromagnetic barrier, Majorana quasiparticles appear in the vicinity of the ferromagnetic barrier.

[0007] Recent studies have suggested that WTe2 multilayer films with a Td-type crystal structure are high-order topological insulators (Y.-B. Choi et al., Nat. Mater 19, 974 (2020)). Td-WTe2 multilayer films are chemically more stable than monolayer films and have the advantage of being easier to handle in the fabrication of qubit devices. In qubit devices using high-order topological insulators, in order to stably generate Majorana quasiparticles, it is important to control the crystal orientation of the high-order topological insulator to uniformly orient the helical channels formed on the b-axis edge of the high-order topological insulator.

[0008] The disclosed technology was developed in view of the above-mentioned points, and aims to stably generate Majorana quasiparticles in a laminated structure in which an s-wave superconductor and a higher-order topological insulator are stacked, by controlling the crystal orientation of the higher-order topological insulator. [Means for solving the problem]

[0009] The laminated structure relating to the disclosed technology comprises a sapphire substrate having a step-and-terrace periodic structure on its surface parallel to the [-12-10] direction, an s-wave superconductor film which is a layered first transition metal dichalcogenide film provided on the surface of the sapphire substrate, and a higher-order topological insulator film which is a layered second transition metal dichalcogenide film provided on the s-wave superconductor multilayer film. [Effects of the Invention]

[0010] According to the disclosed technology, in a laminated structure in which an s-wave superconductor and a higher-order topological insulator are stacked, the crystal orientation of the higher-order topological insulator can be controlled, and Majorana quasiparticles can be stably generated. [Brief explanation of the drawing]

[0011] [Figure 1] This is a perspective view showing an example of a conceptual structure of a qubit device according to an embodiment of the disclosed technology. [Figure 2A] This is a perspective view showing an example of the configuration of a laminated structure according to an embodiment of the disclosed technology. [Figure 2B] This is a cross-sectional view along the line 2B-2B in Figure 2A. [Figure 3A] This is a perspective view showing an example of the configuration of a sapphire substrate according to an embodiment of the disclosed technology. [Figure 3B] This is a cross-sectional view along the line 3B-3B in Figure 3A. [Figure 4A] The image on the left is a plan view of a sapphire substrate, and the image on the right shows the crystal structure of a 2H-NbSe2 multilayer film. [Figure 4B] The left image shows a cross-sectional view along the line 4B-4B in Figure 4A, and the right image shows the crystal structure of the 2H-NbSe2 multilayer film. [Figure 5A] The image on the left is a plan view of a sapphire substrate, and the image on the right shows the crystal structure of a Td-WTe2 multilayer film. [Figure 5B] The left image shows a cross-sectional view along the line 5B-5B in Figure 5A, and the right image shows the crystal structure of the Td-WTe2 multilayer film. [Figure 6A] It is a cross-sectional view showing an example of a method for manufacturing a laminated structure according to an embodiment of the disclosed technology. [Figure 6B] It is a cross-sectional view showing an example of a method for manufacturing a laminated structure according to an embodiment of the disclosed technology. [Figure 6C] It is a cross-sectional view showing an example of a method for manufacturing a laminated structure according to an embodiment of the disclosed technology. [Figure 7A] It is a plan view showing an example of the configuration of a quantum bit device according to an embodiment of the disclosed technology. [Figure 7B] It is a cross-sectional view taken along line 7B-7B in FIG. 7A. [Figure 7C] It is a cross-sectional view taken along line 7C-7C in FIG. 7A. [Figure 8A] It is a plan view showing an example of a method for manufacturing a quantum bit device according to an embodiment of the disclosed technology. [Figure 8B] It is a cross-sectional view taken along line 8B-8B in FIG. 8A. [Figure 8C] It is a cross-sectional view taken along line 8C-8C in FIG. 8A. [Figure 8D] It is a cross-sectional view showing an example of a method for manufacturing a quantum bit device according to an embodiment of the disclosed technology. [Figure 8E] It is a cross-sectional view showing an example of a method for manufacturing a quantum bit device according to an embodiment of the disclosed technology. [Embodiments for Carrying Out the Invention]

[0012] Hereinafter, an example of an embodiment of the disclosed technology will be described while referring to the drawings. In each drawing, the same or equivalent components and parts are given the same reference numerals, and redundant explanations are omitted.

[0013] [First Embodiment] Figure 1 is a perspective view showing an example of a conceptual structure of a qubit device 10 according to an embodiment of the disclosed technology. The qubit device 10 includes an s-wave superconductor multilayer 20 and a higher-order topological insulator multilayer 30. The s-wave superconductor multilayer 20 and the higher-order topological insulator multilayer 30 are each composed of layered transition metal dichalcogenides. The higher-order topological insulator multilayer 30 is typically a Td-WTe2 multilayer.

[0014] In the higher-order topological insulator multilayer film 30, helical channels 31, called hinge states, are formed at the edges in the b-axis direction (

[0010] ), as shown by the thick lines in Figure 1. The helical channels 31 are one-dimensional conduction channels formed by up-spin electrons with positive momentum and down-spin electrons with negative momentum. By inducing a proximity effect from the s-wave superconductor multilayer film 20 to the helical channels 31 of the higher-order topological insulator multilayer film 30, and by providing a ferromagnetic film 40 on the helical channels 31, Majorana quasiparticles γ appear in the vicinity of the ferromagnetic film 40.

[0015] In the qubit device 10, in order to stably generate Majorana quasiparticles, it is important to deposit a highly crystalline high-order topological insulator multilayer film 30 and control the crystal orientation of the high-order topological insulator multilayer film 30 to uniformly orient the helical channels 31. Uniform orientation of the helical channels 31 means that there is little variation in the direction in which the helical channels 31 are connected, and that the helical channels 31 are generally connected in a straight line. To achieve this, the substrate on which the high-order topological insulator multilayer film 30 is deposited must be free from lattice mismatch and impurity elements, and furthermore, there must be no non-essential chemical bonds between the high-order topological insulator multilayer film 30 and the substrate elements.

[0016] A technique for depositing WTe2, a candidate material for higher-order topological insulator multilayer films 30, on the surface of van der Waals layered materials having an inert surface (without dangling bonds), such as graphene, is known (LA Walsh et al., 2D Mater. 4, 025044 (2017)). However, when depositing WTe2 on the surface of graphene, it is difficult to control the crystal orientation of WTe2 (the direction of the b-axis helical channel 31) during layer deposition due to the symmetry of the crystal. In order to realize the stable expression of Majorana quasiparticles and enable their application to qubit devices, a technique is needed to deposit higher-order topological insulator multilayer films on s-wave superconductors of van der Waals layered materials with an inert surface, using heteroepitaxial growth while controlling the crystal orientation.

[0017] Figure 2A is a perspective view showing an example of the configuration of a laminated structure 11 according to an embodiment of the disclosed technology. Figure 2B is a cross-sectional view along the line 2B-2B in Figure 2A. The laminated structure 11 is a structure intended for application to a qubit device utilizing Majorana quasiparticles. The laminated structure 11 comprises a sapphire substrate 60, an s-wave superconductor multilayer film 20, and a higher-order topological insulator multilayer film 30. The s-wave superconductor multilayer film 20 is provided on the surface of the sapphire substrate 60, and the higher-order topological insulator multilayer film 30 is provided on the surface of the s-wave superconductor multilayer film 20.

[0018] Figure 3A is a perspective view showing an example of the configuration of a sapphire substrate 60. Figure 3B is a cross-sectional view along the line 3B-3B in Figure 3A. The sapphire substrate 60 is a substrate made of α-Al2O3 with the main surface being the c-plane. The sapphire substrate 60 is inclined in the [10-10] direction from the main surface, the (0001) plane, and has a step-and-terrace periodic structure parallel to the main surface in the [-12-10] direction. The step-and-terrace periodic structure being parallel to the [-12-10] direction means that the direction in which the steps of the step-and-terrace periodic structure are connected is in the [-12-10] direction. The step-and-terrace periodic structure can be obtained by cutting the sapphire substrate 60 at a predetermined miscut angle (for example, 0.3° to 10°).

[0019] The s-wave superconductor multilayer film 20 is deposited along the step-and-terrace periodic structure of the main surface of the sapphire substrate 60 by heteroepitaxial growth. The s-wave superconductor multilayer film 20 is a multilayer film consisting of layered transition metal dichalcogenides having a 2H-type crystal structure. For example, 2H-NbSe2 (space group: P63mmc, a=0.35nm, b=0.35nm, c=1.38nm) can be used as the material for the s-wave superconductor multilayer film 20. The number of layers in the s-wave superconductor multilayer film 20 is, for example, 20ML (monolayers). When the s-wave superconductor multilayer film 20 is composed of 2H-NbSe2, 1ML is approximately 0.7nm. It is also possible to use NbS2 or NbTe2 as the material for the s-wave superconductor multilayer film 20.

[0020] Figure 4A (left) is a plan view of a sapphire substrate 60 having a step-and-terrace periodic structure, viewed from the direction of the (0001) plane. Figure 4A (right) shows the crystal structure of a 2H-NbSe2 multilayer film 20A, an example of an s-wave superconductor multilayer film formed on the (0001) plane of the sapphire substrate 60, as viewed from the same line of sight as Figure 4A (left). Figure 4B (left) is a cross-sectional view along the line 4B-4B in Figure 4A (left). Figure 4B (right) shows the crystal structure of the 2H-NbSe2 multilayer film 20A as viewed from the same line of sight as Figure 4B (left). The

[0010] direction, which is the b-axis of the 2H-NbSe2 multilayer film 20A, is parallel to the [-12-10] direction, which is the direction in which the steps of the step-and-terrace periodic structure of the sapphire substrate 60 are connected. Furthermore, the

[0210] direction of the 2H-NbSe2 multilayer film 20A is parallel to the [10-10] direction, which is the direction in which the steps of the step-and-terrace periodic structure of the sapphire substrate 60 are aligned. Also, the

[0001] direction, which is the c-axis of the 2H-NbSe2 multilayer film 20A, is perpendicular to the (0001) plane, which is the main surface of the sapphire substrate 60. In this way, by depositing the s-wave superconductor multilayer film 20 on the surface of the sapphire substrate 60 having a step-and-terrace periodic structure using heteroepitaxial growth, it is possible to control the crystal orientation of the s-wave superconductor multilayer film 20.

[0021] The higher-order topological insulator multilayer film 30 is deposited on the surface of the s-wave superconductor multilayer film 20 by heteroepitaxial growth. Similar to the s-wave superconductor multilayer film 20, the higher-order topological insulator multilayer film 30 is deposited along the step-and-terrace periodic structure of the main surface of the sapphire substrate 60. The higher-order topological insulator multilayer film 30 is a multilayer film consisting of layered transition metal dichalcogenides having a Td-type crystal structure. For example, Td-WTe2 (space group: Pmm21, a=0.63nm, b=0.35nm, c=1.41nm) can be used as the material for the higher-order topological insulator multilayer film 30. The number of layers in the higher-order topological insulator multilayer film 30 is, for example, 5ML. When the higher-order topological insulator multilayer film 30 is composed of Td-WTe2, 1ML is approximately 0.7nm.

[0022] Figure 5A (left) is a plan view of a sapphire substrate 60 having a step-and-terrace periodic structure, viewed from the direction of the (0001) plane. Figure 5A (right) shows the crystal structure of a Td-WTe2 multilayer film 30A, an example of a higher-order topological insulator multilayer film formed on the (0001) plane of the sapphire substrate 60, when viewed from the same line of sight as Figure 5A (left). Figure 5B (left) is a cross-sectional view along the line 5B-5B in Figure 5A (left). Figure 5B (right) shows the crystal structure of the Td-WTe2 multilayer film 30A when viewed from the same line of sight as Figure 5B (left). The

[0010] direction, which is the b-axis of the Td-WTe2 multilayer film 30A, is parallel to the [-12-10] direction, which is the direction in which the steps of the step-and-terrace periodic structure of the sapphire substrate 60 are connected. Furthermore, the

[0100] direction, which is the a-axis of the Td-WTe2 multilayer film 30A, is parallel to the [10-10] direction, which is the direction in which the steps of the step-and-terrace periodic structure of the sapphire substrate 60 are aligned. Also, the

[0001] direction, which is the c-axis of the Td-WTe2 multilayer film 30A, is perpendicular to the (0001) plane, which is the main surface of the sapphire substrate 60. In this way, by depositing a higher-order topological insulator multilayer film 30 on a sapphire substrate 60 having a step-and-terrace periodic structure using heteroepitaxial growth, it is possible to control the crystal orientation of the higher-order topological insulator multilayer film 30.

[0023] The manufacturing method of the laminated structure 11 will be described below with reference to Figures 6A to 6C. First, a sapphire substrate 60 (α-Al2O3) is prepared, which is inclined in the [10-10] direction from the (0001) plane and has a step-and-terrace periodic structure on its main surface parallel to the [-12-10] direction (Figure 6A). The step-and-terrace periodic structure can be formed by cutting the sapphire substrate 60 at a predetermined miscut angle. The step height h and step width w can be controlled by the miscut angle. For example, by setting the miscut angle to 3°, a step-and-terrace periodic structure with a step height h of 1.3 nm and a step width w of 50 nm can be obtained. The miscut of the sapphire substrate 60 can be performed, for example, by CMP (Chemical Mechanical Polishing) or Ar ion milling. After miscutting, the sapphire substrate 60 is annealed for about 3 to 5 hours in air at approximately 1200°C or in an oxygen atmosphere at atmospheric pressure. After annealing, the sapphire substrate 60 is immersed in methanol for 20 to 30 minutes, and then rinsed with ultrapure water. These processes form a uniform step-and-terrace periodic structure on the main surface of the sapphire substrate 60. A uniform step-and-terrace periodic structure means that there is little variation in the direction of the steps, and the steps are generally arranged in a straight line.

[0024] Next, a multilayer s-wave superconductor film 20 made of layered transition metal dichalcogenides is formed on the main surface of the sapphire substrate 60 by heteroepitaxial growth (Figure 6B). The s-wave superconductor multilayer film 20 can be deposited using, for example, the MBE (Molecular Beam Epitaxy) method. Here, we will explain the case of depositing a 2H-NbSe2 multilayer film by the MBE method as an example.

[0025] 10 -8In an ultra-high vacuum chamber on the order of Pa, a sapphire substrate 60 is heated to 600°C while Nb is deposited on the surface of the sapphire substrate 60 by electron beam deposition, and Se is deposited on the surface of the sapphire substrate 60 by co-deposition using a K-cell type evaporator (heating temperature 180°C). The deposition rate of Nb is, for example, 0.1 Å / min, and the deposition rate of Se is, for example, 10 Å / min. The deposition time is adjusted so that the number of NbSe2 layers is, for example, about 20 ML. It is known that the superconducting critical temperature of 2H-NbSe2 increases with increasing number of layers. By setting the number of 2H-NbSe2 multilayer layers to about 20 ML, the superconducting critical temperature of the 2H-NbSe2 multilayer can be brought close to the superconducting critical temperature of NbSe2 bulk crystal, which is 7.2 K. After deposition of the 2H-NbSe2 multilayer, post-annealing is performed at 950°C for 30 minutes while continuing only Se deposition. This makes it possible to improve the crystallinity and surface roughness of the 2H-NbSe2 multilayer film at the atomic level. Furthermore, it is also possible to use PLD (Pulsed Laser Deposition) or sputtering as the deposition method for the s-wave superconductor multilayer film 20.

[0026] Next, a higher-order topological insulator multilayer film 30, consisting of layered transition metal dichalcogenides, is formed on the surface of the s-wave superconductor multilayer film by heteroepitaxial growth (Figure 6C). The higher-order topological insulator multilayer film 30 can be deposited, for example, using the MBE method. The s-wave superconductor multilayer film 20 and the higher-order topological insulator multilayer film 30 can be deposited sequentially in situ within the same vacuum chamber. Here, we will explain using the case of depositing a Td-WTe2 multilayer film by the MBE method as an example.

[0027] 10 -8In an ultra-high vacuum chamber on the order of Pa, a sapphire substrate 60 is heated to 325°C while W is deposited on the surface of the s-wave superconductor multilayer film 20 by electron beam deposition, and Te is deposited on the surface of the s-wave superconductor multilayer film 20 by co-deposition using a K-cell type evaporator (heating temperature 300°C). The deposition rate of W is, for example, 0.05 Å / min, and the deposition rate of Te is, for example, 10 Å / min. The deposition time is adjusted so that the number of WTe2 layers is, for example, about 5 ML. After the deposition of the Td-WTe2 multilayer film, post-annealing is performed at 400°C for 30 minutes while continuing only Te deposition. This improves the crystallinity and surface roughness inside the Td-WTe2 multilayer film at the atomic level. It is also possible to use the PLD method or sputtering method as the deposition method for the higher-order topological insulator multilayer film 30.

[0028] As described above, by sequentially depositing an s-wave superconductor multilayer film 20 and a higher-order topological insulator multilayer film 30 on the surface of a sapphire substrate 60 having a step-and-terrace structure on its main surface using heteroepitaxial growth, the crystal orientation of these multilayer films can be controlled. Specifically, the helical channels along the b-axis (

[0010] ) of the Td-WTe2 multilayer film can be oriented parallel to the [-12-10] direction, which is the direction in which the steps of the step-and-terrace periodic structure are connected.

[0029] According to the laminated structure 11 and its manufacturing method according to the embodiments of the disclosed technology, the orientation of the helical channels formed in the higher-order topological insulator multilayer film 30 reflects the step-and-terrace periodic structure formed in the sapphire substrate 60. This makes it possible to uniformly orient the helical channels formed in the higher-order topological insulator multilayer film 30, and when the laminated structure 11 is applied to a qubit device, Majorana quasiparticles can be stably expressed.

[0030] [Second Embodiment] Figure 7A is a plan view showing an example of the configuration of a qubit device 10 according to an embodiment of the disclosed technology. Figure 7B is a cross-sectional view along the line 7B-7B in Figure 7A. Figure 7C is a cross-sectional view along the line 7C-7C in Figure 7A.

[0031] The qubit device 10 comprises a stacked structure 11 according to a first embodiment of the disclosed technology. The qubit device 10 has three gates 70A, 70B, and 70C provided on the surface of a higher-order topological insulator multilayer film 30. Of these three gates, gates 70A and 70C are provided at positions that straddle two adjacent steps ST1 and ST2 of the step-and-terrace periodic structure of the sapphire substrate 60, respectively. Gate 70B is provided at a position that straddles the step ST1 between gates 70A and 70B. That is, gates 70A, 70B, and 70C are provided on helical channels formed along the steps of the step-and-terrace periodic structure of the sapphire substrate 60.

[0032] Gates 70A, 70B, and 70C are constructed by laminating a ferromagnetic film 71 and a conductive film 72, respectively. For example, Cr2Ga2Te6 can be used as the material for the ferromagnetic film 71. The ferromagnetic film 71 only needs to possess ferromagnetic and insulating properties, and a diluted magnetic semiconductor can also be used as the material for the ferromagnetic film 71. For example, gold (Au) can be used as the material for the conductive film 72. For example, other metals that have good adhesion to the ferromagnetic film 71 can also be used as the material for the conductive film 72.

[0033] The surface of the laminated structure 11 is covered with an insulating film 90. The insulating film 90 has openings 91 that expose the surfaces of gates 70A, 70B, and 70C. As the material for the insulating film 90, for example, HfO2, Al2O3, Si3N4, HfSiO, HfAlON, Y2O3, SrTiO3, PbZrTiO3, and BaTiO3 can be used.

[0034] The qubit device 10 has superconducting quantum interferometers (SQUIDs) 80A, 80B, and 80C, which are provided corresponding to gates 70A, 70B, and 70C. The superconducting quantum interferometers 80A, 80B, and 80C are each provided on the surface of the insulating film 90. Superconducting quantum interferometer 80A has a ring-shaped pattern surrounding gate 70A. Superconducting quantum interferometer 80B has a ring-shaped pattern surrounding gate 70B. Superconducting quantum interferometer 80C has a ring-shaped pattern surrounding gate 70C.

[0035] The superconducting quantum interferometers 80A, 80B, and 80C each have a lower electrode 81 made of a superconductor that occupies approximately half of the ring-shaped pattern, and an upper electrode 82 made of a superconductor that occupies the remaining area of ​​the ring-shaped pattern. The superconducting quantum interferometers 80A, 80B, and 80C each have a tunnel barrier layer 83 sandwiched between the upper electrode 82 and the lower electrode 81 at the connection point between these electrodes. In the superconducting quantum interferometers 80A, 80B, and 80C, a Josephson junction is formed by a superconductor-tunnel barrier layer-superconductor stacked structure. For example, Al can be used as the material for the lower electrode 81 and the upper electrode 82. For the tunnel barrier layer 83, AlO with a thickness of several nanometers can be used. X A film can be used. Nb or Pb can be used as the material for the lower electrode 81 and the upper electrode 82, and oxides of these can be used as the material for the tunnel barrier layer 83. Furthermore, copper oxide-based high-temperature superconductors can be used as the material for the lower electrode 81 and the upper electrode 82.

[0036] In the qubit device 10, the helical channels formed in the high-order topological insulator multilayer film 30 are oriented along the steps of the step-and-terrace structure of the sapphire substrate 60. By providing gates 70A, 70B, and 70C, each containing a ferromagnetic film 71, at positions that straddle the steps, four Majorana quasiparticles γ1, γ2, γ3, and γ4 can be generated near gates 70A, 70B, and 70C on the helical channels of the high-order topological insulator multilayer film 30. Braiding of Majorana quasiparticles can be performed by changing the electrostatic potential by applying voltage to gates 70A, 70B, and 70C. The exchange of Majorana quasiparticles γ1 and γ2 can be performed by applying voltage to gate 70A. The minute change in magnetic flux associated with the exchange of Majorana quasiparticles γ1 and γ2 can be detected as a minute change in voltage signal by the superconducting quantum interferometer 80A. The exchange of Majorana quasiparticles γ2 and γ3 can be performed by applying a voltage to gate 70B. The minute change in magnetic flux associated with the exchange of Majorana quasiparticles γ2 and γ3 can be detected as a minute change in voltage signal by the superconducting quantum interferometer 80B. The exchange of Majorana quasiparticles γ3 and γ4 can be performed by applying a voltage to gate 70C. The minute change in magnetic flux associated with the exchange of Majorana quasiparticles γ3 and γ4 can be detected as a minute change in voltage signal by the superconducting quantum interferometer 80C.

[0037] The manufacturing method of the qubit device 10 will be described below with reference to Figures 8A to 8E. Figure 8A is a plan view showing an example of a manufacturing method of the qubit device 10, Figure 8B is a cross-sectional view along the line 8B-8B in Figure 8A, and Figure 8C is a cross-sectional view along the line 8C-8C in Figure 8A. Figures 8D and 8E are cross-sectional views corresponding to Figure 8C, respectively.

[0038] First, the laminated structure 11 is fabricated by the method shown in Figures 6A to 6C. Next, gates 70A, 70B, and 70C are formed on the surface of the higher-order topological insulator multilayer film 30 at positions that span the steps of the step-and-terrace periodic structure of the sapphire substrate 60. Specifically, a mask (not shown) is formed on the surface of the laminated structure 11 for patterning gates 70A, 70B, and 70C by lift-off. The mask is formed, for example, by spin-coating an electron beam resist on the surface of the laminated structure 11 and then patterning it by electron beam lithography.

[0039] Next, a ferromagnetic film 71 and a conductive film 72 are sequentially formed on the surface of the laminated structure 11 via the mask using PLD. Here, we will explain using the case where Cr2Ga2Te6 is used as the material for the ferromagnetic film 71 and Au is used as the conductive film 72 as an example. In the deposition of Cr2Ga2Te6, the substrate temperature is 200°C and the laser energy density is 1.0 J / cm². 2 The laser irradiation frequency is set to 1 Hz, the substrate-target distance to 5 cm, the deposition rate to 1 nm / min, and the thickness of the Cr2Ga2Te6 to 50 nm. For Au deposition, the substrate temperature is room temperature, and the laser energy density is 1.0 J / cm². 2 The laser irradiation frequency is set to 5 Hz, the substrate-target distance to 5 cm, the deposition rate to 5 nm / min, and the thickness of Au to 30 nm. After the deposition of Cr2Ga2Te6 and Au, the Cr2Ga2Te6 and Au deposited on the mask are removed together with the mask to form gates 70A, 70B, and 70C (Figures 8A, 8B, and 8C).

[0040] By providing gates 70A, 70B, and 70C containing a ferromagnetic film 71 at positions that span steps, four Majorana quasiparticles γ1, γ2, γ3, and γ4 can be generated near gates 70A, 70B, and 70C on the helical channel.

[0041] Next, an insulating film 90 is formed to cover the entire surface of the laminated structure 11 (Figure 8D). Here, we will explain using the case where HfO2 is used as the material for the insulating film 90. The deposition of HfO2 can be carried out by ALD using tetrakis(dimethylamino)hafnium and H2O as precursors. The deposition temperature is, for example, 250°C.

[0042] Next, an opening 91 is formed in the insulating film 90 to expose the surfaces of gates 70A, 70B, and 70C. Specifically, a mask (not shown) for forming the opening 91 is formed by electron beam lithography, and the opening 91 is formed by etching the insulating film 90 through the mask using Ar ion milling. The beam acceleration voltage in Ar ion milling is, for example, 280V, and the beam current is, for example, 150mA.

[0043] Next, multiple superconducting quantum interferometers 80A, 80B, and 80C are formed on the surface of the insulating film 90, each containing a superconductor with a ring-shaped pattern surrounding gates 70A, 70B, and 70C (Figure 8E). The superconducting quantum interferometers 80A, 80B, and 80C are formed by sequentially forming a lower electrode 81, a tunnel barrier layer 83 (Figure 7B), and an upper electrode 82 on the surface of the insulating film 90 using electron lithography and lift-off. Here, Al is used as the material for the lower electrode 81 and the upper electrode 82, and AlO is used as the material for the tunnel barrier layer 83. X Let's explain using the example of using [this method].

[0044] A mask (not shown) is formed for patterning the lower electrode 81 by lift-off. The mask is formed, for example, by spin-coating an electron beam resist on the surface of the multilayer structure 11 and then patterning it by electron beam lithography. Next, Al, which constitutes the lower electrode 81, is deposited on the surface of the insulating film 90 via the mask by a vapor deposition method. In the Al deposition, the substrate temperature is set to room temperature, the deposition rate to 5 nm / min, and the film thickness to 50 nm. After Al deposition, the lower electrode 81 is formed by removing the Al deposited on the mask together with the mask.

[0045] Next, a mask (not shown) for patterning the tunnel barrier layer 83 by lift-off is formed. The mask is formed, for example, by spin-coating an electron beam resist on the surface of the stacked structure 11 and patterning this by electron beam lithography. Next, by vapor deposition, AlO that constitutes the tunnel barrier layer 83 is deposited on the surface of the lower electrode 81 through the above mask. X AlO X In the deposition of AlO, the substrate temperature is set to room temperature, the oxygen partial pressure in the vacuum chamber is 50 Pa, and the film thickness is set to 1 nm or more and 5 nm or less. After the deposition of AlO, X the AlO deposited on the mask is removed together with the mask, whereby the tunnel barrier layer 83 is formed. X

[0046] Next, a mask (not shown) for patterning the upper electrode 82 by lift-off is formed. The mask is formed, for example, by spin-coating an electron beam resist on the surface of the stacked structure 11 and patterning this by electron beam lithography. Next, by vapor deposition, Al that constitutes the upper electrode 82 is deposited on the surface of the insulator film 90 through the above mask. In the deposition of Al, the substrate temperature is set to room temperature, the film formation rate is 5 nm / min, and the film thickness is set to 50 nm. After the deposition of Al, the Al deposited on the mask is removed together with the mask, whereby the upper electrode 82 is formed.

[0047] Through the above steps, a quantum bit device 10 that utilizes Majorana quasiparticles that appear on the helical channel of the higher-order topological insulator multilayer film 30, which is oriented along the steps of the step-and-terrace structure of the sapphire substrate 60, is manufactured.

Explanation of Signs

[0048] 10 Quantum bit device 11 Stacked structure 20 s-wave superconductor multilayer film 30 Higher-order topological insulator multilayer film 31 Helical channel 40, 71 Ferromagnetic film 60 Sapphire substrates 70A, 70B, 70C gates 80A, 80B, 80C Superconducting Quantum Interferometer

Claims

1. A sapphire substrate having a step-and-terrace periodic structure parallel to the [-12-10] direction on its surface, A layered s-wave superconductor film, which is a first transition metal dichalcogenide film, is provided on the surface of the sapphire substrate. A higher-order topological insulating film is a layered second-order transition metal dichalcogenide film provided on the aforementioned s-wave superconductor film, A laminated structure having the following characteristics.

2. The s-wave superconductor film has a 2H-type crystal structure, and its [010] direction is parallel to the [-12-10] direction of the sapphire substrate. The aforementioned higher-order topological insulating film has a Td-type crystal structure, and its [010] direction is parallel to the [-12-10] direction of the sapphire substrate. The laminated structure according to claim 1.

3. The aforementioned s-wave superconductor film is NbSe ２ Membrane, NbTe ２ Membrane or NbS ２ It is a membrane, The aforementioned higher-order topological insulator film is WTe ２ It is a membrane. The laminated structure according to claim 2.

4. A sapphire substrate having a step-and-terrace periodic structure parallel to the [-12-10] direction on its surface, A layered first transition metal dichalcogenide film, which is an s-wave superconductor film, is provided on the surface of the sapphire substrate. A higher-order topological insulating film is a layered second-order transition metal dichalcogenide film provided on the aforementioned s-wave superconductor film, A plurality of gates are provided on the higher-order topological insulating film, at positions that span the steps of the step-and-terrace periodic structure of the sapphire substrate, and having a laminated structure of a ferromagnetic film and a conductive film, A plurality of superconducting quantum interferometers, each of which includes a superconductor surrounding one of the plurality of gates, A qubit device having a qubit.

5. A step of forming an s-wave superconductor film, which is a layered first transition metal dichalcogenide film, on the surface of a sapphire substrate having a step-and-terrace periodic structure parallel to the [-12-10] direction on its surface, The process involves forming a higher-order topological insulating film, which is a layered second-order transition metal dichalcogenide film, on the aforementioned s-wave superconductor film. A method for manufacturing a laminated structure including the above.

6. The s-wave superconductor film and the higher-order topological insulator film are formed by heteroepitaxial growth. The manufacturing method according to claim 5.

7. The formation of the s-wave superconductor film and the higher-order topological insulator film is carried out in the same vacuum chamber. The manufacturing method according to claim 6.

8. The step-and-terrace periodic structure is formed on the surface of the sapphire substrate by cutting the sapphire substrate at a predetermined miscut angle. The manufacturing method according to claim 5.

9. A step of forming an s-wave superconductor film, which is a layered first transition metal dichalcogenide film, on the surface of a sapphire substrate having a step-and-terrace periodic structure parallel to the [-12-10] direction on its surface, The process involves forming a higher-order topological insulating film, which is a layered second-order transition metal dichalcogenide film, on the aforementioned s-wave superconductor film. The process of forming a plurality of gates having a laminated structure of a ferromagnetic film and a conductive film on the higher-order topological insulating film, at positions that span the steps of the step-and-terrace periodic structure of the sapphire substrate, A step of forming a plurality of superconducting quantum interferometers, each of which includes a superconductor surrounding one of the plurality of gates, A method for manufacturing a qubit device that includes a qubit.

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