Differential amplifier, measuring instrument, and gain adjustment method

Abstract

To facilitate gain adjustment of a differential amplifier circuit while reducing the impact of pattern inductance between a buffer and the differential amplifier circuit.SOLUTION: A differential amplifier 110 includes: a pair of buffers to which separate signals are input; a first differential amplifier circuit 101 for amplifying a difference between output signals from the pair of buffers; a second differential amplifier circuit 102 for amplifying the difference between the output signals from the pair of buffers with a polarity opposite to the first differential amplifier circuit 101; a third differential amplifier circuit 103 for amplifying the difference between the output signals from the first differential amplifier circuit 101 and the second differential amplifier circuit 102; and damping resistors connected between each of branch points at which the output signals from the pair of buffers branch and each of the first differential amplifier circuit 101 and the second differential amplifier circuit 102.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present disclosure relates to a differential amplifier, a measuring instrument, and a gain adjustment method.

Background Art

[0002] Patent Document 1 discloses a differential amplifier having a high CMRR, a high input impedance, and a wide frequency band. "CMRR" is an abbreviation for common mode rejection ratio.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The copper foil pattern between the input buffer and the differential amplifier circuit behaves as an inductance in a high frequency region of 10 MHz or higher. This inductance component can sometimes cause overshoot or ringing.

[0005] An object of the present disclosure is to make it easy to adjust the gain of the differential amplifier circuit while reducing the influence of the pattern inductance between the buffer and the differential amplifier circuit.

Means for Solving the Problems

[0006] The differential amplifier, the measuring instrument, and the gain adjustment method according to some embodiments will be described below.

[0007] [1] A pair of buffers to which different signals are input, and A first differential amplifier circuit that amplifies the difference between the output signals from the pair of buffers, and A second differential amplifier circuit amplifies the difference between the output signals from the pair of buffers with the opposite polarity to that of the first differential amplifier circuit, A third differential amplifier circuit that amplifies the difference between the output signals from the first differential amplifier circuit and the second differential amplifier circuit, A damping resistor connected between the branching point where each of the output signals from the pair of buffers branches off and the first differential amplifier circuit and the second differential amplifier circuit, A differential amplifier equipped with the following features.

[0008] In such a differential amplifier, the influence of pattern inductance between the buffer and the differential amplifier circuit can be reduced, while also making it easier to adjust the gain of the differential amplifier circuit.

[0009] [2] The first pattern includes a first branching point, where the output signal from the first buffer included in the pair of buffers is branched at the first branching point and transmitted to the first differential amplifier circuit and the second differential amplifier circuit, respectively. The aforementioned branching point includes a second branching point, and the output signal from the second buffer included in the pair of buffers is branched at the second branching point and transmitted to the first differential amplifier circuit and the second differential amplifier circuit, respectively. Furthermore, The differential amplifier described in [1], wherein the damping resistors are inserted one by one between the first branch point of the first pattern and the first differential amplifier circuit, between the first branch point of the first pattern and the second differential amplifier circuit, between the second branch point of the second pattern and the first differential amplifier circuit, and between the second branch point of the second pattern and the second differential amplifier circuit.

[0010] In such a differential amplifier, the gain of the first differential amplifier circuit and the gain of the second differential amplifier circuit can be adjusted independently of each other, thus simplifying the adjustment of the differential amplifier circuit's gain.

[0011] [3] A measuring instrument equipped with the differential amplifier described in [1] or [2].

[0012] Such measuring instruments can incorporate differential amplifiers with high CMRR, high input impedance, wide frequency bandwidth, and high layout flexibility.

[0013] [4] A differential amplifier comprising a pair of buffers into which separate signals are input, a first differential amplifier circuit that amplifies the difference between the output signals from the pair of buffers, a second differential amplifier circuit that amplifies the difference between the output signals from the pair of buffers with the opposite polarity to the first differential amplifier circuit, a third differential amplifier circuit that amplifies the difference between the output signals from the first differential amplifier circuit and the second differential amplifier circuit, and damping resistors connected between the branching point where each of the output signals from the pair of buffers branches and the first differential amplifier circuit and the second differential amplifier circuit, wherein the gain of the first differential amplifier circuit is adjusted. The gain of the second differential amplifier circuit of the differential amplifier is adjusted independently of the gain of the first differential amplifier circuit. A gain adjustment method that includes this.

[0014] In this type of gain adjustment method, the influence of pattern inductance between the buffer and the differential amplifier circuit can be reduced while making it easier to adjust the gain of the differential amplifier circuit.

[0015] [5] The differential amplifier is The first pattern includes a first branching point, where the output signal from the first buffer included in the pair of buffers is branched at the first branching point and transmitted to the first differential amplifier circuit and the second differential amplifier circuit, respectively. The aforementioned branching point includes a second branching point, and the output signal from the second buffer included in the pair of buffers is branched at the second branching point and transmitted to the first differential amplifier circuit and the second differential amplifier circuit, respectively. Furthermore, The damping resistors are inserted one by one between the first branch point of the first pattern and the first differential amplifier circuit, between the first branch point of the first pattern and the second differential amplifier circuit, between the second branch point of the second pattern and the first differential amplifier circuit, and between the second branch point of the second pattern and the second differential amplifier circuit [4] The gain adjustment method described.

[0016] In such a gain adjustment method, the adjustment of the gain of the differential amplifier circuit is simplified.

Effect of the Invention

[0017] According to the present disclosure, while reducing the influence of the pattern inductance between the buffer and the differential amplifier circuit, the gain of the differential amplifier circuit can be easily adjusted.

Brief Description of the Drawings

[0018] [Figure 1] It is a circuit diagram showing the configuration of a differential amplifier according to the first embodiment of the present disclosure. <了 [Figure 2] It is a circuit diagram showing a simulation example of a differential amplifier according to the first embodiment of the present disclosure. [Figure 3] It is a graph showing the simulation result corresponding to FIG. 2. [Figure 4] It is a graph showing the simulation result corresponding to FIG. 2. [Figure 5] It is a circuit diagram showing the configuration of a differential amplifier according to the second embodiment of the present disclosure. [Figure 6] It is a circuit diagram showing a simulation example of a differential amplifier according to the second embodiment of the present disclosure. [Figure 7] It is a graph showing the simulation result corresponding to FIG. 6. [Figure 8] It is a graph showing the simulation result corresponding to FIG. 6. [Figure 9] It is a flowchart showing the gain adjustment method according to the second embodiment of the present disclosure. [Figure 10]This figure shows an example of a combination of a differential amplifier and an attenuator according to the second embodiment of this disclosure. [Figure 11] This figure shows an example of a differential amplifier and sensor combined according to the second embodiment of this disclosure. [Figure 12] This is a schematic diagram showing the configuration of a differential amplifier in a comparative example. [Figure 13] This is a circuit diagram showing the configuration of a differential amplifier in a comparative example. [Modes for carrying out the invention]

[0019] The following comparative examples will be explained with reference to the figures.

[0020] Referring to Figure 12, the configuration of the differential amplifier 900 in the comparative example will be explained.

[0021] The differential amplifier 900 comprises a first differential amplifier circuit 901, a second differential amplifier circuit 902, and a third differential amplifier circuit 903, as well as a pair of buffers including a first buffer 904 and a second buffer 905. The differential amplifier 900 further comprises a pair of input terminals including a first input terminal IN1 and a second input terminal IN2, and an output terminal OUT.

[0022] A signal is input to the first buffer 904 via the first input terminal IN1. A signal is input to the second buffer 905 via the second input terminal IN2. In other words, separate signals are input to the first buffer 904 and the second buffer 905. The first differential amplifier circuit 901 amplifies the difference between the output signals from the first buffer 904 and the second buffer 905. The second differential amplifier circuit 902 amplifies the difference between the output signals from the first buffer 904 and the second buffer 905 with the opposite polarity to that of the first differential amplifier circuit 901. The third differential amplifier circuit 903 amplifies the difference between the output signals from the first differential amplifier circuit 901 and the second differential amplifier circuit 902. The third differential amplifier circuit 903 outputs the amplified signal via the output terminal OUT.

[0023] The differential amplifier 900 has a configuration in which two differential amplifier circuits are connected in stages. The first differential amplifier circuit, the first differential amplifier circuit 901, suppresses common-mode signals due to its inherent CMRR characteristics. Similarly, the second differential amplifier circuit 902, also the first differential amplifier circuit, suppresses common-mode signals due to its inherent CMRR characteristics. Therefore, the signal input to the third differential amplifier circuit 903, the second differential amplifier circuit, is a signal from which common-mode signals have been suppressed by the first differential amplifier circuits, the first differential amplifier circuit 901 and the second differential amplifier circuit 902. The third differential amplifier circuit 903 further suppresses common-mode signals in this input signal, which has had common-mode signals suppressed, due to its inherent CMRR characteristics. As a result, the differential amplifier 900 has a high CMRR.

[0024] The differential amplifier 900 further comprises a first pattern P1 and a second pattern P2. The first pattern P1 includes a first branch point B1. The second pattern P2 includes a second branch point B2.

[0025] In the first pattern P1, the output signal from the first buffer 904 is branched at the first branch point B1 and transmitted to the first differential amplifier circuit 901 and the second differential amplifier circuit 902, respectively. In the second pattern P2, the output signal from the second buffer 905 is branched at the second branch point B2 and transmitted to the first differential amplifier circuit 901 and the second differential amplifier circuit 902, respectively.

[0026] Referring to Figure 13, the configuration of the differential amplifier 900 in the comparative example will be further explained.

[0027] The first buffer 904 and the second buffer 905 are voltage follower circuits. The first buffer 904 includes an operational amplifier U1. The second buffer 905 includes an operational amplifier U2.

[0028] The non-inverting input terminal of operational amplifier U1 is connected to the first input terminal IN1. The inverting input terminal of operational amplifier U1 is connected to the output terminal of operational amplifier U1 and the first pattern P1. In other words, the first buffer 904 has a negative feedback configuration that returns the output of operational amplifier U1 to the inverting input terminal of operational amplifier U2.

[0029] The non-inverting input terminal of operational amplifier U2 is connected to the second input terminal IN2. The inverting input terminal of operational amplifier U2 is connected to the output terminal of operational amplifier U2 and the second pattern P2. In other words, the second buffer 905 has a negative feedback configuration that returns the output of operational amplifier U2 to the inverting input terminal of operational amplifier U2.

[0030] The first differential amplifier circuit 901 comprises an operational amplifier AMP1 and four resistors R1, R2, R3, and R4. The second differential amplifier circuit 902 comprises an operational amplifier AMP2 and four resistors R5, R6, R7, and R8. The second differential amplifier circuit 903 comprises an operational amplifier AMP3 and four resistors R9, R10, R11, and R12.

[0031] One end of resistor R1 is connected to the first pattern P1. The other end of resistor R1 is connected to one end of resistor R2 and to the inverting input terminal of op-amp AMP1. One end of resistor R2 is connected to the other end of resistor R1 and to the inverting input terminal of op-amp AMP1. The other end of resistor R2 is connected to the output terminal of op-amp AMP1 and to one end of resistor R9. One end of resistor R3 is connected to the second pattern P2. The other end of resistor R3 is connected to one end of resistor R4 and to the non-inverting input terminal of op-amp AMP1. One end of resistor R4 is connected to the other end of resistor R3 and to the non-inverting input terminal of op-amp AMP1. The other end of resistor R4 is connected to ground. In other words, the first differential amplifier circuit 901 has a negative feedback configuration in which the output of op-amp AMP1 is returned to the inverting input terminal of op-amp AMP1 by resistor R2.

[0032] One end of resistor R5 is connected to the second pattern P2. The other end of resistor R5 is connected to one end of resistor R6 and to the inverting input terminal of op-amp AMP2. One end of resistor R6 is connected to the other end of resistor R5 and to the inverting input terminal of op-amp AMP2. The other end of resistor R6 is connected to the output terminal of op-amp AMP2 and to one end of resistor R11. One end of resistor R7 is connected to the first pattern P1. The other end of resistor R7 is connected to one end of resistor R8 and to the non-inverting input terminal of op-amp AMP2. One end of resistor R8 is connected to the other end of resistor R7 and to the non-inverting input terminal of op-amp AMP2. The other end of resistor R8 is connected to ground. In other words, the second differential amplifier circuit 902 has a negative feedback configuration in which the output of op-amp AMP2 is returned to the inverting input terminal of op-amp AMP2 by resistor R6.

[0033] One end of resistor R9 is connected to the other end of resistor R2 and to the output terminal of op-amp AMP1. The other end of resistor R9 is connected to one end of resistor R10 and to the inverting input terminal of op-amp AMP3. One end of resistor R10 is connected to the other end of resistor R9 and to the inverting input terminal of op-amp AMP3. The other end of resistor R10 is connected to the output terminal OUT of op-amp AMP3 and to the output terminal OUT. One end of resistor R11 is connected to the other end of resistor R6 and to the output terminal of op-amp AMP2. The other end of resistor R11 is connected to one end of resistor R12 and to the non-inverting input terminal of op-amp AMP3. One end of resistor R12 is connected to the other end of resistor R11 and to the non-inverting input terminal of op-amp AMP3. The other end of resistor R12 is connected to ground. In other words, the third differential amplifier circuit 903 has a negative feedback configuration in which the output of the operational amplifier AMP3 is returned to the inverting input terminal of the operational amplifier AMP3 by resistor R10.

[0034] To widen the frequency bandwidth of the first differential amplifier circuit 901, it is necessary to reduce the resistor R2, and consequently, resistors R1, R3, and R4 must also be reduced. This reduces the input impedance of the first differential amplifier circuit 901. The second differential amplifier circuit 902 has the same configuration as the first differential amplifier circuit 901, so the same applies to the input impedance of the second differential amplifier circuit 902. However, since the differential amplifier 900 is equipped with a first buffer 904 and a second buffer 905 before the first differential amplifier circuit 901 and the second differential amplifier circuit 902, the input impedance of the differential amplifier 900 is high even if the input impedances of the first differential amplifier circuit 901 and the second differential amplifier circuit 902 are low. Therefore, the differential amplifier 900 can achieve both high input impedance and a wide frequency bandwidth.

[0035] As described above, the differential amplifier 900 is equipped with a high-impedance buffer at its input stage, which minimizes the impact on the object being measured when applied to measuring instruments such as probes. The differential amplifier 900 has a structure in which two differential amplifier circuits are stacked in the amplification stage, and when the common-mode gains of the first-stage operational amplifiers AMP1 and AMP2 are equal, the output becomes 0 when a common-mode signal is input. The overall CMRR obtained in this case is the sum of the CMRR of operational amplifier AMP1 and the CMRR of operational amplifier AMP3, or the sum of the CMRR of operational amplifier AMP2 and the CMRR of operational amplifier AMP3, and a good value is obtained.

[0036] In the configuration shown in Figure 13, if resistors R1, R3, R5, and R7 are adjustable resistors, the gain can be set in the first-stage differential amplifier circuit. High CMRR characteristics can be obtained by matching the gain characteristics of op-amp AMP1 and op-amp AMP2. However, if precise gain adjustment in the first-stage differential amplifier circuit is not required and only high CMRR characteristics are needed, for example, resistor R1 may be a fixed resistor and resistors R3, R5, and R7 may be variable resistors. That is, a combination of one fixed resistor and three variable resistors may be used to match the gain characteristics of op-amp AMP2 to the gain characteristics of op-amp AMP1.

[0037] The first pattern P1 and the second pattern P2 behave as inductance in the high-frequency range above 10 MHz. This inductance component can sometimes cause overshoot or ringing. Inserting a damping resistor into the signal line is an effective countermeasure against overshoot and ringing.

[0038] Several embodiments of this disclosure will be described below with reference to the figures.

[0039] In each figure, identical or corresponding parts are denoted by the same reference numerals. In the description of each embodiment, the description of identical or corresponding parts will be omitted or simplified as appropriate.

[0040] Referring to Figure 1, the configuration of the differential amplifier 100 according to the first embodiment will be explained, mainly focusing on the differences from the configuration of the differential amplifier 900 in the comparative example.

[0041] The differential amplifier 100 includes a first differential amplifier circuit 101, a second differential amplifier circuit 102, and a third differential amplifier circuit 103, as well as a pair of buffers including a first buffer 104 and a second buffer 105. The configuration and function of the first differential amplifier circuit 101, the second differential amplifier circuit 102, the third differential amplifier circuit 103, the first buffer 104, and the second buffer 105 are the same as those of the first differential amplifier circuit 901, the second differential amplifier circuit 902, the third differential amplifier circuit 903, the first buffer 904, and the second buffer 905 shown in Figure 13.

[0042] The differential amplifier 100 further includes damping resistors RD1 and RD2.

[0043] Damping resistors RD1 and RD2 are connected between the first buffer 104 and the second buffer 105, respectively, and the first differential amplifier circuit 101 and the second differential amplifier circuit 102, respectively. Specifically, damping resistor RD1 is inserted between the first buffer 104 and the first branch point B1 of the first pattern P1. Damping resistor RD2 is inserted between the second buffer 105 and the second branch point B2 of the second pattern P2.

[0044] As described above, in this embodiment, a damping resistor is inserted between the buffer and the first-stage differential amplifier. Therefore, the influence of pattern inductance between the buffer and the differential amplifier circuit can be reduced. As a result, overshoot and ringing can be prevented.

[0045] However, in the circuit shown in Figure 1, if we focus on the current output from op-amp U1, the current flowing through damping resistor RD1 is divided and flows into resistor R1, which connects damping resistor RD1 to the inverting input terminal of op-amp AMP1, and resistor R7, which connects damping resistor RD1 to the non-inverting input terminal of op-amp AMP2. If the resistance value of resistor R1 is changed to adjust the gain of op-amp AMP1, the current flowing into resistor R7 will change simultaneously, causing an unintended gain change in op-amp AMP2. As an example, a simulation circuit is shown in Figure 2, and the corresponding simulation results are shown in Figures 3 and 4. With the resistance values ​​of resistors R3, R5, and R7 fixed, if the resistance value of resistor R1 is changed by 20Ω to adjust the gain of op-amp AMP1, the output of op-amp AMP2 will shift by about 10mV. Due to the symmetry of the circuit, a similar shift in op-amp AMP1 occurs when adjusting the gain of op-amp AMP2. Due to the mutual influence between op-amp AMP1 and op-amp AMP2 during gain adjustment, it is necessary to repeatedly switch between op-amps AMP1 and AMP2 to match the gain characteristics. Therefore, adjusting the gain of the differential amplifier circuit becomes complex.

[0046] Referring to Figure 5, the configuration of the differential amplifier 110 according to the second embodiment will be explained, mainly focusing on the differences from the configuration of the differential amplifier 100 according to the first embodiment.

[0047] The differential amplifier 100 is equipped with damping resistors RD11, RD12, RD21, and RD22 instead of damping resistors RD1 and RD2.

[0048] Damping resistors RD11, RD12, RD21, and RD22 are connected between the branching points where the output signals from the first buffer 104 and the second buffer 105 each branch off, and the first differential amplifier circuit 101 and the second differential amplifier circuit 102, respectively. Specifically, damping resistor RD11 is inserted between the first branching point B1 of the first pattern P1 and the first differential amplifier circuit 101. Damping resistor RD12 is inserted between the first branching point B1 of the first pattern P1 and the second differential amplifier circuit 102. Damping resistor RD21 is inserted between the second branching point B2 of the second pattern P2 and the first differential amplifier circuit 101. Damping resistor RD22 is inserted between the second branching point B2 of the second pattern P2 and the second differential amplifier circuit 102.

[0049] As described above, in this embodiment, instead of inserting only one damping resistor immediately after the buffer, i.e., before the pattern branch, as in the first embodiment, one damping resistor is inserted for each branch after the pattern branch. In the first embodiment, damping resistors RD1 and RD2 form a common impedance that determines the gain of op-amps AMP1 and AMP2, respectively. As a result, adjusting the gain of one differential amplifier circuit affects the gain of the other differential amplifier circuit. In contrast, in this embodiment, by inserting damping resistors RD11 and RD12 into each branch of the first pattern P1 and damping resistors RD21 and RD22 into each branch of the second pattern P2, it is prevented that damping resistors RD11, RD12, RD21, and RD22 form a common impedance that determines the gain of op-amps AMP1 and AMP2, respectively. In other words, it is possible to circuit-isolate op-amps AMP1 and AMP2.

[0050] Therefore, according to this embodiment, in a high CMRR differential amplifier 110 equipped with a high input impedance buffer, the influence of pattern inductance between the buffer and the differential amplifier circuit is reduced, and the gains of the two first-stage differential amplifier circuits can be adjusted independently, making it easier to adjust the CMRR of the differential amplifier 110. As an example, a simulation circuit is shown in Figure 6, and the corresponding simulation results are shown in Figures 7 and 8. With the resistance values ​​of resistors R3, R5, and R7 fixed, even when the resistance value of resistor R1 is varied by 20Ω to adjust the gain of op-amp AMP1, no fluctuation is observed in the output of op-amp AMP2. In the examples shown in Figures 2 to 4, the fluctuation in the output of op-amp AMP2 is about 10mV, whereas in the examples shown in Figures 6 to 8, the fluctuation in the output of op-amp AMP2 is a very small value of 1uV or less. In this embodiment, since the gains of operational amplifiers AMP1 and AMP2 can be adjusted independently, the adjustment of the first-stage differential amplifier circuit can be completed in just two steps: for example, adjusting the gain of operational amplifier AMP1, and then adjusting the gain of operational amplifier AMP2. This eliminates the need to repeatedly adjust the gain characteristics by switching back and forth between operational amplifiers AMP1 and AMP2, as in the first embodiment. Therefore, the adjustment of the differential amplifier circuit gain becomes simpler.

[0051] The gain adjustment method according to this embodiment will be described with reference to Figure 9.

[0052] In step S1, the gain of the first differential amplifier circuit 101 is adjusted. Then, in step S2, the gain of the second differential amplifier circuit 102 is adjusted independently of the gain of the first differential amplifier circuit 101. Steps S1 and S2 may be performed in the reverse order.

[0053] The differential amplifier 110 can be applied to the amplification section of measuring instruments such as probes or sensors. In particular, the differential amplifier 110 can be used as a differential input / single output circuit for measuring instruments requiring high CMRR, such as differential probes or voltage dividers, or for differential output type sensors such as Hall element magnetic sensors, current sensors, or strain sensors.

[0054] As an example of application, Figure 10 shows a circuit combining a differential amplifier 110 and an attenuator 200. This example allows for the realization of a high CMRR differential amplifier with an arbitrary attenuation ratio. Here, by branching each buffer output after the buffer output and then inserting a damping resistor, overshoot and ringing caused by the pattern inductance between the buffer and the differential amplifier can be suppressed. This provides a flat frequency response over a wide bandwidth while also allowing for easy adjustment of the amplification section, such as providing a measuring instrument like a probe. By selecting the value of the damping resistor to match the pattern length between the buffer and the differential amplifier circuit, the pattern length can be extended, easing constraints on board layout. For example, the value of the damping resistor can be increased as the pattern length is extended.

[0055] As another application example, Figure 11 shows a circuit combining a differential amplifier 110 and a differential output type sensor 300. In this example, similar to the example shown in Figure 10, the occurrence of resonance caused by the pattern inductance between the buffer and the differential amplifier can be suppressed, the amplification section can be adjusted more easily, and an expansion of the flat frequency band and increased flexibility in board layout can be expected.

[0056] This disclosure is not limited to the embodiments described above. For example, two or more blocks shown in the block diagram may be combined, or one block may be divided. Instead of executing two or more steps shown in the flowchart in chronological order as described, they may be executed in parallel or in a different order, depending on the processing capacity of the device performing each step, or as necessary. Other modifications are possible without departing from the spirit of this disclosure. [Explanation of Symbols]

[0057] 100, 110, 900 differential amplifier 101,901 First differential amplifier circuit 102,902 Second differential amplifier circuit 103,903 Third differential amplifier circuit 104,904 Buffer 1 105,905 Second buffer 200 Attenuator 300 sensors

Claims

1. A pair of buffers into which separate signals are input, A first differential amplifier circuit that amplifies the difference between the output signals from the pair of buffers, A second differential amplifier circuit amplifies the difference between the output signals from the pair of buffers with the opposite polarity to that of the first differential amplifier circuit, A third differential amplifier circuit that amplifies the difference between the output signals from the first differential amplifier circuit and the second differential amplifier circuit, A damping resistor connected between the branching point where each of the output signals from the pair of buffers branches off and the first differential amplifier circuit and the second differential amplifier circuit, Equipped with, Each of the first differential amplifier circuit and the second differential amplifier circuit includes at least one variable resistor, and the gain is adjusted by adjusting the resistance value of the at least one variable resistor. The damping resistor is inserted between a first branch point where the output signal from the first buffer included in the pair of buffers branches off and the first differential amplifier circuit, between the first branch point and the second differential amplifier circuit, between the second branch point where the output signal from the second buffer included in the pair of buffers branches off and the first differential amplifier circuit, and between the second branch point and the second differential amplifier circuit in each of these differential amplifiers.

2. A first pattern includes the first branching point, and the output signal from the first buffer is branched at the first branching point and transmitted to the first differential amplifier circuit and the second differential amplifier circuit, A second pattern includes the second branching point, and the output signal from the second buffer is branched at the second branching point and transmitted to the first differential amplifier circuit and the second differential amplifier circuit, respectively. Furthermore, Each of the first differential amplifier circuit and the second differential amplifier circuit includes, as the at least one variable resistor, a variable resistor connected to the first branch point and a variable resistor connected to the second branch point. The differential amplifier according to claim 1, wherein the damping resistor is inserted one at a time between the first branch point and the variable resistor connected to the first branch point of the first differential amplifier circuit, between the first branch point and the variable resistor connected to the first branch point of the second differential amplifier circuit, between the second branch point and the variable resistor connected to the second branch point of the first differential amplifier circuit, and between the second branch point and the variable resistor connected to the second branch point of the second differential amplifier circuit.

3. A measuring instrument comprising a differential amplifier according to claim 1 or claim 2.

4. A differential amplifier comprising a pair of buffers into which separate signals are input, a first differential amplifier circuit that amplifies the difference between the output signals from the pair of buffers, a second differential amplifier circuit that amplifies the difference between the output signals from the pair of buffers with the opposite polarity to that of the first differential amplifier circuit, a third differential amplifier circuit that amplifies the difference between the output signals from the first differential amplifier circuit and the second differential amplifier circuit, and damping resistors connected between the branching point where each of the output signals from the pair of buffers branches and each of the first differential amplifier circuit and the second differential amplifier circuit, and adjusting the gain of the first differential amplifier circuit of the differential amplifier, The gain of the second differential amplifier circuit of the differential amplifier is adjusted independently of the gain of the first differential amplifier circuit. Includes, Each of the first differential amplifier circuit and the second differential amplifier circuit includes at least one variable resistor, and the gain is adjusted by adjusting the resistance value of the at least one variable resistor. A gain adjustment method in which the damping resistor is inserted between a first branch point where the output signal from the first buffer included in the pair of buffers branches off and the first differential amplifier circuit, between the first branch point and the second differential amplifier circuit, between the second branch point where the output signal from the second buffer included in the pair of buffers branches off and the first differential amplifier circuit, and between the second branch point and the second differential amplifier circuit.

5. The differential amplifier is A first pattern includes the first branching point, and the output signal from the first buffer is branched at the first branching point and transmitted to the first differential amplifier circuit and the second differential amplifier circuit, A second pattern includes the second branching point, and the output signal from the second buffer is branched at the second branching point and transmitted to the first differential amplifier circuit and the second differential amplifier circuit, respectively. Furthermore, Each of the first differential amplifier circuit and the second differential amplifier circuit includes, as the at least one variable resistor, a variable resistor connected to the first branch point and a variable resistor connected to the second branch point. The gain adjustment method according to claim 4, wherein the damping resistor is inserted one by one between the first branch point and the variable resistor connected to the first branch point of the first differential amplifier circuit, between the first branch point and the variable resistor connected to the first branch point of the second differential amplifier circuit, between the second branch point and the variable resistor connected to the second branch point of the first differential amplifier circuit, and between the second branch point and the variable resistor connected to the second branch point of the second differential amplifier circuit.

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