Semiconductor device

Abstract

This semiconductor device comprises: first and second conductive plates that are spaced apart from each other in a direction x; a third conductive plate that faces the first and second conductive plates in a direction z; a first semiconductor element that is disposed between the first conductive plate and the third conductive plate; a second semiconductor element that is disposed between the second conductive plate and the third conductive plate; a positive-electrode input terminal that is electrically connected to the first conductive plate; a negative-electrode input terminal that is electrically connected to the second conductive plate; an output terminal that is electrically connected to the third conductive plate; and an encapsulation resin that covers at least the first and second semiconductor elements.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Various configurations have been proposed for semiconductor devices including semiconductor elements. Patent Document 1 discloses an example of a conventional semiconductor device. The semiconductor device disclosed in this document includes leads, two semiconductor elements, and a sealing resin. The two semiconductor elements are transistors each having a switching function and are mounted on the leads. The sealing resin covers a portion of the leads and the two semiconductor elements. The back surfaces of the leads (the surfaces opposite to the mounting surfaces of the semiconductor elements) are exposed from the sealing resin. This configuration allows heat generated in each semiconductor element to be dissipated from the back surfaces of the leads via the leads. In such a semiconductor device, two semiconductor elements are mounted on the leads. This can cause, for example, heat transferred from the two semiconductor elements to interfere with each other in the leads, resulting in reduced heat dissipation.

[0003] Japanese Patent Application Laid-Open No. 2020-47758

[0004] The present disclosure has been made in light of the above circumstances, and an object of the present disclosure is to provide a semiconductor device suitable for improving heat dissipation.

[0005] The semiconductor device provided by the present disclosure includes a first conductive plate having a first main surface facing one side in a thickness direction and a first back surface facing the other side, a second conductive plate having a second main surface facing one side in the thickness direction and a second back surface facing the other side, and spaced apart from the first conductive plate in a first direction perpendicular to the thickness direction, a third conductive plate having a third main surface facing the other side in the thickness direction and facing the first main surface and the second main surface, and a third back surface facing one side in the thickness direction, and spaced apart from the first conductive plate and the second conductive plate on one side in the thickness direction, and a third conductive plate having a second main surface facing the other side in the thickness direction and facing the first main surface and the second main surface, and a third back surface facing one side in the thickness direction, and spaced apart from the first conductive plate and the second conductive plate on one side in the thickness direction, and the third main surface and having a switching function; a second semiconductor element arranged between the third main surface and the second main surface in the thickness direction and having a switching function; a first input terminal that is conductive to the first conductive plate and has a positive electrode; a second input terminal that is conductive to the second conductive plate and has a negative electrode; an output terminal that is conductive to the third conductive plate; and a sealing resin that covers at least a portion of each of the first conductive plate, the second conductive plate, and the third conductive plate, a portion of each of the first input terminal, the second input terminal, and the output terminal, the first semiconductor element, and the second semiconductor element.

[0006] According to the semiconductor device of the present disclosure, heat dissipation can be improved.

[0007] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0008] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a perspective view (transparent to the sealing resin) showing the semiconductor device according to the first embodiment of the present disclosure. FIG. 3 is a plan view (transparent to the sealing resin) of the semiconductor device shown in FIG. 1. FIG. 4 is a front view of the semiconductor device shown in FIG. 1. FIG. 5 is a plan view (transparent to the sealing resin, omitting the third conductive plate and the second semiconductor element) of the semiconductor device shown in FIG. 1. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 3. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 3. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 3. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 3. FIG. 10 is a partially enlarged view of FIG. 6. FIG. 11 is a partially enlarged view of FIG. 6. FIG. 12 is an example of a circuit configuration of a semiconductor device according to a first embodiment of the present disclosure. FIG. 13 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present disclosure. FIG. 14 is a cross-sectional view showing a semiconductor device according to a third embodiment of the present disclosure. FIG. 15 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present disclosure. FIG. 16 is a cross-sectional view showing a semiconductor device according to a fifth embodiment of the present disclosure. FIG. 17 is a plan view (transparent to the sealing resin) showing a semiconductor device according to a sixth embodiment of the present disclosure. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 17. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 17. FIG. 20 is a plan view (transparent to the sealing resin) showing a semiconductor device according to a seventh embodiment of the present disclosure. FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 20. FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 20. FIG. 23 is a plan view (transparent to the sealing resin) showing a semiconductor device according to an eighth embodiment of the present disclosure.

[0009] Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0010] Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not necessarily intended to dictate any ordering of their objects.

[0011] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B with a certain object A in contact with the certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "an object A overlaps an object B when viewed from a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B."

[0012] 1 to 12 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A1 according to this embodiment includes a first conductive plate 1, a second conductive plate 2, a third conductive plate 3, a first semiconductor element 41, a second semiconductor element 42, a first input terminal 51, a second input terminal 52, an output terminal 53, first control terminals 55 and 56, second control terminals 57 and 58, a first conductive bonding material 61, a second conductive bonding material 62, a first metal portion 63, a second metal portion 64, and a sealing resin 7.

[0013] FIG. 1 is a perspective view of the semiconductor device A1. FIG. 2 is a perspective view of the semiconductor device A1. FIG. 3 is a plan view of the semiconductor device A1. FIG. 4 is a front view of the semiconductor device A1. FIG. 5 is a plan view of the semiconductor device A1. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 3. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 3. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 3. FIGS. 10 and 11 are enlarged views of a portion of FIG. 6. FIG. 12 shows an example of the circuit configuration of the semiconductor device according to the first embodiment. For ease of understanding, FIGS. 2, 3, and 5 are shown through the sealing resin 7. The third conductive plate 3 and the second semiconductor element 42 are omitted in FIG. 5.

[0014] In the description of the semiconductor device A1, the thickness direction of the first conductive plate 1 is referred to as the "thickness direction z." One direction perpendicular to the thickness direction z is referred to as the "first direction x." A direction perpendicular to both the thickness direction z and the first direction x is referred to as the "second direction y."

[0015] In this embodiment, the first conductive plate 1, the second conductive plate 2, and the third conductive plate 3 are formed, for example, by punching or bending a metal plate. The constituent material of the first conductive plate 1, the second conductive plate 2, and the third conductive plate 3 is, for example, copper (Cu) or a copper alloy. The thickness (dimension in the thickness direction z) of each of the first conductive plate 1, the second conductive plate 2, and the third conductive plate 3 is not particularly limited and is, for example, approximately 0.1 mm to 2.5 mm, and preferably approximately 2.0 mm.

[0016] The first conductive plate 1 is a member on which the first semiconductor element 41 is mounted. As shown in FIGS. 3 to 7 , the first conductive plate 1 has a first main surface 101 and a first back surface 102. The first main surface 101 faces one side in the thickness direction z, and the first back surface 102 faces the other side in the thickness direction z. The first semiconductor element 41 is mounted on the first main surface 101. The shape of the first conductive plate 1 is not particularly limited. In the illustrated example, the first conductive plate 1 has a chamfered portion 11 and has a rectangular (or approximately rectangular) shape with one corner removed when viewed in the thickness direction z. In addition, as shown in FIGS. 6 and 7 , in this embodiment, the first back surface 102 is exposed from the sealing resin 7.

[0017] In this embodiment, as shown in Figure 10, the first conductive plate 1 includes a base material 12 and a main surface bonding layer 13. The base material 12 is made of copper or a copper alloy. The main surface bonding layer 13 overlaps the base material 12 on one side in the thickness direction z. The main surface bonding layer 13 is, for example, silver (Ag) plating. The surface of the main surface bonding layer 13 facing one side in the thickness direction z corresponds to the first main surface 101 of the first conductive plate 1.

[0018] As shown in FIG. 5 , the second conductive plate 2 is disposed spaced apart in the first direction x from the first conductive plate 1 as viewed in the thickness direction z. In the illustrated example, the second conductive plate 2 is located on the other side of the first conductive plate 1 in the first direction x. As shown in FIGS. 3 to 6 , 8 , and 9 , the second conductive plate 2 has a second main surface 201 and a second back surface 202. The second main surface 201 faces one side in the thickness direction z, and the second back surface 202 faces the other side in the thickness direction z. The shape of the second conductive plate 2 is not particularly limited, and in the illustrated example, it is rectangular (or approximately rectangular) as viewed in the thickness direction z. Furthermore, as shown in FIGS. 6 , 8 , and 9 , in this embodiment, the second back surface 202 is exposed from the sealing resin 7.

[0019] 11 , the second conductive plate 2 includes a base material 22 and a main surface bonding layer 23. The base material 22 is made of copper or a copper alloy. The main surface bonding layer 23 overlaps the base material 22 on one side in the thickness direction z. The main surface bonding layer 23 is, for example, silver plating. The surface of the main surface bonding layer 23 facing one side in the thickness direction z corresponds to the second main surface 201 of the second conductive plate 2.

[0020] 5 , the dimension of the first conductive plate 1 in the first direction x is larger than the dimension of the second conductive plate 2 in the first direction x. The dimension of the first conductive plate 1 in the second direction y is the same as the dimension of the second conductive plate 2 in the second direction y. As a result, the area of ​​the first conductive plate 1 is larger than the area of ​​the second conductive plate 2 when viewed in the thickness direction z.

[0021] As shown in FIGS. 4 and 6 to 9 , the third conductive plate 3 is disposed on one side of the first conductive plate 1 and the second conductive plate 2 in the thickness direction z, spaced apart from them. The third conductive plate 3 is a component on which the second semiconductor element 42 is mounted. As shown in FIGS. 3 , 4 , and 6 to 9 , the third conductive plate 3 has a third main surface 301 and a third back surface 302. The third main surface 301 faces the other side in the thickness direction z, and the third back surface 302 faces one side in the thickness direction z. The third main surface 301 faces both the second main surface 201 of the first conductive plate 1 and the second main surface 201 of the second conductive plate 2. The shape of the third conductive plate 3 is not particularly limited, and in the illustrated example, it is rectangular (or approximately rectangular) when viewed in the thickness direction z. Furthermore, in this embodiment, the third conductive plate 3 overlaps the entire first conductive plate 1 and the entire second conductive plate 2 when viewed in the thickness direction z. As shown in FIGS. 6 to 9, in this embodiment, the third rear surface 302 is exposed from the sealing resin 7.

[0022] In this embodiment, as shown in Figures 10 and 11, the third conductive plate 3 includes a base material 32 and a main surface bonding layer 33. The base material 32 is made of copper or a copper alloy. The main surface bonding layer 33 overlaps the base material 32 on the other side in the thickness direction z. The main surface bonding layer 33 is, for example, silver plating. The surface of the main surface bonding layer 33 facing the other side in the thickness direction z corresponds to the third main surface 301 of the third conductive plate 3.

[0023] The first semiconductor element 41 and the second semiconductor element 42 are electronic components that are central to the functionality of the semiconductor device A10. The first semiconductor element 41 and the second semiconductor element 42 are made of a semiconductor material primarily composed of, for example, silicon carbide (SiC). This semiconductor material is not limited to SiC and may be silicon (Si), gallium nitride (GaN), diamond (C), or the like. The first semiconductor element 41 and the second semiconductor element 42 are power semiconductor chips having a switching function unit Q1 (see FIG. 12 ) such as a metal oxide semiconductor field effect transistor (MOSFET). While this embodiment illustrates a case in which the first semiconductor element 41 and the second semiconductor element 42 are MOSFETs, the present invention is not limited thereto and may be other transistors such as an insulated gate bipolar transistor (IGBT).

[0024] 12, the semiconductor device A1 is configured as, for example, a half-bridge switching circuit. In this case, the first semiconductor element 41 configures the upper arm circuit of the semiconductor device A1, and the second semiconductor element 42 configures the lower arm circuit. The first semiconductor element 41 and the second semiconductor element 42 are connected in series to configure a bridge layer.

[0025] The first semiconductor element 41 is mounted on the first conductive plate 1 via a first conductive bonding material 61. As shown in Figures 6, 7, and 10, the first semiconductor element 41 is disposed between the first main surface 101 of the first conductive plate 1 and the third main surface 301 of the third conductive plate 3 in the thickness direction z.

[0026] As shown in FIGS. 5 and 10 , the first semiconductor element 41 has a first source electrode 411, a first gate electrode 412, a first drain electrode 413, and a first source sense electrode 414. The first source electrode 411, the first gate electrode 412, and the first source sense electrode 414 are provided on a surface of the first semiconductor element 41 facing one side in the thickness direction z, and face that side. The first drain electrode 413 is provided on a surface facing the other side in the thickness direction z, and faces that side. A source current flows from the interior of the first semiconductor element 41 to the first source electrode 411. A drive signal (e.g., a gate voltage) for driving the first semiconductor element 41 is input to the first gate electrode 412. A drain current flows through the first drain electrode 413 toward the interior of the first semiconductor element 41. The first drain electrode 413 is formed, for example, by silver plating. A source current flows through the first source sense electrode 414.

[0027] The second semiconductor element 42 is mounted on the third conductive plate 3 via the second conductive bonding material 62. As shown in Figures 6, 8, 9, and 11, the second semiconductor element 42 is disposed between the third main surface 301 of the third conductive plate 3 and the second main surface 201 of the second conductive plate 2 in the thickness direction z.

[0028] As shown in FIG. 11 , the second semiconductor element 42 has a second source electrode 421, a second gate electrode (not shown), a second drain electrode 423, and a second source sense electrode (not shown). The second source electrode 421, the second gate electrode, and the second source sense electrode are provided on a surface of the second semiconductor element 42 facing the other side in the thickness direction z, and face the other side in the thickness direction z. The second drain electrode 423 is provided on a surface facing one side in the thickness direction z, and faces the other side in the thickness direction z. The second semiconductor element 42 has substantially the same configuration as the first semiconductor element 41, but is disposed in an inverted position in the thickness direction z. A source current flows from inside the second semiconductor element 42 to the second source electrode 421. A drive signal (e.g., a gate voltage) for driving the second semiconductor element 42 is input to the second gate electrode. A drain current flows through the second drain electrode 423 toward the inside of the second semiconductor element 42. The second drain electrode 423 is formed, for example, by silver plating. A source current flows through the second source sense electrode.

[0029] The thickness (dimension in thickness direction z) of each of first semiconductor element 41 and second semiconductor element 42 is not particularly limited, and is, for example, about 0.15 mm.

[0030] When a drive signal (gate voltage) is input to the first gate electrode 412 (second gate electrode) by the switching function unit Q1, the first semiconductor element 41 (second semiconductor element 42) switches between a conductive state and a cutoff state in response to the drive signal. In the conductive state, a current flows from the first drain electrode 413 (second drain electrode 423) to the first source electrode 411 (second source electrode 421). In the cutoff state, no current flows. The first semiconductor element 41 and the second semiconductor element 42 each perform a switching operation using the switching function unit Q1. In the semiconductor device A1, the switching function units Q1 of the first semiconductor element 41 and the second semiconductor element 42 convert a DC voltage input between the first input terminal 51 and the second input terminal 52 into, for example, an AC voltage and output the AC voltage from the output terminal 53. Note that the diode D1 shown in FIG. 12 is, for example, a parasitic diode component of the switching function unit Q1.

[0031] The first input terminal 51, the second input terminal 52, and the output terminal 53 are each made of a metal plate, and are made of, for example, copper or a copper alloy.

[0032] A DC voltage to be converted into power is input to the first input terminal 51 and the second input terminal 52. The first input terminal 51 is a positive terminal (P terminal). The second input terminal 52 is a negative terminal (N terminal). An AC voltage converted into power by the first semiconductor element 41 and the second semiconductor element 42 is output from the output terminal 53.

[0033] The first input terminal 51 is electrically connected to the first conductive plate 1 and is located on one side of the first conductive plate 1 in the second direction y, as shown in FIG. 5 . In this embodiment, the first input terminal 51 is integrally formed with the first conductive plate 1, as shown in FIG. 7 . The first input terminal 51 has a first bent portion 511 and a first extending portion 512. As shown in FIGS. 5 and 7 , the first bent portion 511 is connected to the center of the first conductive plate 1 in the first direction x and to one end of the first conductive plate 1 in the thickness direction z. The first bent portion 511 extends toward one side of the second direction y so as to be located on one side of the thickness direction z. The first extending portion 512 is connected to the tip of the first bent portion 511 and extends along the second direction y to one side of the second direction y. A portion of the first extending portion 512 is exposed from the sealing resin 7.

[0034] The second input terminal 52 is electrically connected to the second conductive plate 2 and is located on one side of the second conductive plate 2 in the second direction y, as shown in FIG. 5 . In this embodiment, the second input terminal 52 is integrally formed with the second conductive plate 2, as shown in FIG. 8 . The second input terminal 52 has a second bent portion 521 and a second extending portion 522. As shown in FIGS. 5 and 8 , the second bent portion 521 is connected to one end of the second conductive plate 2 in the first direction x and to one end of the second conductive plate 2 in the thickness direction z. The second bent portion 521 extends to one side in the second direction y and one side in the first direction x, and extends toward the tip end so as to be located on one side in the thickness direction z. The second extending portion 522 is connected to the tip end of the second bent portion 521 and extends along the second direction y to one side in the second direction y. A portion of the second extending portion 522 is exposed from the sealing resin 7.

[0035] The output terminal 53 is electrically connected to the third conductive plate 3 and is located on one side of the third conductive plate 3 in the second direction y, as shown in FIG. 3 . In this embodiment, the output terminal 53 is integrally formed with the third conductive plate 3, as shown in FIG. 9 . The output terminal 53 has a third bent portion 531 and a third extending portion 532. As shown in FIGS. 3 and 9 , the third bent portion 531 is closer to the other side of the third conductive plate 3 in the first direction x and is connected to the other end of the third conductive plate 3 in the thickness direction z. The third bent portion 531 extends toward one side of the second direction y so as to be located on the other side of the thickness direction z. The third extending portion 532 is connected to the tip of the third bent portion 531 and extends along the second direction y to one side of the second direction y. A portion of the third extending portion 532 is exposed from the sealing resin 7.

[0036] In this embodiment, as shown in Figures 4 and 7 to 9, the first extension portion 512 of the first input terminal 51, the second extension portion 522 of the second input terminal 52, and the third extension portion 532 of the output terminal 53 are aligned in the thickness direction z and overlap each other when viewed in the first direction x.

[0037] The first control terminals 55 and 56 are terminals for controlling the first semiconductor element 41. As shown in Figures 3 to 5, the first control terminals 55, 56 are arranged on one side of the first conductive plate 1 in the second direction y and are spaced apart from each other in the first direction x. The first control terminals 55, 56 extend on one side in the second direction y. A portion of each of the first control terminals 55, 56 is exposed from the sealing resin 7.

[0038] 5 , a wire 43 is bonded to the first control terminal 55 and the first gate electrode 412 of the first semiconductor element 41. Conduction is established between the first gate electrode 412 and the first control terminal 55 via this wire 43. A wire 44 is bonded to the first control terminal 56 and the first source sense electrode 414 of the first semiconductor element 41. Conduction is established between the first source sense electrode 414 and the first control terminal 56 via this wire 44.

[0039] The second control terminals 57 and 58 are terminals for controlling the second semiconductor element 42. As shown in FIGS. 3 to 5 , the second control terminals 57 and 58 are arranged on one side in the second direction y with respect to the second conductive plate 2, and are spaced apart from each other in the first direction x. The second control terminals 57 and 58 extend on one side in the second direction y. A portion of each of the second control terminals 57 and 58 is exposed from the sealing resin 7.

[0040] A wire (not shown) is bonded to the second control terminal 57 and the second gate electrode of the second semiconductor element 42, and the second gate electrode and the second control terminal 57 are electrically connected via this wire. A wire (not shown) is bonded to the second control terminal 58 and the second source sense electrode of the second semiconductor element 42, and the second source sense electrode and the second control terminal 58 are electrically connected via this wire.

[0041] 4 , in the present embodiment, the first control terminals 55, 56 and the second control terminals 57, 58 are aligned in the thickness direction z with the first extending portion 512, the second extending portion 522, and the third extending portion 532. As a result, the first extending portion 512, the second extending portion 522, the third extending portion 532, the first control terminals 55, 56, and the second control terminals 57, 58 overlap one another when viewed in the first direction x.

[0042] 10 , the first conductive bonding material 61 is interposed between the first conductive plate 1 and the first semiconductor element 41, and electrically connects the first main surface 101 and the first drain electrode 413. In the present embodiment, the first conductive bonding material 61 includes a first base layer 611, a first layer 612, and a second layer 613 that are stacked on top of each other.

[0043] The first base layer 611 is made of metal, such as aluminum (Al) or an aluminum alloy, and is, for example, a sheet material.

[0044] The first layer 612 is formed on one side of the first base layer 611 in the thickness direction z. The first layer 612 is interposed between the first base layer 611 and the first drain electrode 413. The first layer 612 is, for example, silver plating. The first layer 612 is bonded to the first drain electrode 413 of the first semiconductor element 41 by, for example, solid-state diffusion of metal. That is, the first layer 612 and the first drain electrode 413 are bonded by solid-state diffusion bonding, and are bonded in a state of direct contact with each other at the bonding interface.

[0045] The second layer 613 is formed on the other side of the first base layer 611 in the thickness direction z. The second layer 613 is interposed between the first base layer 611 and the first conductive plate 1. The second layer 613 is, for example, silver plating. The second layer 613 is bonded to the main surface bonding layer 13 of the first conductive plate 1 by, for example, solid-state diffusion of metal. That is, the second layer 613 and the main surface bonding layer 13 are bonded by solid-state diffusion bonding, and are bonded in direct contact with each other at the bonding interface. Conditions for bonding by solid-state diffusion of metal include, for example, a heating temperature during bonding in the range of approximately 200°C to 350°C, and a pressure applied during bonding in the range of 1 MPa to 100 MPa. The solid-state diffusion may be performed either in air or in a vacuum. Unlike this embodiment, the first conductive bonding material 61 may be made of solder, and the first conductive bonding material 61 may be conductively bonded to both the first main surface 101 and the first drain electrode 413 .

[0046] 11 , the second conductive bonding material 62 is interposed between the third conductive plate 3 and the second semiconductor element 42, and electrically connects the third main surface 301 and the second drain electrode 423. In the present embodiment, the second conductive bonding material 62 includes a second base layer 621, a third layer 622, and a fourth layer 623 stacked on top of each other.

[0047] The second base layer 621 is made of a metal, such as aluminum or an aluminum alloy, and is, for example, a sheet material.

[0048] The third layer 622 is formed on the other side in the thickness direction z of the second base layer 621. The third layer 622 is interposed between the second base layer 621 and the second drain electrode 423. The third layer 622 is, for example, silver plating. The third layer 622 is bonded to the second drain electrode 423 of the second semiconductor element 42 by, for example, solid-state diffusion of metal. That is, the third layer 622 and the second drain electrode 423 are bonded by solid-state diffusion bonding, and are bonded in a state of direct contact with each other at the bonding interface.

[0049] The fourth layer 623 is formed on one side of the second base layer 621 in the thickness direction z. The fourth layer 623 is interposed between the second base layer 621 and the third conductive plate 3. The fourth layer 623 is, for example, silver plating. The fourth layer 623 is bonded to the main surface bonding layer 33 of the third conductive plate 3 by, for example, solid-state diffusion of metal. That is, the fourth layer 623 and the main surface bonding layer 33 are bonded by solid-state diffusion bonding, and are bonded in direct contact with each other at the bonding interface. The bonding conditions by solid-state diffusion of metal may be, for example, a heating temperature in the bonding process ranging from approximately 200°C to 350°C, and a pressure in the bonding process ranging from 1 MPa to 100 MPa. The solid-state diffusion may be performed in either the atmosphere or a vacuum. Unlike this embodiment, the second conductive bonding material 62 may be made of solder, and the second conductive bonding material 62 may be conductively bonded to both the third main surface 301 and the second drain electrode 423 .

[0050] 10 , the first metal portion 63 is interposed between the first source electrode 411 of the first semiconductor element 41 and the third main surface 301 of the third conductive plate 3, and provides electrical continuity between the first source electrode 411 and the third main surface 301. In this embodiment, the first metal portion 63 includes a fifth layer 631 and a sixth layer 632 stacked thereon.

[0051] The first metal portion 63 is made of a metal, such as aluminum, an aluminum alloy, copper, or a copper alloy. The thickness of the first metal portion 63 (the dimension in the thickness direction z) is not particularly limited and is, for example, about 1 mm.

[0052] The fifth layer 631 is formed on one side in the thickness direction z of the first metal portion 63. The fifth layer 631 is interposed between the first metal portion 63 and the third conductive plate 3. The fifth layer 631 is, for example, silver plating. The fifth layer 631 is bonded to the main surface bonding layer 33 of the third conductive plate 3 by, for example, solid-state diffusion of metal. That is, the fifth layer 631 and the main surface bonding layer 33 are bonded by solid-state diffusion bonding, and are bonded in direct contact with each other at the bonding interface.

[0053] The sixth layer 632 is formed on the other side of the first metal portion 63 in the thickness direction z. The sixth layer 632 is interposed between the first metal portion 63 and the first source electrode 411. The sixth layer 632 is, for example, silver plating. The sixth layer 632 is bonded to the first source electrode 411 by, for example, solid-phase diffusion of metal. That is, the sixth layer 632 and the first source electrode 411 are bonded by solid-phase diffusion bonding, and are bonded in direct contact with each other at the bonding interface. The bonding conditions for the above-described metal solid-phase diffusion bonding may be, for example, a heating temperature in the range of approximately 200°C to 350°C, and a pressure in the range of 1 MPa to 100 MPa. The solid-phase diffusion may be performed in air or in a vacuum. Unlike the present embodiment, the first metal portion 63 may be conductively bonded to both the second gate electrode 422 and the third main surface 301 using, for example, solder.

[0054] 11 , the second metal portion 64 is interposed between the second source electrode 421 of the second semiconductor element 42 and the second main surface 201 of the second conductive plate 2, and provides electrical continuity between the second source electrode 421 and the second main surface 201. In the present embodiment, the second metal portion 64 includes a seventh layer 641 and an eighth layer 642 stacked thereon.

[0055] The second metal portion 64 is made of a metal, such as aluminum, an aluminum alloy, copper, or a copper alloy. The thickness of the second metal portion 64 (the dimension in the thickness direction z) is not particularly limited and is, for example, about 1 mm.

[0056] The seventh layer 641 is formed on the other side in the thickness direction z of the second metal portion 64. The seventh layer 641 is interposed between the second metal portion 64 and the second conductive plate 2. The seventh layer 641 is, for example, silver plating. The seventh layer 641 is bonded to the main surface bonding layer 23 of the second conductive plate 2 by, for example, solid-state diffusion of metal. That is, the seventh layer 641 and the main surface bonding layer 23 are bonded by solid-state diffusion bonding, and are bonded in direct contact with each other at the bonding interface.

[0057] The eighth layer 642 is formed on one side of the second metal portion 64 in the thickness direction z. The eighth layer 642 is interposed between the second metal portion 64 and the second source electrode 421. The eighth layer 642 is, for example, silver plating. The eighth layer 642 is bonded to the second source electrode 421 by, for example, solid-state diffusion of metal. That is, the eighth layer 642 and the second source electrode 421 are bonded by solid-state diffusion bonding, and are bonded in direct contact with each other at the bonding interface. The bonding conditions for the above-described solid-state diffusion of metal include, for example, a heating temperature in the range of approximately 200°C to 350°C and a pressure in the range of 1 MPa to 100 MPa. The solid-state diffusion may be performed in air or in a vacuum. Unlike the present embodiment, the second metal portion 64 may be conductively bonded to both the second source electrode 421 and the second main surface 201 using, for example, solder.

[0058] 2 to 4 and 6 to 9, sealing resin 7 covers parts of first conductive plate 1, second conductive plate 2, and third conductive plate 3, parts of first input terminal 51, second input terminal 52, output terminal 53, first control terminals 55 and 56, and second control terminals 57 and 58, and first semiconductor element 41 and second semiconductor element 42. The constituent material of sealing resin 7 is, for example, black epoxy resin.

[0059] As shown in FIGS. 3 to 9 , the sealing resin 7 has a resin main surface 71, a resin back surface 72, a resin first side surface 731, a resin second side surface 732, a resin third side surface 733, and a resin fourth side surface 734. The resin main surface 71 faces one side in the thickness direction z. The resin back surface 72 faces the opposite side from the resin main surface 71 (the other side in the thickness direction z). As shown in FIGS. 6 to 9 , the first back surface 102 of the first conductive plate 1 and the first back surface 102 of the second conductive plate 2 are exposed from the resin main surface 71. The third back surface 302 of the third conductive plate 3 is exposed from the resin main surface 71.

[0060] 6 , the first resin side surface 731 is connected to both the resin main surface 71 and the resin back surface 72 and faces one side in the first direction x. The second resin side surface 732 is connected to both the resin main surface 71 and the resin back surface 72 and faces the other side in the first direction x. The first resin side surface 731 and the second resin side surface 732 are spaced apart from each other in the first direction x.

[0061] As shown in FIGS. 3 and 7 to 9 , the resin third side surface 733 is connected to all of the resin principal surface 71, the resin rear surface 72, the resin first side surface 731, and the resin second side surface 732, and faces one side in the second direction y. The resin fourth side surface 734 is connected to all of the resin principal surface 71, the resin rear surface 72, the resin first side surface 731, and the resin second side surface 732, and faces the other side in the second direction y. The resin third side surface 733 and the resin fourth side surface 734 are spaced apart from each other in the second direction y. Portions of the first input terminal 51, the second input terminal 52, and the output terminal 53 (the first extending portion 512, the second extending portion 522, and the third extending portion 532), as well as portions of the first control terminals 55 and 56 and the second control terminals 57 and 58, protrude from the resin third side surface 733 toward one side in the second direction y.

[0062] In this embodiment, a plurality of recesses 75 are formed in the resin third side surface 733. The recesses 75 are recessed from the resin third side surface 733 to the other side in the second direction y and are formed from the resin main surface 71 to the resin back surface 72 in the thickness direction z. The plurality of recesses 75 are provided in the first direction x between the first input terminal 51 and the second input terminal 52, between the second input terminal 52 and the output terminal 53, between the first input terminal 51 and the first control terminal 56, and between the output terminal 53 and the second control terminal 58. The plurality of recesses 75 are provided to increase the creepage distance between adjacent terminals in the first direction x.

[0063] Next, the operation of this embodiment will be described.

[0064] The semiconductor device A1 includes a first conductive plate 1, a second conductive plate 2, a third conductive plate 3, a first semiconductor element 41, a second semiconductor element 42, a first input terminal 51, a second input terminal 52, and an output terminal 53. The first conductive plate 1 and the second conductive plate 2 are spaced apart in a first direction x, and the third conductive plate 3 is spaced apart from the first conductive plate 1 and the second conductive plate 2 in a thickness direction z. The first semiconductor element 41 is disposed between a first main surface 101 of the first conductive plate 1 and a third main surface 301 of the third conductive plate 3, and the second semiconductor element 42 is disposed between the third main surface 301 of the third conductive plate 3 and a second main surface 201 of the second conductive plate 2. The first input terminal 51 is a positive electrode and is electrically connected to the first conductive plate 1. The second input terminal 52 is a negative electrode and is electrically connected to the second conductive plate 2. The output terminal 53 is electrically connected to the third conductive plate 3. With this configuration, heat generated in the first semiconductor element 41 is mainly conducted to the first conductive plate 1. The second semiconductor element 42 is disposed in an inverted position relative to the first semiconductor element 41 in the thickness direction z. Heat generated in the second semiconductor element 42 is mainly conducted to the third conductive plate 3. This allows the heat generated in the first semiconductor element 41 and the second semiconductor element 42 to be dispersed and dissipated to the first conductive plate 1 and the third conductive plate 3, which are disposed apart from each other in the thickness direction z. This improves the heat dissipation performance of the semiconductor device A1. Furthermore, with the configuration in which the first semiconductor element 41 and the second semiconductor element 42 are disposed in an inverted position relative to the thickness direction z, the inductance due to the current flowing through the semiconductor device A1 can be reduced.

[0065] When viewed in the thickness direction z, the area of ​​the first conductive plate 1 is larger than the area of ​​the second conductive plate 2. With this configuration, heat generated in the first semiconductor element 41 can be efficiently dissipated to the first conductive plate 1 side.

[0066] The semiconductor device A1 includes a first metal portion 63 and a second metal portion 64. The first metal portion 63 is interposed between the first source electrode 411 of the first semiconductor element 41 and the third main surface 301 of the third conductive plate 3, providing electrical continuity between the first source electrode 411 and the third main surface 301. The second metal portion 64 is interposed between the second source electrode 421 of the second semiconductor element 42 and the second main surface 201 of the second conductive plate 2, providing electrical continuity between the second source electrode 421 and the second main surface 201. With this configuration, heat generated in the first semiconductor element 41 is conducted to the third conductive plate 3 via the first metal portion 63. Heat generated in the second semiconductor element 42 is conducted to the second conductive plate 2 via the second metal portion 64. This allows heat generated in both the first semiconductor element 41 and the second semiconductor element 42 to be dissipated more efficiently. This further improves the heat dissipation performance of the semiconductor device A1.

[0067] The first rear surface 102 of the first conductive plate 1, the second rear surface 202 of the second conductive plate 2, and the third rear surface 302 of the third conductive plate 3 are all exposed from the sealing resin 7. This is preferable in terms of improving the heat dissipation properties of the semiconductor device A1.

[0068] The first extending portion 512 (first input terminal 51), the second extending portion 522 (second input terminal 52), and the third extending portion 532 (output terminal 53) are exposed from the sealing resin 7, and each extends from the resin third side surface 733 to one side in the second direction y. The first extending portion 512, the second extending portion 522, and the third extending portion 532 overlap each other when viewed in the first direction x, and are aligned in the thickness direction z. This configuration makes the semiconductor device A1 easy to handle when mounting it on a circuit board or the like (not shown).

[0069] The first conductive bonding material 61 is bonded to both the first drain electrode 413 and the first conductive plate 1, for example, by solid-state diffusion of metal. The first conductive bonding material 61 (first layer 612 and second layer 613) is bonded to both the first drain electrode 413 and the first conductive plate 1 in direct contact with each other at the bonding interfaces. With this configuration, heat generated in the first semiconductor element 41 can be efficiently dissipated to the first conductive plate 1 via the first conductive bonding material 61. The second conductive bonding material 62 is bonded to both the second drain electrode 423 and the third conductive plate 3, for example, by solid-state diffusion of metal. The second conductive bonding material 62 (third layer 622 and fourth layer 623) is bonded to both the second drain electrode 423 and the third conductive plate 3 in direct contact with each other at the bonding interfaces. With this configuration, heat generated in the second semiconductor element 42 can be efficiently dissipated to the first conductive plate 1 via the second conductive bonding material 62. The configuration including the first conductive bonding material 61 and the second conductive bonding material 62 is more preferable in terms of improving the heat dissipation performance of the semiconductor device A1.

[0070] 13 shows a semiconductor device according to a second embodiment of the present disclosure. In the figures following FIG. 13, elements that are the same as or similar to those in the semiconductor device A1 of the above embodiment are denoted by the same reference numerals as in the above embodiment, and descriptions thereof will be omitted as appropriate.

[0071] In semiconductor device A2 of this embodiment, insulating layer 15, insulating layer 25, and insulating layer 35 are additionally provided compared to semiconductor device A1 of the above embodiment. Insulating layer 15 covers first rear surface 102 of first conductive plate 1. Insulating layer 25 covers first rear surface 102 of second conductive plate 2. Insulating layer 35 covers third rear surface 302 of third conductive plate 3. The configuration of these insulating layers 15, 25, and 35 is not particularly limited, and may be made of, for example, a ceramic sheet or an insulating resin sheet.

[0072] In the semiconductor device A2, the first semiconductor element 41 is disposed between the first main surface 101 of the first conductive plate 1 and the third main surface 301 of the third conductive plate 3, and the second semiconductor element 42 is disposed between the third main surface 301 of the third conductive plate 3 and the second main surface 201 of the second conductive plate 2. The first input terminal 51 is a positive electrode and is electrically connected to the first conductive plate 1. The second input terminal 52 is a negative electrode and is electrically connected to the second conductive plate 2. The output terminal 53 is electrically connected to the third conductive plate 3. With this configuration, heat generated in the first semiconductor element 41 is mainly conducted to the first conductive plate 1. The second semiconductor element 42 is disposed in an inverted position relative to the first semiconductor element 41 in the thickness direction z. Heat generated in the second semiconductor element 42 is mainly conducted to the third conductive plate 3. This allows heat generated in the first semiconductor element 41 and the second semiconductor element 42 to be dispersed and released to the first conductive plate 1 and the third conductive plate 3, which are spaced apart in the thickness direction z, thereby improving the heat dissipation performance of the semiconductor device A2.

[0073] The semiconductor device A2 includes insulating layers 15, 25, and 35 that cover the first back surface 102, the second back surface 202, and the third back surface 302. This configuration ensures electrical insulation on both sides of the semiconductor device A2 in the thickness direction z. In addition, within the same configuration as the semiconductor device A1 of the above embodiment, the semiconductor device A2 achieves the same effects as the above embodiment.

[0074] 14 shows a semiconductor device according to a third embodiment of the present disclosure. In a semiconductor device A3 of this embodiment, the configuration of the sealing resin 7 is different from that of the semiconductor device A1 of the above embodiment.

[0075] In the semiconductor device A3, unlike the above-described embodiment, the sealing resin 7 covers each of the first rear surface 102, the second rear surface 202, and the third rear surface 302. A first dimension L1, which is the distance in the thickness direction z between the first rear surface 102 and the resin rear surface 72, is smaller than the thickness T1 of the first conductive plate 1. A second dimension L2, which is the distance in the thickness direction z between the second rear surface 202 and the resin rear surface 72, is smaller than the thickness T2 of the second conductive plate 2. A third dimension L3, which is the distance in the thickness direction z between the third rear surface 302 and the resin main surface 71, is smaller than the thickness T3 of the third conductive plate 3. Each of the first dimension L1, the second dimension L2, and the third dimension L3 is, for example, approximately 0.1 mm to 0.3 mm.

[0076] The constituent material of the sealing resin 7 in this embodiment is different from that of the above-described embodiment. In this embodiment, the sealing resin 7 has predetermined thermal properties, and the thermal conductivity of the sealing resin 7 is 5 W / mK or higher. An example of the constituent material of such sealing resin 7 is an epoxy resin containing a filler. Examples of such fillers include aluminum oxide (AlO), boron nitride (BN), aluminum nitride (AlN), and silicon nitride (SiN), and the sealing resin 7 contains at least one of these. Such sealing resin 7 is a highly thermally conductive resin with a thermal conductivity of 5 W / mK or higher. If the thermal conductivity of the sealing resin 7 is 5 W / mK or higher, the heat dissipation properties of the portions covering the first rear surface 102, the second rear surface 202, or the third rear surface 302 are better than those of a general insulating sheet.

[0077] In the semiconductor device A3, the first semiconductor element 41 is disposed between the first main surface 101 of the first conductive plate 1 and the third main surface 301 of the third conductive plate 3, and the second semiconductor element 42 is disposed between the third main surface 301 of the third conductive plate 3 and the second main surface 201 of the second conductive plate 2. The first input terminal 51 is a positive electrode and is electrically connected to the first conductive plate 1. The second input terminal 52 is a negative electrode and is electrically connected to the second conductive plate 2. The output terminal 53 is electrically connected to the third conductive plate 3. With this configuration, heat generated in the first semiconductor element 41 is mainly conducted to the first conductive plate 1. The second semiconductor element 42 is disposed in an inverted position relative to the first semiconductor element 41 in the thickness direction z. Heat generated in the second semiconductor element 42 is mainly conducted to the third conductive plate 3. This allows heat generated in the first semiconductor element 41 and the second semiconductor element 42 to be dispersed and released to the first conductive plate 1 and the third conductive plate 3, which are spaced apart in the thickness direction z, thereby improving the heat dissipation performance of the semiconductor device A3.

[0078] In the semiconductor device A3, the sealing resin 7 covers the first back surface 102, the second back surface 202, and the third back surface 302. This configuration ensures electrical insulation on both sides of the thickness direction z in the semiconductor device A3. Furthermore, the sealing resin 7 has a relatively high thermal conductivity, and the thicknesses (first dimension L1, second dimension L2, and third dimension L3) of the portions covering the first back surface 102, the second back surface 202, and the third back surface 302 are relatively small. This configuration can suppress a decrease in heat dissipation performance on the first back surface 102 side of the first conductive plate 1, the second back surface 202 side of the second conductive plate 2, and the third back surface 302 side of the third conductive plate 3. Additionally, within the same configuration as the semiconductor device A1 of the above embodiment, the same effects as those of the above embodiment can be achieved.

[0079] 15 shows a semiconductor device according to a fourth embodiment of the present disclosure. In the semiconductor device A4 of this embodiment, a first substrate 81 and a second substrate 82 are additionally provided compared to the semiconductor device A1 of the above embodiment.

[0080] The first substrate 81 is disposed on the other side of the first conductive plate 1 and the second conductive plate 2 in the thickness direction z. The first substrate 81 includes a first insulating layer 811, a first metal layer 812, and a second metal layer 813. The first substrate 81 is formed, for example, of a DBC (Direct Bonded Copper) substrate or an AMB (Active Metal Brazing) substrate. The first insulating layer 811 is made of, for example, ceramics with excellent thermal conductivity. An example of such ceramics is AlN (aluminum nitride). When viewed in the thickness direction z, the first insulating layer 811 overlaps both the first back surface 102 (first conductive plate 1) and the second back surface 202 (second conductive plate 2).

[0081] The first metal layer 812 is formed on one side of the first insulating layer 811 in the thickness direction z. The constituent material of the first metal layer 812 includes, for example, copper. The first metal layer 812 includes a first portion 812A and a second portion 812B. The first portion 812A and the second portion 812B are spaced apart in the first direction x. The first portion 812A is bonded to the first rear surface 102 (first conductive plate 1). The second portion 812B is bonded to the second rear surface 202 (second conductive plate 2). The second metal layer 813 is formed on the other side of the first insulating layer 811 in the thickness direction z. The constituent material of the second metal layer 813 is the same as the constituent material of the first metal layer 812. In the illustrated example, the surface of the second metal layer 813 facing the other side in the thickness direction z is exposed from the sealing resin 7.

[0082] The second substrate 82 is disposed on the other side in the thickness direction z of the third conductive plate 3. The second substrate 82 includes a second insulating layer 821, a third metal layer 822, and a fourth metal layer 823. Like the first substrate 81, the second substrate 82 is formed of, for example, a DBC substrate or an AMB substrate. The materials constituting the second insulating layer 821, the third metal layer 822, and the fourth metal layer 823 are the same as the materials constituting the first insulating layer 811, the first metal layer 812, and the second metal layer 813 of the first substrate 81. The second insulating layer 821 overlaps the third back surface 302 (the third conductive plate 3) when viewed in the thickness direction z.

[0083] The third metal layer 822 is formed on the other side in the thickness direction z of the second insulating layer 821. The third metal layer 822 is joined to the third rear surface 302 (third conductive plate 3). The fourth metal layer 823 is formed on one side in the thickness direction z of the second insulating layer 821. In the illustrated example, the surface of the fourth metal layer 823 facing one side in the thickness direction z is exposed from the sealing resin 7.

[0084] In the semiconductor device A4, the first semiconductor element 41 is disposed between the first main surface 101 of the first conductive plate 1 and the third main surface 301 of the third conductive plate 3, and the second semiconductor element 42 is disposed between the third main surface 301 of the third conductive plate 3 and the second main surface 201 of the second conductive plate 2. The first input terminal 51 is a positive electrode and is electrically connected to the first conductive plate 1. The second input terminal 52 is a negative electrode and is electrically connected to the second conductive plate 2. The output terminal 53 is electrically connected to the third conductive plate 3. With this configuration, heat generated in the first semiconductor element 41 is mainly conducted to the first conductive plate 1. The second semiconductor element 42 is disposed in an inverted position relative to the first semiconductor element 41 in the thickness direction z. Heat generated in the second semiconductor element 42 is mainly conducted to the third conductive plate 3. This allows heat generated in the first semiconductor element 41 and the second semiconductor element 42 to be dispersed and released to the first conductive plate 1 and the third conductive plate 3, which are spaced apart in the thickness direction z, thereby improving the heat dissipation performance of the semiconductor device A4.

[0085] The semiconductor device A4 includes a first insulating layer 811 and a second insulating layer 821. The first insulating layer 811 is disposed on the other side in the thickness direction z of the first back surface 102 and the second back surface 202, and overlaps the first back surface 102 and the second back surface 202 as viewed in the thickness direction z. The second insulating layer 821 is disposed on one side in the thickness direction z of the third back surface 302, and overlaps the third back surface 302 as viewed in the thickness direction z. With this configuration, electrical insulation is ensured on both sides in the thickness direction z in the semiconductor device A4.

[0086] Furthermore, in the semiconductor device A4, the first insulating layer 811 and the second insulating layer 821 form part of the first substrate 81 and the second substrate 82 (e.g., a DBC substrate or an AMB substrate). The first metal layer 812 of the first substrate 81 is bonded to the first conductive plate 1 and the second conductive plate 2, and the third metal layer 822 of the second substrate 82 is bonded to the third conductive plate 3. This configuration allows heat from the first conductive plate 1, the second conductive plate 2, and the third conductive plate 3 to be dissipated to the first substrate 81 and the second substrate 82. This is preferable for improving the heat dissipation of the semiconductor device A4. Additionally, within the same configuration as the semiconductor device A1 of the above embodiment, the semiconductor device A4 achieves the same effects as the above embodiment.

[0087] 16 shows a semiconductor device according to a fifth embodiment of the present disclosure. In the semiconductor device A5 of this embodiment, a first insulating layer 83, a conductive plate 84, a second insulating layer 85, and a conductive plate 86 are additionally provided compared to the semiconductor device A1 of the above embodiment.

[0088] The first insulating layer 83 and the conductive plate 84 are disposed on the other side of the first conductive plate 1 and the second conductive plate 2 in the thickness direction z. In this embodiment, the first conductive plate 1, the second conductive plate 2, the first insulating layer 83, and the conductive plate 84 are formed, for example, by an AMB substrate. The first conductive plate 1 and the second conductive plate 2 constitute part of the AMB substrate. The first insulating layer 83 is made, for example, of a ceramic with excellent thermal conductivity. An example of such a ceramic is AlN. When viewed in the thickness direction z, the first insulating layer 83 overlaps both the first rear surface 102 (first conductive plate 1) and the second rear surface 202 (second conductive plate 2).

[0089] The first conductive plate 1 and the second conductive plate 2 are formed on one side of the first insulating layer 83 in the thickness direction z. The constituent material of the first conductive plate 1 and the second conductive plate 2 includes, for example, copper. The conductive plate 84 is formed on the other side of the first insulating layer 83 in the thickness direction z. The constituent material of the conductive plate 84 is the same as the constituent material of the first conductive plate 1 and the second conductive plate 2. In the illustrated example, the surface of the conductive plate 84 facing the other side in the thickness direction z is exposed from the sealing resin 7.

[0090] The second insulating layer 85 and the conductive plate 86 are disposed on one side of the third conductive plate 3 in the thickness direction z. In this embodiment, the third conductive plate 3, the second insulating layer 85, and the conductive plate 86 are formed, for example, from an AMB substrate. The third conductive plate 3 constitutes part of the AMB substrate. The constituent material of the third conductive plate 3 is the same as the constituent material of the first conductive plate 1 and the second conductive plate 2. The constituent material of the second insulating layer 85 is the same as the constituent material of the first insulating layer 83. The constituent material of the conductive plate 86 is the same as the constituent material of the conductive plate 84. The second insulating layer 85 overlaps the third back surface 302 (the third conductive plate 3) when viewed in the thickness direction z.

[0091] The third conductive plate 3 is formed on the other side in the thickness direction z of the second insulating layer 85. The conductive plate 86 is formed on one side in the thickness direction z of the second insulating layer 85. In the illustrated example, the surface of the conductive plate 86 facing one side in the thickness direction z is exposed from the sealing resin 7.

[0092] In the semiconductor device A5, the first semiconductor element 41 is disposed between the first main surface 101 of the first conductive plate 1 and the third main surface 301 of the third conductive plate 3, and the second semiconductor element 42 is disposed between the third main surface 301 of the third conductive plate 3 and the second main surface 201 of the second conductive plate 2. The first input terminal 51 is a positive electrode and is electrically connected to the first conductive plate 1. The second input terminal 52 is a negative electrode and is electrically connected to the second conductive plate 2. The output terminal 53 is electrically connected to the third conductive plate 3. With this configuration, heat generated in the first semiconductor element 41 is mainly conducted to the first conductive plate 1. The second semiconductor element 42 is disposed in an inverted position relative to the first semiconductor element 41 in the thickness direction z. Heat generated in the second semiconductor element 42 is mainly conducted to the third conductive plate 3. This allows heat generated in the first semiconductor element 41 and the second semiconductor element 42 to be dispersed and released to the first conductive plate 1 and the third conductive plate 3, which are spaced apart in the thickness direction z, thereby improving the heat dissipation performance of the semiconductor device A5.

[0093] The semiconductor device A5 includes a first insulating layer 83 and a second insulating layer 85. The first insulating layer 83 is disposed on the other side of the first back surface 102 and the second back surface 202 in the thickness direction z, and overlaps the first back surface 102 and the second back surface 202 as viewed in the thickness direction z. The second insulating layer 85 is disposed on one side of the third back surface 302 in the thickness direction z, and overlaps the third back surface 302 as viewed in the thickness direction z. This configuration ensures electrical insulation on both sides of the thickness direction z in the semiconductor device A5. Additionally, within the same configuration as the semiconductor device A1 of the above embodiment, the semiconductor device A5 achieves the same effects as the above embodiment.

[0094] 17 to 19 show a semiconductor device according to a sixth embodiment of the present disclosure. In the semiconductor device A6 of this embodiment, the arrangement of the second input terminal 52 and the output terminal 53 is different from that of the semiconductor device A1 of the above embodiment.

[0095] In the semiconductor device A1 of the above embodiment, the output terminal 53 is disposed closer to the other side in the first direction x of the third conductive plate 3 (see FIG. 3 ), but in the semiconductor device A6, the output terminal 53 is disposed in the center in the first direction x of the third conductive plate 3. The second input terminal 52 is disposed on the other side in the first direction x with respect to the output terminal 53. In the semiconductor device A6, the positions of the second input terminal 52 and the output terminal 53 are swapped compared to the semiconductor device A1.

[0096] In the semiconductor device A6, the first semiconductor element 41 is disposed between the first main surface 101 of the first conductive plate 1 and the third main surface 301 of the third conductive plate 3, and the second semiconductor element 42 is disposed between the third main surface 301 of the third conductive plate 3 and the second main surface 201 of the second conductive plate 2. The first input terminal 51 is a positive electrode and is electrically connected to the first conductive plate 1. The second input terminal 52 is a negative electrode and is electrically connected to the second conductive plate 2. The output terminal 53 is electrically connected to the third conductive plate 3. With this configuration, heat generated in the first semiconductor element 41 is mainly conducted to the first conductive plate 1. The second semiconductor element 42 is disposed in an inverted position relative to the first semiconductor element 41 in the thickness direction z. Heat generated in the second semiconductor element 42 is mainly conducted to the third conductive plate 3. This allows heat generated in the first semiconductor element 41 and the second semiconductor element 42 to be dispersed and released to the first conductive plate 1 and the third conductive plate 3, which are spaced apart in the thickness direction z, thereby improving the heat dissipation performance of the semiconductor device A6.

[0097] The semiconductor device A6 differs from the semiconductor device A1 in the arrangement of the second input terminals 52 and the output terminals 53. The semiconductor device A6 can provide a variation in terminal arrangement different from that of the semiconductor device A1. In addition, within the scope of the same configuration as the semiconductor device A1 of the above embodiment, the semiconductor device A6 achieves the same effects as the above embodiment.

[0098] 20 to 22 show a semiconductor device according to a seventh embodiment of the present disclosure. A semiconductor device A7 according to this embodiment differs from the semiconductor device A1 according to the above embodiment mainly in the arrangement of the output terminals 53.

[0099] In the semiconductor device A1 of the above embodiment, the output terminal 53 is disposed on one side in the second direction y with respect to the third conductive plate 3 (see FIG. 3), but in the semiconductor device A7, the output terminal 53 is disposed on the other side in the second direction y with respect to the third conductive plate 3. The output terminal 53 is disposed at the center of the third conductive plate 3 in the first direction x.

[0100] In the semiconductor device A7, the first semiconductor element 41 is disposed between the first main surface 101 of the first conductive plate 1 and the third main surface 301 of the third conductive plate 3, and the second semiconductor element 42 is disposed between the third main surface 301 of the third conductive plate 3 and the second main surface 201 of the second conductive plate 2. The first input terminal 51 is a positive electrode and is electrically connected to the first conductive plate 1. The second input terminal 52 is a negative electrode and is electrically connected to the second conductive plate 2. The output terminal 53 is electrically connected to the third conductive plate 3. With this configuration, heat generated in the first semiconductor element 41 is mainly conducted to the first conductive plate 1. The second semiconductor element 42 is disposed in an inverted position relative to the first semiconductor element 41 in the thickness direction z. Heat generated in the second semiconductor element 42 is mainly conducted to the third conductive plate 3. This allows heat generated in the first semiconductor element 41 and the second semiconductor element 42 to be dispersed and released to the first conductive plate 1 and the third conductive plate 3, which are spaced apart in the thickness direction z, thereby improving the heat dissipation performance of the semiconductor device A7.

[0101] In the semiconductor device A7, the output terminal 53 is disposed on the opposite side of the third conductive plate 3 from the first input terminal 51 and the second input terminal 52 in the thickness direction z. This configuration increases the degree of freedom in arranging the various terminals. In addition, within the same range of configuration as the semiconductor device A1 of the above embodiment, the same effects as those of the above embodiment can be achieved.

[0102] 23 shows a semiconductor device according to an eighth embodiment of the present disclosure. The semiconductor device A8 of this embodiment differs from the semiconductor device A1 of the above embodiment mainly in the arrangement of the first control terminals 55 and 56 and the second control terminals 57 and 58.

[0103] In the semiconductor device A1 of the above embodiment, the first control terminals 55, 56 and the second control terminals 57, 58 were arranged on one side of the third conductive plate 3 in the second direction y (see Figure 3), but in the semiconductor device A8, the first control terminals 55, 56 and the second control terminals 57, 58 are arranged on the other side of the third conductive plate 3 in the second direction y.

[0104] In the semiconductor device A8, the first semiconductor element 41 is disposed between the first main surface 101 of the first conductive plate 1 and the third main surface 301 of the third conductive plate 3, and the second semiconductor element 42 is disposed between the third main surface 301 of the third conductive plate 3 and the second main surface 201 of the second conductive plate 2. The first input terminal 51 is a positive electrode and is electrically connected to the first conductive plate 1. The second input terminal 52 is a negative electrode and is electrically connected to the second conductive plate 2. The output terminal 53 is electrically connected to the third conductive plate 3. With this configuration, heat generated in the first semiconductor element 41 is mainly conducted to the first conductive plate 1. The second semiconductor element 42 is disposed in an inverted position relative to the first semiconductor element 41 in the thickness direction z. Heat generated in the second semiconductor element 42 is mainly conducted to the third conductive plate 3. This allows heat generated in the first semiconductor element 41 and the second semiconductor element 42 to be dispersed and released to the first conductive plate 1 and the third conductive plate 3, which are spaced apart in the thickness direction z, thereby improving the heat dissipation performance of the semiconductor device A8.

[0105] In the semiconductor device A8, the first control terminals 55, 56 and the second control terminals 57, 58 are arranged on the opposite side of the third conductive plate 3 from the first input terminal 51, the second input terminal 52, and the output terminal 53 when viewed in the thickness direction z. This configuration makes it possible to suppress the influence of noise from the first input terminal 51, the second input terminal 52, and the output terminal 53 on the first control terminals 55, 56 and the second control terminals 57, 58. In addition, within the same range of configuration as the semiconductor device A1 of the above embodiment, the same effects as those of the above embodiment can be achieved.

[0106] The semiconductor device according to the present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the semiconductor device according to the present disclosure can be freely modified in various ways.

[0107] The present disclosure includes the embodiments described in the following appendices.

[0108] Supplementary Note 1. A first conductive plate having a first main surface facing one side in a thickness direction and a first back surface facing the other side; a second conductive plate having a second main surface facing one side in the thickness direction and a second back surface facing the other side, and spaced apart from the first conductive plate in a first direction perpendicular to the thickness direction; a third conductive plate facing the other side in the thickness direction and having a third main surface facing the first main surface and the second main surface, and a third back surface facing one side in the thickness direction, and spaced apart from the first conductive plate and the second conductive plate on one side in the thickness direction; a first semiconductor element disposed between the first main surface and the third main surface in the thickness direction and having a switching function; a second semiconductor element disposed between the third main surface and the second main surface in the thickness direction and having a switching function; a first input terminal electrically connected to the first conductive plate and having a positive electrode; and a second input terminal electrically connected to the second conductive plate and having a negative electrode. A semiconductor device comprising: an output terminal electrically connected to the third conductive plate; and a sealing resin covering at least a portion of each of the first conductive plate, the second conductive plate, and the third conductive plate, a portion of each of the first input terminal, the second input terminal, and the output terminal, and the first semiconductor element and the second semiconductor element. Appendix 2. The semiconductor device according to Appendix 1, wherein an area of ​​the first conductive plate is larger than an area of ​​the second conductive plate when viewed in the thickness direction. Appendix 3. The semiconductor device according to Appendix 1 or 2, wherein the first back surface, the second back surface, and the third back surface are exposed from the sealing resin. Appendix 4. The semiconductor device according to Appendix 3, further comprising an insulating layer covering each of the first back surface, the second back surface, and the third back surface. Appendix 5. The semiconductor device according to Appendix 1 or 2, wherein the first back surface, the second back surface, and the third back surface are covered with the sealing resin, and the thermal conductivity of the sealing resin is 5 W / mK or more.Supplementary Note 6. The semiconductor device according to Supplementary Note 5, wherein the sealing resin has a resin main surface facing one side in the thickness direction and a resin back surface facing the other side, a first dimension between the first back surface and the resin back surface in the thickness direction is smaller than a thickness of the first conductive plate, a second dimension between the second back surface and the resin back surface in the thickness direction is smaller than a thickness of the second conductive plate, and a third dimension between the third back surface and the resin main surface in the thickness direction is smaller than a thickness of the third conductive plate. Supplementary Note 7. The semiconductor device according to Supplementary Note 1 or 2, further comprising: a first insulating layer arranged on the other side of the first back surface in the thickness direction and overlapping with the first back surface and the second back surface as viewed in the thickness direction; and a second insulating layer arranged on one side of the third back surface in the thickness direction and overlapping with the third back surface as viewed in the thickness direction. Supplementary Note 8. The semiconductor device according to any one of Supplementary Notes 1 to 7, wherein the first input terminal has a first extending portion exposed from the sealing resin and extending in the second direction perpendicular to both the thickness direction and the first direction, the second input terminal has a second extending portion exposed from the sealing resin and extending in the second direction, and the output terminal has a third extending portion exposed from the sealing resin and extending in the second direction.Supplementary Note 9. The semiconductor device according to Supplementary Note 8, wherein the first extending portion is located on one side in the second direction with respect to the first conductive plate and extends to one side in the second direction, the second extending portion is located on one side in the second direction with respect to the second conductive plate and extends to one side in the second direction, and the third extending portion is located on one side in the second direction with respect to the third conductive plate and extends to one side in the second direction.Supplementary Note 10. The semiconductor device according to claim 9, wherein the first extending portion, the second extending portion, and the third extending portion overlap each other when viewed in the first direction. Appendix 11. The semiconductor device according to any of claims 8 to 10, further comprising a first control terminal and a second control terminal for controlling the first semiconductor element and the second semiconductor element, and the sealing resin covers a portion of each of the first control terminal and the second control terminal.Appendix 12. The semiconductor device according to Appendix 11, wherein the first control terminal is spaced apart from the first conductive plate in the second direction and extends in the second direction, and the second control terminal is spaced apart from the third conductive plate in the second direction and extends in the second direction. Appendix 13. The semiconductor device according to any one of Appendixes 1 to 12, further comprising a first conductive bonding material and a second conductive bonding material, wherein the first semiconductor element has a first source electrode facing one side in the thickness direction and a first drain electrode facing the other side in the thickness direction, the second semiconductor element has a second source electrode facing the other side in the thickness direction and a second drain electrode facing the one side in the thickness direction, the first conductive bonding material conductively bonds the first main surface and the first drain electrode, and the second conductive bonding material conductively bonds the third main surface and the second drain electrode. Appendix 14. The semiconductor device according to claim 13, further comprising: a first metal portion interposed between the first source electrode and the third major surface and providing electrical continuity between the first source electrode and the third major surface; and a second metal portion interposed between the second source electrode and the second major surface and providing electrical continuity between the second source electrode and the second major surface. the first conductive bonding material includes a first metal base layer, a first layer interposed between the first base layer and the first drain electrode and bonded to each other in direct contact at a bonding interface with the first drain electrode, and a second layer interposed between the first base layer and the first conductive plate and bonded to each other in direct contact at a bonding interface with the first conductive plate, the second conductive bonding material includes a second metal base layer, a third layer interposed between the second base layer and the second drain electrode and bonded to each other in direct contact at a bonding interface with the second drain electrode, and a fourth layer interposed between the second base layer and the third conductive plate and bonded to each other in direct contact at a bonding interface with the third conductive plate.Supplementary Note 17. The semiconductor device according to any one of Supplementary Notes 1 to 16, wherein each of the first conductive plate, the second conductive plate, and the third conductive plate contains copper.

[0109] A1, A2, A3, A4, A5, A6, A7, A8: semiconductor device 1: first conductive plate 101: first main surface 102: first back surface 11: chamfered portion 12: substrate 13: main surface bonding layer 15: insulating layer 2: second conductive plate 2 201: second main surface 202: second back surface 22: substrate 23: main surface bonding layer 25: insulating layer 3: third conductive plate 301: third main surface 302: third back surface 32: substrate 33: main surface bonding layer 35: insulating layer 41: first semiconductor element 411: first source electrode 412: first gate electrode 413: first drain electrode 414: first source sense electrode 42: second semiconductor element 421: second source electrode 423: second drain electrode 43, 44: wire 51: First input terminal 511: First bent portion 512: First extending portion 52: Second input terminal 521: Second bent portion 522: Second extending portion 53: Output terminal 531: Third bent portion 532: Third extending portion 55, 56: First control terminal 57, 58: Second control terminal 61: First conductive bonding material 611: First base layer 612: First layer 613: Second layer 62: Second conductive bonding material 621: Second base layer 622: Third layer 623: Fourth layer 63: First metal portion 631: Fifth layer 632: Sixth layer 64: Second metal portion 641: Seventh layer 642: Eighth layer 7: Sealing resin 71: Resin main surface 72: Resin back surface 731: Resin first side surface 732: Resin second side surface 733: Resin third side surface 734: Resin fourth side surface 75: Recess 81: First substrate 811: First insulating layer 812: First metal layer 812A: First section 812B: Second section 813: Second metal layer 82: Second substrate 821: Second insulating layer 822: Third metal layer 823: Fourth metal layer 83: First insulating layer 84: Conductive plate 85: Second insulating layer 86: Conductive plate D1: Diode L1: First dimension L2: Second dimension L3: Third dimension Q1: Switching function section T1: Thickness (first conductive plate) T2: Thickness (second conductive plate) T3: Thickness (third conductive plate) x: First direction y: Second direction z: Thickness direction

Claims

1. A first conductive plate having a first main surface facing one side in the thickness direction and a first back surface facing the other side; A second conductive plate having a second main surface facing one side in the thickness direction and a second back surface facing the other side, and being spaced apart from the first conductive plate in a first direction orthogonal to the thickness direction; A third conductive plate facing the other side in the thickness direction, having a third main surface facing the first main surface and the second main surface, and a third back surface facing one side in the thickness direction, and being spaced apart from the first conductive plate and the second conductive plate on one side in the thickness direction; A first semiconductor element disposed between the first main surface and the third main surface in the thickness direction and having a switching function; A second semiconductor element disposed between the third main surface and the second main surface in the thickness direction and having a switching function; A first input terminal that is electrically connected to the first conductive plate and is the positive electrode; A second input terminal that is electrically connected to the second conductive plate and is the negative electrode; An output terminal that is electrically connected to the third conductive plate; A semiconductor device comprising a sealing resin that covers at least a part of each of the first conductive plate, the second conductive plate, and the third conductive plate, a part of each of the first input terminal, the second input terminal, and the output terminal, the first semiconductor element, and the second semiconductor element.

2. The semiconductor device according to claim 1, wherein, when viewed in the thickness direction, the area of the first conductive plate is larger than the area of the second conductive plate.

3. The semiconductor device according to claim 1 or 2, wherein the first back surface, the second back surface, and the third back surface are exposed from the sealing resin.

4. The semiconductor device according to claim 3, further comprising an insulating layer that covers each of the first back surface, the second back surface, and the third back surface.

5. The first back surface, the second back surface, and the third back surface are covered by the sealing resin, The semiconductor device according to claim 1 or 2, wherein the thermal conductivity of the sealing resin is 5 W / mK or more.

6. The sealing resin has a resin main surface facing one side in the thickness direction and a resin back surface facing the other side, A first dimension between the first back surface and the resin back surface in the thickness direction is smaller than the thickness of the first conductive plate, A second dimension between the second back surface and the resin back surface in the thickness direction is smaller than the thickness of the second conductive plate, The semiconductor device according to claim 5, wherein a third dimension between the third back surface and the resin main surface in the thickness direction is smaller than the thickness of the third conductive plate.

7. A first insulating layer disposed on the other side of the thickness direction with respect to the first back surface and overlapping the first back surface and the second back surface when viewed in the thickness direction; The semiconductor device according to claim 1 or 2, further comprising: a second insulating layer disposed on one side of the thickness direction with respect to the third back surface and overlapping the third back surface when viewed in the thickness direction.

8. The first input terminal has a first extending portion that is exposed from the encapsulating resin and extends in a second direction orthogonal to both the thickness direction and the first direction; The second input terminal has a second extending portion that is exposed from the encapsulating resin and extends in the second direction; The semiconductor device according to claim 1 or 2, wherein the output terminal has a third extending portion that is exposed from the encapsulating resin and extends in the second direction.

9. The first extending portion is located on one side of the second direction with respect to the first conductive plate and extends on one side of the second direction; The second extending portion is located on one side of the second direction with respect to the second conductive plate and extends on one side of the second direction; The semiconductor device according to claim 8, wherein the third extending portion is located on one side of the second direction with respect to the third conductive plate and extends on one side of the second direction.

10. The semiconductor device according to claim 9, wherein the first extending portion, the second extending portion, and the third extending portion overlap each other when viewed in the first direction.

11. Further comprising a first control terminal and a second control terminal for controlling the first semiconductor element and the second semiconductor element; The semiconductor device according to claim 8, wherein the encapsulating resin covers a part of each of the first control terminal and the second control terminal.

12. The first control terminal is spaced apart from the first conductive plate in the second direction and extends in the second direction; The semiconductor device according to claim 11, wherein the second control terminal is spaced apart from the third conductive plate in the second direction and extends in the second direction.

13. Further comprising a first conductive bonding material and a second conductive bonding material; The first semiconductor element has a first source electrode facing one side of the thickness direction and a first drain electrode facing the other side of the thickness direction. The second semiconductor element has a second source electrode facing the other side in the thickness direction and a second drain electrode facing one side in the thickness direction. The first conductive bonding material conductively bonds the first main surface and the first drain electrode. The semiconductor device according to claim 1 or 2, wherein the second conductive bonding material conductively bonds the third main surface and the second drain electrode.

14. A first metal portion interposed between the first source electrode and the third main surface and conducting the first source electrode and the third main surface; The semiconductor device according to claim 13, further comprising: a second metal portion interposed between the second source electrode and the second main surface and conducting the second source electrode and the second main surface.

15. The first conductive bonding material includes a first metal layer, a first layer interposed between the first metal layer and the first drain electrode and bonded in a state of being in direct contact with each other at the bonding interface with the first drain electrode, and a second layer interposed between the first metal layer and the first conductive plate and bonded in a state of being in direct contact with each other at the bonding interface with the first conductive plate. The semiconductor device according to claim 13, wherein the second conductive bonding material includes a second metal layer, a third layer interposed between the second metal layer and the second drain electrode and bonded in a state of being in direct contact with each other at the bonding interface with the second drain electrode, and a fourth layer interposed between the second metal layer and the third conductive plate and bonded in a state of being in direct contact with each other at the bonding interface with the third conductive plate.

16. Each of the first metal layer and the second metal layer contains aluminum. The semiconductor device according to claim 15, wherein each of the first layer, the second layer, the third layer and the fourth layer contains silver.

17. Each of the first conductive plate, the second conductive plate and the third conductive plate contains copper. The semiconductor device according to claim 1 or 2.