Semiconductor device

Abstract

This semiconductor device is equipped with a terminal, a signal substrate, a support conductor and an adhesive layer. The terminal includes a conductive cylindrical holder and a metal pin which is inserted into the holder. The signal substrate includes a wiring layer and an insulative substrate. The support conductor supports the wiring layer with the insulative substrate interposed therebetween. The adhesive layer is interposed between the support conductor and the signal substrate. The insulative substrate has a main surface and a rear surface which are separated from one another in the thickness direction of the signal substrate. The wiring layer is formed on the main surface and has the terminal secured thereto. The holder is joined to the wiring layer. The metal pin extends in the thickness direction. The adhesive layer electrically insulates the signal substrate and the support conductor from one another.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Conventionally, semiconductor devices including power switching elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors) have been known. Such semiconductor devices are installed in a variety of electronic devices, from industrial equipment to home appliances, information terminals, and automotive equipment. Patent Document 1 (Patent Document 1) discloses a conventional semiconductor device (power module). The power module described in Patent Document 1 includes a plurality of transistors, a main substrate, a signal substrate, and signal terminals. The plurality of transistors are mounted on the main substrate. The signal substrate is mounted on the main substrate. A signal wiring pattern is mounted on the signal substrate. The signal wiring pattern includes, for example, a gate signal wiring pattern and a source sense signal wiring pattern. The signal terminal is connected to the signal wiring pattern on the signal substrate. The signal terminal includes a gate terminal connected to the gate signal wiring pattern and a source sense terminal connected to the source sense signal wiring pattern.

[0003] JP 2015-126342 A

[0004] In a power module such as that described in Patent Document 1, if the signal board is arranged at an angle relative to the main board, there is a risk of poor bonding of the signal terminals to the signal board, variations in the positions of the signal terminals, etc. Therefore, such an angle of the signal board relative to the main board leads to a decrease in the reliability of the power module.

[0005] The present disclosure has been made in view of the above circumstances, and an object of the present disclosure is to provide a semiconductor device with improved reliability.

[0006] The semiconductor device provided by the present disclosure comprises a conductive cylindrical holder, a terminal including a metal pin inserted into the holder, a signal board including a wiring layer and an insulating substrate, a support conductor supporting the wiring layer via the insulating substrate, and an adhesive layer interposed between the support conductor and the signal board, wherein the insulating substrate has a main surface and a back surface spaced apart in the thickness direction of the signal board, the wiring layer is formed on the main surface and has the terminal fixed thereto, the holder is bonded to the wiring layer, the metal pin extends along the thickness direction, and the adhesive layer includes an insulating layer that electrically insulates the signal board and the support conductor.

[0007] According to the semiconductor device of the present disclosure, the reliability of the semiconductor device can be improved.

[0008] FIG. 1 is a perspective view showing a semiconductor device of the present disclosure. FIG. 2 is a perspective view of FIG. 1 with multiple wires and a resin member omitted. FIG. 3 is a perspective view of FIG. 2 with a first conductive member omitted. FIG. 4 is a plan view showing a semiconductor device of the present disclosure. FIG. 5 is a view showing the resin member in imaginary lines in the plan view of FIG. 4. FIG. 6 is a right side view showing the semiconductor device of the present disclosure with the resin member in imaginary lines. FIG. 7 is a left side view showing the semiconductor device of the present disclosure with the resin member in imaginary lines. FIG. 8 is a view showing the plan view of FIG. 5 with the resin member and first conductive member omitted and the second conductive member in imaginary lines. FIG. 9 is a right side view showing the semiconductor device of the present disclosure. FIG. 10 is a bottom view showing the semiconductor device of the present disclosure. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 5. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 5. FIG. 13 is a partially enlarged view of a portion of FIG. 12 . FIG. 14 is a partially enlarged view of a portion of FIG. 12 . FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 5 . FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 5 . FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 5 . FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 5 . FIG. 19 is an enlarged cross-sectional view of a main portion of a semiconductor device according to a first modified example of the present disclosure, which is an enlarged view of a portion of the cross section corresponding to FIG. 12 . FIG. 20 is an enlarged cross-sectional view of a main portion of a semiconductor device according to a second modified example of the present disclosure, which is an enlarged view of a portion of the cross section corresponding to FIG. 12 . FIG. 21 is an enlarged cross-sectional view of a main portion of a semiconductor device according to a third modified example of the present disclosure, which is an enlarged view of a portion of the cross section corresponding to FIG. 12 . FIG. 22 is an enlarged cross-sectional view of a main portion of a semiconductor device according to a fourth modified example of the present disclosure, which is an enlarged view of a portion of the cross section corresponding to FIG. 12 .

[0009] Preferred embodiments of the semiconductor device of the present disclosure will be described below with reference to the drawings. Hereinafter, identical or similar components will be designated by the same reference numerals, and redundant descriptions will be omitted. Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not intended to necessarily assign any order to their objects.

[0010] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an) object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an) object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on (an) object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an) object B" includes "a certain object A is in contact with a certain object B and is located on (an) object B" and "a certain object A is located on (an) object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "when viewed from a certain direction, an object A overlaps an object B" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B."

[0011] 1 to 18 show a semiconductor device A1 according to one embodiment of the present disclosure. The semiconductor device A1 includes a plurality of semiconductor elements 1, a support conductor 2, a support substrate 3, a plurality of power terminals 41 to 43, a plurality of control terminals 44, a signal substrate 5, an adhesive layer 6, a first conductive member 71, a second conductive member 72, a plurality of wires 73 to 76, a resin member 8, and a resin filling portion 88. The plurality of semiconductor elements 1 include a plurality of first switching elements 1A and a plurality of second switching elements 1B. The support conductor 2 includes a first conductive portion 2A and a second conductive portion 2B. The plurality of control terminals 44 include a plurality of first control terminals 45 and a plurality of second control terminals 46. The signal substrate 5 includes a first signal substrate 5A and a second signal substrate 5B. The adhesive layer 6 includes a first adhesive body 6A and a second adhesive body 6B.

[0012] For convenience of explanation, the three mutually orthogonal directions are referred to as the x-direction, y-direction, and z-direction. As an example, the z-direction is the thickness direction of the semiconductor device A1. The x-direction is the left-right direction in the plan view of the semiconductor device A1 (see FIG. 4). The y-direction is the up-down direction in the plan view of the semiconductor device A1 (see FIG. 4). In the following explanation, "plan view" refers to the view in the z-direction. Note that terms such as "upper," "lower," "upper side," "lower side," "top surface," and "bottom surface" indicate the relative positional relationship of each component, etc. in the z-direction, and do not necessarily define the relationship with the direction of gravity. The x-direction is an example of a "first direction."

[0013] Each of the multiple semiconductor elements 1 is an electronic component that is central to the function of the semiconductor device A1. The constituent material of each of the multiple semiconductor elements 1 is a semiconductor material primarily composed of, for example, SiC (silicon carbide). This semiconductor material is not limited to SiC and may be Si (silicon), GaN (gallium nitride), C (diamond), or the like. Each semiconductor element 1 is, for example, a power semiconductor chip with a switching function, such as a MOSFET (metal oxide semiconductor field effect transistor). In this embodiment, each semiconductor element 1 is illustrated as a MOSFET, but is not limited thereto and may be other transistors such as an IGBT (insulated gate bipolar transistor). Each semiconductor element 1 is the same element. Each semiconductor element 1 is, for example, an n-channel MOSFET, but may also be a p-channel MOSFET.

[0014] The multiple semiconductor elements 1 include multiple first switching elements 1A and multiple second switching elements 1B. As shown in FIG. 8 , the semiconductor device A1 includes four first switching elements 1A and four second switching elements 1B, but the number of first switching elements 1A and the number of second switching elements 1B are not limited to this configuration. The number of first switching elements 1A and the number of second switching elements 1B can be changed as appropriate depending on the performance required of the semiconductor device A1. The number of first switching elements 1A and the number of second switching elements 1B may be equal to or different from each other. The number of first switching elements 1A and the number of second switching elements 1B is determined by the current capacity handled by the semiconductor device A1.

[0015] The semiconductor device A1 is configured as, for example, a half-bridge switching circuit. In this case, a plurality of first switching elements 1A form an upper arm circuit of the semiconductor device A1, and a plurality of second switching elements 1B form a lower arm circuit of the semiconductor device A1. In the upper arm circuit, the plurality of first switching elements 1A are connected in parallel with each other, and in the lower arm circuit, the plurality of second switching elements 1B are connected in parallel with each other. Furthermore, each first switching element 1A and each second switching element 1B are connected in series.

[0016] 13 and 14, each of the semiconductor elements 1 (the first switching elements 1A and the second switching elements 1B) has a main surface 10a and a back surface 10b. In each semiconductor element 1, the main surface 10a and the back surface 10b are spaced apart in the z direction. The main surface 10a faces the z2 direction, and the back surface 10b faces the z1 direction.

[0017] As shown in FIGS. 8 , 12 , 13 , and 17 , the multiple first switching elements 1A are each mounted on a support conductor 2 (first conductive portion 2A). In the example shown in FIG. 8 , the multiple first switching elements 1A are arranged, for example, in the y direction and spaced apart from one another. Each of the multiple first switching elements 1A is conductively joined to the support conductor 2 (first conductive portion 2A) via a conductive bonding material 19. The conductive bonding material 19 is, for example, solder, a metal paste material, or a sintered metal. When each first switching element 1A is joined to the first conductive portion 2A, the element back surface 10b faces the support conductor 2 (first conductive portion 2A).

[0018] As shown in FIGS. 8 , 12 , 14 , and 16 , the second switching elements 1B are mounted on a support conductor 2 (second conductive portion 2B). In the example shown in FIG. 8 , the second switching elements 1B are arranged, for example, in the y direction and spaced apart from one another. Each of the second switching elements 1B is conductively joined to the support conductor 2 (second conductive portion 2B) via a conductive bonding material 19. When each second switching element 1B is joined to the second conductive portion 2B, the element back surface 10b faces the support conductor 2 (second conductive portion 2B). As can be seen from FIG. 8 , the first switching elements 1A and the second switching elements 1B overlap when viewed in the x direction. However, the first switching elements 1A and the second switching elements 1B do not necessarily have to overlap when viewed in the x direction.

[0019] As shown in FIGS. 8 , 13 , and 14 , each of the semiconductor elements 1 (the first switching elements 1A and the second switching elements 1B) has a first principal surface electrode 11, a second principal surface electrode 12, a third principal surface electrode 13, and a back surface electrode 15. The configurations of the first principal surface electrode 11, the second principal surface electrode 12, the third principal surface electrode 13, and the back surface electrode 15, which will be described below, are common to all semiconductor elements 1. The first principal surface electrode 11, the second principal surface electrode 12, and the third principal surface electrode 13 are provided on the element's main surface 10 a. The first principal surface electrode 11, the second principal surface electrode 12, and the third principal surface electrode 13 are insulated by an insulating film (not shown). The back surface electrode 15 is provided on the element's back surface 10 b. The back surface electrode 15 covers the entire area (or substantially the entire area) of the element's back surface 10 b. The back surface electrode 15 is formed, for example, by Ag (silver) plating.

[0020] In an example in which each semiconductor element 1 is configured as a MOSFET, the first principal surface electrode 11 is, for example, a gate electrode to which a drive signal (e.g., gate voltage) for driving each semiconductor element 1 is input. The second principal surface electrode 12 is, for example, a source electrode through which a source current flows. The third principal surface electrode 13 is, for example, a source sense electrode, and is at the same potential as the second principal surface electrode 12. The third principal surface electrode 13 passes the same source current as the second principal surface electrode 12. The back surface electrode 15 is, for example, a drain electrode through which a drain current flows.

[0021] When a drive signal (gate voltage) is input to the first principal surface electrode 11 (gate electrode), each semiconductor element 1 switches between a conductive state and a cutoff state in response to the drive signal. This switching between the conductive state and the cutoff state is called a switching operation. In the conductive state, a forward current flows from the back surface electrode 15 (drain electrode) to the second principal surface electrode 12 (source electrode), and in the cutoff state, this forward current does not flow. The semiconductor device A1 converts a first power supply voltage (e.g., a DC voltage) into a second power supply voltage (e.g., an AC voltage) using the function of each semiconductor element 1. The first power supply voltage is input (applied) between a power terminal 41 and two power terminals 42, and the second power supply voltage is input (applied) to two power terminals 43.

[0022] 5 and 8, the semiconductor device A1 includes two thermistors 17. Each thermistor 17 is used as a sensor for detecting temperature.

[0023] The support conductor 2 supports the plurality of semiconductor elements 1 (the plurality of first switching elements 1A and the plurality of second switching elements 1B). The support conductor 2 is bonded to the support substrate 3 via a conductive bonding material 29. The conductive bonding material 29 is, for example, solder, a metal paste material, or a sintered metal. The bonding between the support conductor 2 and the support substrate 3 may be by solid-state diffusion rather than by bonding using the conductive bonding material 29. The support conductor 2 has, for example, a rectangular shape in a plan view. The support conductor 2, together with the first conductive member 71 and the second conductive member 72, constitutes a path for a main circuit current switched by the plurality of first switching elements 1A and the plurality of second switching elements 1B.

[0024] The support conductor 2 includes a first conductive portion 2A and a second conductive portion 2B. The first conductive portion 2A and the second conductive portion 2B are each a plate-shaped member made of metal. This metal is Cu (copper) or a Cu alloy. The first conductive portion 2A and the second conductive portion 2B, together with the plurality of power terminals 41-43, form conduction paths to the plurality of first switching elements 1A and the plurality of second switching elements 1B. The first conductive portion 2A and the second conductive portion 2B are each, for example, rectangular in plan view. The first conductive portion 2A and the second conductive portion 2B each have, for example, an x-direction dimension of 15 mm to 25 mm, a y-direction dimension of 30 mm to 40 mm, and a z-direction dimension of 1.0 mm to 5.0 mm (preferably approximately 2.0 mm). The dimensions of the first conductive portion 2A and the second conductive portion 2B are not limited to the above-mentioned numerical example and can be changed as appropriate depending on the specifications of the semiconductor device A1.

[0025] As shown in FIGS. 11 to 18 , the first conductive portion 2A and the second conductive portion 2B are each bonded to the support substrate 3 via a conductive bonding material 29. A plurality of first switching elements 1A are bonded to the first conductive portion 2A via a conductive bonding material 19. A plurality of second switching elements 1B are bonded to the second conductive portion 2B via a conductive bonding material 19. The first conductive portion 2A and the second conductive portion 2B are spaced apart in the x direction as shown in FIGS. 3 , 8 , 11 , 12 , and 15 . In the example shown in these figures, the first conductive portion 2A is positioned further in the x1 direction than the second conductive portion 2B. The first conductive portion 2A and the second conductive portion 2B overlap when viewed in the x direction.

[0026] The supporting conductor 2 (each of the first conductive portion 2A and the second conductive portion 2B) has a main surface 201 and a back surface 202. The main surface 201 and the back surface 202 are spaced apart in the z direction, as shown in FIGS. 11 to 18 . The main surface 201 faces the z2 direction, and the back surface 202 faces the z1 direction. The back surface 202 faces the supporting substrate 3.

[0027] The support substrate 3 supports the support conductors 2. The support substrate 3 is formed, for example, of a DBC (Direct Bonded Copper) substrate. Alternatively, the support substrate 3 may be formed, for example, of a DBA (Direct Bonded Aluminum) substrate. The support substrate 3 includes an insulating layer 31, a first metal layer 32, and a second metal layer 33.

[0028] The insulating layer 31 is made of, for example, a ceramic having excellent thermal conductivity. Examples of such ceramic include AlN (aluminum nitride), SiN (silicon nitride), AlO (aluminum oxide), and ZTA (zirconia-reinforced alumina). The insulating layer 31 may be made of an insulating resin instead of ceramic. The insulating layer 31 has, for example, a rectangular shape in a plan view.

[0029] The first metal layer 32 is formed on the upper surface (surface facing the z2 direction) of the insulating layer 31. The constituent material of the first metal layer 32 includes, for example, Cu. The constituent material may include Al (aluminum) instead of Cu. The first metal layer 32 includes a first portion 32A and a second portion 32B. The first portion 32A and the second portion 32B are spaced apart in the x direction. The first portion 32A is located on the x1 direction side of the second portion 32B. The first portion 32A is joined to the first conductive portion 2A and supports the first conductive portion 2A. The second portion 32B is joined to the second conductive portion 2B and supports the second conductive portion 2B. The first portion 32A and the second portion 32B are each, for example, rectangular in plan view.

[0030] The second metal layer 33 is formed on the lower surface (surface facing the z1 direction) of the insulating layer 31. The constituent material of the second metal layer 33 is the same as the constituent material of the first metal layer 32. The lower surface (surface facing the z1 direction) of the second metal layer 33 is exposed from the resin member 8, as shown in FIGS. 10 to 18 . Alternatively, the lower surface of the second metal layer 33 may be covered with the resin member 8. In a configuration in which the lower surface of the second metal layer 33 is exposed from the resin member 8, a heat dissipation member (e.g., a heat sink) (not shown) or the like can be attached to the lower surface. In a plan view, the second metal layer 33 overlaps both the first portion 32A and the second portion 32B.

[0031] Each of the power terminals 41 to 43 is made of a metal plate. The metal plate is made of, for example, Cu or a Cu alloy. In the example shown in Figures 1 to 5, 8 and 10, the semiconductor device A1 includes one power terminal 41, two power terminals 42 and two power terminals 43.

[0032] The first power supply voltage is applied between the power terminal 41 and the two power terminals 42. The power terminal 41 is, for example, a terminal (P terminal) connected to the positive pole of a DC power supply, and the two power terminals 42 are, for example, terminals (N terminals) connected to the negative pole of the DC power supply. Alternatively, the power terminal 41 may be an N terminal and the two power terminals 42 may each be a P terminal. In this case, the wiring inside the package may be appropriately changed in accordance with the change in terminal polarity. The second power supply voltage is applied to the two power terminals 43. The two power terminals 43 are output terminals that output voltages (the second power supply voltages) converted by the switching operations of the multiple first switching elements 1A and the multiple second switching elements 1B. Each of the multiple power terminals 41 to 43 includes a portion covered by the resin member 8 and a portion exposed from the resin member 8.

[0033] As shown in Figures 8, 12, and 15, the power terminal 41 is formed integrally with the first conductive portion 2A. Alternatively, the power terminal 41 may be separated from the first conductive portion 2A and conductively joined to the first conductive portion 2A. As shown in Figure 8, the power terminal 41 is located in the x2 direction relative to the multiple semiconductor elements 1 and the first conductive portion 2A (support conductor 2). The insulating layer 31 is electrically connected to the first conductive portion 2A and, via the first conductive portion 2A, to the back electrodes 15 (drain electrodes) of the multiple first switching elements 1A. The power terminal 41 is an example of a "first power terminal."

[0034] As shown in Figures 8 and 11 , each of the two power terminals 42 is spaced apart from the first conductive portion 2A. A second conductive member 72 is joined to each of the two power terminals 42. As shown in Figure 8 , each of the two power terminals 42 is located further in the x2 direction than the multiple semiconductor elements 1 and the first conductive portion 2A (support conductor 2). Each of the two power terminals 42 is electrically connected to the second conductive member 72 and is electrically connected to the second main surface electrodes 12 (source electrodes) of the multiple second switching elements 1B via the second conductive member 72. Each power terminal 42 is an example of a "second power terminal."

[0035] The power terminal 41 and the two power terminals 42 each protrude from the resin member 8 in the x2 direction. The power terminal 41 and the two power terminals 42 are spaced apart from each other. The two power terminals 42 are located on opposite sides of the power terminal 41 in the y direction. As can be seen from FIGS. 6, 7, and 9, the power terminal 41 and the two power terminals 42 overlap each other when viewed in the y direction.

[0036] As shown in FIGS. 8 and 11 , the two power terminals 43 are each formed integrally with, for example, the second conductive portion 2B. Alternatively, the two power terminals 43 may be separated from the second conductive portion 2B and conductively joined to the second conductive portion 2B. As shown in FIG. 8 , the two power terminals 43 are each located further in the x1 direction than the multiple semiconductor elements 1 and the second conductive portion 2B (support conductor 2). Each power terminal 43 is electrically connected to the first conductive portion 2A and, via the first conductive portion 2A, to the back electrode 15 (drain) of each second switching element 1B. The number of power terminals 43 is not limited to two and may be, for example, one or three or more. For example, when there is one power terminal 43, it is preferably connected to the center portion of the second conductive portion 2B in the y direction. Each power terminal 43 is an example of a “third power terminal.”

[0037] The control terminals 44 are pin-shaped terminals for controlling the driving of the semiconductor elements 1 (the first switching elements 1A and the second switching elements 1B). The control terminals 44 are, for example, press-fit terminals. The z-direction dimension of each of the control terminals 44 is, for example, 10 mm to 30 mm (15.8 mm, for example). The z-direction dimension of the control terminal 44 is the length from the lower end (the end on the z1 direction side) of a holder 441 (described below) to the upper end (the end on the z2 direction side) of a metal pin 442 (described below). As shown in FIGS. 1 and 4 , the control terminals 44 include a plurality of first control terminals 45 and a plurality of second control terminals 46. The first control terminals 45 are used to control the first switching elements 1A. The second control terminals 46 are used to control the second switching elements 1B.

[0038] As shown in Fig. 4, the multiple first control terminals 45 are arranged at intervals in the y direction. The multiple first control terminals 45 are fixed to the signal board 5 (first signal board 5A). As shown in Figs. 5 to 7 and 12, the multiple first control terminals 45 are located in the x direction between the multiple first switching elements 1A and the multiple power terminals 41, 42. As shown in Figs. 1 and 4, the multiple first control terminals 45 include a first drive terminal 45A and multiple first detection terminals 45B to 45E.

[0039] The first drive terminal 45A is a terminal (gate terminal) for inputting a drive signal for the plurality of first switching elements 1A. A first drive signal for driving the plurality of first switching elements 1A is input to the first drive terminal 45A (for example, a gate voltage is applied).

[0040] The first detection terminal 45B is a terminal (source sense terminal) for detecting source signals of the multiple first switching elements 1A. The first detection terminal 45B outputs a first detection signal for detecting the conduction state of the multiple first switching elements 1A. For example, the first detection terminal 45B detects, as the first detection signal, a voltage (a voltage corresponding to a source current) applied to the second principal surface electrode 12 (source electrode) of the first switching element 1A.

[0041] The first detection terminal 45C and the first detection terminal 45D are terminals that are each electrically connected to one of the two thermistors 17. The one thermistor 17 is mounted on a first signal board 5A, which will be described later.

[0042] The first detection terminal 45E is a terminal (drain sense terminal) for detecting drain signals of the first switching elements 1A. The first detection terminal 45E detects a voltage (a voltage corresponding to a drain current) applied to each back electrode 15 (drain electrode) of the first switching elements 1A.

[0043] As shown in Fig. 4, the multiple second control terminals 46 are arranged at intervals in the y direction. The multiple second control terminals 46 are fixed to the signal board 5 (second signal board 5B). As shown in Figs. 5 to 7 and 12, the multiple second control terminals 46 are located in the x direction between the multiple second switching elements 1B and the multiple power terminals 43. As shown in Figs. 1 and 4, the multiple second control terminals 46 include a second drive terminal 46A and multiple second detection terminals 46B to 46E.

[0044] The second drive terminal 46A is a terminal (gate terminal) for inputting a drive signal for the plurality of second switching elements 1B. A second drive signal for driving the plurality of second switching elements 1B is input to the second drive terminal 46A (for example, a gate voltage is applied).

[0045] The second detection terminals 46B are terminals (source sense terminals) for detecting source signals of the plurality of second switching elements 1B. The plurality of second detection terminals 46B output second detection signals for detecting the conduction states of the plurality of second switching elements 1B. For example, the second detection terminals 46B detect, as the second detection signal, a voltage (a voltage corresponding to a source current) applied to the second principal surface electrode 12 (source electrode) of the second switching element 1B.

[0046] The second detection terminal 46C and the second detection terminal 46D are terminals that are respectively electrically connected to the other of the two thermistors 17. The other thermistor 17 is mounted on a second signal board 5B, which will be described later.

[0047] The second detection terminal 46E is a terminal (drain sense terminal) for detecting drain signals of the second switching elements 1B. The second detection terminal 46E detects a voltage (a voltage corresponding to a drain current) applied to each back electrode 15 (drain electrode) of the second switching elements 1B.

[0048] Each of the plurality of control terminals 44 (the plurality of first control terminals 45 and the plurality of second control terminals 46 ) includes a holder 441 and a metal pin 442 .

[0049] The holder 441 is made of a conductive material. As shown in FIGS. 13 and 14 , the holder 441 is bonded to the signal board 5 (first metal layer 52 described below) via a conductive bonding material 449. The holder 441 includes a cylindrical portion, an upper flange, and a lower flange. The upper flange is connected to the upper end of the cylindrical portion in the z direction (direction z2), and the lower flange is connected to the lower end of the cylindrical portion in the z direction (direction z1). A metal pin 442 is inserted through at least the upper flange and the cylindrical portion of the holder 441. The holder 441 is covered with a resin member 8.

[0050] The metal pin 442 is a rod-shaped member extending in the z direction. The metal pin 442 is supported by being press-fitted into the holder 441. The metal pin 442 is electrically connected to the signal board 5 (a first metal layer 52 described below) at least via the holder 441. As shown in FIGS. 13 and 14 , when the lower end (the end on the z1 direction side) of the metal pin 442 is in contact with the conductive bonding material 449 inside the insertion hole of the holder 441, the metal pin 442 is electrically connected to the signal board 5 also via the conductive bonding material 449.

[0051] The signal substrate 5 supports a plurality of control terminals 44. The signal substrate 5 is interposed between the support conductor 2 and each control terminal 44 in the z direction. The thickness of the signal substrate 5 (dimension in the thickness direction z) is, for example, 0.5 mm or more and 1.0 mm or less. The dimension in the thickness direction z of each control terminal 44 is 20 times or more and 30 times or less the thickness of the signal substrate 5 (dimension in the thickness direction z). The signal substrate 5 includes a first signal substrate 5A and a second signal substrate 5B.

[0052] 5, 12, and 13, the first signal substrate 5A is disposed on the first conductive portion 2A and supports a plurality of first control terminals 45. The first signal substrate 5A is adhered to the first conductive portion 2A via an adhesive layer 6 (first adhesive body 6A) as shown in FIGS.

[0053] 5, 12, and 14, the second signal substrate 5B is disposed on the second conductive portion 2B and supports a plurality of second control terminals 46. As shown in FIGS. 12, 14, and 15, the second signal substrate 5B is adhered to the second conductive portion 2B via an adhesive layer 6 (second adhesive body 6B).

[0054] The signal substrates 5 (each of the first signal substrate 5A and the second signal substrate 5B) are formed of, for example, a DBC substrate. The signal substrate 5 has an insulating substrate 51, a first metal layer 52, and a second metal layer 53 stacked on top of each other. Unless otherwise specified, the insulating substrate 51, the first metal layer 52, and the second metal layer 53 described below are common to the first signal substrate 5A and the second signal substrate 5B.

[0055] The insulating substrate 51 is made of, for example, ceramic. Examples of such ceramics include AlN, SiN, and Al2O3. The insulating substrate 51 has, for example, a rectangular shape in a plan view. As shown in FIGS. 13 and 14 , the insulating substrate 51 has a main surface 51a and a back surface 51b. The main surface 51a and the back surface 51b are spaced apart in the z direction. The main surface 51a faces the z2 direction, and the back surface 51b faces the z1 direction. The back surface 51b faces the supporting conductor 2.

[0056] As shown in Figures 13 and 14, the second metal layer 53 is formed on the back surface 51b of the insulating substrate 51. The second metal layer 53 is adhered to the support conductor 2 via an adhesive layer 6. The second metal layer 53 of the first signal substrate 5A is adhered to the first conductive portion 2A via a first adhesive 6A described below, and the second metal layer 53 of the second signal substrate 5B is adhered to the second conductive portion 2B via a second adhesive 6B. The second metal layer 53 is made of, for example, Cu or a Cu alloy. The second metal layer 53 is an example of a "metal layer".

[0057] As shown in FIGS. 13 and 14 , the first metal layer 52 is formed on the main surface 51 a of the insulating substrate 51. The plurality of control terminals 44 are provided upright on the first metal layer 52. The first metal layer 52 of the first signal substrate 5A has a plurality of first control terminals 45 provided upright, and the first metal layer 52 of the second signal substrate 5B has a plurality of second control terminals 46 provided upright. The first metal layer 52 is made of, for example, Cu or a Cu alloy. As shown in FIG. 8 , the first metal layer 52 includes a plurality of wiring layers 521 to 526. The plurality of wiring layers 521 to 526 are spaced apart and insulated from one another.

[0058] 8 , a plurality of wires 73 are bonded to the wiring layer 521, and the wiring layer 521 is electrically connected to the first principal surface electrodes 11 (gate electrodes) of the semiconductor elements 1 via the respective wires 73. The wiring layer 521 of the first signal substrate 5A is electrically connected to the first principal surface electrodes 11 of the respective first switching elements 1A via the respective wires 73. The wiring layer 521 of the second signal substrate 5B is electrically connected to the first principal surface electrodes 11 of the respective second switching elements 1B via the respective wires 73.

[0059] 8 , a plurality of wires 75 are joined to the wiring layer 526, and the wiring layer 526 is electrically connected to the wiring layer 521 via the wires 75. The wiring layer 526 of the first signal substrate 5A is electrically connected to the first principal surface electrodes 11 (gate electrodes) of the first switching elements 1A via the wires 75, the wiring layer 521 of the first signal substrate 5A, and the wires 73. The wiring layer 526 of the second signal substrate 5B is electrically connected to the first principal surface electrodes 11 (gate electrodes) of the second switching elements 1B via the wires 75, the wiring layer 521 of the second signal substrate 5B, and the wires 73. A first drive terminal 45A is joined to the wiring layer 526 of the first signal substrate 5A, and a second drive terminal 46A is joined to the wiring layer 526 of the second signal substrate 5B.

[0060] 8 , a plurality of wires 74 are bonded to the wiring layer 522, and the wiring layer 522 is electrically connected to the third principal surface electrode 13 (source sense electrode) of each semiconductor element 1 via the respective wires 74. The wiring layer 522 of the first signal substrate 5A is electrically connected to the third principal surface electrode 13 (source sense electrode) of each first switching element 1A via the respective wires 74. The wiring layer 522 of the second signal substrate 5B is electrically connected to the third principal surface electrode 13 (source sense electrode) of each second switching element 1B via the respective wires 74. The first detection terminal 45B is bonded to the wiring layer 522 of the first signal substrate 5A, and the second detection terminal 46B is bonded to the wiring layer 522 of the second signal substrate 5B.

[0061] As shown in Fig. 8, the thermistor 17 is bonded to the wiring layer 523 and the wiring layer 524. As shown in Fig. 8, the first detection terminal 45C and the first detection terminal 45D are bonded to the wiring layer 523 and the wiring layer 524 of the first signal substrate 5A, respectively. The second detection terminal 46C and the second detection terminal 46D are bonded to the wiring layer 523 and the wiring layer 524 of the second signal substrate 5B, respectively.

[0062] Wires 76 are bonded to the wiring layer 525, and the wiring layer 525 is electrically connected to the support conductors 2 via the wires 76. As shown in Fig. 8 , the wiring layer 525 of the first signal substrate 5A is electrically connected to the first conductive portion 2A via the wires 76. The wiring layer 525 of the second signal substrate 5B is electrically connected to the second conductive portion 2B via the wires 76. A first detection terminal 45E is bonded to the wiring layer 525 of the first signal substrate 5A. A second detection terminal 46E is bonded to the wiring layer 525 of the second signal substrate 5B.

[0063] The signal board 5 may be a printed circuit board such as a glass epoxy board instead of a DBC board, and at least the wiring layers 521 to 526 are formed on the printed circuit board.

[0064] The adhesive layer 6 bonds the signal substrate 5 and the support conductor 2. The adhesive layer 6 is interposed between the signal substrate 5 and the support conductor 2 in the z direction. The adhesive layer 6 overlaps the signal substrate 5 in a plan view. The thickness (dimension in the z direction) of the adhesive layer 6 is, for example, not less than 20 μm and not more than 200 μm (85 μm in one example).

[0065] As shown in Figures 12 to 14, the adhesive layer 6 includes a first adhesive body 6A and a second adhesive body 6B. The first adhesive body 6A bonds the first signal substrate 5A and the first conductive portion 2A together. The first adhesive body 6A is interposed between the first signal substrate 5A and the first conductive portion 2A and overlaps the first signal substrate 5A in a planar view. The second adhesive body 6B bonds the second signal substrate 5B and the second conductive portion 2B together. The second adhesive body 6B is interposed between the second signal substrate 5B and the second conductive portion 2B and overlaps the second signal substrate 5B in a planar view.

[0066] 13 and 14, the adhesive layer 6 (each of the first adhesive body 6A and the second adhesive body 6B) includes an insulating layer 61 and a pair of adhesive layers 62, 63. Unless otherwise specified, the insulating layer 61 and the pair of adhesive layers 62, 63 described below are common to both the first adhesive body 6A and the second adhesive body 6B.

[0067] The insulating layer 61 is made of a resin material. Considering its heat resistance and insulating properties, polyimide is a preferable resin material. The insulating layer 61 of the first adhesive body 6A electrically insulates the first signal substrate 5A from the first conductive portion 2A, and the insulating layer 61 of the second adhesive body 6B electrically insulates the second signal substrate 5B from the second conductive portion 2B. The insulating layer 61 is, for example, a film. The insulating layer 61 may be a sheet or plate instead of a film. In this disclosure, a sheet refers to a material that is as soft as a film but thicker than a film. A plate refers to a material that is harder, less flexible, and thicker than a film or sheet. The definitions of film, sheet, and plate are not limited to these and may be modified as appropriate according to conventional classifications. The thickness of the insulating layer 61 (dimension in the thickness direction z) is 0.1% to 1.0% of the dimension in the thickness direction z of each control terminal 44. The thickness (dimension in thickness direction z) of insulating layer 61 is 20% to 75% of the thickness (dimension in thickness direction z) of adhesive layer 6. The thickness (dimension in z direction) of insulating layer 61 is, for example, 10 μm to 150 μm (25 μm in one example).

[0068] 13 and 14 , the insulating layer 61 includes a principal surface 61 a and a rear surface 61 b. The principal surface 61 a and the rear surface 61 b ​​are spaced apart in the z direction. The principal surface 61 a faces the z2 direction (upward in the z direction), and the rear surface 61 b ​​faces the z1 direction (downward in the z direction).

[0069] The pair of adhesive layers 62, 63 are formed on both sides of the insulating layer 61 in the z direction. Each of the pair of adhesive layers 62, 63 is made of, for example, a silicone-based adhesive or an acrylic-based adhesive. The thickness (dimension in the thickness direction z) of each of the pair of adhesive layers 62, 63 is 10% to 150% of the thickness (dimension in the thickness direction z) of the insulating layer 61. The thickness (dimension in the z direction) of each of the pair of adhesive layers 62, 63 is, for example, 5 μm to 50 μm (30 μm in one example).

[0070] 13 and 14 , the adhesive layer 62 is formed on the main surface 61 a. The adhesive layer 62 is interposed between the insulating layer 61 and the signal substrate 5 in the z direction. The adhesive layer 62 of the first adhesive body 6A is interposed between the insulating layer 61 of the first adhesive body 6A and the first signal substrate 5A in the z direction, and the adhesive layer 62 of the second adhesive body 6B is interposed between the insulating layer 61 of the second adhesive body 6B and the second signal substrate 5B in the z direction.

[0071] 13 and 14 , the adhesive layer 63 is formed on the back surface 61b. The adhesive layer 63 is interposed between the insulating layer 61 and the supporting conductor 2 in the z direction. The adhesive layer 63 of the first adhesive body 6A is interposed between the insulating layer 61 of the first adhesive body 6A and the first conductive portion 2A in the z direction, and the adhesive layer 63 of the second adhesive body 6B is interposed between the insulating layer 61 of the second adhesive body 6B and the second conductive portion 2B.

[0072] As can be understood from the above configuration, the adhesive layer 6 of the present disclosure is, for example, a double-sided adhesive tape. In the manufacturing process of the semiconductor device A1, the adhesive layer 6 is attached to, for example, a signal substrate 5 to which a plurality of control terminals 44 are bonded, and then attached to the support conductors 2. Note that the adhesive layer 6 does not have to be a double-sided adhesive tape, and any adhesive that temporarily melts, such as solder, when bonding two components together may be used. In other words, the adhesive layer 6 may be any adhesive that can bond two components together without melting.

[0073] The first conductive member 71 and the second conductive member 72, together with the support conductor 2, constitute a path for a main circuit current switched by the plurality of semiconductor elements 1 (the plurality of first switching elements 1A and the plurality of second switching elements 1B). The first conductive member 71 and the second conductive member 72 are spaced apart in the z2 direction from the respective main surfaces 201 of the first conductive portion 2A and the second conductive portion 2B and overlap the respective main surfaces 201 in a plan view. The first conductive member 71 and the second conductive member 72 are each made of, for example, a metal plate material. The metal is, for example, Cu or a Cu alloy. The first conductive member 71 and the second conductive member 72 are appropriately bent.

[0074] The first conductive member 71 electrically connects the plurality of first switching elements 1A to the second conductive portion 2B. As shown in FIGS. 5 and 8 , the first conductive member 71 is connected to the second main surface electrode 12 (source electrode) of each first switching element 1A and the second conductive portion 2B, thereby electrically connecting the second main surface electrode 12 of each first switching element 1A to the second conductive portion 2B. The first conductive member 71 forms a path for a main circuit current switched by the plurality of first switching elements 1A. As shown in FIGS. 5 , 8 , and 12 , the first conductive member 71 includes a main portion 711, a plurality of first connection ends 712, and a plurality of second connection ends 713.

[0075] The main portion 711 is located between the multiple first switching elements 1A and the second conductive portion 2B in the x direction. The main portion 711 is a strip-shaped portion extending in the y direction. As shown in FIG. 12 , the main portion 711 is located further in the z2 direction than the multiple first connection ends 712 and the multiple second connection ends 713. In this embodiment, as shown in FIGS. 5 , 8 , and 12 , the main portion 711 has multiple openings 711 a formed therein. Each of the multiple openings 711 a is a through-hole that penetrates the first conductive member 71 (main portion 711) in the z direction. The multiple openings 711 a are arranged at intervals in the y direction. The multiple openings 711 a do not overlap the second conductive member 72 in a plan view. The plurality of openings 711a are formed to facilitate the flow of the resin material between the upper side (z2 direction side) and the lower side (z1 direction side) near the main portion 711 (first conductive member 71) when injecting the fluid resin material to form the resin member 8. The shape of the main portion 711 is not limited to this configuration, and for example, the openings 711a may not be formed.

[0076] The first connection ends 712 and the second connection ends 713 are each connected to the main portion 711 and are disposed opposite the first switching elements 1A. As shown in FIG. 12 , the first connection ends 712 are each bonded to the second principal surface electrodes 12 of the first switching elements 1A via a conductive bonding material 719. The second connection ends 713 are each bonded to the second conductive portion 2B via a conductive bonding material 719. The conductive bonding material 719 may be, for example, solder, a metal paste material, or a sintered metal. In the examples shown in FIGS. 8 , 12 , 13 , and 17 , an opening 712 a is formed in each first connection end 712. Preferably, each opening 712 a is formed so as to overlap the center of each first switching element 1A in a plan view. As shown in FIGS. 12 , 13 , and 17 , the openings 712 a are, for example, through-holes that penetrate each first connection end 712 in the z-direction. The opening 712 a is used, for example, when positioning the first conductive member 71 with respect to the supporting conductor 2 .

[0077] In the illustrated example, the plurality of first connection ends 712 and the plurality of second connection ends 713 are connected to one another by the main portion 711, but instead of this configuration, the main portion 711 may be divided into a plurality of portions, and the divided portions may connect each of the plurality of first connection ends 712 and each of the plurality of second connection ends 713. In other words, a configuration may be provided in which one first conducting member 71 is provided for each of the plurality of first switching elements 1A.

[0078] As shown in FIG. 5 , the second conductive member 72 is connected to the second main surface electrode 12 (source electrode) of each second switching element 1B and the multiple power terminals 42, thereby electrically connecting the second main surface electrode 12 of each second switching element 1B and each power terminal 42. The second conductive member 72 forms a path for a main circuit current switched by the multiple second switching elements 1B. The second conductive member 72 has a maximum dimension in the x direction of, for example, 25 mm to 40 mm, and a maximum dimension in the y direction of, for example, 30 mm to 45 mm. As shown in FIG. 5 and other figures, the second conductive member 72 includes a pair of first wiring portions 721, second wiring portions 722, third wiring portions 723, and fourth wiring portions 724.

[0079] One of the pair of first wiring portions 721 is connected to one of the pair of power terminals 42, and the other of the pair of first wiring portions 721 is connected to the other of the pair of power terminals 42. As shown in FIG. 5 , each of the pair of first wiring portions 721 has a strip shape extending in the x direction in a plan view. The pair of first wiring portions 721 are spaced apart in the y direction and arranged parallel (or approximately parallel). As shown in FIGS. 5 and 11 , each of the pair of first wiring portions 721 includes a first end portion 721 a. Each first end portion 721 a is an end of each first wiring portion 721 on the x2 direction side. As shown in FIG. 11 , each first end portion 721 a is positioned further in the z1 direction than other portions of each first wiring portion 721. As shown in FIG. 11 , each first end portion 721 a is joined to each of the pair of power terminals 42 via a conductive bonding material 729. The conductive bonding material 729 is, for example, solder, metal paste, or sintered metal. 5, a plurality of notches are formed in each first wiring portion 721. The plurality of notches formed in each first wiring portion 721 are, for example, semicircular in plan view, and overlap the supporting conductor 2 in plan view.

[0080] As shown in FIG. 5 , the second wiring portion 722 is connected to both of the pair of first wiring portions 721. The second wiring portion 722 is sandwiched between the pair of first wiring portions 721 in the y direction. The second wiring portion 722 has a strip shape extending in the y direction in a plan view. As shown in FIG. 5 , the second wiring portion 722 overlaps with the plurality of second switching elements 1B. The second wiring portion 722 is connected to each of the second switching elements 1B. The second wiring portion 722 has a plurality of recessed regions 722a. As shown in FIG. 16 , each of the recessed regions 722a protrudes downward in the z direction (z1 direction) further than other portions of the second wiring portion 722. As shown in FIG. 16 , each recessed region 722a of the second wiring portion 722 and each second principal surface electrode 12 (source electrode) of each of the plurality of second switching elements 1B are joined via a conductive bonding material 729. 5 and 16, a slit is formed in each recessed region 722a. The slit is located at the center of each recessed region 722a in the y direction and extends in the x direction. Each recessed region 722a is made up of two parts separated in the y direction by the slit. Note that each recessed region 722a does not necessarily have to have a slit.

[0081] As shown in FIG. 5 , the third wiring portion 723 is connected to both of the pair of first wiring portions 721. The first wiring portion 721 is sandwiched between the pair of first wiring portions 721 in the y direction. The third wiring portion 723 has a strip shape extending in the y direction in a plan view. The third wiring portion 723 is spaced apart from the second wiring portion 722 in the x direction. The third wiring portion 723 is disposed parallel (or approximately parallel) to the second wiring portion 722. As shown in FIG. 5 , the third wiring portion 723 overlaps the multiple first switching elements 1A in a plan view. The third wiring portion 723 is located above each first connection end portion 712 of the first conductive member 71 in the z direction (z2 direction). The third wiring portion 723 overlaps the first connection end portion 712 in a plan view.

[0082] As shown in FIG. 5 , each of the multiple fourth wiring portions 724 is connected to both the second wiring portion 722 and the third wiring portion 723. Each fourth wiring portion 724 is sandwiched between the second wiring portion 722 and the third wiring portion 723 in the x direction. Each fourth wiring portion 724 has a strip shape extending in the x direction in a plan view. The multiple fourth wiring portions 724 are spaced apart in the y direction and arranged parallel (or approximately parallel) in a plan view. Furthermore, the multiple fourth wiring portions 724 are arranged parallel (or approximately parallel) to the pair of first wiring portions 721. One end in the x direction of each of the multiple fourth wiring portions 724 is connected to a portion of the third wiring portion 723 that overlaps between two first switching elements 1A adjacent in the y direction in a plan view. The other end in the x direction of each of the plurality of fourth wiring portions 724 is connected to a portion of the second wiring portion 722 that overlaps between two second switching elements 1B adjacent in the y direction in plan view. Each of the plurality of fourth wiring portions 724 overlaps, for example, the first conductive member 71 (main portion 711).

[0083] Each of the wires 73 to 76 is, for example, a bonding wire, and connects two separate portions together. The material of each of the wires 73 to 76 includes, for example, Au (gold), Al, or Cu.

[0084] The plurality of wires 73 are bonded to the wiring layer 521 and the first principal surface electrodes 11 (gate electrodes) of each semiconductor element 1, thereby providing electrical continuity therebetween. As shown in Fig. 8 , the plurality of wires 73 include wires bonded to the wiring layer 521 of the first signal substrate 5A and the first principal surface electrodes 11 of each first switching element 1A, and wires bonded to the wiring layer 521 of the second signal substrate 5B and the first principal surface electrodes 11 of each second switching element 1B.

[0085] The plurality of wires 74 are bonded to the wiring layer 522 and the third principal surface electrodes 13 (source sense electrodes) of each semiconductor element 1, thereby providing electrical continuity therebetween. As shown in Fig. 8 , the plurality of wires 74 include wires bonded to the wiring layer 522 of the first signal substrate 5A and the third principal surface electrodes 13 of each first switching element 1A, and wires bonded to the wiring layer 522 of the second signal substrate 5B and the third principal surface electrodes 13 of each second switching element 1B. In a configuration in which each semiconductor element 1 does not have a third principal surface electrode 13, the plurality of wires 74 are bonded to each second principal surface electrode 12 instead of each third principal surface electrode 13.

[0086] The plurality of wires 75 are bonded to the wiring layer 521 and the wiring layer 526 to provide electrical continuity therebetween. As shown in Fig. 8 , the plurality of wires 75 include wires bonded to the wiring layer 521 of the first signal substrate 5A and the wiring layer 526 of the first signal substrate 5A, and wires bonded to the wiring layer 521 of the second signal substrate 5B and the wiring layer 526 of the second signal substrate 5B.

[0087] The plurality of wires 76 are joined to the wiring layer 525 and the support conductor 2, and provide electrical continuity therebetween. As shown in Fig. 8 , the plurality of wires 76 include wires joined to the wiring layer 525 and the first conductive portion 2A of the first signal substrate 5A and wires joined to the wiring layer 525 and the second conductive portion 2B of the second signal substrate 5B.

[0088] The resin member 8 is a sealing material that protects the multiple semiconductor elements 1 (the multiple first switching elements 1A and the multiple second switching elements 1B). The resin member 8 covers the multiple semiconductor elements 1 (the multiple first switching elements 1A and the multiple second switching elements 1B), the support conductor 2 (the first conductive portion 2A and the second conductive portion 2B), the support substrate 3 (excluding the lower surface of the second metal layer 33), a portion of each of the multiple power terminals 41 to 43, a portion of each of the multiple control terminals 44, the signal substrate 5 (the first signal substrate 5A and the second signal substrate 5B), the adhesive layer 6 (the first adhesive body 6A and the second adhesive body 6B), the first conductive member 71, the second conductive member 72, and the multiple wires 73 to 76. The resin member 8 is made of, for example, black epoxy resin. The resin member 8 is formed, for example, by molding. The resin member 8 has, for example, a dimension in the x direction of about 35 mm to 60 mm, a dimension in the y direction of about 35 mm to 50 mm, and a dimension in the z direction of about 4 mm to 15 mm. These dimensions are the maximum sizes along each direction. The resin member 8 has a resin main surface 81, a resin back surface 82, and multiple resin side surfaces 831 to 834.

[0089] As shown in FIGS. 6 , 7 , 9 , 11 , 12 , and 15 to 18 , the resin main surface 81 and the resin back surface 82 are spaced apart in the z direction. The resin main surface 81 faces the z2 direction, and the resin back surface 82 faces the z1 direction. Multiple control terminals 44 (multiple first control terminals 45 and multiple second control terminals 46) protrude from the resin main surface 81. As shown in FIG. 10 , the resin back surface 82 has a frame shape surrounding the lower surface of the second metal layer 33 of the support substrate 3 in a plan view. The lower surface of the second metal layer 33 is exposed from the resin back surface 82 and is, for example, flush with the resin back surface 82. Multiple resin side surfaces 831 to 834 are each connected to both the resin main surface 81 and the resin back surface 82 and are sandwiched between them in the z direction. As shown in FIG. 4 and other figures, the resin side surface 831 and the resin side surface 832 are spaced apart in the x direction. Resin side surface 831 faces the x1 direction, and resin side surface 832 faces the x2 direction. Two power terminals 43 protrude from resin side surface 831, and multiple power terminals 41 and 42 protrude from resin side surface 832. As shown in Figure 4 and other figures, resin side surface 833 and resin side surface 834 are spaced apart in the y direction. Resin side surface 833 faces the y1 direction, and resin side surface 834 faces the y2 direction.

[0090] As shown in FIG. 4 , a plurality of recesses 832 a are formed on the resin side surface 832. Each recess 832 a is a portion recessed in the x direction in plan view. In plan view, the plurality of recesses 832 a include one formed between the power terminal 41 and one of the two power terminals 42 and one formed between the power terminal 41 and the other of the two power terminals 42. The plurality of recesses 832 a are provided to increase the creepage distance along the resin side surface 832 between the power terminal 41 and one of the two power terminals 42 and the creepage distance along the resin side surface 832 between the power terminal 41 and the other of the two power terminals 42.

[0091] As shown in FIGS. 11 and 12 , the resin member 8 has a plurality of first protrusions 851 , a plurality of second protrusions 852 , and a resin cavity 86 .

[0092] Each of the multiple first protrusions 851 protrudes in the z direction from the resin main surface 81. The multiple first protrusions 851 are arranged near the four corners of the resin member 8 in a plan view. A first protrusion end surface 851a is formed at the tip (end in the z2 direction) of each of the first protrusions 851. Each of the multiple first protrusions 851 has a first protrusion end surface 851a parallel (or approximately parallel) to the resin main surface 81. The multiple first protrusion end surfaces 851a are arranged on the same plane (x-y plane). Each of the first protrusions 851 has, for example, a bottomed, hollow truncated cone shape. The multiple first protrusions 851 are used as spacers when the semiconductor device A1 is mounted on a control circuit board or the like. The control circuit board is included in a device that uses power generated by the semiconductor device A1. 11 , each of the plurality of first protrusions 851 has a recess 851b and an inner wall surface 851c formed in the recess 851b. The shape of each of the first protrusions 851 may be columnar, and is preferably cylindrical. It is preferable that the shape of the recess 851b is cylindrical, and that the inner wall surface 851c is a single perfect circle in plan view.

[0093] The semiconductor device A1 may be fixed to the control circuit board or the like by a method such as screwing. In this case, a female screw thread may be formed on the inner wall surface 851c of the recess 851b of each first protrusion 851. An insert nut or the like may be embedded in the recess 851b of each first protrusion 851.

[0094] As shown in FIG. 12 and other figures, the multiple second protrusions 852 protrude in the z direction from the resin main surface 81. The multiple second protrusions 852 overlap the multiple control terminals 44 in a plan view. Each metal pin 442 of the multiple control terminals 44 protrudes from each second protrusion 852. Each second protrusion 852 has a truncated cone shape. Each second protrusion 852 covers the holder 441 and a portion of the metal pin 442 of each control terminal 44.

[0095] 11 , resin voids 86 extend in the z direction from resin main surface 81 to each main surface 201 of first conductive portion 2A and second conductive portion 2B. Resin voids 86 are tapered, and the cross-sectional area in a plane perpendicular to the z direction decreases from resin main surface 81 toward each main surface 201 in the z direction. Resin voids 86 are formed during molding of resin member 8, and are portions where resin member 8 is not formed during molding.

[0096] Resin voids 86 are formed, for example, when a presser member is present during molding of resin member 8 and prevents fluid resin material from filling the voids. The presser member applies a pressing force to each main surface 201 during molding, and is inserted into the notches formed in each first wiring portion 721 of second conductive member 72. This allows the presser member to press support conductor 2 (first conductive portion 2A and second conductive portion 2B) without interfering with second conductive member 72, thereby suppressing warping of support substrate 3 to which support conductor 2 is bonded.

[0097] 11 , the semiconductor device A1 includes a resin filling portion 88. The resin filling portion 88 is filled into the resin void portion 86 so as to fill the resin void portion 86. The resin filling portion 88 is made of, for example, an epoxy resin like the resin member 8, but may also be made of a resin material different from that of the resin member 8.

[0098] The semiconductor device A1 has the following functions and effects.

[0099] The semiconductor device A1 includes a signal substrate 5 including control terminals 44 and wiring layers 521-526, a support conductor 2, and an adhesive layer 6. Each control terminal 44 is fixed to each wiring layer 521-526. The support conductor 2 supports each wiring layer 521-526 via an insulating substrate 51. The adhesive layer 6 is interposed between the support conductor 2 and the signal substrate 5. The adhesive layer 6 includes an insulating layer 61 that electrically insulates the support conductor 2 from the signal substrate 5. In this configuration, the signal substrate 5 is supported by the support conductor 2 via the adhesive layer 6. In a different configuration, in which the signal substrate 5 is supported by the support conductor 2 via solder rather than the adhesive layer 6, solder is interposed between the signal substrate 5 and the support conductor 2. Because the solder is temporarily in a molten state during the joining process, it is difficult to control the thickness of the solder (dimension in the z-direction), and variations in the solder thickness may occur. As a result, the signal substrate 5 is tilted relative to the support conductor 2. In contrast, in the semiconductor device A1, an adhesive layer 6, which is different from solder, is interposed between the signal substrate 5 and the support conductor 2, thereby suppressing the above-mentioned thickness variations. This makes it possible to prevent the signal substrate 5 from being tilted relative to the support conductor 2. In other words, it is possible to prevent the wiring layers 521 to 526, to which the control terminals 44 are fixed, from being tilted relative to the support conductor 2. Therefore, the semiconductor device A1 can suppress poor connection of the control terminals 44 and suppress variations in the position of the control terminals 44, thereby improving reliability.

[0100] In the semiconductor device A1, each control terminal 44 includes a holder 441 and a metal pin 442. The holder 441 is bonded to the first metal layer 52 (each of the wiring layers 521 to 526) of the signal substrate 5, and the metal pin 442 extends along the z direction. That is, each control terminal 44 is configured as a pin-shaped terminal extending in the z direction. In this configuration, the inclination of the tip of each metal pin 442 relative to the support conductor 2 is greater than the inclination of the signal substrate 5 relative to the support conductor 2. In particular, if the dimension of each control terminal 44 in the thickness direction z is 20 times or more the dimension of the signal substrate 5 in the thickness direction z, this inclination of the tip of the metal pin 442 becomes more pronounced. For this reason, it is desirable to position the signal substrate 5 more parallel to the support conductor 2. Therefore, by adhering (sticking) the signal substrate 5 to the support conductor 2 with the adhesive layer 6, the inclination of each of the wiring layers 521 to 526 relative to the support conductor 2 is suppressed, which is effective in suppressing poor bonding of each of the control terminals 44 and suppressing variations in the position of each of the control terminals 44. Furthermore, by configuring each of the control terminals 44 as a pin-shaped terminal extending in the z direction, the semiconductor device A1 can be made smaller in plan view compared to a configuration in which each signal terminal extends along a plane perpendicular to the z direction, as in, for example, Patent Document 1. In other words, the semiconductor device A1 is suitable for achieving miniaturization in plan view.

[0101] In the semiconductor device A1, the insulating layer 61 of the adhesive layer 6 is film-like, and a pair of adhesive layers 62, 63 are formed on both sides of the insulating layer 61. In this configuration, the adhesive layer 6 is formed, for example, of double-sided adhesive tape. Therefore, in the manufacturing process of the semiconductor device A1, the signal substrate 5 can be easily attached to the support conductor 2 by simply attaching the signal substrate 5 to the support conductor 2 using the adhesive layer 6. Furthermore, because the adhesive layer 6 is configured to use the film-like insulating layer 61 as a base material, the dimension of the adhesive layer 6 in the z-direction can be reduced. As a result, even if variation occurs in the thickness of the adhesive layer 6, the variation is small. Therefore, because variation in the thickness of the adhesive layer 6 is suppressed, the semiconductor device A1 can suppress poor connection of each control terminal 44 and variation in the position of each control terminal 44.

[0102] In the semiconductor device A1, the insulating layer 61 of the adhesive layer 6 is made of, for example, polyimide. In the semiconductor device A1, heat is generated by the switching operations of the multiple semiconductor elements 1. This heat from each semiconductor element 1 is transferred to the supporting conductors 2. However, in the semiconductor device A1, the heat insulating properties of the insulating layer 61 can suppress the transfer of heat from the supporting conductors 2 to the signal substrate 5. As a result, the semiconductor device A1 can suppress the transfer of heat from each semiconductor element 1 to the wires 73 to 76 bonded to the signal substrate 5 (each wiring layer 521 to 526). In other words, the semiconductor device A1 can reduce the thermal load on each wire 73 to 76.

[0103] In the semiconductor device A1, the multiple first control terminals 45 are fixed to the wiring layers 521-526 of the first signal substrate 5A and are supported by the first conductive portion 2A via the first signal substrate 5A. The multiple first control terminals 45 are arranged on the x2 side of the multiple first switching elements 1A. The multiple second control terminals 46 are fixed to the wiring layers 521-526 of the second signal substrate 5B and are supported by the second conductive portion 2B via the second signal substrate 5B. The multiple second control terminals 46 are arranged on the x1 side of the multiple second switching elements 1B. The multiple first control terminals 45 and the multiple second control terminals 46 are arranged at intervals in the y direction. As a result, the multiple first control terminals 45 and the multiple second control terminals 46 are appropriately arranged in regions corresponding to the multiple first switching elements 1A constituting the upper arm circuit and the multiple second switching elements 1B constituting the lower arm circuit, respectively. Therefore, the semiconductor device A1 is preferable in terms of reducing the parasitic inductance component and achieving miniaturization.

[0104] Next, modified examples of the semiconductor device of the present disclosure will be described below.

[0105] 19 shows a semiconductor device A2 according to Modification 1. As shown in Fig. 19, the semiconductor device A2 differs from the semiconductor device A1 in that the signal substrates 5 (each of the first signal substrate 5A and the second signal substrate 5B) do not include the second metal layer 53.

[0106] In the semiconductor device A2, the signal substrate 5 does not include the second metal layer 53, and therefore the insulating substrate 51 is adhered to the support conductor 2 by the adhesive layer 6. That is, the insulating substrate 51 of the first signal substrate 5A is adhered to the first conductive portion 2A by the first adhesive body 6A, and the insulating substrate 51 of the second signal substrate 5B is adhered to the second conductive portion 2B by the second adhesive body 6B.

[0107] In the semiconductor device A2, as in the semiconductor device A1, an adhesive layer 6 other than solder is interposed between the signal substrate 5 and the support conductor 2, thereby preventing the wiring layers 521 to 526 from being tilted relative to the support conductor 2. Therefore, the semiconductor device A2 can prevent poor bonding of the control terminals 44 and variations in the position of the control terminals 44, thereby improving reliability.

[0108] In the semiconductor device A2, similar to the semiconductor device A1, the signal substrate 5 is bonded to the support conductor 2 by an adhesive layer 6. In a configuration different from the semiconductor device A2, in which solder is used instead of the adhesive layer 6, it would be difficult to bond the signal substrate 5 to the support conductor 2 unless the signal substrate 5 included the second metal layer 53, as in the semiconductor device A1. On the other hand, in the semiconductor device A2, similar to the semiconductor device A1, the adhesive layer 6 is formed by a pair of pressure-sensitive adhesive layers 62, 63 on both sides of the insulating substrate 51 in the z direction. This makes it possible to bond the signal substrate 5 to the support conductor 2 even if the insulating substrate 51 does not include the second metal layer 53. However, when the signal substrate 5 includes the second metal layer 53, it is more effective than when it does not include the second metal layer 53 in the following respects. First, warping of the signal substrate 5 is suppressed. Second, the second metal layer 53 increases the heat capacity of the signal substrate 5, thereby suppressing temperature rise of the signal substrate 5.

[0109] Fig. 20 shows a semiconductor device A3 according to a second modification. As shown in Fig. 20, the semiconductor device A3 differs from the semiconductor device A2 in that the signal substrates 5 (each of the first signal substrate 5A and the second signal substrate 5B) do not include the insulating substrate 51.

[0110] In the semiconductor device A3, the signal substrate 5 does not include the insulating substrate 51 and the second metal layer 53, and therefore the first metal layer 52 (each of the wiring layers 521 to 526) is adhered to the support conductor 2 by the adhesive layer 6. That is, the first metal layer 52 (each of the wiring layers 521 to 526) of the first signal substrate 5A is adhered to the first conductive portion 2A by the first adhesive body 6A, and the first metal layer 52 (each of the wiring layers 521 to 526) of the second signal substrate 5B is adhered to the second conductive portion 2B by the second adhesive body 6B.

[0111] In the semiconductor device A3, the adhesive layer 6, which is different from the solder, is interposed between each of the wiring layers 521 to 526 and the support conductor 2, thereby preventing each of the wiring layers 521 to 526 from being tilted relative to the support conductor 2. Therefore, the semiconductor device A3 can prevent poor bonding of each of the control terminals 44 and prevent variations in the position of each of the control terminals 44, thereby improving reliability.

[0112] In the semiconductor device A3, similarly to the semiconductor devices A1 and A2, the adhesive layer 6 includes an insulating layer 61. With this configuration, even if there is no insulating substrate 51 between each of the wiring layers 521 to 526 and the support conductor 2 (each of the first conductive portion 2A and the second conductive portion 2B), the adhesive layer 6 can insulate each of the wiring layers 521 to 526 from the support conductor 2 (each of the first conductive portion 2A and the second conductive portion 2B), while allowing the adhesive layer 6 to bond each of the wiring layers 521 to 526 to the support conductor 2 (each of the first conductive portion 2A and the second conductive portion 2B).

[0113] Fig. 21 shows a semiconductor device A4 according to Modification 3. As shown in Fig. 21 , the semiconductor device A4 differs from the semiconductor device A3 in that the adhesive layer 6 (each of the first adhesive body 6A and the second adhesive body 6B) does not include a pair of pressure-sensitive adhesive layers 62, 63.

[0114] In the semiconductor device A4, the insulating layer 61 is made of an adhesive insulating material in the adhesive layer 6 (each of the first adhesive body 6A and the second adhesive body 6B), thereby bonding the first metal layer 52 (each of the wiring layers 521 to 526) to the support conductor 2 and insulating the first metal layer 52 (each of the wiring layers 521 to 526) from the support conductor 2.

[0115] In the semiconductor device A4, similarly to the semiconductor device A3, an adhesive layer 6 other than solder is interposed between each of the wiring layers 521 to 526 and the support conductor 2, thereby preventing each of the wiring layers 521 to 526 from being tilted relative to the support conductor 2. Therefore, the semiconductor device A4 can prevent poor bonding of each of the control terminals 44 and variation in the position of each of the control terminals 44, thereby improving reliability.

[0116] In the example shown in FIG. 21, the semiconductor device A4 has a signal substrate 5 composed of a first metal layer 52 (each of the wiring layers 521 to 526). However, unlike this configuration, the signal substrate 5 (each of the first signal substrate 5A and the second signal substrate 5B) may further include an insulating substrate 51, as in the semiconductor device A2, or may further include an insulating substrate 51 and a second metal layer 53, as in the semiconductor device A1.

[0117] Fig. 22 shows a semiconductor device A5 according to a fourth modification. As shown in Fig. 22, the semiconductor device A5 differs from the semiconductor device A1 in that it does not include the supporting conductors 2 (the first conductive portion 2A and the second conductive portion 2B).

[0118] Because the semiconductor device A5 does not include a support conductor 2, the signal substrate 5 is adhered to the first metal layer 32 of the support substrate 3 by an adhesive layer 6. That is, the first signal substrate 5A is adhered to the first portion 32A by a first adhesive body 6A, and the second signal substrate 5B is adhered to the second portion 32B by a second adhesive body 6B. In this modification, the first portion 32A and the second portion 32B are examples of a "support conductor," the first portion 32A is an example of a "first conductive portion," and the second portion 32B is an example of a "second conductive portion." In this example, the power terminal 41 is conductively joined to the first portion 32A, and each power terminal 43 is conductively joined to the second portion 32B. Furthermore, a plurality of first switching elements 1A are mounted on the first portion 32A, and a plurality of second switching elements 1B are mounted on the second portion 32B.

[0119] In the semiconductor device A5, the adhesive layer 6, which is different from solder, is interposed between the signal substrate 5 and the first metal layer 32, thereby preventing the wiring layers 521 to 526 from being tilted relative to the first metal layer 32. Therefore, the semiconductor device A5 can prevent poor bonding of the control terminals 44 and variations in the positions of the control terminals 44, thereby improving reliability.

[0120] In each of the semiconductor devices A1 to A4, an example has been shown in which each control terminal 44 is fixed to each wiring layer 521 to 526, and the wiring layers 521 to 526 are supported by the support conductor 2 via the adhesive layer 6, but instead of this configuration, each power terminal 41 to 43 may be fixed to a wiring layer different from the wiring layers 521 to 526, and the wiring layer may be supported by the support conductor 2 via the adhesive layer 6. In this case, each power terminal 41 to 43 is an example of a "terminal."

[0121] In each of the semiconductor devices A1 to A5, the control terminals 44 (each of the plurality of first control terminals 45 and the plurality of second control terminals 46) are press-fit terminals including a holder 441 and a metal pin 442, but the present invention is not limited to this. The control terminals 44 (each of the plurality of first control terminals 45 and the plurality of second control terminals 46) may be metal plate materials. In this case, the metal plate materials (control terminals 44) may be bent to extend in the z direction, or may not be bent to extend along a plane perpendicular to the z direction (x-y plane).

[0122] The semiconductor device according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed in various ways. The present disclosure includes the embodiments described in the following appendices. Appendix 1. A semiconductor device comprising: a terminal including a conductive cylindrical holder and a metal pin inserted into the holder; a signal board including a wiring layer and an insulating substrate; a support conductor supporting the wiring layer via the insulating substrate; and an adhesive layer interposed between the support conductor and the signal board, wherein the insulating substrate has a main surface and a back surface spaced apart in a thickness direction of the signal board, the wiring layer is formed on the main surface and the terminal is fixed thereto, the holder is bonded to the wiring layer, the metal pin extends along the thickness direction, and the adhesive layer includes an insulating layer that electrically insulates the signal board and the support conductor. Appendix 2. The semiconductor device according to Appendix 1, wherein the adhesive layer further includes a pair of adhesive layers formed on both surfaces of the insulating layer in the thickness direction. Appendix 3. The semiconductor device according to Appendix 2, wherein the dimension in the thickness direction of each of the pair of adhesive layers is 10% to 150% of the dimension in the thickness direction of the insulating layer. Appendix 4. The semiconductor device according to any of Appendix 1 to Appendix 3, wherein the dimension in the thickness direction of the insulating layer is 0.1% to 1.0% of the dimension in the thickness direction of the terminal. Appendix 5. The semiconductor device according to any of Appendix 1 to Appendix 4, wherein the dimension in the thickness direction of the terminal is 20 to 30 times the dimension in the thickness direction of the signal substrate. Appendix 6. The semiconductor device according to any of Appendix 2 to Appendix 5, wherein the insulating layer is in a film form. Appendix 7. The semiconductor device according to Appendix 6, wherein the insulating layer includes a resin material. Appendix 8. The semiconductor device according to Appendix 7, wherein the resin material is polyimide. Appendix 9. The semiconductor device according to any of Appendix 1 to Appendix 8, wherein the insulating substrate includes ceramic. Appendix 10. 10. The semiconductor device according to claim 1, wherein the signal substrate includes a metal layer formed on the back surface, and the metal layer is adhered to the support conductor by the adhesive layer.Appendix 11. The semiconductor device according to Appendix 10, further comprising a semiconductor element electrically connected to the terminal, the semiconductor element being bonded to the support conductor. Appendix 12. The semiconductor device according to Appendix 11, wherein the terminal is a control terminal for controlling the semiconductor element. Appendix 13. The semiconductor device according to Appendix 12, wherein the support conductor includes a first conductive portion and a second conductive portion spaced apart from each other in a first direction orthogonal to the thickness direction, the semiconductor element includes a first switching element bonded to the first conductive portion and a second switching element bonded to the second conductive portion, the control terminal includes a first control terminal for controlling the first switching element and a second control terminal for controlling the second switching element, the signal substrate includes a first signal substrate supporting the first control terminal and a second signal substrate supporting the second control terminal, and the adhesive layer includes a first adhesive that bonds the first signal substrate to the first conductive portion and a second adhesive that bonds the second signal substrate to the second conductive portion. Appendix 14. The semiconductor device according to Supplementary Note 13, wherein the first control terminal includes a first drive terminal for driving the first switching element and a first detection terminal for detecting the conduction state of the first switching element, and the second control terminal includes a second drive terminal for driving the second switching element and a second detection terminal for detecting the conduction state of the second switching element.Supplementary Note 15. The semiconductor device according to Supplementary Note 13 or Supplementary Note 14, further comprising: a first power terminal and a second power terminal to which a first power supply voltage is applied; and a third power terminal to which a second power supply voltage is applied, wherein the first power terminal is connected to the first conductive portion and electrically connected to the first switching element via the first conductive portion, the second power terminal is electrically connected to the second switching element, and the third power terminal is connected to the second conductive portion and electrically connected to both the first switching element and the second switching element via the second conductive portion.Appendix 16. The semiconductor device according to Appendix 15, further comprising a resin member covering portions of the first control terminal and the second control terminal, the first signal substrate and the second signal substrate, and the first switching element and the second switching element, wherein each of the first control terminal and the second control terminal protrudes from the resin member in the thickness direction. Appendix 17. The semiconductor device according to Appendix 16, wherein the resin member has a resin main surface and a resin back surface spaced apart in the thickness direction, and a pair of resin side surfaces each sandwiched between the resin main surface and the resin back surface in the thickness direction, the pair of resin side surfaces being spaced apart from each other in the first direction, the first power terminal and the second power terminal protruding in the first direction from one of the pair of resin side surfaces, and the third power terminal protruding in the first direction from the other of the pair of resin side surfaces. Appendix 18. The semiconductor device according to any of Appendix 13 to Appendix 17, further comprising a support substrate supporting the first conductive portion and the second conductive portion.

[0123] A1 to A5: semiconductor device 1: semiconductor element 1A: first switching element 1B: second switching element 10a: element main surface 10b: element back surface 11: first main surface electrode 12: second main surface electrode 13: third main surface electrode 15: back surface electrode 17: thermistor 19: conductive bonding material 2: supporting conductor 2A: first conductive portion 2B: second conductive portion 201: main surface 202: back surface 29: conductive bonding material 3: supporting substrate 31: insulating layer 32: first metal layer 32A: first portion 32B: second portion 33: second metal layer 41, 42, 43: power terminal 44: control terminal 441: holder 442: metal pin 449: conductive bonding material 45: first control terminal 45A: first drive terminal 45B to 45E: first detection terminal 46: Second control terminal 46A: Second drive terminal 46B-46E: Second detection terminal 5: Signal board 5A: First signal board 5B: Second signal board 51: Insulating board 51a: Main surface 51b: Back surface 52: First metal layer 521-526: Wiring layer 53: Second metal layer 6: Adhesive layer 6A: First adhesive body 6B: Second adhesive body 61: Insulating layer 61a: Main surface 61b: Back surface 62, 63: Adhesive layers 71: First conductive member 711: Main portion 711a: Opening 712: First connecting end 712a: Opening 713: Second connecting end 719: Conductive bonding material 72: Second conductive member 721: First wiring portion 721a: First end 722: Second wiring portion 722a: Concave region 723: Third wiring portion 724: Fourth wiring portion 729: Conductive bonding material 73 to 76: Wire 8: Resin member 81: Resin main surface 82: Resin back surface 831 to 834: Resin side surface 832a: Concave portion 851: First protruding portion 851a: First protruding end surface 851b: Concave portion 851c: Inner wall surface 852: Second protruding portion 86: Resin void portion 88: Resin filled portion

Claims

1. A terminal including a cylindrical holder having conductivity and a metal pin inserted into the holder, A signal board including a wiring layer and an insulating substrate, A support conductor that supports the wiring layer via the insulating substrate, An adhesive layer interposed between the support conductor and the signal board, Characterized in that it comprises: The insulating substrate has a front surface and a back surface spaced apart in the thickness direction of the signal substrate, The wiring layer is formed on the front surface and the terminal is fixed thereto, The holder is joined to the wiring layer, The metal pin extends along the thickness direction, The adhesive layer includes an insulating layer that electrically insulates the signal substrate and the support conductor, a semiconductor device.

2. The semiconductor device according to claim 1, wherein the adhesive layer further includes a pair of adhesive layers formed on each of both surfaces in the thickness direction of the insulating layer.

3. The semiconductor device according to claim 2, wherein the dimension in the thickness direction of each of the pair of adhesive layers is 10% or more and 150% or less with respect to the dimension in the thickness direction of the insulating layer.

4. The semiconductor device according to claim 1, wherein the dimension in the thickness direction of the insulating layer is 0.1% or more and 1.0% or less with respect to the dimension in the thickness direction of the terminal.

5. The semiconductor device according to claim 1, wherein the dimension in the thickness direction of the terminal is 20 times or more and 30 times or less with respect to the dimension in the thickness direction of the signal substrate.

6. The semiconductor device according to claim 2, wherein the insulating layer is in the form of a film.

7. The semiconductor device according to claim 6, wherein the insulating layer contains a resin material.

8. The semiconductor device according to claim 7, wherein the resin material is polyimide.

9. The semiconductor device according to claim 1, wherein the insulating substrate contains ceramic.

10. The signal substrate includes a metal layer formed on the back surface, The semiconductor device according to claim 1, wherein the metal layer is adhered to the support conductor by the adhesive layer.

11. Further comprising a semiconductor element electrically connected to the terminal, The semiconductor device according to claim 10, wherein the semiconductor element is joined to the support conductor.

12. The semiconductor device according to claim 11, wherein the terminal is a control terminal for controlling the semiconductor element.

13. The support conductor includes a first conductive portion and a second conductive portion spaced apart from each other in a first direction orthogonal to the thickness direction, The semiconductor element includes a first switching element joined to the first conductive portion and a second switching element joined to the second conductive portion. The control terminal includes a first control terminal for controlling the first switching element and a second control terminal for controlling the second switching element. The signal substrate includes a first signal substrate that supports the first control terminal and a second signal substrate that supports the second control terminal. The semiconductor device according to claim 12, wherein the adhesive layer includes a first adhesive that adheres the first signal substrate to the first conductive portion and a second adhesive that adheres the second signal substrate to the second conductive portion.

14. The first control terminal includes a first drive terminal for driving the first switching element and a first detection terminal for detecting a conduction state of the first switching element. The semiconductor device according to claim 13, wherein the second control terminal includes a second drive terminal for driving the second switching element and a second detection terminal for detecting a conduction state of the second switching element.

15. A first power terminal and a second power terminal to which a first power supply voltage is applied; A third power terminal to which a second power supply voltage is applied; further comprising: The first power terminal is connected to the first conductive portion and is electrically connected to the first switching element via the first conductive portion. The second power terminal is electrically connected to the second switching element. The semiconductor device according to claim 13 or claim 14, wherein the third power terminal is connected to the second conductive portion and is electrically connected to both the first switching element and the second switching element via the second conductive portion.

16. further comprising a resin member that covers part of the first control terminal and the second control terminal, the first signal substrate and the second signal substrate, and the first switching element and the second switching element. The semiconductor device according to claim 15, wherein each of the first control terminal and the second control terminal protrudes in the thickness direction of the resin member.

17. The resin member has a resin front surface and a resin back surface that are spaced apart in the thickness direction, and a pair of resin side surfaces each sandwiched between the resin front surface and the resin back surface in the thickness direction. The pair of resin side surfaces are spaced apart from each other in the first direction. The first power terminal and the second power terminal protrude in the first direction from one of the pair of resin side surfaces. The semiconductor device according to claim 16, wherein the third power terminal protrudes in the first direction from the other of the pair of resin side surfaces.

18. The semiconductor device according to claim 13 or claim 14, further comprising a support substrate that supports the first conductive portion and the second conductive portion.