Photoelectric conversion device

Abstract

Provided is a photoelectric conversion device characterized by having an APD arranged on a semiconductor layer having a first surface and a second surface, and a first wiring structure in contact with the second surface, wherein: the APD has a first semiconductor region of a first conductivity type arranged at a first depth, a second semiconductor region of a second conductivity type arranged at a second depth that is greater than the first depth with respect to the second surface, a third semiconductor region provided in contact with an end section of the first semiconductor region in a plan view, a first wiring section connected to the first semiconductor region, and a second wiring section connected to the second semiconductor region; and a first pad for applying a first voltage to the photoelectric conversion device is provided to the first wiring structure; and at least a portion of a boundary section between an insulating film, which faces the first wiring section, and the second wiring section overlaps the third semiconductor region and does not overlap the first semiconductor region in a plan view.

Description

Photoelectric conversion device

[0001] The present invention relates to a photoelectric conversion device and a photoelectric conversion system.

[0002] There is a photoelectric conversion device in which a reflector is provided in a wiring layer to reflect incident light that has passed through a semiconductor substrate, thereby lengthening the optical path length of the incident light within the photoelectric conversion element and improving the quantum conversion efficiency. Patent Document 1 describes a single-photon avalanche diode (SPAD) that uses an anode wiring as a reflector. Similarly, Patent Document 2 describes a single-photon avalanche diode (SPAD) that has an extended anode wiring.

[0003] US Patent Application Publication No. 2020 / 0286946 US Patent Application Publication No. 2019 / 0181177

[0004] In the structure described in Patent Document 1, because the cathode wiring is located directly above the guard ring region, there is a problem that hot carriers are trapped near the cathode region, which changes the potential around the strong electric field region and causes the breakdown voltage to change over time. Also, in the structure described in Patent Document 2, there is a concern that the anode wiring located directly above the guard ring region causes the electric field to concentrate at the end of the cathode region, which increases the dark count rate (DCR).

[0005] The present invention has been made in view of the above-mentioned problems, and has as its object to reduce the change over time in breakdown voltage caused by injection of hot carriers into the semiconductor substrate interface while suppressing DCR.

[0006] One aspect of the present invention is a photoelectric conversion device having an avalanche diode arranged in a semiconductor layer having a first surface and a second surface opposite the first surface, and a first wiring structure in contact with the second surface, wherein the avalanche diode has a first semiconductor region of a first conductivity type arranged at a first depth, a second semiconductor region of a second conductivity type arranged at a second depth deeper than the first depth relative to the second surface, a third semiconductor region provided in contact with an end of the first semiconductor region in a planar view, a first wiring portion connected to the first semiconductor region, and a second wiring portion connected to the second semiconductor region, wherein a first pad for applying a first voltage to the photoelectric conversion device is provided in the first wiring structure, and in a planar view, at least a portion of a boundary between an insulating film facing the first wiring portion and the second wiring portion overlaps with the third semiconductor region but does not overlap with the first semiconductor region.

[0007] Another aspect of the present invention is a photoelectric conversion device having a plurality of avalanche diodes arranged in a semiconductor layer having a first surface and a second surface opposite to the first surface, and a first wiring structure in contact with the second surface, wherein the avalanche diodes include a first semiconductor region of a first conductivity type arranged at a first depth, a second semiconductor region of a second conductivity type arranged at a second depth that is deeper than the first depth relative to the second surface, and a second wiring structure provided in contact with an end of the first semiconductor region in a plan view. a third semiconductor region, a first wiring portion connected to the first semiconductor region, and a second wiring portion connected to the second semiconductor region, wherein a first pad for applying a first voltage to the photoelectric conversion device is provided in the first wiring structure, and in a planar view, at least a part of a line dividing an equidistant boundary between the first wiring portion and an insulating film and a boundary between the second wiring portion and the insulating film overlaps the third semiconductor region but does not overlap the first semiconductor region.

[0008] Yet another aspect of the present invention is a photoelectric conversion device having an avalanche diode arranged in a semiconductor layer having a first surface and a second surface opposite the first surface, and a first wiring structure in contact with the second surface, wherein the avalanche diode has: a first semiconductor region of a first conductivity type arranged at a first depth; an avalanche multiplication region formed between the first semiconductor region and a second semiconductor region of a second conductivity type arranged at a second depth that is deeper with respect to the second surface than the first depth; an electric field relaxation region surrounding the avalanche multiplication region in a planar view; a first wiring portion connected to the first semiconductor region; and a second wiring portion connected to the second semiconductor region, wherein a first pad for applying a first voltage to the photoelectric conversion device is provided in the first wiring structure, and in a planar view, at least a portion of a boundary between an insulating film facing the first wiring portion and the second wiring portion overlaps the electric field relaxation region.

[0009] Yet another aspect of the present invention is a photoelectric conversion device including an avalanche diode disposed in a semiconductor layer having a first surface and a second surface opposite to the first surface, and a first wiring structure in contact with the second surface, wherein the avalanche diode includes a first semiconductor region of a first conductivity type disposed at a first depth, an avalanche multiplication region formed between the first semiconductor region and a second semiconductor region of a second conductivity type disposed at a second depth deeper than the first depth relative to the second surface, A photoelectric conversion device comprising: an electric field relaxation region surrounding the avalanche multiplication region in a planar view; a first wiring portion connected to the first semiconductor region; and a second wiring portion connected to the second semiconductor region, wherein a first pad for applying a first voltage to the photoelectric conversion device is provided in the first wiring structure; and wherein, in a planar view, at least a portion of a line dividing an equidistant boundary between the first wiring portion and an insulating film and a boundary between the second wiring portion and the insulating film overlaps with the electric field relaxation region.

[0010] According to the present invention, it is possible to reduce the change over time in breakdown voltage caused by injection of hot carriers into the semiconductor substrate interface while suppressing DCR.

[0011] 1 is a schematic diagram of a photoelectric conversion device according to an embodiment; FIG. 2 is a schematic diagram of a PD substrate of a photoelectric conversion device according to an embodiment; FIG. 3 is a schematic diagram of a circuit board of a photoelectric conversion device according to an embodiment; FIG. 4 is a configuration example of a pixel circuit of a photoelectric conversion device according to an embodiment; FIG. 5 is a schematic diagram showing driving of a pixel circuit of a photoelectric conversion device according to an embodiment; FIG. 6 is a cross-sectional view of a photoelectric conversion element according to a first embodiment; FIG. 7 is a plan view of a photoelectric conversion element according to the first embodiment; FIG. 8 is a potential diagram of a photoelectric conversion element according to the first embodiment; FIG. 9 is a comparative example of a photoelectric conversion element according to the first embodiment; FIG. 10 is a potential diagram of a photoelectric conversion element according to the first embodiment; FIG. 11 is a potential diagram of a photoelectric conversion element according to the first embodiment; FIG. 12 is a cross-sectional view of a photoelectric conversion element according to a second embodiment; FIG. 13 is a plan view of a photoelectric conversion element according to the second embodiment; FIG. 14 is a cross-sectional view of a photoelectric conversion element according to a modification of the second embodiment; FIG. 15 is a cross-sectional view of a photoelectric conversion element according to a third embodiment; FIG. 16 is a plan view of a photoelectric conversion device according to the third embodiment; FIG. 17 is a plan view of a photoelectric conversion device according to the third embodiment; FIG. 18 is a cross-sectional view of a photoelectric conversion element according to a fourth embodiment. 10. A plan view of a photoelectric conversion element according to a fourth embodiment. A plan view of a photoelectric conversion element according to the fourth embodiment. A cross-sectional view of a photoelectric conversion element according to a fifth embodiment. A plan view of a photoelectric conversion element according to the fifth embodiment. A plan view of a photoelectric conversion element according to the fifth embodiment. A plan view of a photoelectric conversion element according to the sixth embodiment. A plan view of a photoelectric conversion element according to the seventh embodiment. A plan view of a photoelectric conversion element according to the eighth embodiment. A plan view of a photoelectric conversion element according to the ninth embodiment. A plan view of a photoelectric conversion element according to the tenth embodiment. A functional block diagram of a photoelectric conversion system according to an eleventh embodiment. A functional block diagram of a photoelectric conversion system according to a twelfth embodiment. A functional block diagram of a photoelectric conversion system according to the twelfth embodiment. A functional block diagram of a photoelectric conversion system according to a thirteenth embodiment. A functional block diagram of a photoelectric conversion system according to a fourteenth embodiment. A functional block diagram of a photoelectric conversion system according to a fifteenth embodiment. A functional block diagram of a photoelectric conversion system according to the fifteenth embodiment.

[0012] The embodiments shown below are intended to embody the technical concept of the present invention and are not intended to limit the present invention. The size and positional relationship of components shown in each drawing may be exaggerated for clarity. In the following description, the same components may be designated by the same reference numerals and their description may be omitted.

[0013] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, terms indicating specific directions or positions (for example, "upper," "lower," "right," "left," and other terms including these terms) will be used as necessary. The use of these terms is intended to facilitate understanding of the embodiments with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention.

[0014] In this specification, a planar view refers to a view from a direction perpendicular to the light incident surface of the semiconductor layer. A cross-sectional view refers to a surface perpendicular to the light incident surface of the semiconductor layer. When the light incident surface of the semiconductor layer is a rough surface when viewed microscopically, the planar view is defined based on the light incident surface of the semiconductor layer when viewed macroscopically.

[0015] In the following description, the anode of the avalanche photodiode (APD) is set to a fixed potential, and a signal is extracted from the cathode side. Therefore, the first conductivity type semiconductor region, which has majority carriers of charges of the same polarity as the signal charge, is an N-type semiconductor region, and the second conductivity type semiconductor region, which has majority carriers of charges of a polarity opposite to that of the signal charge, is a P-type semiconductor region. Note that the present invention also applies when the cathode of the APD is set to a fixed potential, and a signal is extracted from the anode side. In this case, the first conductivity type semiconductor region, which has majority carriers of charges of the same polarity as the signal charge, is a P-type semiconductor region, and the second conductivity type semiconductor region, which has majority carriers of charges of a polarity opposite to that of the signal charge, is an N-type semiconductor region. The following description will be given of a case where one node of the APD is set to a fixed potential, but the potentials of both nodes may fluctuate.

[0016] In this specification, when the term "impurity concentration" is simply used, it means the net impurity concentration minus the amount compensated by impurities of the opposite conductivity type. In other words, "impurity concentration" refers to the net doping concentration. A region where the concentration of P-type added impurities is higher than the concentration of N-type added impurities is a P-type semiconductor region. Conversely, a region where the concentration of N-type added impurities is higher than the concentration of P-type added impurities is an N-type semiconductor region.

[0017] A configuration common to each embodiment of a photoelectric conversion device and a driving method thereof according to the present invention will be described with reference to FIGS. 1 to 5. FIG.

[0018] FIG. 1 is a diagram showing the configuration of a stacked-type photoelectric conversion device 100 according to an embodiment of the present invention. The photoelectric conversion device 100 is configured by stacking and electrically connecting two substrates, a sensor substrate 11 and a circuit substrate 21. The sensor substrate 11 has a first semiconductor layer having a photoelectric conversion element 102 (described later) and a first wiring structure. The circuit substrate 21 has a second semiconductor layer having circuits such as a signal processing unit 103 (described later) and a second wiring structure. The photoelectric conversion device 100 is configured by stacking the second semiconductor layer, the second wiring structure, the first wiring structure, and the first semiconductor layer in this order. The photoelectric conversion device described in each embodiment is a back-illuminated photoelectric conversion device in which light is incident from a first surface and a circuit substrate is disposed on a second surface.

[0019] In the following description, the sensor substrate 11 and the circuit substrate 21 are described as diced chips, but are not limited to chips. For example, each substrate may be a wafer. Furthermore, each substrate may be stacked in the wafer state and then diced, or may be chipped and then the chips may be stacked and bonded.

[0020] The sensor substrate 11 has a pixel region 12 arranged thereon, and the circuit substrate 21 has a circuit region 22 arranged thereon for processing signals detected in the pixel region 12 .

[0021] 2 is a diagram showing an example of the arrangement of the sensor substrate 11. Pixels 101, each having a photoelectric conversion element 102 including an avalanche photodiode (hereinafter, referred to as an APD), are arranged in a two-dimensional array in a plan view to form a pixel region 12.

[0022] The pixel 101 is typically a pixel for forming an image, but when used for TOF (Time of Flight), it does not necessarily have to form an image. That is, the pixel 101 may be a pixel for measuring the time and amount of light that arrives.

[0023] 3 is a configuration diagram of the circuit board 21. It has a signal processing unit 103 that processes the electric charges photoelectrically converted by the photoelectric conversion element 102 in FIG. 2, a readout circuit 112, a control pulse generating unit 115, a horizontal scanning circuit unit 111, a signal line 113, and a vertical scanning circuit unit 110.

[0024] The photoelectric conversion element 102 in FIG. 2 and the signal processing unit 103 in FIG. 3 are electrically connected via connection wiring provided for each pixel.

[0025] The vertical scanning circuit section 110 receives the control pulses supplied from the control pulse generating section 115 and supplies the control pulses to each pixel. The vertical scanning circuit section 110 uses logic circuits such as a shift register and an address decoder.

[0026] The signal output from the photoelectric conversion element 102 of the pixel is processed by the signal processing unit 103. The signal processing unit 103 is provided with a counter, a memory, etc., and the memory holds digital values.

[0027] The horizontal scanning circuit unit 111 inputs a control pulse to the signal processing unit 103 to sequentially select each column in order to read out the signal from the memory of each pixel in which the digital signal is held.

[0028] A signal is output to the signal line 113 from the signal processing unit 103 of the pixel selected by the vertical scanning circuit unit 110 for the selected column.

[0029] The signal output to the signal line 113 is output via an output circuit 114 to a recording unit or a signal processing unit outside the photoelectric conversion device 100 .

[0030] 2, the photoelectric conversion elements in the pixel region may be arranged one-dimensionally. Furthermore, the effects of the present invention can be obtained even with a single pixel, and the case of a single pixel is also included in the present invention. The function of the signal processing unit does not necessarily need to be provided for each photoelectric conversion element. For example, a single signal processing unit may be shared by multiple photoelectric conversion elements, and signal processing may be performed sequentially.

[0031] 2 and 3 , a plurality of signal processing units 103 are arranged in a region overlapping the pixel region 12 in a plan view. A vertical scanning circuit unit 110, a horizontal scanning circuit unit 111, column circuits 112, output circuits 114, and a control pulse generating unit 115 are arranged so as to overlap between an end of the sensor substrate 11 and an end of the pixel region 12 in a plan view. In other words, the sensor substrate 11 has the pixel region 12 and a non-pixel region arranged around the pixel region 12, and the vertical scanning circuit unit 110, the horizontal scanning circuit unit 111, the column circuits 112, the output circuits 114, and the control pulse generating unit 115 are arranged in a region overlapping the non-pixel region in a plan view.

[0032] FIG. 4 is an example of a block diagram including the equivalent circuits of FIGS.

[0033] In FIG. 2, the photoelectric conversion element 102 having the APD 201 is provided on a sensor substrate 11 , and the other members are provided on a circuit board 21 .

[0034] The APD 201 generates charge pairs in response to incident light through photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the APD 201. A voltage VH (second voltage) higher than the voltage VL supplied to the anode is supplied to the cathode of the APD 201. A reverse bias voltage is supplied to the anode and cathode so that the APD 201 performs avalanche multiplication. With such a voltage supplied, the charge generated by the incident light undergoes avalanche multiplication, generating an avalanche current.

[0035] When a reverse bias voltage is supplied, there are two modes: Geiger mode, in which the anode and cathode are operated at a potential difference greater than the breakdown voltage, and linear mode, in which the anode and cathode are operated at a potential difference close to or less than the breakdown voltage.

[0036] An APD operated in Geiger mode is called a SPAD. For example, the voltage VL (first voltage) is −30 V, and the voltage VH (second voltage) is 1 V. The APD 201 may be operated in either linear mode or Geiger mode. A SPAD is preferable because the potential difference is larger than that of a linear mode APD, resulting in a more pronounced effect of withstanding voltage.

[0037] The quench element 202 is connected to a power supply that supplies voltage VH and the APD 201. The quench element 202 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication, suppressing the voltage supplied to the APD 201 and suppressing avalanche multiplication (quench operation). The quench element 202 also functions to return the voltage supplied to the APD 201 to voltage VH by flowing a current equivalent to the voltage drop caused by the quench operation (recharge operation).

[0038] The signal processing unit 103 has a waveform shaping unit 210, a counter circuit 211, and a selection circuit 212. In this specification, the signal processing unit 103 may have any one of the waveform shaping unit 210, the counter circuit 211, and the selection circuit 212.

[0039] The waveform shaping unit 210 shapes the potential change of the cathode of the APD 201 obtained when photons are detected, and outputs a pulse signal. For example, an inverter circuit is used as the waveform shaping unit 210. While Fig. 4 shows an example in which one inverter is used as the waveform shaping unit 210, a circuit in which multiple inverters are connected in series, or another circuit that has a waveform shaping effect, may also be used.

[0040] The counter circuit 211 counts the pulse signal output from the waveform shaping unit 210 and holds the count value. When a control pulse pRES is supplied via a drive line 213, the signal held in the counter circuit 211 is reset.

[0041] 3 via a drive line 214 (not shown in FIG. 3) in FIG. 4, and switches between electrical connection and disconnection between the counter circuit 211 and the signal line 113. The selection circuit 212 includes, for example, a buffer circuit for outputting a signal.

[0042] The electrical connection may be switched by disposing a switch such as a transistor between the quench element 202 and the APD 201 or between the photoelectric conversion element 102 and the signal processing unit 103. Similarly, the supply of the voltage VH or the voltage VL to the photoelectric conversion element 102 may be electrically switched using a switch such as a transistor.

[0043] In this embodiment, a configuration using the counter circuit 211 has been described. However, instead of the counter circuit 211, the photoelectric conversion device 100 may be configured to acquire pulse detection timing using a time-to-digital converter (hereinafter, referred to as TDC) and a memory. In this case, the generation timing of the pulse signal output from the waveform shaping unit 210 is converted into a digital signal by the TDC. To measure the timing of the pulse signal, a control pulse pREF (reference signal) is supplied to the TDC from the vertical scanning circuit unit 110 in FIG. 1 via a drive line. The TDC acquires, as a digital signal, a signal obtained by converting the input timing of the signal output from each pixel via the waveform shaping unit 210 into a relative time based on the control pulse pREF.

[0044] FIG. 5 is a diagram showing a schematic diagram of the relationship between the operation of the APD and the output signal.

[0045] Fig. 5(a) is a diagram excerpting the APD 201, quench element 202, and waveform shaping unit 210 of Fig. 4. Here, the input side of the waveform shaping unit 210 is referred to as node A, and the output side is referred to as node B. Fig. 5(b) shows the waveform change of node A in Fig. 5(a), and Fig. 5(c) shows the waveform change of node B in Fig. 5(a).

[0046] Between time t0 and time t1, a potential difference of VH-VL is applied to the APD 201 in FIG. 5A. When a photon is incident on the APD 201 at time t1, avalanche multiplication occurs in the APD 201, an avalanche multiplication current flows through the quench element 202, and the voltage at node A drops. When the amount of voltage drop further increases and the potential difference applied to the APD 201 decreases, avalanche multiplication in the APD 201 stops, as at time t2, and the voltage level at node A no longer drops below a certain value. Thereafter, between time t2 and time t3, a current that compensates for the voltage drop from voltage VL flows through node A, and at time t3, node A settles to its original potential level. At this time, the portion of the output waveform at node A that exceeds a certain threshold is shaped by the waveform shaping unit 210 and output as a signal at node B.

[0047] The arrangement of the signal lines 113, the column circuits 112, and the output circuits 114 is not limited to that shown in Fig. 3. For example, the signal lines 113 may be arranged to extend in the row direction, and the column circuits 112 may be arranged at the ends of the signal lines 113.

[0048] The photoelectric conversion devices of the respective embodiments will be described below.

[0049] First Embodiment A photoelectric conversion device according to a first embodiment will be described with reference to FIGS. 6 to 10B.

[0050] FIG. 6 is a cross-sectional view of two pixels of the photoelectric conversion element 102 of the photoelectric conversion device according to the first embodiment, taken in a direction perpendicular to the surface direction of the substrate, and corresponds to the AA' cross section in FIG. 7A.

[0051] The structure and function of the photoelectric conversion element 102 will be described. The photoelectric conversion element 102 has an N-type first semiconductor region 311, a third semiconductor region 313, a fifth semiconductor region 315, and a sixth semiconductor region 316. It also includes a P-type second semiconductor region 312, a fourth semiconductor region 314, a seventh semiconductor region 317, and a ninth semiconductor region 319.

[0052] 6, an N-type first semiconductor region 311 is formed near the surface facing the light incident surface, and an N-type third semiconductor region 313 is formed around it. A P-type second semiconductor region 312 is formed at a position overlapping the first semiconductor region and the second semiconductor region in a planar view. An N-type fifth semiconductor region 315 is further disposed at a position overlapping the second semiconductor region 312 in a planar view, and an N-type sixth semiconductor region 316 is formed around it.

[0053] The first semiconductor region 311 has a higher N-type impurity concentration than the third semiconductor region 313 and the fifth semiconductor region 315. A PN junction is formed between the P-type second semiconductor region 312 and the N-type first semiconductor region 311. By making the impurity concentration of the second semiconductor region 312 lower than that of the first semiconductor region 311, the entire region of the second semiconductor region 312 that overlaps the center of the first semiconductor region in a planar view becomes a depletion layer region. At this time, the potential difference between the first semiconductor region 311 and the second semiconductor region 312 is greater than the potential difference between the second semiconductor region 312 and the fifth semiconductor region 315. Furthermore, this depletion layer region extends to a portion of the first semiconductor region 311, and a strong electric field is induced in the extended depletion layer region. This strong electric field causes avalanche multiplication in the depletion layer region that extends to the portion of the first semiconductor region 311, and a current based on the amplified charge is output as signal charge. When light incident on the photoelectric conversion device 102 is photoelectrically converted and avalanche multiplication occurs in this depletion layer region (avalanche multiplication region), the generated charges of the first conductivity type are collected in the first semiconductor region 311 .

[0054] 6, the third semiconductor region 313 and the fifth semiconductor region 315 are formed to have approximately the same size, but the size of each semiconductor region is not limited to this. For example, the fifth semiconductor region 315 may be formed to be larger than the third semiconductor region 313 so that charges can be collected in the first semiconductor region 311 from a wider range.

[0055] Furthermore, the third semiconductor region 313 may be a P-type semiconductor region instead of an N-type semiconductor region. In this case, the impurity concentration of the third semiconductor region 313 is set lower than the impurity concentration of the second semiconductor region 312. If the impurity concentration of the third semiconductor region 313 is too high, an avalanche multiplication region will be formed between the third semiconductor region 313 and the first semiconductor region 311, and the DCR (Dark Count Rate) will increase.

[0056] A trench-based uneven structure 325 is formed on the light-incident surface of the semiconductor layer. The uneven structure 325 is surrounded by a P-type fourth semiconductor region 314 and scatters light incident on the photoelectric conversion element 102. Because incident light travels obliquely through the photoelectric conversion element, an optical path length equal to or greater than the thickness of the semiconductor layer 301 can be ensured, enabling photoelectric conversion of light with longer wavelengths than in a case where the uneven structure 325 is not formed. Furthermore, the uneven structure 325 prevents reflection of incident light within the substrate, thereby improving the photoelectric conversion efficiency of the incident light. Furthermore, by combining this with the extended anode wiring, a feature of the present invention, the anode wiring efficiently reflects light diffracted obliquely by the uneven structure 325, further improving near-infrared sensitivity. The uneven structure 325 is not an essential component of the present invention, and the effects of the present invention can be achieved even in a photoelectric conversion element without the uneven structure 325.

[0057] The fifth semiconductor region 315 and the uneven structure 325 are formed so as to overlap in a planar view. The area where the fifth semiconductor region 315 and the uneven structure 325 overlap in a planar view is larger than the area of ​​the portion of the fifth semiconductor region 315 that does not overlap with the uneven structure 325. Charges generated at a position far from the avalanche multiplication region formed between the first semiconductor region 311 and the fifth semiconductor region 315 take longer to travel to the avalanche multiplication region than charges generated at a position close to the avalanche multiplication region. This may increase timing jitter. By arranging the fifth semiconductor region 315 and the uneven structure 325 so as to overlap in a planar view, the electric field deep in the photodiode can be increased, and the collection time of charges generated at a position far from the avalanche multiplication region can be shortened, thereby reducing timing jitter.

[0058] Furthermore, the fourth semiconductor region 314 three-dimensionally covers the concave-convex structure, thereby suppressing the generation of thermally excited charges at the interface of the concave-convex structure, thereby suppressing the DCR of the photoelectric conversion element.

[0059] Pixels are separated by a pixel separation section 324 having a trench structure, and a P-type seventh semiconductor region 317 formed around the pixel separation section 324 separates adjacent photoelectric conversion elements by a potential barrier. Because the photoelectric conversion elements are also separated by the potential of the seventh semiconductor region 317, a trench structure such as the pixel separation section 324 is not essential for the pixel separation section. Even when a pixel separation section 324 having a trench structure is provided, its depth and position are not limited to the configuration shown in FIG. 6 . The pixel separation section 324 may be a deep trench isolation (DTI) that penetrates the semiconductor layer, or a DTI that does not penetrate the semiconductor layer. Metal may be embedded in the DTI to improve light-blocking performance. The pixel separation section 324 may be made of SiO, a fixed charge film, a metal member, Poly-Si, or a combination of these. The pixel separating portion 324 may be configured to surround the entire periphery of the photoelectric conversion element in a plan view, or may be configured only on the opposite side of the photoelectric conversion element. A voltage may be applied to the embedded member to induce charges at the trench interface, thereby suppressing DCR.

[0060] The distance from the pixel separation portion to the pixel separation portion of an adjacent pixel or the pixel located at the nearest position can also be considered to be the size of one photoelectric conversion element 102. For example, suppose a second avalanche diode is located between a first avalanche diode and a third avalanche diode. A first pixel separation portion is located between the first avalanche diode and the second avalanche diode, and a second pixel separation portion is located between the second avalanche diode and the third avalanche diode. The distance between this first pixel separation portion and the second pixel separation portion can also be considered to be the size of one photoelectric conversion element 102.

[0061] When the size of one photoelectric conversion element 102 is L, the distance d from the light incident surface to the avalanche multiplication region satisfies L√2 / 4<d<L×√2. When the size and depth of the photoelectric conversion element satisfy this relationship, the strength of the electric field in the depth direction near the first semiconductor region 311 becomes approximately the same as the strength of the electric field in the planar direction. Since the variation in the time required for charge collection can be suppressed, timing jitter can be improved.

[0062] A pinning film 321, a planarizing film 322, and a microlens 323 are further formed on the light incident surface side of the semiconductor layer. A filter layer (not shown) may also be disposed on the light incident surface side. The filter layer may be any of various optical filters such as a color filter, an infrared light cut filter, or a monochrome filter. The color filter may be an RGB color filter, an RGBW color filter, or the like.

[0063] A wiring structure including a conductor and an insulating film is provided on the surface of the semiconductor layer facing the light incident surface. The photoelectric conversion element 102 shown in FIG. 6 has, from the side closest to the semiconductor layer, an oxide film 341 and a protective film 342, and further has a wiring layer made of a conductor laminated thereon. An interlayer film 343, which is an insulating film, is provided between the wiring and the semiconductor layer and between the wiring layers. The protective film 342 is a film that protects the avalanche diode from plasma damage and metal contamination during etching. SiN, a nitride film, is generally used, but SiON, SiC, SiCN, etc. may also be used.

[0064] The cathode wiring 331A is connected to the first semiconductor region 311, and the anode wiring 331B supplies voltage to the seventh semiconductor region 317 via the ninth semiconductor region 319, which serves as an anode contact. In this embodiment, the cathode wiring 331A and the anode wiring 331B are formed in the same wiring layer. The wiring is made of a conductor containing a metal such as Cu or Al. In this cross section, the outer periphery of the cathode wiring is designated as 332A, and the inner periphery of the anode wiring facing 332A is designated as 332B. The dotted line 332C is an imaginary line that divides the distance between the outer periphery of the cathode wiring 332A and the inner periphery of the anode wiring 332B at an equal distance.

[0065] 7A and 7B are pixel plan views of two pixels of the photoelectric conversion device according to the first embodiment, where Fig. 7A is a plan view seen from a surface opposite to the light incident surface, and Fig. 7B is a plan view seen from the light incident surface side.

[0066] 7A , the first semiconductor region 311, the third semiconductor region 313, and the fifth semiconductor region 315 are circular and arranged concentrically. This structure suppresses localized electric field concentration at the edge of the strong electric field region between the first semiconductor region 311 and the second semiconductor region 312, thereby achieving the effect of reducing DCR. The shape of each semiconductor region is not limited to a circle, and may be, for example, a polygon with its center of gravity aligned.

[0067] The dotted lines on the first semiconductor region 311 and the third semiconductor region 313 indicate the ranges in which the cathode wiring 331A and the anode wiring 331B are provided in a plan view. The cathode wiring 331A is circular in a plan view, and its outer periphery 332A overlaps the first semiconductor region 311 in a plan view. The anode wiring 331B has a surface with a circular hole in its inner periphery, and the entire surface of 332B overlaps the third semiconductor region in a plan view. In other words, the boundary between the insulating film facing the cathode wiring 331A and the anode wiring 331B overlaps the third semiconductor region. In this case, a virtual line 332C equally dividing the space between the cathode wiring outer periphery 332A and the anode wiring inner periphery 332B overlaps the third semiconductor region 313, but does not overlap the first semiconductor region 311.

[0068] An avalanche multiplication region is formed between the first semiconductor region 311 and the second semiconductor region 312 in the depth direction, and an electric field relaxation region is provided to surround this avalanche multiplication region. The electric field relaxation region does not need to cover the entire periphery of the avalanche multiplication region; it need only cover a portion of the periphery of the avalanche multiplication region. The boundary between the insulating film facing the cathode wiring 331A and the anode wiring 331B overlaps this electric field relaxation region in a plan view. Alternatively, it can be said that an imaginary line 332C equally dividing the space between the cathode wiring outer periphery 332A and the anode wiring inner periphery 332B overlaps the electric field relaxation region.

[0069] 7A (the diagonal direction of the pixel), and is not formed in the cross section along the B-B' direction (the opposite side direction of the pixel). In the cross section along the B-B' direction, the ninth semiconductor region 319 is not formed, and instead the seventh semiconductor region 317 extends to the surface facing the light incident surface.

[0070] In FIG. 7B , the uneven structure 325 is formed in a lattice shape in a planar view. The uneven structure 325 is formed to overlap the first semiconductor region 311 and the fifth semiconductor region 315, and the center of gravity of the uneven structure 325 is contained within the avalanche multiplication region in a planar view. In the lattice-shaped trench structure shown in FIG. 7B , the trench depth at the trench intersection is deeper than the trench depth at the trench portion where the trench extends alone. However, the bottom of the trench at the trench intersection is located closer to the light incident surface than half the thickness of the semiconductor layer. Here, the trench depth is the depth from the second surface to the bottom, and can also be referred to as the depth of the recess of the uneven structure 325.

[0071] FIG. 8 is a potential diagram of the photoelectric conversion element 102 shown in FIG.

[0072] A dotted line 70 in FIG. 8 indicates the potential distribution of the line segment FF' in FIG. 6, and a solid line 71 in FIG. 8 indicates the potential distribution of the line segment EE' in FIG. 6. FIG. 8 shows the potential as seen from the perspective of electrons, which are the main carrier charges in the N-type semiconductor region. When the main carrier charges are holes, the relationship between high and low potentials is reversed. Furthermore, depth A (first depth) in FIG. 8 corresponds to height A in FIG. 6. Similarly, depth B (third depth) corresponds to height B, depth C corresponds to height C, and depth D (second depth) corresponds to height D.

[0073] 8, the potential height of the solid line 71 at depth A is A1, the potential height of the dotted line 70 is A2, the potential height of the solid line 71 at depth B is B1, and the potential height of the dotted line 70 is B2. Also, the potential height of the solid line 71 at depth C is C1, the potential height of the dotted line 70 is C2, and the potential height of the solid line 71 at depth D is D1, and the potential height of the dotted line 70 is D2.

[0074] 6 and 8, the potential height of the first semiconductor region 311 corresponds to A1, and the potential height near the center of the second semiconductor region 312 corresponds to B1. Furthermore, the potential height of the fifth semiconductor region 315 corresponds to A2, and the potential height of the outer edge of the second semiconductor region 312 corresponds to B2.

[0075] 8, the potential gradually decreases from depth D to depth C. Then, the potential gradually increases from depth C to depth B, and the potential reaches the B2 level at depth B. Furthermore, the potential decreases from depth B to depth A, and reaches the A2 level at depth A.

[0076] On the other hand, with respect to the solid line 71, the potential gradually decreases from depth D to depth C and from depth C to depth B, reaching a B1 level at depth B. Then, the potential sharply decreases from depth B to depth A, reaching a A1 level at depth A. At depth D, the potentials of the dotted line 70 and the solid line 71 are approximately the same height, and in the regions indicated by the line segments EE' and FF', there is a potential gradient that gradually decreases toward the second surface of the semiconductor layer 301. Therefore, charges generated in the photodetector move toward the second surface due to the gentle potential gradient.

[0077] In the avalanche diode of this embodiment, the P-type second semiconductor region 312 has a lower impurity concentration than the N-type first semiconductor region 311, and potentials are supplied to the first semiconductor region 311 and the second semiconductor region 312 such that they are reverse biased to each other. As a result, a depletion layer region is formed on the second semiconductor region 312 side. With this structure, the second semiconductor region 312 acts as a potential barrier for charges photoelectrically converted in the fourth semiconductor region 314, making it easier for the charges to be collected in the first semiconductor region 311.

[0078] In FIG. 6 , the second semiconductor region 312 is formed over the entire surface of the photoelectric conversion element. However, for example, the portion overlapping the first semiconductor region 311 in a plan view may be an N-type semiconductor region, without providing the second semiconductor region 312, which is a P-type semiconductor region. The impurity concentration of this N-type semiconductor region is set lower than the impurity concentration of the first semiconductor region 311. When an N-type semiconductor layer is used, the second semiconductor region 312 may be omitted from the portion overlapping the first semiconductor region 311 in a plan view. In this case, it is also possible to recognize that a fourth semiconductor region 314 having a slit is formed. In this case, due to the potential difference between the second semiconductor region 312 and the slit portion, the potential decreases from the line segment FF' to the line segment EE' at depth C in FIG. 6 . This facilitates the movement of charges photoelectrically converted in the fourth semiconductor region 314 toward the first semiconductor region 311. On the other hand, when the second semiconductor region 312 is formed over the entire surface as shown in Figure 6, the applied voltage to obtain the strong electric field required for avalanche multiplication can be lowered compared to when a slit is formed, and noise caused by the formation of a localized strong electric field region can be suppressed.

[0079] The charges that have moved to the vicinity of the second semiconductor region 312 are accelerated by the steep potential gradient from depth B to depth A of the solid line 71 in FIG. 8, that is, by the strong electric field, and are avalanche multiplied.

[0080] 6 and the P-type second semiconductor region 312, i.e., from depth B to depth A of the dotted line 70 in FIG. 8, the potential distribution is such that avalanche multiplication does not occur. Therefore, the charge generated in the fourth semiconductor region 314 can be counted as signal charge without increasing the area of ​​the strong electric field region (avalanche multiplication region) relative to the size of the photodiode. Note that although the fifth semiconductor region 315 has been described so far as having an N-type conductivity, it may also be a P-type semiconductor region as long as its concentration satisfies the above-mentioned potential relationship.

[0081] Furthermore, the charges photoelectrically converted in the second semiconductor region 312 flow into the fourth semiconductor region 314 due to the potential gradient from depth B to depth C of the dotted line 70 in FIG. 8. For the reasons described above, the fourth semiconductor region 314 is structured so that the charges easily move to the second semiconductor region 312. Therefore, the charges photoelectrically converted in the second semiconductor region 312 move to the first semiconductor region 311 and are detected as signal charges by avalanche multiplication. Therefore, the fourth semiconductor region 314 is sensitive to the charges photoelectrically converted in the second semiconductor region 312.

[0082] 3. In addition, dotted line 70 in FIG. 8 indicates the cross-sectional potential of line segment FF' in FIG. 3. In the dotted line 70, the intersection of height A and line segment FF' in FIG. 6 is designated A2, the intersection of height B and line segment FF' is designated B2, the intersection of height C and line segment FF' is designated C2, and the intersection of height D and line segment FF' is designated D2. Electrons photoelectrically converted in the fourth semiconductor region 314 in FIG. 6 move along the potential D2 to C2 in FIG. 8, but the area from C2 to B2 forms a potential barrier for the electrons, making them unable to overcome it. Therefore, the electrons move to near the center of the fourth semiconductor region 314 in FIG. 6, indicated by line segment EE'. The migrated electrons move along the potential gradient from C1 to B1 in FIG. 8, are avalanche-multiplied by the steep potential gradient from B1 to A1, and are detected as signal charges after passing through the first semiconductor region 311.

[0083] 6 moves along the potential gradient from potential B2 to C2 in FIG. 8. Then, as described above, it moves to the center of the fourth semiconductor region 314 shown by the line segment EE' in FIG. 6. Then, it is avalanche-multiplied by the steep potential gradient from B1 to A1. The avalanche-multiplied charge passes through the first semiconductor region 311 and is detected as signal charge.

[0084] Here, a strong electric field is applied around the first semiconductor region, which causes an imbalance in the thermal state between the sensor substrate and the carriers, resulting in the generation of hot carriers. Hot carriers are trapped in trap sites around the cathode region near the wiring layer. As the number of trapped hot carriers increases over time, the potential near the cathode region and the electric field strength in the strong electric field region also change over time, raising concerns about changes in the breakdown voltage over time.

[0085] The problems and effects of this embodiment will be explained using the comparative cross-sectional view of photoelectric conversion element 102 shown in Fig. 9 and the potential distribution and electric field strength distribution near the wiring layer in each of the comparative cross-sectional views of Fig. 9 shown in Fig. 10A and Fig. 10B. The cross section of Fig. 9 corresponds to the B-B' cross section of Fig. 7A, and Fig. 9(I) shows a case where the anode wiring is insufficiently extended, Fig. 9(II) shows a case where the anode wiring is appropriately extended, and Fig. 9(III) shows a case where the anode wiring is excessively extended.

[0086] As shown in Figure 9(I), if the imaginary line 332C that divides the distance between the cathode wiring outer periphery 332A and the anode wiring inner periphery 332B does not overlap the third semiconductor region, the anode wiring is not sufficiently extended, and the effect of suppressing the change in breakdown voltage over time cannot be obtained. On the other hand, if the anode wiring is extended so that the imaginary line 332C overlaps the first semiconductor region 311, as shown in Figure 9(III), the extension is excessive, and the electric field concentrates at the end of the first semiconductor region 311, increasing the DCR. Figure 9(II) shows a configuration having an anode wiring that is appropriately extended so that the imaginary line 332C overlaps the third semiconductor region but does not overlap the first semiconductor region 311.

[0087] 10A is a schematic diagram of the potential distribution along the ZZ' cross section in each cross section of FIG. 9, and FIG. 10B is a schematic diagram of the electric field strength distribution along the XX' cross section in each cross section of FIG.

[0088] To suppress changes in the breakdown voltage over time, it is desirable that the potential at height A in the Z-Z' cross section in the third semiconductor region 313 be higher than the potential at the location from height A to height Z. In other words, it is desirable that a potential barrier be formed at height A between Z-Z'. As shown in I to III in FIG. 10A , the closer the end 332B of the anode wiring 331B is to the center of the pixel, i.e., near the Z-Z' cross section, the more likely this potential arrangement is satisfied.

[0089] On the other hand, as shown in III of Figure 10B, if the anode wiring 331B is extended so that the end 332B of the anode wiring 331B overlaps the first semiconductor region 311 in plan view, electric field concentration is induced at the end of the first semiconductor region 311. The electric field concentrates at the end of the first semiconductor region 311, increasing the dark current and increasing the DCR. Therefore, it is desirable to design the anode wiring 331B with an appropriate extension amount, as shown in Figure 9 (II).

[0090] In this way, by suitably extending the anode wiring, it is possible to reduce the change in breakdown voltage over time while suppressing DCR. Furthermore, to further enhance the effect of suppressing the change in breakdown voltage over time, it is desirable to shorten the depthwise distance between the semiconductor layer and the anode wiring 331B. Specifically, the wiring layer on which the anode wiring 331B is provided is the layer among the multiple wiring layers that is as close as possible to the semiconductor layer, preferably the closest layer. Here, the multiple wiring layers refer to wiring layers that are arranged above the top surfaces of the contact plugs that connect the anode wiring 331A and the first semiconductor region. That is, in a direction perpendicular to the in-plane direction of the second surface of the semiconductor layer, the distance between the wiring layers constituting the multiple wiring layers and the second surface is configured to be greater than the distance between the portion of the contact plug farthest from the second surface (the top surface of the contact plug) and the second surface of the semiconductor layer.

[0091] Second Embodiment A photoelectric conversion device according to a second embodiment will be described with reference to FIG.

[0092] The following description will omit the parts that are common to the first embodiment, and will mainly focus on the parts that are different from the first embodiment. In this embodiment, the cathode wiring 331A and the anode wiring 331B are formed at different heights relative to the semiconductor layer.

[0093] FIG. 11 is a cross-sectional view of two pixels of the photoelectric conversion element 102 of the photoelectric conversion device according to the second embodiment, taken in a direction perpendicular to the surface direction of the substrate, and corresponds to the AA' cross section in FIG.

[0094] In the first embodiment, the cathode wiring 331A and the anode wiring 331B are formed in the same wiring layer. In this embodiment, the cathode wiring 331A and the anode wiring 331B are formed at different positions in the depth direction of the semiconductor layer. This makes it easier to ensure the distance between the cathode wiring 331A and the anode wiring 331B, and increases the degree of freedom in the wiring layout.

[0095] 12A and 12B are pixel plan views of two pixels of a photoelectric conversion device according to the second embodiment, where Fig. 12A is a plan view seen from a surface opposite to the light incident surface, and Fig. 12B is a plan view seen from the light incident surface side.

[0096] The dotted lines on the first semiconductor region 311 and the third semiconductor region 313 indicate the ranges in which the cathode wiring 331A and the anode wiring 331B are provided in a plan view. The cathode wiring 331A is polygonal in a plan view, and the anode wiring has a surface with a polygonal hole in its inner periphery. In FIG. 12B , the planar shape of the cathode wiring 331A and the inner periphery of the hole of the anode wiring 331B are similar in shape, but the shapes of the cathode wiring 331A and the anode wiring 331B are not limited to this. In this embodiment, the outer periphery 332A of the cathode wiring 331A entirely overlaps the third semiconductor region 331 in a plan view, but it may also partially or entirely overlap the first semiconductor region 311, for example. Furthermore, only a portion of the inner periphery 332B of the anode wiring 331B overlaps the third semiconductor region 313 in a planar view, but the shape and arrangement of 332B are not limited to this as long as the entire virtual line 332C is arranged to overlap the third semiconductor region 313 in a planar view.

[0097] (Modification of Second Embodiment) A modification of the second embodiment will be described with reference to FIG.

[0098] In this modification, the anode wiring 331B is formed of a Poly-Si wiring. A virtual line 332C that equally divides the space between the cathode wiring outer peripheral portion 332A and the anode wiring inner peripheral portion 332B overlaps the third semiconductor region 313 but does not overlap the first semiconductor region 311, which is common to the first and second embodiments.

[0099] By forming the anode wiring 331B from Poly-Si wiring, the distance between the semiconductor layer and the anode wiring 331B in the depth direction becomes short, which can enhance the effect of suppressing the change in breakdown voltage over time.

[0100] Third Embodiment A photoelectric conversion device according to a third embodiment will be described with reference to FIGS. 14, 15A, and 15B.

[0101] The description of the parts common to the first and second embodiments will be omitted, and the description will focus mainly on the parts different from the first embodiment. In this embodiment, a configuration will be described in which the effect of suppressing the change in breakdown voltage over time can be obtained even if the end of the anode wiring 331B and the third semiconductor region 313 do not overlap in a plan view.

[0102] 14 is a cross-sectional view of two pixels of the photoelectric conversion element 102 of the photoelectric conversion device according to this modification, taken in a direction perpendicular to the surface direction of the substrate, and corresponds to the A-A' cross section in Fig. 15A. The photoelectric conversion element 102 has a tenth semiconductor region 320 between the third semiconductor region 313 and the ninth semiconductor region 319, and an inner periphery 332B of the anode wiring 331B overlaps with the tenth semiconductor region 320 in a planar view.

[0103] As described in the first embodiment, the potential at height A of the third semiconductor region is affected by the potential of the anode wiring 331B. Approximately, it is considered that the influence of the potential of the anode wiring 331B reaches the Si interface up to the imaginary line 332C that is equidistant from the cathode wiring 331A and the anode wiring 331B. Therefore, even if the anode wiring 331B and the third semiconductor region 313 do not overlap in a planar view, the effect of suppressing the change in breakdown voltage over time can be obtained as long as at least a portion of the imaginary line 332C overlaps with the third semiconductor region in a planar view.

[0104] 15A and 15B are pixel plan views of two pixels of a photoelectric conversion device according to the third embodiment, in which Fig. 15A is a plan view seen from a surface opposite to the light incident surface, and Fig. 15B is a plan view seen from the light incident surface side.

[0105] In FIG. 15A, an inner periphery 332B of an anode wiring 331B does not overlap the third semiconductor region 313 in a plan view, and an imaginary line 332C entirely overlaps the third semiconductor region 313 in a plan view.

[0106] In the pixel according to this embodiment, in the cross section along the A-A' direction (the diagonal direction of the pixel), the seventh semiconductor region 317 and the ninth semiconductor region 319 extend from the light incident surface side to the surface opposite the light incident surface. On the other hand, in the cross section along the B-B' direction (the opposite side direction of the pixel), the seventh semiconductor region 317 does not extend to the surface opposite the light incident surface side, and the seventh semiconductor region 317 and the tenth semiconductor region 320 are separated from each other. By forming the tenth semiconductor region 320, dark charges generated at the corners of the pixel are collected in the first semiconductor region 311 by the lateral electric field, and are easily discharged without passing through the strong electric field region that induces avalanche multiplication. This suppresses DCR.

[0107] Fourth Embodiment A photoelectric conversion device according to a fourth embodiment will be described with reference to FIGS. 16, 17A, and 17B.

[0108] The following description will omit the parts that overlap with the first to third embodiments, and will mainly focus on the parts that are different from the first embodiment. In the first embodiment, the anode wiring is extended symmetrically, but in this embodiment, the anode wiring is extended only in a specific direction.

[0109] 16 is a cross-sectional view of two pixels of the photoelectric conversion element 102 of the photoelectric conversion device according to the second embodiment, taken in a direction perpendicular to the surface direction of the substrate, and corresponds to the A-A' cross section in Fig. 17A. In one direction, the anode wiring 331B satisfies the relationship in which the virtual line 332C and the third semiconductor region 313 overlap in plan view, but does not satisfy this relationship in another direction.

[0110] 17A and 17B are pixel plan views of two pixels of a photoelectric conversion device 102 according to the fourth embodiment. FIG. 17A is a plan view seen from the surface opposite the light incident surface, and FIG. 17B is a plan view seen from the light incident surface side. The cathode wiring 331A of the left photoelectric conversion device 102 extends to the right from the center of the photoelectric conversion device, and the cathode wiring 332A of the right photoelectric conversion device 102 extends to the left from the center of the photoelectric conversion device. The anode wiring 331B of each photoelectric conversion device 102 is common to both the left and right photoelectric conversion devices 102, and at least a portion of the inner periphery 332B has a hole overlapping with the third semiconductor region 313 of each of the left and right photoelectric conversion devices. The virtual line 332C partially overlaps with the third semiconductor region 313 in plan view.

[0111] With this configuration, the distance between the cathode wirings 331A of adjacent pixels can be shortened, facilitating miniaturization of pixels.

[0112] Fifth Embodiment A photoelectric conversion device according to a fifth embodiment will be described with reference to FIGS. 18, 19A, and 19B.

[0113] The explanation of the parts common to the first to fourth embodiments will be omitted, and the parts different from the first embodiment will be mainly explained.

[0114] 18 is a cross-sectional view perpendicular to the plane direction of the semiconductor layer of the photoelectric conversion element 102 of the photoelectric conversion device according to the fifth embodiment, and corresponds to the A-A' cross section in Fig. 19A. In the photoelectric conversion device according to this embodiment, the N-type first semiconductor region 311 occupies a larger proportion of the light receiving surface of the pixel, and the area of ​​the P-type second semiconductor region 312 relative to the light receiving surface of the pixel is smaller than in the photoelectric conversion device according to the first embodiment.

[0115] The incident light is avalanche multiplied in the avalanche multiplication region formed between the first semiconductor region 311 and the second semiconductor region 312. Therefore, when the pixel opening is designed so that the first semiconductor region 311 and the second semiconductor region 312 are exposed, the aperture ratio of the photoelectric conversion device according to this embodiment is smaller than the aperture ratios of the photoelectric conversion devices according to the first to fourth embodiments. By reducing the aperture ratio, the volume of the photoelectric conversion region where a signal can be detected can be reduced, thereby making it possible to reduce crosstalk.

[0116] Furthermore, the uneven structure 325 has a quadrangular pyramidal shape, with its cross section forming a triangle with the light incident surface as the base. Such uneven structure 325 can be formed by etching along the crystal plane, and therefore has high manufacturing stability.

[0117] In the photoelectric conversion device according to this embodiment, a high concentration of N is implanted into the surface of the first semiconductor region 311. This makes it easier to shield the influence of potential changes caused by hot carriers being injected into the surface of the first semiconductor region 311, and makes it easier to suppress changes in the breakdown voltage over time.

[0118] 19A and 19B are pixel plan views of two pixels of a photoelectric conversion device according to the fifth embodiment, in which Fig. 19A is a plan view seen from a surface opposite to the light incident surface, and Fig. 19B is a plan view seen from the light incident surface side.

[0119] 19A and 19B , the region of the first semiconductor region 311 that does not overlap with the second semiconductor region 312 in plan view serves as an electric field relaxation region, surrounding the avalanche multiplication region. At least a portion of the boundary between the insulating film facing the cathode wiring 331A overlaps with the electric field relaxation region in plan view. Furthermore, the entire imaginary line 332B overlaps with the first semiconductor region 311 in plan view, and at least a portion of the imaginary line 332B overlaps with the charge relaxation region in plan view.

[0120] Sixth Embodiment A photoelectric conversion device according to a sixth embodiment will be described with reference to FIG.

[0121] The explanation of the parts common to the first to fifth embodiments will be omitted, and the parts different from the first embodiment will be mainly explained.

[0122] Fig. 20 is a cross-sectional view of the photoelectric conversion device 100, and light is incident from the upper side of Fig. 20. A first substrate 301 and a second substrate 401 are stacked from the light incident surface side.

[0123] The first substrate 301 is composed of a semiconductor layer 302 (first semiconductor layer) of the first substrate and a wiring structure 303 (first wiring structure) of the first substrate. The second substrate 401 is composed of a semiconductor layer 402 (second semiconductor layer) of the second substrate and a wiring structure 403 (second wiring structure) of the second substrate. The semiconductor layer 302 has a first surface P1 and a second surface P2 opposite the first surface P1. For example, the first surface P1 is the front surface, and the second surface P2 is the back surface. The semiconductor layer 402 has a third surface P3 and a fourth surface P4 opposite the third surface P3. For example, the third surface P3 is the front surface, and the fourth surface P4 is the back surface. The first substrate 301 and the second substrate 401 are bonded together so that the first wiring structure 303 and the second wiring structure 403 face each other and are in contact. The bonding surface is designated as a fifth surface P5. The fifth plane P5 is the top surface of the wiring structure 303 and can be the top surface of the wiring structure 403.

[0124] A first semiconductor region 311 of a first conductivity type, a second semiconductor region 312 of a second conductivity type, a third semiconductor region 313 of the first conductivity type, and a fourth semiconductor region 314 of the second conductivity type are arranged in the first semiconductor layer 302. A fifth semiconductor region 315 of a second conductivity type, a sixth semiconductor region 316 of the first conductivity type, and a seventh semiconductor region 317 of the first conductivity type are further arranged in the first semiconductor layer 302.

[0125] The first semiconductor region 311 and the second semiconductor region 312 form a PN junction, constituting an APD.

[0126] A third semiconductor region 313 is configured closer to the light incident surface than the second semiconductor region 312. The impurity concentration of the third semiconductor region 313 is lower than the impurity concentration of the second semiconductor region 312. Here, "impurity concentration" means the net impurity concentration compensated for by impurities of the opposite conductivity type. In other words, "impurity concentration" refers to the NET concentration. For example, a region in which the concentration of P-type added impurities is higher than the concentration of N-type added impurities is a P-type semiconductor region. Conversely, a region in which the concentration of N-type added impurities is higher than the concentration of P-type added impurities is an N-type semiconductor region.

[0127] Each pixel is separated by a fourth semiconductor region 314. A fifth semiconductor region 315 is provided on the light incident surface side of the fourth semiconductor region 314. The fifth semiconductor region 315 is provided in common to each pixel.

[0128] A voltage VPDL (first voltage) is supplied to the fourth semiconductor region 314, and a voltage VDD (second voltage) is supplied to the first semiconductor region 311. A reverse bias voltage is supplied to the second semiconductor region 312 and the first semiconductor region 311 by the voltage supplied to the fourth semiconductor region 314 and the voltage supplied to the first semiconductor region 311. This supplies a reverse bias voltage that causes the APD to perform avalanche multiplication operation.

[0129] A pinning layer 321 is provided closer to the light incident surface than the fifth semiconductor region 315. The pinning layer 321 is a layer disposed to suppress dark current. The pinning layer 321 is formed using, for example, hafnium oxide (HfO2). The pinning layer 321 may also be formed using zirconium dioxide (ZrO2), tantalum oxide (Ta2O5), or the like.

[0130] A planarization layer 322 and a microlens 323 are provided on the pinning layer 321. The planarization layer 322 may include any configuration, such as an insulating film, a light-shielding film, or a color filter. A grid-shaped light-shielding film for optically isolating each pixel may be provided between the microlens 323 and the pinning layer 321. Any material that can block light may be used as the light-shielding film, and examples of such materials include tungsten (W), aluminum (Al), and copper (Cu).

[0131] The second semiconductor layer 402 is provided with an active region 411 made of a semiconductor region and an isolation region 412. The isolation region 412 is a field region made of an insulator.

[0132] The first wiring structure 303 has multiple insulator layers and multiple wiring layers 380. The multiple wiring layers 380 are composed of, from the first semiconductor layer 302 side, a first wiring layer (M1), a second wiring layer (M2), and a third wiring layer (M3). A first bonding portion 385 is provided on the top layer of the first wiring structure 303 so as to be exposed. The first wiring structure 303 also has a first pad opening 353 and a second pad opening 355, and a first pad electrode 352 and a second pad electrode 354 are provided at the bottoms of the first pad opening 353 and the second pad opening 355, respectively. A voltage is supplied to each of the first pad electrode 352 and the second pad electrode 354 from outside the photoelectric conversion device 100. The pad electrode is electrically connected to the outside of the photoelectric conversion device 100 by wire bonding shown in FIG. 25 , solder bonding, a TSV (Through Silicon Via), or the like. The first pad electrode 352 is an electrode for supplying a voltage to the circuit of the first substrate. For example, a voltage VPDL (first voltage) is supplied from the first pad electrode 352 to the fourth semiconductor region 314 via a via wiring (not shown) or a contact wiring (not shown).

[0133] The second wiring structure 403 has multiple insulator layers and multiple wiring layers 390. The multiple wiring layers 390 are composed of a first wiring layer (M1) to a fifth wiring layer (M5) from the second semiconductor layer 402 side. A second bonding portion 395 is provided on the top layer of the second wiring structure 403 so as to be exposed. The bonding portion 385 of the first substrate is in contact with the bonding portion 395 of the second substrate, and is electrically connected. This bonding between the first bonding portion 385 exposed on the bonding surface of the first substrate and the second bonding portion 395 exposed on the bonding surface of the second substrate is sometimes referred to as a metal bonding (MB) structure or metal bonding portion. This bonding is often performed between copper (Cu) and is therefore sometimes referred to as Cu-Cu bonding (Cu-Cu bonding). The bonding between the first bonding portion 385 and the second bonding portion 395 and the bonding between the insulating layer of the first wiring structure 303 and the insulating layer of the second wiring structure 403 are sometimes referred to as hybrid bonding.

[0134] The second pad electrode 354 provided in the first wiring structure 303 is electrically connected to any one of the plurality of wirings provided in the plurality of wiring layers 390 via a first bonding portion 385 and a second bonding portion 395. For example, the second pad electrode 354 supplies a voltage VSS (third voltage) to a circuit provided in the pixel circuit 3000. The pad electrode 354 also supplies a voltage VDD (second voltage) to a circuit provided in the pixel circuit 3000. Furthermore, the second pad electrode 354 supplies a voltage to the wirings of the plurality of wiring layers 390 via the first bonding portion 385 and the second bonding portion 395, and supplies a voltage to the wirings of the plurality of wiring layers 380 via the second bonding portion 395 and the first bonding portion 385. For example, in such a path, the voltage VDD (second voltage) electrically connected to the quench element 3010 is supplied from the second pad electrode 354. Specifically, VDD (second voltage) is supplied from the second pad electrode 354 to the first bonding portion 385, the second bonding portion 395, and the wiring of the plurality of wiring layers 390. Then, VDD (second voltage) is supplied from the wiring of the plurality of wiring layers 390 to the first semiconductor region 311 via the quench element 3010 provided on the second substrate, the wiring of the plurality of wiring layers 390, the second bonding portion 395, and the first bonding portion 385. Although only one pad electrode is shown as the second pad electrode 354 in FIG. 25 , a configuration is possible in which a plurality of second pad electrodes 354 are provided and voltages having different values ​​are supplied.

[0135] 25, the first pad electrode 352 and the second pad electrode 354 are located between the second surface P2 and the fifth surface P5, more specifically, between the first surface P1 and the fifth surface P2. The first pad electrode 352 and the second pad electrode 354 can be disposed between the second surface P2 and the fourth surface P4.

[0136] Seventh Embodiment A photoelectric conversion device according to a seventh embodiment will be described with reference to FIG.

[0137] The explanation of the parts common to the first to sixth embodiments will be omitted, and the parts different from the first embodiment will be mainly explained.

[0138] Fig. 21 shows a modified example of the photoelectric conversion device 100. Fig. 21 corresponds to the cross-sectional view shown in Fig. 6. In this example, the positions of the first pad electrode 352 and the second pad electrode 354 are changed from those of the configuration of embodiment 1.

[0139] 20 , a wiring layer of the wiring structure 303, for example, the third wiring layer, includes the first pad electrode 352 and the second pad electrode 354. However, in FIG. 21 , a wiring layer of the wiring structure 403, for example, the fifth wiring layer, includes the first pad electrode 352 and the second pad electrode 354. The depths of the first pad opening 353 and the second pad opening 355 are greater than the depths of the first pad opening 353 and the second pad opening 355 shown in FIG. 20 . Here, the depth refers to, for example, the distance from the back surface of the semiconductor layer 302. The first pad electrode 352 and the second pad electrode 354 can be located between the fifth surface P5 and the fourth surface P4, for example, between the fifth surface P5 and the third surface P3. The back surface of the semiconductor layer 302 is, for example, the interface with the pinning layer 321. The first pad opening 353 and the second pad opening 355 penetrate the bonding surface and extend from the semiconductor layer 302. The photoconversion device 100 of the present invention can also have such a configuration. Here, a configuration in which the wiring layer includes the first pad electrode 352 and the second pad electrode 354 has been described, but the pad electrodes may be formed separately from the wiring layer.

[0140] Eighth Embodiment A photoelectric conversion device according to an eighth embodiment will be described with reference to FIG.

[0141] The explanation of the parts common to the first to seventh embodiments will be omitted, and the parts different from the first embodiment will be mainly explained.

[0142] Fig. 22 shows a modified example of the photoelectric conversion device 100. Fig. 22 corresponds to the cross-sectional view shown in Fig. 6. In this example, the position of the second pad electrode 354 is changed from the configuration of the eighth embodiment.

[0143] In FIG. 20 , the wiring layer of the wiring structure 303, for example, the third wiring layer, includes the second pad electrode 354. However, in FIG. 27 , the wiring layer of the wiring structure 403, for example, the fifth wiring layer, includes the second pad electrode 354. That is, the second pad electrode 354 can be located between the fifth surface P5 and the fourth surface P4, for example, between the fifth surface P5 and the third surface P3. The second pad electrode 352 can be located between the second surface P2 and the fifth surface P5, for example, between the first surface P1 and the fifth surface P1. Alternatively, the wiring layer of the wiring structure 403 may include the first pad electrode 352, and the wiring layer of the wiring structure 303 may include the second pad electrode 354. The photoconversion device 100 of the present invention may also have such a configuration.

[0144] Here, the configuration in which the wiring layer includes the first pad electrode 352 and the second pad electrode 354 has been described, but the pad electrodes may be formed separately from the wiring layer.

[0145] Ninth Embodiment A photoelectric conversion device according to a ninth embodiment will be described with reference to FIG.

[0146] The explanation of the parts common to the first to eighth embodiments will be omitted, and the parts different from the sixth embodiment will be mainly explained.

[0147] Fig. 23 shows a modified example of the photoelectric conversion device 100. Fig. 23 corresponds to the cross-sectional view shown in Fig. 6. In this embodiment, the structures of the first pad electrode 352 and the second pad electrode 354 are modified from those of the eighth embodiment.

[0148] The wiring structure 303 includes first to third wiring layers M1 to M3 and a connection portion 385. The wiring structure 403 includes first to fifth wiring layers M1 to M5 and a connection portion 395. Each wiring layer is a so-called copper wiring.

[0149] In wiring structure 303 and wiring structure 403, the first wiring layer includes a conductor pattern whose main component is copper. The conductor pattern of wiring layer 1 has a single damascene structure. Contacts are arranged for electrical connection between the first wiring layer and semiconductor layer 302. The contacts are conductor patterns whose main component is tungsten. The second and third wiring layers include conductor patterns whose main component is copper. The conductor patterns of the second and third wiring layers have a dual damascene structure, and include portions that function as wiring and portions that function as vias. The fourth and fifth wiring layers are similar to the second and third wiring layers.

[0150] The first pad electrode 352 and the second pad electrode 354 are conductor patterns primarily composed of aluminum. The first pad electrode 352 and the second pad electrode 354 are provided across the second and third wiring layers of the wiring structure 303. For example, they include a portion that functions as a via connecting the first wiring layer and the second wiring layer to a portion that functions as a wiring in the third wiring layer. The first pad electrode 352 and the second pad electrode 354 are located, for example, between the second surface P1 and the fifth surface P5. The first pad electrode 352 and the second pad electrode 354 can be provided between the second surface P2 and the fourth surface P4, or can also be provided between the second surface P2 and the fifth surface P5.

[0151] The first pad electrode 352 and the second pad electrode 354 have a first surface and a second surface opposite to the first surface. The first surface is partially exposed by an opening in the semiconductor layer.

[0152] The exposed portions of the first pad electrode 352 and the second pad electrode 354 can function as connection portions with external terminals, so-called pad portions. The first pad electrode 352 and the second pad electrode 354 are connected on their second surfaces to a plurality of conductors whose main component is copper.

[0153] As an alternative to this embodiment, the first pad electrode 352 and the second pad electrode 354 may have electrical connection portions in unexposed portions on the first surface side. For example, the first pad electrode 352 and the second pad electrode 354 may have vias made of a conductor mainly composed of aluminum, and may be electrically connected to a conductor mainly composed of copper located on the first surface side through the vias. Furthermore, the first pad electrode 352 and the second pad electrode 354 may be connected to the first wiring layer of the wiring structure 303 on the first surface by a conductor mainly composed of tungsten.

[0154] The first pad electrode 352 and the second pad electrode 354 can be formed, for example, by the following procedure: After forming an insulator covering the third wiring layer, a portion of the insulator is removed, and an aluminum-based film that will become the first pad electrode 352 and the second pad electrode 354 is formed and patterned. By forming the first pad electrode 352 and the second pad electrode 354 after forming the copper wiring, the first pad electrode 352 and the second pad electrode 354 can be formed with a thick film thickness while maintaining the flatness of the fine copper wiring.

[0155] In this embodiment, the first pad electrode 352 and the second pad electrode 354 are shown as being included in the wiring structure 303, but they may also be included in the wiring structure 403. The position at which the pad electrodes are provided may be either in the wiring structures 303 and 403 and is not limited. The materials and structures of the wiring layers of the wiring structures 303 and 403 are not limited to those exemplified, and for example, a conductor layer may be further provided between the wiring layer 1 and the semiconductor layer. Also, a stack contact structure in which two contact layers are stacked may be used.

[0156] Tenth Embodiment A photoelectric conversion device according to a tenth embodiment will be described with reference to FIG.

[0157] The explanation of the parts common to the first to ninth embodiments will be omitted, and the parts different from the sixth embodiment will be mainly explained.

[0158] Fig. 24 shows a modified example of the photoelectric conversion device 100. Fig. 24 is an enlarged cross-sectional view of the vicinity of the pad electrode 354 in the cross-sectional view shown in Fig. 6. In this embodiment, the structure of the second pad electrode 354 is mainly modified from the configuration of the first embodiment.

[0159] The wiring structure 303 includes first and second wiring layers M1 and M2 and a connection portion 385. The wiring structure 403 includes first to fourth wiring layers M1 to M4 and a connection portion 395. Each wiring layer is a so-called copper wiring.

[0160] In wiring structure 303 and wiring structure 403, the first wiring layer includes a conductor pattern whose main component is copper. The conductor pattern of wiring layer 1 has a single damascene structure. Contacts are arranged for electrical connection between the first wiring layer and semiconductor layer 302. The contacts are conductor patterns whose main component is tungsten. The second and third wiring layers include conductor patterns whose main component is copper. The conductor patterns of the second and third wiring layers have a dual damascene structure, and include portions that function as wiring and portions that function as vias. The fourth wiring layer is similar to the second and third wiring layers.

[0161] The second pad electrode 354 is a conductor pattern mainly composed of aluminum. The second pad electrode 354 is not a wiring structure, but is disposed in an opening in the semiconductor layer 302. Here, the second pad electrode 354 has an exposed surface on the second surface P2 and the first surface P1, but the exposed surface of the pad electrode may be located on the second surface P2.

[0162] A method for forming this structure will be briefly described. An opening 353 is formed in the semiconductor layer 302 so that a portion of the wiring layer M1 of the wiring structure 303 is exposed. Then, an insulator 24-101 is formed so as to cover the second surface P2 of the semiconductor layer 302 and the first pad opening 353. An opening that will become a via for the second pad electrode 354 is formed in the insulator 24-101. After forming a conductive film that will become the second pad electrode 354, unnecessary portions of the conductive film are removed to form the desired pattern. Furthermore, even after forming the insulator 24-102, an opening 24-105 that exposes the second pad electrode 354 is formed. This configuration can be formed using this method.

[0163] Furthermore, a through electrode 24-104 may be provided from the second surface P2 side. The through electrode 24-104 is made of a conductor containing copper as a main component, and may have a barrier metal between the semiconductor layer 302 and the conductor.

[0164] A conductor 24-103 is disposed on the through electrode 24-104. The conductor 24-103 may be provided in common with other through electrodes, and may have the function of reducing diffusion of the conductor of the through electrode 24-104.

[0165] The first pad electrode 352 (not shown) can have the same configuration as the second pad electrode 354. The materials and structures of the wiring layers of the wiring structures 303 and 403 are not limited to those exemplified, and for example, a conductor layer may be further provided between the wiring layer 1 and the semiconductor layer. Also, a stack contact structure in which two contact layers are stacked may be provided.

[0166] Although the first pad electrode 352 and the second pad electrode 354 are located between the second surface P2 and the fourth surface P4, they may be located above the second surface P2.

[0167] The first pad opening 353 and the second pad opening 355 may be provided in the second substrate 12. When the openings are located in the second substrate 12, through electrodes may be formed in the openings. An electrical connection portion between the through electrodes and an external device can be provided on the fourth surface P4.

[0168] Furthermore, pad electrodes, which are electrical connection portions with an external device, may be provided on both the fourth surface P4 side of the second substrate 12 and the second surface P2 side of the first substrate 301.

[0169] Eleventh Embodiment A photoelectric conversion system according to this embodiment will be described with reference to Fig. 25. Fig. 25 is a block diagram showing a schematic configuration of the photoelectric conversion system according to this embodiment.

[0170] The photoelectric conversion devices described in the first to tenth embodiments can be applied to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in photoelectric conversion systems. Figure 25 illustrates a block diagram of a digital still camera as an example of such systems.

[0171] 25 includes an image pickup device 1004, which is an example of a photoelectric conversion device, and a lens 1002 that forms an optical image of a subject on the image pickup device 1004. The system further includes an aperture 1003 that adjusts the amount of light passing through the lens 1002, and a barrier 1001 that protects the lens 1002. The lens 1002 and aperture 1003 form an optical system that focuses light on the image pickup device 1004. The image pickup device 1004 is a photoelectric conversion device according to any of the above embodiments, and converts the optical image formed by the lens 1002 into an electrical signal.

[0172] The photoelectric conversion system also includes a signal processing unit 1007, which is an image generation unit that generates an image by processing an output signal output from the imaging device 1004. The signal processing unit 1007 performs various corrections and compressions as necessary to output image data. The signal processing unit 1007 may be formed on the same semiconductor substrate on which the imaging device 1004 is provided, or may be formed on a semiconductor substrate separate from the imaging device 1004.

[0173] The photoelectric conversion system further includes a memory unit 1010 for temporarily storing image data, and an external interface unit (external I / F unit) 1013 for communicating with an external computer or the like. The photoelectric conversion system further includes a recording medium 1012 such as a semiconductor memory for recording or reading out image data, and a recording medium control interface unit (recording medium control I / F unit) 1011 for recording or reading out data from the recording medium 1012. The recording medium 1012 may be built into the photoelectric conversion system or may be detachable.

[0174] The photoelectric conversion system further includes an overall control / calculation unit 1009 that performs various calculations and controls the entire digital still camera, and a timing generation unit 1008 that outputs various timing signals to the image capture device 1004 and the signal processing unit 1007. Here, timing signals and the like may be input from outside, and the photoelectric conversion system only needs to include at least the image capture device 1004 and the signal processing unit 1007 that processes the output signal output from the image capture device 1004.

[0175] The imaging device 1004 outputs an imaging signal to the signal processing unit 1007. The signal processing unit 1007 performs predetermined signal processing on the imaging signal output from the imaging device 1004 and outputs image data. The signal processing unit 1007 generates an image using the imaging signal.

[0176] As described above, according to this embodiment, it is possible to realize a photoelectric conversion system to which the photoelectric conversion device (image pickup device) according to any one of the above embodiments is applied.

[0177] Twelfth Embodiment A photoelectric conversion system and a moving object according to this embodiment will be described with reference to Fig. 26A and Fig. 26B. Fig. 26A and Fig. 26B are diagrams showing the configurations of the photoelectric conversion system and the moving object according to this embodiment.

[0178] FIG. 26A illustrates an example of a photoelectric conversion system for an in-vehicle camera. The photoelectric conversion system 1300 includes an image capture device 1310. The image capture device 1310 is the photoelectric conversion device described in any of the above embodiments. The photoelectric conversion system 1300 includes an image processing unit 1312 that performs image processing on multiple pieces of image data acquired by the image capture device 1310, and a parallax acquisition unit 1314 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 1300. The photoelectric conversion system 1300 also includes a distance acquisition unit 1316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 1318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 1314 and the distance acquisition unit 1316 are examples of distance information acquisition means that acquire distance information to the object. In other words, the distance information includes information regarding the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 1318 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0179] The photoelectric conversion system 1300 is connected to a vehicle information acquisition device 1320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 1300 is also connected to a control ECU 1330, which is a control unit that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 1318. The photoelectric conversion system 1300 is also connected to an alarm device 1340 that issues an alarm to the driver based on the determination result of the collision determination unit 1318. For example, if the determination result of the collision determination unit 1318 indicates a high collision possibility, the control ECU 1330 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 1340 warns the user by sounding an alarm, displaying alarm information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0180] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 1300. Fig. 26B shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 1350). The vehicle information acquisition device 1320 sends instructions to the photoelectric conversion system 1300 or the imaging device 1310. This configuration can further improve the accuracy of distance measurement.

[0181] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from a lane, etc. Furthermore, the photoelectric conversion system is not limited to vehicles such as the subject vehicle, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0182] Thirteenth Embodiment A photoelectric conversion system of this embodiment will be described with reference to Fig. 27. Fig. 27 is a block diagram showing an example of the configuration of a range image sensor, which is the photoelectric conversion system of this embodiment.

[0183] 27, the range image sensor 401 is configured to include an optical system 407, a photoelectric conversion device 408, an image processing circuit 404, a monitor 405, and a memory 406. The range image sensor 401 receives light (modulated light or pulsed light) that is projected toward the subject from a light source device 409 and reflected from the surface of the subject, thereby obtaining a range image according to the distance to the subject.

[0184] The optical system 407 is configured to have one or more lenses, and guides image light (incident light) from a subject to the photoelectric conversion device 408 , forming an image on the light receiving surface (sensor portion) of the photoelectric conversion device 408 .

[0185] The photoelectric conversion device 408 is the photoelectric conversion device of each of the above-described embodiments, and a distance signal indicating a distance determined from a light reception signal output from the photoelectric conversion device 408 is supplied to the image processing circuit 404.

[0186] The image processing circuit 404 performs image processing to construct a distance image based on the distance signal supplied from the photoelectric conversion device 408. The distance image (image data) obtained by this image processing is then supplied to a monitor 405 for display, or supplied to a memory 406 for storage (recording).

[0187] In the range image sensor 401 configured in this way, by applying the above-described photoelectric conversion device, it is possible to obtain, for example, a more accurate range image as the pixel characteristics improve.

[0188] Fourteenth Embodiment A photoelectric conversion system according to this embodiment will be described with reference to Fig. 28. Fig. 28 is a diagram showing an example of the schematic configuration of an endoscopic surgery system, which is the photoelectric conversion system according to this embodiment.

[0189] 28 shows an operator (doctor) 1131 performing surgery on a patient 1132 on a patient bed 1133 using an endoscopic surgery system 1150. As shown in the figure, the endoscopic surgery system 1150 is composed of an endoscope 1100, a surgical tool 1110, and a cart 1134 on which various devices for endoscopic surgery are mounted.

[0190] The endoscope 1100 is composed of a lens barrel 1101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 1132, and a camera head 1102 connected to the base end of the lens barrel 1101. In the illustrated example, the endoscope 1100 is configured as a so-called rigid lens barrel having a rigid lens barrel 1101, but the endoscope 1100 may also be configured as a so-called flexible lens barrel having a flexible lens barrel.

[0191] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 1101. A light source device 1203 is connected to the endoscope 1100, and light generated by the light source device 1203 is guided to the tip of the lens barrel 1101 by a light guide extending inside the lens barrel 1101, and is irradiated via the objective lens toward an observation target inside a body cavity of a patient 1132. The endoscope 1100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0192] An optical system and a photoelectric conversion device are provided inside the camera head 1102, and light reflected from an observation object (observation light) is focused onto the photoelectric conversion device by the optical system. The observation light is photoelectrically converted by the photoelectric conversion device to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observation image. The photoelectric conversion device may be any of the photoelectric conversion devices described in the above-described embodiments. The image signal is transmitted to a camera control unit (CCU) 1135 as RAW data.

[0193] The CCU 1135 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 1100 and the display device 1136. Furthermore, the CCU 1135 receives an image signal from the camera head 1102 and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0194] Under the control of the CCU 1135 , the display device 1136 displays an image based on the image signal that has been subjected to image processing by the CCU 1135 .

[0195] The light source device 1203 is configured from a light source such as an LED (Light Emitting Diode), and supplies the endoscope 1100 with irradiation light when photographing an operation site or the like.

[0196] The input device 1137 is an input interface for the endoscopic surgery system 1150. A user can input various information and instructions to the endoscopic surgery system 1150 via the input device 1137.

[0197] The treatment tool control device 1138 controls the driving of the energy treatment tool 1112 for cauterizing tissue, incising, sealing blood vessels, or the like.

[0198] The light source device 1203, which supplies illumination light to the endoscope 1100 when photographing the surgical site, can be configured from a white light source formed, for example, by an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 1203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source in a time-division manner and controlling the drive of the image sensor of the camera head 1102 in synchronization with the irradiation timing. This method allows color images to be obtained without providing a color filter to the image sensor.

[0199] Furthermore, the light source device 1203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 1102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0200] The light source device 1203 may also be configured to provide light in a predetermined wavelength band corresponding to special light observation. Special light observation utilizes, for example, the wavelength dependence of light absorption in body tissue. Specifically, by irradiating light with a narrower band than the light (i.e., white light) used during normal observation, a specific tissue, such as a blood vessel on the surface of a mucous membrane, can be imaged with high contrast. Alternatively, special light observation may involve fluorescence observation, in which an image is obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto a body tissue and observing the fluorescence from the body tissue, or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the body tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 1203 may be configured to provide narrow-band light and / or excitation light corresponding to such special light observation.

[0201] Fifteenth Embodiment A photoelectric conversion system of this embodiment will be described with reference to FIGS. 29A and 29B. FIG. 29A illustrates glasses 1600 (smart glasses) which are the photoelectric conversion system of this embodiment. The glasses 1600 have a photoelectric conversion device 1602. The photoelectric conversion device 1602 is the photoelectric conversion device described in each of the above embodiments. A display device including a light-emitting device such as an OLED or LED may be provided on the back side of the lens 1601. There may be one or more photoelectric conversion devices 1602. A combination of multiple types of photoelectric conversion devices may also be used. The arrangement position of the photoelectric conversion device 1602 is not limited to that shown in FIG. 29A.

[0202] The glasses 1600 further include a control device 1603. The control device 1603 functions as a power source that supplies power to the photoelectric conversion device 1602 and the display device. The control device 1603 also controls the operations of the photoelectric conversion device 1602 and the display device. The lens 1601 is formed with an optical system for focusing light onto the photoelectric conversion device 1602.

[0203] FIG. 29B illustrates glasses 1610 (smart glasses) according to one application example. The glasses 1610 include a control device 1612, which is equipped with a photoelectric conversion device corresponding to the photoelectric conversion device 1602 and a display device. A lens 1611 includes an optical system for projecting light emitted from the photoelectric conversion device and the display device, and an image is projected onto the lens 1611. The control device 1612 functions as a power source for supplying power to the photoelectric conversion device and the display device, and controls the operation of the photoelectric conversion device and the display device. The control device may also include a gaze detection unit for detecting the gaze of the wearer. Infrared light may be used for gaze detection. The infrared light emitter emits infrared light toward the eyeball of a user gazing at a displayed image. An imaging unit with a light-receiving element detects the reflected light of the emitted infrared light from the eyeball, thereby obtaining an image of the eyeball. A reduction unit for reducing light from the infrared light emitter to the display unit in a planar view reduces degradation of image quality.

[0204] The gaze of the user relative to the displayed image is detected from an image of the eyeball obtained by capturing infrared light. Any known method can be used for gaze detection using an image of the eyeball. One example is a gaze detection method based on the Purkinje image formed by reflection of irradiated light on the cornea.

[0205] More specifically, gaze detection processing is performed based on the pupil-corneal reflex method, which calculates a gaze vector representing the direction (rotation angle) of the eyeball based on the pupil image and Purkinje image included in the captured image of the eyeball, thereby detecting the user's gaze.

[0206] The display device of this embodiment may have a photoelectric conversion device having a light receiving element, and may control the image displayed on the display device based on information about the user's line of sight from the photoelectric conversion device.

[0207] Specifically, the display device determines a first field of view area where the user gazes and a second field of view area other than the first field of view area based on the line-of-sight information. The first field of view area and the second field of view area may be determined by a control device of the display device, or may be determined by an external control device and received. In the display area of ​​the display device, the display resolution of the first field of view area may be controlled to be higher than the display resolution of the second field of view area. In other words, the resolution of the second field of view area may be lower than that of the first field of view area.

[0208] The display area may include a first display area and a second display area different from the first display area, and a high-priority area may be determined from the first display area and the second display area based on line-of-sight information. The first field of view area and the second field of view area may be determined by a control device of the display device, or may be determined by an external control device and received. The resolution of the high-priority area may be controlled to be higher than the resolution of areas other than the high-priority area. In other words, the resolution of an area with a relatively low priority may be lowered.

[0209] Note that AI may be used to determine the first field of view area and the high-priority area. The AI ​​may be a model configured to estimate the line of sight angle and the distance to an object in the line of sight from the image of the eyeball, using as training data an image of the eyeball and the actual direction in which the eyeball in the image was looking. The AI ​​program may be included in the display device, the photoelectric conversion device, or an external device. If included in the external device, it is transmitted to the display device via communication.

[0210] When display control is performed based on visual recognition detection, the present invention is preferably applied to smart glasses that further include a photoelectric conversion device for capturing images of the outside world. The smart glasses can display captured external information in real time.

[0211] [Modified Embodiments] The present invention is not limited to the above-described embodiments and can be modified in various ways.

[0212] For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is replaced with another embodiment, is also included in the embodiments of the present invention.

[0213] Furthermore, the photoelectric conversion systems shown in the ninth and twelfth embodiments are examples of photoelectric conversion systems to which a photoelectric conversion device can be applied, and photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 25 to 26B The same applies to the ToF system shown in the thirteenth embodiment, the endoscope shown in the fourteenth embodiment, and the smart glasses shown in the fifteenth embodiment.

[0214] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features.

[0215] The present invention is not limited to the above-described embodiments, and various modifications and variations can be made without departing from the spirit and scope of the present invention. Therefore, the following claims are appended to apprise the public of the scope of the present invention.

Claims

1. A photoelectric conversion device comprising: an avalanche diode disposed in a semiconductor layer having a first surface and a second surface opposite to the first surface; and a first wiring structure in contact with the second surface, The avalanche diode is a first semiconductor region of a first conductivity type disposed at a first depth; a second semiconductor region of a second conductivity type disposed at a second depth relative to the second surface that is deeper than the first depth and forming an avalanche multiplication region between the first semiconductor region and the second semiconductor region; a third semiconductor region provided in contact with an end portion of the first semiconductor region in a plan view; a first wiring portion electrically connected to the first semiconductor region; a second wiring portion electrically connected to the second semiconductor region; having a first pad for applying a first voltage to the photoelectric conversion device is provided on the first wiring structure; A photoelectric conversion device characterized in that, in a planar view, at least a portion of a boundary between an insulating film facing the first wiring portion and the second wiring portion overlaps the third semiconductor region and does not overlap the first semiconductor region.

2. A photoelectric conversion device comprising: a plurality of avalanche diodes disposed in a semiconductor layer having a first surface and a second surface opposite to the first surface; and a first wiring structure in contact with the second surface, The avalanche diode is a first semiconductor region of a first conductivity type disposed at a first depth; a second semiconductor region of a second conductivity type disposed at a second depth relative to the second surface that is deeper than the first depth and forming an avalanche multiplication region between the first semiconductor region and the second semiconductor region; a third semiconductor region provided in contact with an end portion of the first semiconductor region in a plan view; a first wiring portion electrically connected to the first semiconductor region; a second wiring portion electrically connected to the second semiconductor region; having a first pad for applying a first voltage to the photoelectric conversion device is provided on the first wiring structure; A photoelectric conversion device characterized in that, in a planar view, at least a portion of a line dividing an equal distance between a boundary between the first wiring portion and the insulating film and a boundary between the second wiring portion and the insulating film overlaps the third semiconductor region and does not overlap the first semiconductor region.

3. 3. The photoelectric conversion device according to claim 1, wherein an area of ​​the first semiconductor region is smaller than an area of ​​the third semiconductor region in a plan view.

4. 4. The photoelectric conversion device according to claim 1, wherein the third semiconductor region has an impurity concentration lower than an impurity concentration in the first semiconductor region.

5. A photoelectric conversion device comprising: an avalanche diode disposed in a semiconductor layer having a first surface and a second surface opposite to the first surface; and a first wiring structure in contact with the second surface, The avalanche diode is a first semiconductor region of a first conductivity type disposed at a first depth; an avalanche multiplication region formed between the first semiconductor region and a second semiconductor region of a second conductivity type disposed at a second depth relative to the second surface that is deeper than the first depth; an electric field relaxation region surrounding the avalanche multiplication region in a plan view; a first wiring portion electrically connected to the first semiconductor region; a second wiring portion electrically connected to the second semiconductor region; having a first pad for applying a first voltage to the photoelectric conversion device is provided on the first wiring structure; A photoelectric conversion device, comprising: an insulating film facing said first wiring portion; and a second wiring portion, the insulating film facing said first wiring portion and the second wiring portion being disposed on said first wiring portion.

6. A photoelectric conversion device comprising: an avalanche diode disposed in a semiconductor layer having a first surface and a second surface opposite to the first surface; and a first wiring structure in contact with the second surface, The avalanche diode is a first semiconductor region of a first conductivity type disposed at a first depth; an avalanche multiplication region formed between the first semiconductor region and a second semiconductor region of a second conductivity type disposed at a second depth relative to the second surface that is deeper than the first depth; an electric field relaxation region surrounding the avalanche multiplication region in a plan view; a first wiring portion electrically connected to the first semiconductor region; a second wiring portion electrically connected to the second semiconductor region; having a first pad for applying a first voltage to the photoelectric conversion device is provided on the first wiring structure; A photoelectric conversion device characterized in that, in a planar view, at least a portion of a line dividing the boundary between the first wiring portion and the insulating film and the boundary between the second wiring portion and the insulating film at an equal distance overlaps the electric field relaxation region.

7. 7. The photoelectric conversion device according to claim 5, wherein an area of ​​the first semiconductor region is smaller than an area of ​​the electric field relaxation region in a plan view.

8. the first wiring portion and the second wiring portion are formed in a plurality of wiring layers stacked on the second surface side, The photoelectric conversion device according to any one of claims 1 to 7, characterized in that the second wiring portion is formed in a wiring layer that is farther from the second surface than a contact that connects the first semiconductor region and the first wiring portion, and in a wiring layer among the multiple wiring layers that is closest to the second surface.

9. 9. The photoelectric conversion device according to claim 1, wherein the first wiring portion and the second wiring portion are formed in a same wiring layer stacked on the second surface side.

10. A distance from the second surface to the second wiring portion in a direction perpendicular to the second surface is 10. The photoelectric conversion device according to claim 1, wherein the distance is shorter than a distance from the first wiring portion to the second wiring portion in a direction parallel to the second surface.

11. 11. The photoelectric conversion device according to claim 1, wherein the first surface is a light incidence surface.

12. In plan view, 12. The photoelectric conversion device according to claim 1, wherein the second wiring portion surrounds a periphery of the first wiring portion.

13. 13. The photoelectric conversion device according to claim 1, wherein the first semiconductor region is included in the second semiconductor region in a plan view.

14. 14. The photoelectric conversion device according to claim 1 , further comprising a fourth semiconductor region of the second conductivity type arranged at a third depth that is deeper than the second depth relative to the second surface.

15. a fifth semiconductor region of the first conductivity type is provided between the second semiconductor region and the fourth semiconductor region; 15. The photoelectric conversion device according to claim 14, wherein a concentration of the first conductive type impurity in the fifth semiconductor region is lower than a concentration of the first conductive type impurity in the first semiconductor region.

16. 16. The photoelectric conversion device according to claim 15, wherein a potential difference between the first semiconductor region and the second semiconductor region is larger than a potential difference between the second semiconductor region and the fifth semiconductor region.

17. the photoelectric conversion device includes a plurality of the avalanche diodes, the plurality of avalanche diodes include a first avalanche diode and a second avalanche diode adjacent to the first avalanche diode; 17. The photoelectric conversion device according to claim 1, further comprising a pixel separating section between the first avalanche diode and the second avalanche diode.

18. the plurality of avalanche diodes includes a third avalanche diode adjacent to the second avalanche diode; a first pixel isolation portion between the first avalanche diode and the second avalanche diode; a second pixel isolation portion between the second avalanche diode and the third avalanche diode; 18. The photoelectric conversion device according to claim 17, wherein the second semiconductor region in the second avalanche diode extends from the first pixel isolation portion to the second pixel isolation portion in a cross section perpendicular to the first surface.

19. 19. The photoelectric conversion device according to claim 1, wherein the semiconductor layer has an oxide film and a nitride film stacked on the second surface.

20. 20. The photoelectric conversion device according to claim 1, wherein the semiconductor layer has a plurality of uneven structures provided on the first surface.

21. The photoelectric conversion device according to claim 20 , wherein at least a portion of a boundary portion of the second wiring portion that faces the first wiring portion is included in an area in which the multiple uneven structures are formed in a planar view.

22. A photoelectric conversion device having a second wiring structure in contact with the first wiring structure, 22. The photoelectric conversion device according to claim 1, wherein a second pad for applying a second voltage to the photoelectric conversion device is provided on the second wiring structure.

23. 23. The photoelectric conversion device according to claim 22, wherein the second wiring structure includes a plurality of wiring layers, and the second pad is provided on one of the plurality of wiring layers.

24. 24. The photoelectric conversion device according to claim 1, wherein the first wiring structure includes a plurality of wiring layers, and the first pad is provided in one of the plurality of wiring layers.

25. the plurality of wiring layers included in the first wiring structure include wiring mainly made of copper, 25. The photoelectric conversion device according to claim 24, wherein the first pad is mainly made of aluminum.

26. A photoelectric conversion device comprising: an avalanche diode disposed in a semiconductor layer having a first surface and a second surface opposite to the first surface; a first wiring structure in contact with the second surface; and a second wiring structure in contact with the first wiring structure, The avalanche diode is a first semiconductor region of a first conductivity type disposed at a first depth; a second semiconductor region of a second conductivity type disposed at a second depth relative to the second surface that is deeper than the first depth and forming an avalanche multiplication region between the first semiconductor region and the second semiconductor region; a third semiconductor region provided in contact with an end portion of the first semiconductor region in a plan view; a first wiring portion electrically connected to the first semiconductor region; a second wiring portion electrically connected to the second semiconductor region; having a first pad for applying a first voltage to the photoelectric conversion device is provided on the second wiring structure; A photoelectric conversion device characterized in that, in a planar view, at least a portion of a boundary between an insulating film facing the first wiring portion and the second wiring portion overlaps the third semiconductor region and does not overlap the first semiconductor region.

27. A photoelectric conversion device comprising: an avalanche diode disposed in a semiconductor layer having a first surface and a second surface opposite to the first surface; a first wiring structure in contact with the second surface; and a second wiring structure in contact with the first wiring structure, The avalanche diode is a first semiconductor region of a first conductivity type disposed at a first depth; an avalanche multiplication region formed between the first semiconductor region and a second semiconductor region of a second conductivity type disposed at a second depth relative to the second surface that is deeper than the first depth; an electric field relaxation region surrounding the avalanche multiplication region in a plan view; a first wiring portion electrically connected to the first semiconductor region; a second wiring portion electrically connected to the second semiconductor region; having a first pad for applying a first voltage to the photoelectric conversion device is provided on the second wiring structure; A photoelectric conversion device, comprising: an insulating film facing said first wiring portion; and a second wiring portion, the insulating film facing said first wiring portion and the second wiring portion being disposed on said first wiring portion.

28. 28. The photoelectric conversion device according to claim 26, wherein a second pad for applying a second voltage is provided on the second wiring structure.

29. The photoelectric conversion device according to any one of claims 1 to 28, a signal processing unit that generates an image using a signal output from the photoelectric conversion device.

30. A moving object comprising the photoelectric conversion device according to any one of claims 1 to 28, A moving body comprising: a control unit that controls the movement of the moving body using a signal output from the photoelectric conversion device.