Solid-state imaging device

Abstract

This solid-state imaging device (100) comprises a pixel circuit (3a) whereby a plurality of pixel signals are output, a detection circuit (52), and a signal processing unit (70). The pixel circuit (3a) comprises: a photodiode (PD); a transfer transistor (TG) that reads the signal of the photodiode (PD) to a charge storage unit (FD0); and storage capacity (C2) for storing a charge overflowing from the photodiode (PD). The detection circuit (52) compares a signal from the storage capacity (C2) and a reference signal, initializes the photodiode (PD) and the storage capacity (C2) when the signal from the storage capacity (C2) reaches the reference signal, and counts the number of initializations. The signal processing unit (70) calculates a first signal indicating the intensity of incident light on the basis of the number of initializations, the signal from the photodiode (PD) read to the charge storage unit (FD0) by the transfer transistor (TG), and the signal from the storage capacity (C2).

Description

solid-state imaging device

[0001] The present disclosure relates to a solid-state imaging device.

[0002] Japanese Patent Application Laid-Open Nos. 2003-129999 and 2003-129999 disclose methods for achieving a wide dynamic range (WDR) in a solid-state imaging device.

[0003] Patent No. 3878613 Patent No. 4497366

[0004] The solid-state imaging device disclosed in Patent Document 1 uses a pulse width modulation (PWM) method to detect the light intensity of a photodiode signal. The PWM method detects the intensity of incident light as the width of a pulse signal or the frequency of occurrence of a pulse signal. However, because the PWM method is performed only on the photodiode signal, it is difficult to expand the dynamic range. Furthermore, since there is no transfer transistor, it is not possible to read the reset component at each initialization. This means that correlated double sampling (CDS) to remove the reset component is not possible, resulting in a problem of worsening low-light noise. Furthermore, the signal-to-noise ratio (SNR) of the photodiode remains unchanged even when digitally multiplied by N, which is not an improvement.

[0005] The solid-state imaging device disclosed in Patent Document 2 uses a method in which signals that exceed a predetermined threshold and overflow from a photodiode are stored in a storage capacitor via an overflow element. However, because the storage capacitor is determined by process constraints and is fixed, it is difficult to further expand the dynamic range.

[0006] Therefore, the present disclosure provides a solid-state imaging device that can easily expand the dynamic range.

[0007] A solid-state imaging device according to the present disclosure includes a pixel circuit that outputs a plurality of pixel signals, a detection circuit, a pixel control circuit that controls the pixel circuit, and a signal processing unit. The pixel circuit includes a photodiode, a first transfer transistor that reads out the signal of the photodiode to a floating diffusion, and a storage capacitance that accumulates charge that overflows from the photodiode. The detection circuit compares the signal of the storage capacitance with a first reference value, and when the signal of the storage capacitance reaches the first reference value, initializes the photodiode and the storage capacitance via the pixel control circuit and counts the number of initializations. The signal processing unit calculates a first signal that indicates the intensity of incident light based on the number of initializations and a mixed signal of the signal of the photodiode and the signal of the storage capacitance that is read out to the floating diffusion by the first transfer transistor.

[0008] These comprehensive or specific aspects may be realized as a system, a method, an integrated circuit, a computer program, or a computer-readable recording medium such as a CD-ROM, or may be realized as any combination of a system, a method, an integrated circuit, a computer program, and a recording medium.

[0009] According to a solid-state imaging device according to an aspect of the present disclosure, the dynamic range can be easily expanded.

[0010] FIG. 1 is a block diagram showing an example of the configuration of a solid-state imaging device according to an embodiment. FIG. 2A is a block diagram showing an example of the configuration of a pixel circuit and a logic circuit according to an embodiment. FIG. 2B is a block diagram showing an example of the configuration of a pixel circuit and a logic circuit according to an embodiment. FIG. 2C is a block diagram showing an example of the configuration of a pixel circuit and a logic circuit according to an embodiment. FIG. 3 is a block diagram showing an example of the configuration of a pixel circuit and a logic circuit according to an embodiment. FIG. 4 is a block diagram showing an example of the configuration of a pixel circuit and a logic circuit according to an embodiment. FIG. 5 is a diagram for explaining sharing of a logic circuit by multiple pixel circuits. FIG. 6 is a diagram showing an example of the configuration of a sample and hold circuit. FIG. 7 is a diagram showing an overview of a method for implementing WDR combining within a pixel. FIG. 8 is a diagram showing an example of the configuration of a signal processing unit that performs WDR combining using three signals. FIG. 9 is a diagram showing an example of the configuration of a signal processing unit that performs WDR combining using two signals selected from three signals. FIG. 10 is a diagram showing an example of the basic readout timing of a pixel circuit. FIG. 11 is a diagram showing the timing of a selective WDR method. FIG. 12 is a diagram showing an example of the basic timing of a PWM method. FIG. 13 is a diagram showing an example of the timing when an AD conversion circuit is used in the PWM method. FIG. 14 is a diagram illustrating an example of selecting an HCG signal, an MCG signal, and an LCG signal by prioritizing the maximum signal of each color in Bayer units. FIG. 15 is a diagram illustrating an example of selecting an HCG signal, an MCG signal, and an LCG signal independently for each color. FIG. 16 is a diagram illustrating an example of a solid-state imaging device according to an embodiment configured as a stacked image sensor. FIG. 17 is a diagram illustrating an example of a solid-state imaging device according to an embodiment configured as a stacked image sensor. FIG. 18 is a diagram illustrating an example of a solid-state imaging device according to an embodiment configured as a stacked image sensor. FIG. 19 is a diagram illustrating an example of a solid-state imaging device according to an embodiment configured as a stacked image sensor. FIG. 20 is a diagram illustrating an example of a connection between a pixel circuit and a logic circuit according to an embodiment. FIG. 21 is a diagram illustrating an example of a connection between a pixel circuit and a logic circuit according to an embodiment. FIG. 22 is a diagram illustrating an example of a timing when an HCG signal and an MCG signal are selected. FIG. 23 is a diagram illustrating an example of a timing when an MCG signal and an LCG signal are selected.Fig. 24 is a diagram showing an example of timing when the saturation level of the LCG signal and the residual signal are selected. Fig. 25 is a diagram showing the SN of the HCG signal, the MCG signal, and the saturation signal and residual signal of the LCG signal. Fig. 26 is a diagram showing an example of an imaging device to which the solid-state imaging device according to the embodiment is applied. Fig. 27 is a diagram showing an example of a distance measuring imaging device to which the solid-state imaging device according to the embodiment is applied.

[0011] A solid-state imaging device according to one aspect of the present disclosure includes a pixel circuit that outputs a plurality of pixel signals, a detection circuit, a pixel control circuit that controls the pixel circuit, and a signal processing unit. The pixel circuit includes a photodiode, a first transfer transistor that reads out the signal of the photodiode to a floating diffusion, and a storage capacitance that accumulates charge that overflows from the photodiode. The detection circuit compares the signal of the storage capacitance with a first reference value, and when the signal of the storage capacitance reaches the first reference value, initializes the photodiode and the storage capacitance via the pixel control circuit and counts the number of initializations. The signal processing unit calculates a first signal that indicates the intensity of incident light based on the number of initializations and a mixed signal of the signal of the photodiode and the signal of the storage capacitance that is read out to the floating diffusion by the first transfer transistor.

[0012] When high-intensity (high illuminance) incident light is incident, charge overflows from the photodiode and accumulates in the storage capacitor. However, there are cases where the incident light is so intense that it cannot be stored in the storage capacitor. Even in such cases, when the signal from the storage capacitor reaches a first reference value, the photodiode and storage capacitor are initialized, allowing charge to continue to be accumulated. At this time, the number of initializations is counted, thereby determining the amount of charge in the photodiode and storage capacitor that has been initialized. Then, by using a mixed signal of the photodiode signal and the storage capacitor signal when the signal from the storage capacitor no longer reaches the first reference value and the number of initializations, i.e., the amount of charge in the photodiode and storage capacitor that has been initialized one or more times since the incident light was incident, the intensity of the incident light can be calculated, even for high-intensity incident light. Therefore, the dynamic range can be easily expanded. For example, the dynamic range can be expanded more than when the PWM method is not used.

[0013] For example, the solid-state imaging device may include a sample-and-hold circuit and an AD conversion circuit.

[0014] For example, at least one pixel signal among the plurality of pixel signals may not be held by the sample-and-hold circuit but may be directly AD converted by the AD conversion circuit, and at least one other pixel signal among the plurality of pixel signals may be held by the sample-and-hold circuit, and the held signal may be AD converted by the AD conversion circuit.

[0015] This allows for the reduction of low-light noise by directly converting some pixel signals into digital data using an AD conversion circuit. For example, providing a sample-and-hold circuit for each pixel circuit eliminates the need for a memory corresponding to each of the multiple pixel signals. This is effective in miniaturized cells, where there are area limitations.

[0016] For example, when the number of initializations is 1 or more, the pixel circuit may output, during exposure, a mixed signal of the photodiode and the storage capacitor when the signal of the storage capacitor reaches the first reference value as a second signal, the photodiode and the storage capacitor are initialized, the second signal is held by the sample and hold circuit, and the held signal is A / D converted by the A / D conversion circuit, and the pixel circuit may output, at the end of exposure, a mixed signal remaining in the photodiode and the storage capacitor when the signal of the storage capacitor has not reached the first reference value as a third signal, and the third signal may be directly A / D converted by the A / D conversion circuit without being held by the sample and hold circuit.

[0017] According to this, the amount of charge per initialization can be maintained by holding in the sample-and-hold circuit the second signal, which is a mixed signal of the photodiode and the storage capacitor when the signal of the storage capacitor reaches the first reference value. Note that at the end of exposure, the third signal, which is a mixed signal remaining in the photodiode and the storage capacitor because the signal of the storage capacitor has not reached the first reference value, is directly AD converted by the AD conversion circuit because the second signal is already held in the sample-and-hold circuit.

[0018] For example, the signal processing unit may calculate the first signal by calculating the sum of the product of the second signal and the number of initializations and the third signal.

[0019] In this way, the first signal can be calculated by multiplying the second signal by the number of initializations and adding the third signal.

[0020] For example, the sample and hold circuit may include a first sample and hold capacitance element for a reset component and a second sample and hold capacitance element for a signal component, and when the number of initializations is 1 or more, the reset component may be held in the first sample and hold capacitance element after the photodiode and the storage capacitance are initialized during exposure, and the second signal may be held as a signal component in the second sample and hold capacitance element when the signal of the storage capacitance reaches the first reference value during exposure, and the AD conversion circuit may AD convert the pixel signal level by comparing a pixel signal level obtained by subtracting the reset component from the signal component with a second reference value.

[0021] In this way, by performing CDS, the second signal can be read accurately.

[0022] For example, when the number of initializations is 0, the pixel circuit outputs a fourth signal in a low-illuminance mode for low illuminance, and outputs a fifth signal in a mode for higher illuminance than the low-illuminance mode, the fourth signal is not held by the sample-and-hold circuit but is directly AD-converted by the AD conversion circuit, and the fifth signal is held by the sample-and-hold circuit, and the held signal is AD-converted by the AD conversion circuit.

[0023] According to this, the fourth signal output in the low-illuminance mode is directly AD-converted, thereby reducing low-illuminance noise. The fifth signal output in a mode for higher illuminance than the low-illuminance mode is held in a sample-and-hold circuit, which generates kTC noise during sampling. However, by combining the fifth signal with the fourth signal using WDR, the influence of kTC noise can be suppressed. Therefore, WDR with excellent S / N ratio in low illuminance can be achieved.

[0024] For example, the pixel circuit may include a second transfer transistor that transfers charge in the storage capacitance to the floating diffusion, a first amplification transistor that outputs a signal from the photodiode and a signal from the storage capacitance, a first selection transistor connected to the first amplification transistor, a second amplification transistor connected to the storage capacitance, and a second selection transistor connected to the second amplification transistor, wherein the detection circuit is connected to the storage capacitance via the second selection transistor and the second amplification transistor, and the pixel circuit outputs the signal from the photodiode as the fourth signal from the first amplification transistor via the first transfer transistor in the low illumination mode, and the high illumination mode includes a high illumination mode in which the pixel circuit outputs the signal from the storage capacitance from the first amplification transistor via the second transfer transistor as a sixth signal, and the sixth signal may belong to the fifth signal.

[0025] In this way, in the low-illuminance mode, the first amplifier transistor outputs a fourth signal for low illuminance via the first transfer transistor, and in the high-illuminance mode, the first amplifier transistor outputs a sixth signal for high illuminance via the second transfer transistor. Furthermore, since the signal of the storage capacitor can be detected via the second amplifier transistor, it is possible to determine whether the signal of the storage capacitor has reached the first reference value, or in other words, to count the number of initializations. For example, it is possible to suppress missed LED flicker.

[0026] For example, the pixel circuit may include a reset transistor, and the detection circuit may control the reset transistor, the first transfer transistor, and the second transfer transistor via the pixel control circuit based on a comparison result between the signal of the storage capacitance and a first reference value, thereby draining the charge of the photodiode and the storage capacitance and initializing the photodiode and the storage capacitance.

[0027] This makes it possible to reset the reset transistor, the first transfer transistor, and the second transfer transistor by controlling the pixel control circuit, and to more reliably discharge and initialize the charge in the storage capacitor and the photodiode.

[0028] For example, the pixel circuit may include a gain switching transistor that switches the gain of the photodiode signal, and the high illumination mode may include a medium illumination mode in which the gain switching transistor is controlled to cause the pixel circuit to output the photodiode signal from the first amplifying transistor as a seventh signal, and the seventh signal may belong to the fifth signal.

[0029] In this way, in the medium illumination mode, the seventh signal for medium illumination is output from the first amplifying transistor by controlling the gain switching transistor, and it is possible to reduce the S / N difference at the boundaries (transition regions) between the sixth signal for high illumination, the seventh signal for medium illumination, and the fourth signal for low illumination.

[0030] For example, the second reference value may be a saturation level of the fourth signal.

[0031] By setting the saturation level of the fourth signal for low illumination as the second reference value, it is possible to determine whether the intensity of incident light is low illumination or not, and then, depending on the result of the determination, a signal can be selected from among a plurality of pixel signals (e.g., the fourth signal, the sixth signal, and the seventh signal), thereby realizing a reduced area, higher speed, and lower power consumption of the solid-state imaging device.

[0032] For example, the signal processing unit may include a WDR processing unit, which generates an output signal from at least the first signal when the number of initializations is 1 or more, and generates an output signal from at least one of the fourth signal and the fifth signal when the number of initializations is 0.

[0033] In this way, when the number of initializations is 1 or more, i.e., when the incident light is of high illuminance, the output signal is generated by the first signal, and when the number of initializations is 0, i.e., when the incident light is of medium or low illuminance, the output signal is generated by the fourth or fifth signal (e.g., the sixth or seventh signal). This makes it possible to expand the dynamic range from low illuminance to high illuminance.

[0034] For example, the AD conversion circuit may include a comparator, and when the number of initializations is 0, the pixel circuit may output three or more pixel signals, and the comparator may compare one pixel signal among the three or more pixel signals with a second reference value after AD conversion, and when the one pixel signal reaches the second reference value, generate a selection signal that instructs selection of at least two pixel signals among the three or more pixel signals, and the pixel control circuit may select the at least two pixel signals from the three or more pixel signals based on the selection signal.

[0035] According to this, by selecting at least two pixel signals from three or more pixel signals output from the pixel circuit, it is possible to reduce the area, increase the speed, and reduce the power consumption of the solid-state imaging device. Note that if the counter circuit of the AD conversion circuit is a binary counter type, the digital signal is proportional to the level of the pixel signal, so at least two pixel signals can be selected. However, if the counter circuit of the AD conversion circuit is a Gray code counter type, the digital signal is not proportional to the level of the pixel signal, so at least two pixel signals cannot be selected. For this reason, this is particularly effective when a Gray code counter is used to achieve low power consumption.

[0036] For example, the AD conversion circuit and the detection circuit may be provided for each of the pixel circuits, and the pixel control circuit may control each of the pixel circuits.

[0037] This makes it possible to achieve faster AD conversion in the AD conversion circuit. In particular, with a global shutter, the problem of PLS ​​(parasitic sensitivity) occurs due to the longer waiting time of the charge in the floating diffusion, but PLS can be improved.

[0038] For example, the AD conversion circuit and the detection circuit may be provided for each of a plurality of the pixel circuits, the pixel control circuit may control each of the pixel circuits, and the detection circuit may compare the signal of the storage capacitance of the pixel circuit with the first reference value while synchronizing the corresponding pixel circuit with the pixel control circuit.

[0039] According to this, during exposure, the detection circuit and pixel control circuit operate in synchronization to target the same pixel circuit, making it possible to operate using pulse width modulation for each of the multiple pixel circuits shared by the AD conversion circuit and detection circuit.

[0040] For example, the pixel control circuit may synchronize the control of the first selection transistor, the second selection transistor, and the sample-and-hold circuit of the corresponding pixel circuit.

[0041] According to this, while the control of the first selection transistor, the second selection transistor, and the sample-and-hold circuit is synchronized, the pixel signal output from the first amplification transistor is input to the AD conversion circuit via the first selection transistor and the sample-and-hold circuit and is AD-converted. Similarly, while the control of the first selection transistor, the second selection transistor, and the sample-and-hold circuit is synchronized, the signal of the storage capacitor output from the second amplification transistor continues to be detected by the detection circuit via the second selection transistor. In this way, the first selection transistor, the second selection transistor, and the sample-and-hold circuit in the pixel circuit operate in synchronization with the control signal from the pixel control circuit, so that the signal level of the pixel signal (especially a pixel signal for high illuminance) can be correctly read for each pixel circuit.

[0042] For example, the plurality of pixel circuits may correspond to array pixels of a color filter, and the pixel control circuit may perform the same pixel control for the plurality of pixel circuits in accordance with the maximum signal level of the array pixels of the color filter.

[0043] This allows for WDR synthesis to be performed in units of color filter arrays, for example, in units of a Bayer array consisting of four colors (R, Gr, B, Gr), even if the color temperature of the subject changes, by using the gain of the maximum signal level of the four colors, it is possible to change the boundary portion, which is the WDR transition region, in a linked manner. As a result, the gain of each color becomes the same, and it is possible to prevent coloration due to deviation in the linearity of each color from occurring before and after the boundary portion.

[0044] For example, the solid-state imaging device may include a first semiconductor substrate having the pixel circuit and a second semiconductor substrate having the detection circuit and the AD conversion circuit, and the first semiconductor substrate and the second semiconductor substrate may be stacked.

[0045] If the first semiconductor substrate and the second semiconductor substrate are not stacked, there is a problem that the area of ​​the photodiode becomes small. However, by providing a stacked structure, it is possible to provide a detection circuit and an AD conversion circuit without affecting the area of ​​the photodiode.

[0046] For example, the first reference value may be a saturation level of the storage capacity.

[0047] According to this, when the storage capacitance is saturated, the photodiode and the storage capacitance are initialized, and the number of initializations can be counted.

[0048] A solid-state imaging device according to one aspect of the present disclosure comprises: a pixel circuit having a photodiode, a floating diffusion from which a signal of the photodiode is read out, a storage capacitance for storing charge overflowing from the photodiode, and reset means for initializing the photodiode, the floating diffusion, and the storage capacitance; and a detection circuit having a comparator for comparing the signal of the storage capacitance with a first reference value and an initialization circuit for controlling the reset means based on the comparison result of the comparator, wherein the pixel circuit is formed on a first semiconductor substrate made of one or more semiconductor layers, and the detection circuit is formed on a second semiconductor substrate made of one or more semiconductor layers, and the first semiconductor substrate and the second semiconductor substrate are stacked.

[0049] When high-intensity (high illuminance) incident light is incident, charge overflows from the photodiode and accumulates in the storage capacitor. However, there are cases where incident light of such intensity is too intense for the storage capacitor to store. Even in such cases, when the signal from the storage capacitor reaches a first reference value, the photodiode and storage capacitor are initialized, allowing charge to continue to accumulate. At that time, if the number of initializations is counted, the amount of charge in the photodiode and storage capacitor corresponding to the number of initializations can be determined. Then, by using a mixed signal of the photodiode signal and the storage capacitor signal when the signal from the storage capacitor no longer reaches the first reference value and the number of initializations, i.e., the amount of charge in the photodiode and storage capacitor corresponding to the number of initializations since the incident light was first detected, the intensity of the incident light can be calculated, even for high-intensity incident light. Therefore, the dynamic range can be easily expanded. For example, the dynamic range can be expanded more than when the PWM method is not used.

[0050] For example, the pixel circuit may include a first transfer transistor that reads out a signal from the photodiode to the floating diffusion, and a second transfer transistor that transfers a signal from the storage capacitor to the floating diffusion.

[0051] In this configuration, the signal from the photodiode during low-illuminance exposure (low-illuminance mode) is controlled by the first transfer transistor, and the signal from the storage capacitor during high-illuminance exposure (high-illuminance mode) is controlled by the second transfer transistor. This allows the former and latter signals to be read out at different times and used to combine the WDR, thereby further expanding the dynamic range.

[0052] For example, the detection circuit may have a counter function for counting the comparison results of the comparator.

[0053] According to this, by providing the detection circuit with a counter function that counts the comparison results of the comparator, it is possible to perform counting faster and more accurately. As a result, even when high-intensity light is temporarily incident on some pixel circuits that make up the pixel array, it is possible to capture the light without any loss, thereby improving the high-intensity signal-to-noise ratio.

[0054] For example, the pixel circuit may further include an AD conversion function formed on the second semiconductor substrate that converts the signal of the floating diffusion into a digital value, and the input terminals of the comparator and the AD conversion function may be connected to different output terminals of the pixel circuit, respectively.

[0055] In the solid-state imaging device disclosed in Patent Document 1, the low-illuminance signal, which is the remaining signal of the photodiode after PWM, cannot be read out, resulting in a deterioration in low-illuminance SNR. However, according to this aspect, the low-illuminance signal, which is the remaining signal after PWM, can be read out and processed using an AD conversion function, thereby improving the low-illuminance SNR.

[0056] For example, the detection circuit may further include an AD conversion function formed on the second semiconductor substrate for converting the signal of the floating diffusion into a digital value, and a selection circuit formed on the first semiconductor substrate or the second semiconductor substrate for receiving as input a signal from the storage capacitor and a signal from the floating diffusion and selecting an output, wherein the output of the selection circuit is input to the AD conversion function, and the detection circuit and the AD conversion function share the comparator.

[0057] According to this, the detection circuit and the AD conversion function share the comparator, so that the area of ​​the logic circuit can be reduced.

[0058] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0059] The embodiments described below are all comprehensive or specific examples, and the numerical values, shapes, materials, components, arrangement positions and connection forms of the components shown in the following embodiments are merely examples and are not intended to limit the present disclosure.

[0060] (Embodiments) [Configuration Example of Solid-State Imaging Device] A solid-state imaging device according to an embodiment will be described below.

[0061] FIG. 1 is a block diagram showing an example of the configuration of a solid-state imaging device 100 according to an embodiment.

[0062] The solid-state imaging device 100 includes a pixel array section 1, a vertical scanning circuit 14, input / output signal lines 19, a timing control section 20, a reference signal generation section 27, a signal processing section 70, and an output circuit 28. The solid-state imaging device 100 also includes an MCLK terminal for receiving an external master clock signal, a DATA terminal for transmitting and receiving commands or data to and from the outside, a D1 terminal for transmitting video data to the outside, and other terminals to which a power supply voltage and a ground voltage are supplied.

[0063] The pixel array unit 1 has a plurality of pixel circuits 3 arranged in a matrix. The pixel circuits 3 output a plurality of pixel signals. As will be described in detail later, the plurality of pixel signals include, for example, an HCG (High Conversion Gain) signal, an MCG (Middle Conversion Gain) signal, and an LCG (Low Conversion Gain) signal. There are various configuration examples for the pixel circuit 3, and pixel circuits 3a, 3b, and 3c will be described later as configuration examples of the pixel circuit 3. However, when there is no need to distinguish between the pixel circuits 3a, 3b, and 3c, they will be referred to as pixel circuits 3. The plurality of pixel circuits 3 are arranged in n rows and m columns in FIG. 1 .

[0064] The pixel array section 1 includes a plurality of logic circuits 4 provided corresponding to a plurality of pixel circuits 3. In the example shown in Fig. 1, the pixel array section 1 includes one logic circuit 4 for one pixel circuit 3. Note that a plurality of logic circuits 4 may be provided for a plurality of pixel circuits 3. The logic circuit 4 has a function such as AD conversion of pixel signals output from the pixel circuits 3. There are at least two types of pixel signals: a reset component and a signal component.

[0065] The AD converted pixel signal is output to the signal processing unit 70 via the input / output signal line 19 .

[0066] To implement GS (global shutter), the vertical scanning circuit 14 simultaneously and collectively controls horizontal scanning lines (also referred to as row control lines) 15 provided for each row of pixel circuits 3 in the pixel array unit 1. Output signals from the logic circuit 4 are simultaneously output to m input / output signal lines 19 (vertical signal lines) and transferred to the signal processing unit 70.

[0067] In FIG. 1, a group of n horizontal scanning lines 15 (V1, V2, . . . , Vn) is provided for a plurality of pixel circuits 3, and each of the horizontal scanning lines 15 includes control lines for the reset transistor, transfer transistor, and selection transistor in the pixel circuit 3.

[0068] The timing control unit 20 generates a variety of control signals to control the entire solid-state imaging device 100. The various control signals include control signals CN1, CN4, CN5, and CN8, and a counter clock signal CK0. The timing control unit 20 receives a master clock via an MCLK terminal, generates various internal clocks, and controls the vertical scanning circuit 14 and the like.

[0069] The reference signal generating unit 27 generates a reference signal RAMP including a triangular wave and outputs the reference signal RAMP to the positive input terminal of a comparator 511 in an AD conversion circuit 51, which will be described later. As shown in FIG. 2A and other figures, the reference signal generating unit 27 includes reference signal generating units 271 and 272. The reference signal generating unit 271 generates a reference signal 1 and outputs it to the logic circuit 4. The reference signal 1 is an example of a first reference value. The reference signal generating unit 272 generates a reference signal 2 and outputs it to the logic circuit 4. The reference signal 2 is an example of a second reference value. The reference signal 2 becomes the reference signal RAMP used in AD conversion and the saturation level of the HCG signal, which will be described later.

[0070] The signal processing unit 70 is a processing unit that performs WDR combining, and includes a WDR combining circuit 76 and a memory 77. The WDR combining circuit 76 and the memory 77 will be described in detail later.

[0071] The output circuit 28 outputs the digital pixel signal to a D1 terminal.

[0072] As described above, there are various configuration examples for the pixel circuit 3, and each configuration example will be described with reference to FIGS. 2A to 4. FIG.

[0073] 2A to 4 are block diagrams showing configuration examples of a pixel circuit 3 and a logic circuit 4 according to an embodiment. Figures 2A to 2C show configuration examples of a horizontal overflow drain (OFD) pixel circuit 3, and Figures 3 and 4 show configuration examples of a vertical OFD pixel circuit 3.

[0074] [Configuration Example of Pixel Configuration (Horizontal OFD)] First, a configuration example of the pixel circuit 3 of a horizontal OFD will be described with reference to FIG. 2A.

[0075] 2A, pixel circuit 3a is shown as one of a plurality of pixel circuits 3 arranged in a matrix in pixel array section 1. Solid-state imaging device 100 can also include a sample-and-hold circuit 30 connected to pixel circuit 3a. This configuration is suitable for the global shutter system.

[0076] The pixel circuit 3a has a horizontal OFD pixel configuration, and the horizontal OFD has a configuration in which storage circuits are arranged in the horizontal direction.

[0077] The pixel circuit 3a includes a photodiode PD, a transfer transistor TG, a charge storage unit FD0, amplification transistors SF1 and SF2, a reset transistor RS, and selection transistors SEL1 and SEL2. The pixel circuit 3a further includes a storage capacitor C1, a gain control transistor GC1, a storage capacitor C2, and a gain control transistor TGC, which are arranged in a horizontal direction from the viewpoint of charge transfer.

[0078] The photodiode PD is a photoelectric conversion element that converts incident light into a signal charge.

[0079] The charge storage unit FD0 is formed as, for example, a floating diffusion layer, and is a floating diffusion that holds the signal charge generated in the photodiode PD. In the drawing, the storage capacitance of the charge storage unit FD0 is designated as storage capacitance C0.

[0080] The amplification transistor SF1 outputs a pixel signal corresponding to the signal charge of the charge storage unit FD0 to the logic circuit 4 via the selection transistor SEL1. The amplification transistor SF1 is an example of a first amplification transistor that outputs a signal from the photodiode PD and a signal from the storage capacitor C2.

[0081] The selection transistor SEL1 is a switch element that selects whether or not to output a pixel signal from the amplification transistor SF1 to the logic circuit 4. The selection transistor SEL1 is an example of a first selection transistor connected to the amplification transistor SF1.

[0082] The reset transistor RS is an example of a reset means that initializes the photodiode PD, the charge storage unit FD0, and the storage capacitance C2. The reset transistor RS can be reset in three ways under the control of the gain control transistor GC1 and the TGC. That is, the reset transistor RS can reset the charge storage units FD0, FD1, and FD2. The storage capacitance of the charge storage unit FD1 is defined as storage capacitance C1, and the storage capacitance of the charge storage unit FD2 is defined as storage capacitance C2.

[0083] When the transfer transistor TG is in the ON state, the charge that overflows from the charge storage section FD0 is transferred to and held in the storage capacitor C1 as indicated by the dotted arrow A in the figure.

[0084] The gain control transistor GC1 controls the connection between the charge storage unit FD0 and the storage capacitor C1. The gain control transistor GC1 acts as a switching element and is in an ON state or an OFF state. The gain control transistor GC1 is an example of a gain switching transistor that switches the gain of the signal from the photodiode PD.

[0085] Signal charge that overflows the photodiode PD during exposure is transferred to and held in the storage capacitor C2, as indicated by the dotted arrow B in the figure. An overflow element OF is located between the photodiode PD and the storage capacitor C2, and during exposure, the signal charge that overflows from the photodiode PD is transferred to the storage capacitor C2 via the overflow element OF rather than being transferred to the storage capacitor C1 via the transfer transistor TG. The storage capacitor C2 stores the charge that overflows from the photodiode PD.

[0086] Furthermore, the signal charge that has overflowed the storage capacitor C2 is discharged to the power supply via the gain control transistor TGC and the reset transistor RS.

[0087] Furthermore, as indicated by the dotted arrow B, the signal charge overflowing from the photodiode PD is accumulated in the accumulation capacitor C2 without passing through the charge accumulation unit FD0, thereby reducing the influence of the dark current component in the charge accumulation unit FD0. Furthermore, the presence of the overflow element OF makes it possible to control the overflow level and the depth of the charge channel, thereby reducing the influence of the dark current component generated in the surface layer.

[0088] The gain control transistor TGC is a transistor for gain control that controls the connection between the storage capacitors C1 and C2. The gain control transistor TGC acts as a switching element and is in an ON state or an OFF state. The gain control transistor TGC is an example of a second transfer transistor that transfers the charge (signal) of the storage capacitor C2 to the charge storage unit FD0.

[0089] To hold the signal charge overflowing from the photodiode PD, an overflow storage circuit is provided, each consisting of a switch element and a storage capacitor. The first-stage storage circuit is a pair of a gain control transistor GC1 and a storage capacitor C1. The second-stage storage circuit is a pair of a gain control transistor TGC and a storage capacitor C2.

[0090] For example, in a global shutter system, all pixels are exposed simultaneously, and then the signals of all pixels are read out to the sample-and-hold circuit 30 simultaneously.

[0091] Such a configuration example makes it possible to achieve both an expansion of the dynamic range and an improvement in the S / N ratio.

[0092] The logic circuit 4 includes an AD conversion circuit 51, a detection circuit 52, and a local pixel control circuit 61. In this embodiment, when the AD conversion circuit 51 and the detection circuit 52 are provided for each single or multiple pixel circuits 3 a, the pixel control circuit that controls the pixel circuit 3 a is particularly called the local pixel control circuit 61.

[0093] The AD conversion circuit 51 is an example of an AD conversion function that converts the signal of the charge storage unit FD0 into a digital value. The AD conversion circuit 51 includes a comparator 511, a counter circuit 512, and a memory 513.

[0094] The comparator 511 compares the analog pixel signal output from the pixel circuit 3a with the RAMP waveform (i.e., triangular wave) that is the reference signal 2 generated by the reference signal generation unit 27, and inverts the output signal that indicates the comparison result when, for example, the former becomes larger than the latter.

[0095] The counter circuit 512 counts the time from when the triangular wave in the reference signal RAMP, which is the reference signal 2, starts to change until the output signal of the comparator 511 inverts. Since the time until inversion is determined according to the value of the analog pixel signal, this count value becomes a digitized pixel signal. In this way, AD conversion is performed.

[0096] The memory 513 holds the count value of the counter circuit 512, that is, the digital pixel signal.

[0097] The detection circuit 52 is connected to the storage capacitor C2 via the selection transistor SEL2 and the amplification transistor SF2. The detection circuit 52 operates in a PWM mode. The detection circuit 52 compares the signal of the storage capacitor C2 with a reference signal 1, and when the signal of the storage capacitor C2 reaches the reference signal 1, the detection circuit 52 initializes the photodiode PD and the storage capacitor C2 almost simultaneously via a local pixel control circuit 61 and counts the number of initializations N. The local pixel control circuit 61 is an example of a pixel control circuit that controls the pixel circuit 3a. The detection circuit 52 includes a comparator 521, a counter circuit 522, a memory 523, and an initialization circuit 524.

[0098] The comparator 521 compares the signal of the storage capacitor C2 with the reference signal 1. When the storage capacitor C2 reaches the saturation level of the reference signal 1, the output signal of the comparator 521 is inverted, and the detection circuit 52 counts the number of inversions in the counter circuit 522, i.e., the initialization count N, and stores the count in the memory 523. The counter circuit 522 is an example of a counter function that counts the comparison results of the comparator 521.

[0099] The initialization circuit 524 controls the reset transistor RS based on the comparison result of the comparator 521. Specifically, when the storage capacitance C2 reaches the reference signal 1, which is the saturation level, that is, when the inverted output signal of the comparator 521 is input, the initialization circuit 524 outputs an initialization signal to the local pixel control circuit 61 to operate the local pixel control circuit 61, and the local pixel control circuit 61 performs pixel control necessary for initializing the pixel circuit 3 a.

[0100] In the circuit shown in FIG. 2A, the input terminals of the comparator 521 and the AD conversion circuit 51 are connected to different output terminals of the pixel circuit 3a.

[0101] For example, based on the comparison result between the signal of the storage capacitor C2 and the reference signal 1, the detection circuit 52 controls the reset transistor RS, the transfer transistor TG, and the gain control transistor TGC via the local pixel control circuit 61 to drain the charge from the photodiode PD and the storage capacitor C2 and initialize the photodiode PD and the storage capacitor C2.

[0102] The logic circuit 4 can expand the dynamic range by using a PWM method for the pixel circuits 3a with an overflow structure in the global shutter. Furthermore, as described below, the AD conversion circuit 51 selectively reads at least two pixel signals from the plurality of pixel signals, rather than redundantly reading all of the pixel signals. By reducing the number of pixel signals to at least two, the number of bits in the memories 513 and 523 can be reduced, yield can be improved, and the subsequent stages can be made faster and consume less power. Furthermore, the signal processing unit 70 can also achieve higher speeds and lower power consumption while maintaining a dynamic range equivalent to that when there are multiple (at least three) pixel signals.

[0103] In the global shutter method, all pixels are exposed to light at the same time, and then signals from all pixels are simultaneously read out to the sample-and-hold circuit 30. Alternatively, signals from all pixels are directly AD-converted by the AD conversion circuit 51. Then, a plurality of pixel signals are supplied from the AD conversion circuit 51 to the signal processing unit 70.

[0104] The circuits shown in Figures 2B and 2C are modifications of the circuit shown in Figure 2A, in which a single comparator is shared by the detection circuit 52 and the AD conversion circuit 51. Figure 2B shows an example in which the detection circuit 52 and the AD conversion circuit 51 share a comparator 521, and Figure 2C shows an example in which the detection circuit 52 and the AD conversion circuit 51 share a comparator 511.

[0105] 2B and 2C, the solid-state imaging device 100 (logic circuit 4) may include a selection circuit SW1 that receives a signal from the storage capacitor C2 and a signal from the charge storage unit FD0 and selects an output. The solid-state imaging device 100 (logic circuit 4) may also include a selection circuit SW2.

[0106] 2B, the signal of the storage capacitor C2 and the signal of the charge storage unit FD0 are input to the selection circuit SW1, and the selected signal is input to one end of the comparator 521. On the other hand, the reference signal 1 of the reference signal generation unit 271 and the reference signal 2 of the reference signal generation unit 272 are input to the selection circuit SW2, and the selected signal is input to the other end of the comparator 521.

[0107] 2C , the signal of the storage capacitor C2 and the signal of the charge storage unit FD0 are input to the selection circuit SW1, and the selected signal is input to one end of the comparator 511. On the other hand, the reference signal 1 of the reference signal generation unit 271 and the reference signal 2 of the reference signal generation unit 272 are input to the selection circuit SW2, and the selected signal is input to the other end of the comparator 511.

[0108] 2A, the signal of the storage capacitor C2 is compared with a reference signal 1, and the signal of the charge storage unit FD0 is compared with a reference signal 2. The control signals of the selection circuits SW1 and SW2 cause the former comparison operation to be performed during the exposure time, and the latter comparison operation to be performed during the AD conversion (ADC) time, in a time-exclusive manner.

[0109] In this way, the detection circuit 51 and the AD conversion circuit 52 share the comparator, so that the area of ​​the logic circuit 4 can be reduced.

[0110] 3 to 5, similarly to FIG. 2B or FIG. 2C, one comparator may be shared by the detection circuit 51 and the AD conversion circuit 52.

[0111] [Configuration Example 1 of Pixel Configuration (Vertical OFD)] Next, configuration example 1 of the pixel circuit 3 of the vertical OFD will be described with reference to Fig. 3. In configuration example 1 of the vertical OFD, the storage circuits of the above-mentioned horizontal OFD are connected in two stages in the vertical direction.

[0112] 3, pixel circuit 3b is shown as one of a plurality of pixel circuits 3 arranged in a matrix in pixel array section 1. Solid-state imaging device 100 can also include a sample-and-hold circuit 30 connected to pixel circuit 3b. This configuration is suitable for the global shutter system.

[0113] The pixel circuit 3b will be described below, focusing on the differences from the pixel circuit 3a.

[0114] In the pixel circuit 3b, the storage capacitor C1, the gain control transistor GC1, the storage capacitor C2, and the gain control transistor TGC are arranged in the vertical direction from the viewpoint of charge movement.

[0115] The signal charge that overflows the photodiode PD during exposure is transferred to and held in the storage capacitor C1, as indicated by the dotted arrow D in the figure. Furthermore, the signal charge that overflows from the storage capacitor C1 is transferred to and held in the storage capacitor C2.

[0116] The storage capacitor C1 holds signal charges that overflow from the photodiode PD. For example, the storage capacitor C1 stores signal charges that overflow from the photodiode PD during exposure via the transfer transistor TG and the gain control transistor GC1.

[0117] The gain control transistor GC1 controls the connection between the charge storage unit FD0 and the storage capacitor C1. The gain control transistor GC1 acts as a switching element, being in an ON state or an OFF state. Note that the gate voltages of the transfer transistor TG and the gain control transistor GC1 do not have to be completely OFF during exposure, and may be set so that signal charge overflowing from the photodiode PD can be transmitted from the transfer transistor TG to the storage capacitor C1 via the charge storage unit FD0 and the gain control transistor GC1.

[0118] The storage capacitor C2 holds the signal charge that has overflowed from the storage capacitor C1. For example, the storage capacitor C2 stores the signal charge that has overflowed from the storage capacitor C1 via the gain control transistor TGC.

[0119] The gain control transistor TGC controls the connection between the storage capacitor C1 and the storage capacitor C2. The gain control transistor TGC acts as a switching element and is in an ON state or an OFF state. The gate voltage of the gain control transistor TGC does not have to be completely OFF during exposure, and may be set so that signal charge overflowing from the storage capacitor C1 can be transmitted to the storage capacitor C2 via the gain control transistor TGC.

[0120] Such a configuration example makes it possible to achieve both an expansion of the dynamic range and an improvement in the S / N ratio.

[0121] The logic circuit 4 is the same as that described in FIG. 2A, and therefore a description thereof will be omitted.

[0122] [Configuration Example 2 of Pixel Configuration (Vertical OFD)] Next, Configuration Example 2 of the pixel circuit 3 of the vertical OFD will be described with reference to Fig. 4. Configuration Example 2 of the vertical OFD is a modification of Configuration Example 1 of the vertical OFD described above.

[0123] 4, pixel circuit 3c is shown as one of a plurality of pixel circuits 3 arranged in a matrix in pixel array section 1. Solid-state imaging device 100 can also include a sample-and-hold circuit 30 connected to pixel circuit 3c. This configuration is suitable for the global shutter system.

[0124] The pixel circuit 3c will be described below, focusing on the differences from the pixel circuit 3a.

[0125] In the pixel circuit 3c, the storage capacitor C1, the gain control transistor GC1, the storage capacitor C2, and the gain control transistor TGC are arranged in the vertical direction from the viewpoint of charge movement.

[0126] The signal charge that overflows the photodiode PD during exposure is transferred to and held in the storage capacitor C2 as indicated by the dotted arrow E in the figure.

[0127] The gain control transistor GC1 controls the connection between the charge storage unit FD0 and the storage capacitor C1. The gain control transistor GC1 acts as a switching element and is in an ON state or an OFF state.

[0128] The storage capacitor C2 holds signal charge that overflows from the photodiode PD. For example, the storage capacitor C2 stores the signal charge that overflows from the photodiode PD during exposure via the transfer transistor TG and the gain control transistor TGC. Note that the gate voltages of the transfer transistor TG and the gain control transistor TGC do not have to be completely OFF during exposure, and may be set so that the signal charge that overflows from the photodiode PD can be transmitted from the transfer transistor TG to the storage capacitor C2 via the charge storage unit FD0 and the gain control transistor TGC.

[0129] The gain control transistor TGC controls the connection between the charge storage unit FD0 and the storage capacitor C2. The gain control transistor TGC acts as a switching element and is in an ON state or an OFF state.

[0130] Such a configuration example makes it possible to achieve both an expansion of the dynamic range and an improvement in the S / N ratio.

[0131] The logic circuit 4 is the same as that described in FIG. 2A, and therefore a description thereof will be omitted.

[0132] 2A to 4 have described an example in which the AD conversion circuit 51 and the detection circuit 52 are provided for each single pixel circuit 3, and the local pixel control circuit 61 controls each single pixel circuit 3, but the AD conversion circuit 51 and the detection circuit 52 may be provided for each plurality of pixel circuits 3, and the local pixel control circuit 62 may control each single pixel circuit 3. This will be described using FIG.

[0133] 5 is a diagram illustrating the sharing of a logic circuit 4d by a plurality of pixel circuits 3. In FIG. 5, pixel circuits A to D are shown as a plurality of pixel circuits 3, which are grouped into a pixel circuit group 3d. Note that any of pixel circuits 3a, 3b, and 3c may be used as the pixel circuit 3. Regarding logic circuit 4d, differences from logic circuit 4 will be described.

[0134] The pixel circuit group 3d (pixel circuits A to D) share one AD conversion circuit 51 and one detection circuit 52. Note that the memory 515 included in the AD conversion circuit 51 and the memory 525 included in the detection circuit 52 are provided with an area for each pixel circuit 3. In Fig. 5, A to D are written within the memories 515 and 525, which schematically shows that the memories 515 and 525 are provided with areas for each of the pixel circuits A to D.

[0135] Furthermore, the local pixel control circuit 62 is an example of a pixel control circuit that controls each pixel circuit 3 individually. In Fig. 5, A to D are written within the local pixel control circuit 62, which schematically shows that the local pixel control circuit 62 controls each pixel circuit 3 individually.

[0136] The detection circuit 52 synchronizes the corresponding pixel circuit 3 with the local pixel control circuit 62, and compares the signal of the storage capacitance C2 of the pixel circuit 3 with the reference signal 1. For example, the detection circuit 52 synchronizes the pixel circuit A with the local pixel control circuit 62, and compares the signal of the storage capacitance C2 of the pixel circuit A with the reference signal 1. This makes it possible to determine for each pixel circuit 3 whether the storage capacitance C2 has reached the saturation level of the reference signal 1.

[0137] Furthermore, the local pixel control circuit 62 synchronizes the control of the select transistors SEL1 and SEL2 of the corresponding pixel circuit 3 and the sample and hold circuit 30. For example, the sample and hold circuit 30 includes a capacitance element CR for a reset component and a capacitance element CS for a signal component, and the local pixel control circuit 62 synchronizes the control of the select transistors SEL1 and SEL2 of the corresponding pixel circuit 3 and the capacitance elements CR and CS. The capacitance element CR is an example of a first sample and hold capacitance element, and the capacitance element CS is an example of a second sample and hold capacitance element.

[0138] During exposure, AD conversion circuit 51, detection circuit 52, and local pixel control circuit 62 are synchronized to target the same pixel circuit 3. For the target pixel circuit 3, the pixel signal value is held in an area of ​​memory 515 of AD conversion circuit 51 for the target pixel circuit 3, and the number of initializations N detected by detection circuit 52 is held in an area of ​​memory 525 for the target pixel circuit 3, and local pixel control circuit 62 independently controls selection transistors SEL1 and SEL2 and sample-and-hold circuit 30 of the target pixel circuit 3 while synchronizing them. With this configuration, PWM operation can be performed on multiple pixel circuits 3 during exposure.

[0139] Note that because detection is performed for the pixel circuit group 3d in the order of pixel circuits A, B, C, and D, for example, the detection timing by the detection circuit 52 differs for each pixel circuit 3, resulting in a delay between the time when the signal in the storage capacitor C2 exceeds the reference signal 1 and the time when the detection circuit 52 actually detects it. However, for each pixel circuit 3, when the detection circuit 52 detects that the storage capacitor C2 has reached the saturation level, the signal component at the saturation level is held in the sample and hold capacitor element CS of the sample and hold circuit 30. This allows each pixel circuit 3 to correctly hold the signal component at the time of detection by the detection circuit 52. Then, for each pixel circuit 3, CDS of the signal component is performed using the reset component previously held in the capacitor element CR when the storage capacitor C2 and the photodiode PD are initialized, thereby correctly detecting the signal at the saturation level of the storage capacitor C2. In this way, even when multiple pixel circuits 3 share a single detection circuit 52, the PWM method can be used.

[0140] This is particularly effective when the AD conversion circuit 51 and the detection circuit 52 cannot be provided for each pixel circuit 3 in a fine cell.

[0141] [Sample-and-Hold Circuit] FIG. 6 is a diagram showing an example of the configuration of the sample-and-hold circuit 30. As shown in FIG.

[0142] The reset component is held in the capacitance element CR by the sample and hold signal SHR. The signal component is held in the capacitance element CS by the sample and hold signal SHS. When the sample and hold signal SHRST is set to a high level, the capacitance elements CR and CS can be discharged.

[0143] At least one pixel signal among the plurality of pixel signals including the HCG signal, the MCG signal, and the LCG signal is not held by the sample-and-hold circuit 30 and is directly AD-converted by the AD conversion circuit 51, and at least one other pixel signal among the plurality of pixel signals is held by the sample-and-hold circuit 30 and the held signal is AD-converted by the AD conversion circuit 51.

[0144] [Expansion of Dynamic Range with WDR] Here, the WDR synthesis circuit 76 included in the signal processing unit 70 will be described. The WDR synthesis circuit 76 is an example of a WDR processing unit. The WDR synthesis circuit 76 performs WDR synthesis, which synthesizes multiple pixel signals output from the pixel circuits 3. As described above, the multiple pixel signals include an HCG signal, an MCG signal, and an LCG signal.

[0145] The signal processing unit 70 (WDR synthesis circuit 76) calculates a first signal indicating the intensity of the incident light based on the number of initializations N and a mixed signal of the signal of the photodiode PD read out to the charge storage unit FD0 by the transfer transistor TG and the signal of the storage capacitor C2.

[0146] When the number of initializations N is 1 or greater, the pixel circuit 3 outputs a mixed signal of the photodiode PD and the storage capacitor C2 when the signal of the storage capacitor C2 reaches the reference signal 1 during exposure as the saturation signal Qsat of the LCG signal, and the photodiode PD and the storage capacitor C2 are initialized. The saturation signal Qsat is held by the sample-and-hold circuit 30, and the held signal is AD-converted by the AD conversion circuit 51. At the end of exposure, the pixel circuit 3 outputs a mixed signal remaining in the photodiode PD and the storage capacitor C2 when the signal of the storage capacitor C2 has not yet reached the reference signal 1 as the residual signal of the LCG signal. The residual signal is not held by the sample-and-hold circuit 30, but is directly AD-converted by the AD conversion circuit 51. The first signal includes the saturation signal Qsat and the residual signal of the LCG signal. The saturation signal Qsat is an example of a second signal, and the residual signal is an example of a third signal. The signal processing unit 70 (WDR synthesis circuit 76) calculates the first signal by calculating the sum of the product of the saturation signal Qsat and the number of initializations N and the residual signal.

[0147] When the number of initializations N is 1 or greater, the sample-and-hold circuit 30 holds a reset component in the capacitance element CR after the photodiode PD and the storage capacitor C2 are initialized during exposure. Furthermore, when the signal in the storage capacitor C2 reaches the reference signal 1 during exposure, the sample-and-hold circuit 30 holds a saturation signal Qsat as a signal component in the capacitance element CS. The AD conversion circuit 51 then performs AD conversion of the pixel signal level by comparing the pixel signal level, obtained by subtracting the reset component from the signal component, with the reference signal 2.

[0148] When the number of initializations N is 0, the pixel circuit 3 outputs the HCG signal in a low-illuminance mode for low illuminance. The HCG signal is an example of a fourth signal. Also, when the number of initializations N is 0, the pixel circuit 3 outputs the MCG signal or the LCG signal in a mode for higher illuminance than the low-illuminance mode. The LCG signal is an example of a sixth signal. The MCG signal is an example of a seventh signal. The LCG signal and the MCG signal belong to the fifth signal.

[0149] In the low illuminance mode, the pixel circuit 3 outputs the signal of the photodiode PD as the HCG signal from the amplification transistor SF1 via the transfer transistor TG. Specifically, the low illuminance mode is a mode in which the storage capacitor C0 of the storage capacitors C0, C1, and C2 is used, and is a mode in which the sensitivity to incident light of low illuminance is high.

[0150] Modes for higher illumination than the low illumination mode include a medium illumination mode and a high illumination mode.

[0151] In the medium illumination mode, the pixel circuit 3 controls the gain control transistor GC1 to output the signal of the photodiode PD as the MCG signal from the amplification transistor SF1. Specifically, the medium illumination mode is a mode in which the storage capacitors C0 and C1 of the storage capacitors C0, C1, and C2 are used and incident light of a medium illumination intensity can be detected.

[0152] In the high illuminance mode, the pixel circuit 3 outputs the signal of the storage capacitor C2 as an LCG signal from the amplification transistor SF1 via the gain control transistors TGC and GC1. Specifically, the high illuminance mode is a mode in which the storage capacitors C0, C1, and C2 are used and in which high illuminance incident light can be detected.

[0153] The HCG signal is not held by the sample-and-hold circuit 30, but is directly AD-converted by the AD conversion circuit 51. The MCG signal or LCG signal is held by the sample-and-hold circuit 30, and the held signal is AD-converted by the AD conversion circuit 51.

[0154] The WDR combining circuit 76 generates an output signal from at least the first signal when the initialization count N is 1 or greater. When the initialization count N is 0, the WDR combining circuit 76 generates an output signal from at least one of the HCG signal, the MCG signal, and the LCG signal. The generated output signal is output to the output circuit 28.

[0155] As will be described in detail later, when performing WDR synthesis, the pixel signal used to generate the output signal can be determined from only the HCG signal among the multiple pixel signals. This allows the number of pixel signals output from the pixel circuit 3 to be reduced, thereby realizing faster readout in the logic circuit 4. Furthermore, the number of bits in the memories 513 and 523 of the logic circuit 4 can be reduced, making it possible to reduce the area and prevent a decrease in yield.

[0156] The exposure control of the three frames obtained by WDR composition using high-illuminance exposure (high-illuminance mode), medium-illuminance exposure (medium-illuminance mode), and low-illuminance exposure (low-illuminance mode) is performed using the global shutter method, and because they are exposed at exactly the same timing and use exactly the same pixels, false colors, coloring, and temporal blurring do not occur.In other words, because each frame is exposed simultaneously, temporal blurring and coloring do not occur between frames.

[0157] The pixel signal in a frame in a low-illuminance region (low-illuminance exposure) is an HCG signal with a high intra-pixel gain, the pixel signal in a frame in a medium-illuminance region (medium-illuminance exposure) is an MCG signal with a medium intra-pixel gain, and the pixel signal in a frame in a high-illuminance region (high-illuminance exposure) is an LCG signal with a low intra-pixel gain. By using these pixel signals, it is possible to improve noise in low illumination and expand the dynamic range in high illumination.

[0158] FIG. 7 is a diagram showing an overview of how WDR combining is performed within a pixel.

[0159] 8 is a diagram showing an example configuration of a signal processing unit 70 that performs WDR synthesis using three signals. In this example, the signal processing unit 70 includes an HCG signal generation circuit 71, an MCG signal generation circuit 72, and an LCG signal generation circuit 73. The HCG signal generation circuit 71 generates an HCG signal from the digital values ​​of pixel signals in low illumination mode. The MCG signal generation circuit 72 generates an MCG signal from the digital values ​​of pixel signals in medium illumination mode. The LCG signal generation circuit 73 generates an LCG signal from the digital values ​​of pixel signals in high illumination mode.

[0160] WDR synthesis is performed using the signal charge Q0 (charge on storage capacitor C0) of the HCG signal resulting from low-illuminance exposure (low-illuminance mode), the signal charges Q0 and Q1 (charges on storage capacitors C0 and C1) of the MCG signal resulting from medium-illuminance exposure (medium-illuminance mode), and the signal charges Q0, Q1, and Q2 (charges on storage capacitors C0, C1, and C1) of the LCG signal resulting from high-illuminance exposure (high-illuminance mode). The horizontal axes in (a) to (d) of Figure 7 represent the product of illuminance and exposure time, illuminance for a fixed period of time, or exposure time at a fixed illuminance. The vertical axes represent the charge accumulation level in (a) of Figure 7, the signal potential of the pixel unit in (b) of Figure 7, the value after AD conversion in (c) of Figure 7, and the S / N level in (d) of Figure 7.

[0161] 7(c) and 7(d) are diagrams for explaining the details of the WDR synthesis circuit 76 constituting the signal processing unit 70. At boundary T1, which is a transition region between low-illuminance exposure and medium-illuminance exposure in the "illuminance / exposure time," the charge in storage capacitor C0 becomes charge Q0' just before saturation as shown in FIG. 7(a), and the signal potential of the pixel unit becomes signal potential FDH as shown in FIG. 7(b). At boundary T2, which is a transition region between medium-illuminance exposure and high-illuminance exposure in the "illuminance / exposure time," the charge in storage capacitors C0 and C1 becomes charge Q0+Q1' just before saturation as shown in FIG. 7(a), and the signal potential of the pixel unit becomes signal potential FDM as shown in FIG. At the boundary T3 of "illuminance / exposure time" in the maximum high-illuminance exposure region, the charges of the storage capacitors C0, C1, and C2 become Q0+Q1+Q2' just before they are saturated, as shown in FIG. 7(a), and the signal potential of the pixel portion becomes FDL, as shown in FIG. 7(b).

[0162] The WDR synthesis circuit 76 realizes the WDR function by synthesizing the pixel signal of the low-illuminance frame (low-illuminance exposure), the pixel signal of the medium-illuminance frame (medium-illuminance exposure), and the pixel signal of the high-illuminance frame (high-illuminance exposure), i.e., the dynamic range is expanded.

[0163] 9 is a diagram showing an example of the configuration of a signal processing unit that performs WDR synthesis using two signals selected from three signals. In this example, a signal processing unit 70 includes an interpolation circuit 74.

[0164] The memory 77 stores the gain ratios or sensitivity ratios of the pixel values ​​of the HCG signal, MCG signal, and LCG signal corresponding to the illuminance and exposure time. The gain ratios or sensitivity ratios are measured in advance and stored in the memory 77. For example, the memory 77 stores Gain1 and Gain2 shown in FIG. 7C. Gain1 is the gain ratio between the MCG signal and the HCG signal. Gain2 is the gain ratio between the LCG signal and the HCG signal. The gain ratio between the LCG signal and the MCG signal may be calculated by Gain2 / Gain1, or a pre-measured value may be stored. In this way, once one value of the HCG signal, MCG signal, and LCG signal is identified, the other two values ​​can be calculated by interpolation processing by the interpolation circuit 74 using the above gain ratios. The memory 77 may store sensitivity ratios instead of gain ratios.

[0165] The interpolation circuit 74 determines, by interpolation processing, the pixel value of the one pixel signal not selected by the logic circuit 4, based on two pixel signals selected by the logic circuit 4 out of the three pixel signals, the HCG signal, the MCG signal, and the LCG signal. The pixel value of the one pixel signal not selected by the logic circuit 4 is determined by interpolation processing in the interpolation circuit 74 and input to the WDR synthesis circuit 76. The interpolation processing means interpolation or estimation.

[0166] The WDR synthesis circuit 76 synthesizes the three pixel signals so that they are linear, based on the pixel signals selected by the logic circuit 4 and the pixel signals obtained by the interpolation process of the interpolation circuit 74, using the gain ratio or sensitivity ratio data stored in the memory 77.

[0167] For example, as shown in (b) of FIG. 7, when pixel values ​​PH and PM of pixel signals enclosed by dashed lines are selected for the HCG signal and the MCG signal, the LCG signal is obtained by interpolation processing from the gain ratio or sensitivity ratio stored in the memory 77.

[0168] Similarly, as shown in (b) of FIG. 7, when pixel values ​​PM and PL of pixel signals enclosed by dashed lines are selected for the MCG signal and the LCG signal, the HCG signal is obtained by interpolation processing from the gain ratio or sensitivity ratio stored in memory 77.

[0169] In this way, the signal processing unit 70 obtains two of the pixel value PH of the HCG signal, the pixel value PM of the MCG signal, and the pixel value PL of the LCG signal. The signal processing unit 70 also obtains one of the pixel value PH of the HCG signal, the pixel value PM of the MCG signal, and the pixel value PL of the LCG signal by interpolation using the interpolation circuit 74. The signal processing unit 70 combines the three pixel values ​​obtained in this way so that they are linear, thereby obtaining the linear digital pixel signal shown in FIG. 7C corresponding to the mixed electric charges shown in FIG. 7A.

[0170] It is preferable to suppress as much as possible any sudden changes in the SN of the subject near the boundary T1, which is the transition region between low-illuminance exposure and medium-illuminance exposure, and the boundary T2, which is the transition region between medium-illuminance exposure and high-illuminance exposure.

[0171] [Basic Readout Operation of HCG Signal, MCG Signal, and LCG Signal in WDR Combining] FIG. 10 is a diagram showing an example of basic readout timing of the pixel circuit 3. In FIG.

[0172] First, from time t1 to time t2, the photodiode PD and the charge storage units FD0, FD1, and FD2 are reset and wait until exposure starts. Then, from time t3 to time t4, a shutter operation is performed and exposure starts. The exposure time ends at time t5.

[0173] At time t5, the signal charge accumulated in the photodiode PD is transferred to the charge accumulation unit FD1 by turning on the gain control transistor GC1. A reset operation is performed between time t5 and time t6. The reset component of the MCG signal is read out between time t6 and time t7.

[0174] Next, a reset operation is performed between time t7 and time t8, and the reset component of the HCG signal is read out between time t8 and time t9.

[0175] Next, from time t9 to time t10, the signal charge accumulated in the photodiode PD is transferred to the charge accumulation unit FD0 by the transfer transistor TG. Between time t10 and time t11, the HCG signal component is read out.

[0176] At time t11, the signal charge accumulated in the photodiode PD is transferred to the charge accumulation unit FD1 by turning on the gain control transistor GC1. Between time t11 and time t12, the signal charge accumulated in the photodiode PD is transferred to the charge accumulation unit FD1 by the transfer transistor TG. Between time t12 and time t13, the MCG signal component is read out.

[0177] At time t13, the signal charge accumulated in the photodiode PD is transferred to the charge accumulation unit FD2 by turning on the gain control transistor TGC. Between time t13 and time t14, the signal charge accumulated in the storage capacitor C2 is transferred to the charge accumulation unit FD2 by the gain control transistor TGC. Between time t14 and time t15, the LCG signal component is read out.

[0178] The reset operation is performed between time t15 and time t16, and the reset component of the LCG signal is read out between time t16 and time t17.

[0179] At time t16, each transistor is turned OFF.

[0180] In this manner, the HCG signal, the MCG signal, and the LCG signal are read out.

[0181] [Selective Readout Operation of Two Signals, HCG Signal, MCG Signal, and LCG Signal, in WDR Combining] Fig. 11 is a timing chart showing the selective WDR method. Using Fig. 11, an example will be described in which two signals are selected from three signals, HCG signal, MCG signal, and LCG signal, by detecting the level of the HCG signal.

[0182] In the single-slope AD conversion circuit 51, if the counter circuit 512 is a binary counter, the digital value is proportional to the HCG signal level, and therefore the optimal two signals can be selected. However, in order to reduce power consumption, a Gray code counter is more suitable, and since the digital value is not proportional to the HCG signal level, the optimal two signals cannot be selected.

[0183] For this reason, during the HCG signal AD conversion period from time t104 to time t106 shown in FIG. 11 , the HCG signal is AD converted by the comparison operation of the comparator 511 of the AD conversion circuit 51, and then during the HCG signal detection period from time t106 to time t107 shown in FIG. 11 , the reference signal 2 is set to the saturation level of the HCG signal (signal potential FDH in (b) of FIG. 7 ). During this period, the reference signal 2 is at the saturation level of the HCG signal, and if the pixel signal does not exceed this saturation level, it becomes the HCG signal. For this reason, the comparator 511 outputs a low level as the selection signal S1, and the HCG signal and the MCG signal are selected. On the other hand, if the saturation level (signal potential FDH) is exceeded, the pixel signal is not an HCG signal, so the comparator 511 outputs a high level as the selection signal S1, and the MCG signal and the LCG signal are selected.

[0184] Specifically, the comparator 511 compares the magnitude relationship between the potential of the charge storage section FD0 of the storage capacitor C0 and the potential of the reference signal 2 output from the reference signal generation section 272 via the amplification transistor SF1 and the selection transistor SEL1, and outputs a selection signal S1 of low level to the local pixel control circuit 61 if the potential of the charge storage section FD0 of the storage capacitor C0 is higher, or of high level if the potential is lower, to control the pixel circuit 3.

[0185] In this way, when the initialization count N is 0, the pixel circuit 3 outputs three or more pixel signals, and the comparator 511 compares one pixel signal (e.g., an HCG signal) of the three or more pixel signals with a reference signal 2 (e.g., the saturation level of the HCG signal) after AD conversion, and generates a selection signal S1 that instructs the selection of at least two pixel signals (e.g., an MCG signal and an LCG signal) from the three or more pixel signals when the one pixel signal reaches the reference signal 2. Then, the local pixel control circuit 61 selects at least two pixel signals from the three or more pixel signals based on the selection signal S1.

[0186] As a result, two signals can be selected from the three signals of the HCG signal, the MCG signal, and the LCG signal.

[0187] [Occurrence of kTC Noise in Sample-and-Hold Circuit] When a sample-and-hold circuit 30 is connected to the output of the amplifier transistor SF1 (a so-called voltage-domain system), kTC noise occurs when sampling pixel signals (both reset and signal components). In this case, the signal-to-noise ratio (SNR) at low illumination levels deteriorates, making it difficult to expand the dynamic range. To reduce kTC noise, high-density, low-leakage capacitance elements are required, but this is difficult to achieve in terms of the process.

[0188] For this reason, in the present disclosure, the HCG signal in WDR synthesis is directly AD converted to reduce noise, and the data is transferred to the signal processing unit 70. On the other hand, the MCG signal and the LCG signal, which have less strict noise characteristics, are sampled and held by the sample and hold circuit 30, and then AD converted, and the memory 513 that has become empty is used.

[0189] In this way, the memory 513 is provided for only one of the HCG signal, the MCG signal, and the LCG signal, which makes it possible to suppress deterioration of the noise characteristics of the WDR synthesis, an increase in the area of ​​the memory 513, and a decrease in yield.

[0190] [Basic Operation of PWM Method] An example of timing of the PWM method will be described with reference to FIG.

[0191] Fig. 12 is a diagram showing an example of the basic timing of the PWM method. The timing diagram in Fig. 12 shows an imaging operation for two frames. The first frame corresponds to a relatively strong incident light, and the second frame corresponds to a relatively weak incident light.

[0192] The photodiode PD generates electric charge through photoelectric conversion, and the electric charge overflowing from the photodiode PD is accumulated in the storage capacitor C2 via the overflow element OF, and the storage capacitor C2 maintains a potential according to the amount of generated electric charge. Since electric charge is generated according to the amount of incident light, the potential of the charge accumulation portion FD2 of the storage capacitor C2 decreases over time from the initial voltage.

[0193] When the potential of the charge storage section FD2 of the storage capacitor C2 drops to the reference signal 1, the local pixel control circuit 61 initializes the storage capacitor C2 to an initial voltage.

[0194] Here, the reference signal 1 is preferably a voltage equivalent to the charge Q2' accumulated in the storage capacitor C2 shown in Fig. 7(a). The voltage of the reference signal 1 is given by Q2' / C2.

[0195] For example, when the potential of the charge storage section FD2 of the storage capacitor C2 drops to the reference signal 1, the local pixel control circuit 61 sets the reset transistor RS, the transfer transistor TG, the gain control transistor GC1, and the gain control transistor TGC to a high level to initialize the photodiode PD and the storage capacitor C2. The initial voltage may be, for example, a power supply voltage or a predetermined voltage value. After the photodiode PD and the storage capacitor C2 are initialized, the local pixel control circuit 61 turns off the reset transistor RS, the transfer transistor TG, and the gain control transistors GC1 and TGC, and the initialization is released.

[0196] The counter circuit 522 starts a counting operation from an initial value of 0. The counter circuit 522 counts the number of initializations N that the local pixel control circuit 61 has initialized the photodiode PD and the storage capacitor C2, and outputs a signal corresponding to the number of initializations N as a digital output signal OUT1 that is N times the saturation signal Qsat of the LCG signal that indicates the intensity of incident light.

[0197] In this way, the solid-state imaging device 100 outputs the digital output signal OUT1 for each pixel cell as the number of initializations N. This makes it possible to expand the dynamic range, and even when the photodiode PD is irradiated with light so strong that it exceeds the saturation charge amount of the storage capacitor C2, the photodiode PD and the storage capacitor C2 generate a digital signal while being initialized, making it possible to capture an image even in bright scenes where the level of light greatly exceeds the saturation charge amount of the storage capacitor C2.

[0198] [PWM Method and AD Conversion Method] FIG. 13 is a diagram showing an example of timing when the AD conversion circuit 51 is used in the PWM method.

[0199] The comparator 521 compares the potential of the charge storage section FD2 of the storage capacitor C2 with the reference signal 1, and if they match, the local pixel control circuit 61 turns on the reset transistor RS, the transfer transistor TG, the gain control transistors GC1 and TGC to perform initialization.

[0200] Specifically, the comparator 521 compares the potential of the charge storage section FD2 of the storage capacitor C2 with the potential of the reference signal 1 output by the reference signal generation section 271 via the amplification transistor SF2 and the selection transistor SEL2, and if the potential of the charge storage section FD2 of the storage capacitor C2 is lower, outputs a high level to the local pixel control circuit 61 as a control signal for initializing the reset transistor RS, the transfer transistor TG, the gain control transistor GC1, and the gain control transistor TGC.

[0201] The initialization circuit 524 generates an initialization signal. The initialization signal may be, for example, a power supply voltage or another voltage value. The initialization signal is supplied as a control signal to initialize the photodiode PD and the storage capacitor C2 via the local pixel control circuit 61.

[0202] The reference signal generating unit 271 generates a reference signal 1. The reference signal 1 may be, for example, the saturation level of the storage capacitance C2 (the voltage value of the charge storage unit FD2 when the charge held in the storage capacitance C2 is saturated), or may be a voltage value between that voltage value and the power supply voltage.

[0203] Here, the reference signal 1 is preferably a voltage equivalent to the charge Q2' accumulated in the storage capacitor C2 shown in Fig. 7(a). The voltage of the reference signal 1 is given by Q2' / C2.

[0204] The count control signal generating unit 80 generates a count initialization signal INIT and a count stop signal STOP to control the counter circuit 522. The count initialization signal INIT is a control signal for initializing the count value of the counter circuit 522 to 0. The count stop signal STOP is a signal for controlling whether the counter circuit 522 starts or stops its counting operation.

[0205] When the initialization signal is at a high level, the local pixel control circuit 61 turns on the reset transistor RS, the transfer transistor TG, and the gain control transistors GC1 and TGC to initialize the photodiode PD and the storage capacitor C2.

[0206] When the count stop signal STOP output by the count control signal generating unit 80 is at a low level, the counter circuit 522 counts the number of initialization times N at which the initialization signal transitions from a low level to a high level and outputs the count result as a digital output signal OUT1, and when the count stop signal STOP is at a high level, the counter circuit 522 stops counting, and when the count initialization signal INIT becomes a high level, initializes the count value to 0.

[0207] Furthermore, for example, by setting the reference signal 1 to a power supply voltage higher than the output voltage VINI of the amplification transistor SF2, the initialization signal becomes high level, and the photodiode PD and the storage capacitor C2 can be initialized. By setting the count initialization signal INIT and count stop signal STOP of the counter circuit 522 to high level, the digital output signal OUT1 is initialized to "0".

[0208] Furthermore, for example, by setting the count initialization signal INIT and count stop signal STOP to low levels and setting the reference signal 1 to a voltage lower than the output voltage VINI of the amplifier transistor SF2, the initialization signal goes to low level and initialization can be stopped. The output voltage of the amplifier transistor SF2 drops from the output signal VINI at a rate corresponding to the amount of light irradiation, and when it reaches the reference signal 1, the initialization signal transitions to high level, the digital output signal OUT1 becomes "1", the photodiode PD and storage capacitor C2 are initialized, the output voltage of the amplifier transistor SF2 becomes the output signal VINI, and the initialization signal goes to low level.

[0209] Furthermore, the output voltage of the amplifier transistor SF2 decreases from the output signal VINI at a rate corresponding to the amount of light irradiation, and when it reaches the reference signal 1, the initialization signal transitions to a high level, the digital output signal OUT1 becomes "2", the photodiode PD and the storage capacitor C2 are initialized, the output voltage of the amplifier transistor SF2 becomes the output signal VINI, and the initialization signal becomes a low level.

[0210] This operation is continued until the exposure time ends, and the digital output signal OUT1 increases until the exposure time ends. The digital output signal OUT1 at the end of the exposure time corresponds to the initialization count N.

[0211] Furthermore, when the count stop signal STOP goes high, the counter circuit 522 continues to hold the count value at that time and generates a digital output signal OUT1 that is a digital signal corresponding to the amount of light irradiated onto the photodiode PD for each pixel cell.

[0212] The solid-state imaging device 100 resets the storage capacitor C2 when a certain amount of charge has accumulated, and outputs the number of resets as a digital value. The solid-state imaging device 100 is capable of high-speed imaging by generating a digital signal for each pixel cell. Furthermore, even when the photodiode PD is irradiated with light so intense that the storage capacitor C2 cannot perform photoelectric conversion, the photodiode PD and storage capacitor C2 are initialized while a digital signal is generated, making it possible to capture images even in bright scenes that greatly exceed the saturation charge capacity of the photodiode PD and storage capacitor C2.

[0213] Furthermore, since the photodiode PD and the storage capacitor C2 can capture an image with initialization even if the light receiving area is reduced, the solid-state imaging device 100 can be made smaller and less expensive.

[0214] Next, an example of the operation of the AD conversion circuit 51 will be described with reference to FIG.

[0215] The AD conversion circuit 51 converts the pixel signal (LCG signal) at high illuminance and the residual signal resulting from the FD mixing of the photodiode PD and the storage capacitor C2 after the last initialization, and outputs the AD converted data as a digital output signal OUT2 indicating the intensity of the incident light.

[0216] Specifically, the AD conversion circuit 51 outputs a digital output signal OUT2 corresponding to the saturation signal Qsat and the FD mixed potential of the photodiode PD and the storage capacitor C2 after the counter circuit 512 stops counting.

[0217] The signal processing unit 70 generates a digital output signal OUT3 (i.e., a first signal) that indicates the intensity of the incident light by combining the digital output signal OUT1 and the digital output signal OUT2.

[0218] 13, the digital output signal OUT1 of the counter circuit 522 is N, and the digital output signal OUT2 of the counter circuit 512 is M. The digital value of the saturation signal Qsat obtained by mixing the FD of the photodiode PD and the storage capacitor C2 is taken as Dsat. At this time, in the signal processing unit 70, the total digital output signal OUT3 is "Dsat×N+M."

[0219] The solid-state imaging device 100 performs AD conversion on the residual signal and outputs it digitally together with the number of initializations. This makes it possible to output a higher-resolution digital signal according to the amount of light irradiation, enabling good imaging that reproduces brightness and color closer to the outside world.

[0220] [Signal Selection in Units of Color Filter Array] Signal selection in units of color filter array will be described using a typical Bayer array of four colors (R, Gr, B, Gb) as an example.

[0221] Here, the relationship between the boundary T1 between the HCG signal and the MCG signal, the boundary T2 between the MCG signal and the LCG signal, and the color filters will be described with reference to FIG.

[0222] Generally, the boundaries T1 and T2, which are the transition regions, change in conjunction with the analog gain or the digital gain.

[0223] For example, in the case of a Bayer array, the sensitivity differs among the four colors (R, Gr, B, Gb), with Gr and Gb having the greatest sensitivity and B and R having lower sensitivity. Therefore, the boundaries T1 and T2 of Gr and Gb are lower than those of B and R. In conjunction with this, the voltage levels of the boundaries T1 and T2 of each color change.

[0224] There are two methods for combining WDRs, which will be described with reference to FIGS.

[0225] FIG. 14 is a diagram for explaining an example of selecting an HCG signal, an MCG signal, and an LCG signal by prioritizing the maximum signal of each color in Bayer units.

[0226] The first is a synthesis method in which, in the case of a Bayer array, three frames are synthesized using the gain of the maximum signal of the four colors (R, Gr, B, Gb) shown in bold in FIG.

[0227] In this case, the signal level is adjusted to the color with the highest signal level among the four colors (R, Gr, B, Gb). For example, if the color with the highest signal level is Gr and is detected as an LCG signal, the other three colors (R, B, Gb) are also similarly determined to be LCG signals. For example, if the color with the highest signal level is R and is detected as an MCG signal, the other three colors (Gr, B, Gb) are also similarly determined to be MCG signals.

[0228] In this way, the multiple pixel circuits 3 correspond to the array pixels of the color filter, and the local pixel control circuit 62 may perform the same pixel control on the multiple pixel circuits 3 in accordance with the maximum signal level of the array pixels of the color filter.

[0229] This allows the gain to be the same for each color filter array, for example, a Bayer array consisting of four colors, preventing coloration due to deviations in linearity that may occur when the gains for each color are different. Even when the gains for each color change due to AE control, the maximum signal levels of the four colors (R, Gr, B, and Gb) can always be used at the S / N level shown in (d) of Figure 7 to change the boundaries T1 and T2, which are transition regions, in conjunction with each other. Because the gains for each color (HCG signal, MCG signal, and LCG signal) are the same before and after the boundary, which is the transition region of the WDR, coloration due to deviations in linearity for each color does not occur.

[0230] FIG. 15 is a diagram for explaining an example in which an HCG signal, an MCG signal, and an LCG signal are selected independently for each color.

[0231] The second is a synthesis method in which, in the case of a Bayer array, three frames are individually synthesized using individual gains for the four color (R, Gr, B, Gb) signals shown in Figure 15. Even when the gain for each color changes due to AE operation, the boundaries T1 and T2, which are the transition regions for the four colors (R, Gr, B, Gb), are always changed independently at the S / N level shown in Figure 7(d). In this case, each color selects an HCG signal, an MCG signal, or an LCG signal according to its respective signal level.

[0232] This allows, for example, when adjusting the gain for each color, particularly when the white balance changes as the color temperature of the subject changes, WDR synthesis of each frame can be performed even if the analog gain or digital gain for each color is varied by AE control.

[0233] This has the effect of improving the S / N ratio since the boundaries T1 and T2 of each color can be maximized in WDR synthesis.

[0234] [Configuration Example of Pixel Circuit and Detection / Selection Circuit Using Stacked BSI] Next, a configuration example of the pixel circuit 3 and the logic circuit 4 using stacked BSI (Back Side Illumination) will be described.

[0235] 16 to 19 are diagrams showing an example in which the solid-state imaging device 100 according to the embodiment is configured as a stacked image sensor.

[0236] The solid-state imaging device 100 in each figure (FIGS. 16 to 19) includes a first semiconductor chip (first semiconductor substrate) and a second semiconductor chip (second semiconductor substrate) bonded together, or three or more semiconductor chips. The semiconductor chip is an example of a semiconductor substrate. The first semiconductor chip and the second semiconductor chip are bonded together on their respective wiring layer sides and stacked. In each figure, PD represents a photodiode PD, C represents a sample-and-hold capacitance (e.g., capacitance elements CR and CS), Ana represents an analog circuit (e.g., comparators 511 and 521), Logic and LG represent logic circuits (e.g., counter circuits 512 and 522), and MEM represents a memory circuit (e.g., memories 513 and 523).

[0237] The pixel circuit 3 is formed on a first semiconductor substrate consisting of one or more semiconductor layers, the detection circuit 52 is formed on a second semiconductor substrate consisting of one or more semiconductor layers, and the first and second semiconductor substrates are stacked. The AD conversion circuit 51 is formed on the second semiconductor substrate. The selection circuits SW1 and SW2 are formed on the first or second semiconductor substrate.

[0238] The first semiconductor chip is referred to as a pixel chip in the drawings and includes a main part of the solid-state imaging device 100 as a back-illuminated CMOS image sensor. This first semiconductor chip includes the photodiode PD and storage capacitor C2 of each pixel circuit 3.

[0239] The second semiconductor chips are denoted as logic chips in the drawings (logic chips A and B in FIG. 18 ), and have a detection circuit 52 and an AD conversion circuit 51. The second semiconductor chips include main analog circuits (e.g., comparators 511 and 521) such as a signal processing unit 70, and logic circuits (e.g., counter circuits 512 and 522).

[0240] In this solid-state imaging device 100, a pixel circuit 3 can be mounted on the pixel chip as a stacked BSI type CIS (contact image sensor), and a logic circuit 4 can be mounted on the logic chip. That is, a photodiode PD can be mounted on each pixel circuit 3 on the pixel chip, and the logic circuit 4 can be configured on the logic chip. Furthermore, pixel signals can be directly read out to the logic circuit 4, so the logic chip is composed only of analog and logic circuits, facilitating integration and reducing the layout area. Furthermore, at least two optimal signals are selected by the logic circuit 4 from the multiple pixel signals from the pixel array unit 1. This allows the number of bits and the area of ​​the memories 513 and 523 of the logic circuit 4 to be reduced. Furthermore, the memories 513 and 523 and the signal processing unit 70 can be made faster and consume less power.

[0241] 20 and 21 are diagrams showing examples of joining pixel circuits 3 and logic circuits 4 according to the embodiment.

[0242] The pixel chip and the logic chip may be provided with the joints A and B shown in Figures 20 and 21. Figure 20 corresponds to Figures 2 to 4, and Figure 21 corresponds to Figure 5.

[0243] In the example shown in Figure 16, a capacitive element of the sample and hold circuit 30 is mounted on each pixel circuit 3 of the pixel chip, and a logic circuit 4 is mounted on the logic chip. The capacitive element of the sample and hold circuit 30 can be configured on the pixel chip, thereby improving noise resistance against sneaking of digital signals. The logic chip is composed only of analog circuits and logic circuits, which facilitates integration and reduces the layout area. At least two optimal signals are selected from the multiple pixel signals from the pixel array unit 1 by the logic circuit 4, reducing the number of pixel signals, thereby reducing the time and power required to transfer digital signals to the signal processing unit 70, thereby achieving higher speeds and lower power consumption.

[0244] In the example shown in FIG. 17 , each pixel is mounted on a pixel chip, and a capacitive element of a sample and hold circuit 30 is mounted on a logic chip corresponding to each pixel circuit 3. A logic circuit 4 is mounted on the logic chip. The capacitive element of the sample and hold circuit 30 can be configured on the logic chip, thereby improving parasitic sensitivity. Note that if there are restrictions on the mounting area, the capacitive element of the sample and hold circuit 30 may be mounted separately on the pixel chip and the logic chip. The example shown in FIG. 17 can also achieve high speed and low power consumption, similar to the example shown in FIG. 16 .

[0245] 18, each pixel is mounted on a pixel chip, a capacitor element of a sample and hold circuit 30 is mounted on a logic chip A corresponding to each pixel circuit 3, and a memory is mounted on a logic chip B corresponding to each pixel circuit 3. The memory can be configured on the logic chip B, and the speed of the output signal from the memory can be increased. In the example shown in FIG. 18, high speed and low power consumption can be achieved in the same way as in the example shown in FIG. 16.

[0246] In the example shown in FIG. 19 , a capacitive element of the sample and hold circuit 30 for each pixel circuit 3 is mounted on the pixel chip, and a logic circuit 4d is mounted on the logic chip. The capacitance of the sample and hold circuit 30 can be configured on the pixel chip, thereby improving noise resistance against sneaking of digital signals. The multiple pixel circuits 3 that make up the pixel circuit group 3d share the logic circuit 4d. The logic chip is composed only of analog circuits and logic circuits, which facilitates integration and reduces the layout area. The example shown in FIG. 19 can also achieve high speed and low power consumption, similar to the example shown in FIG. 16 .

[0247] [Specific Operation Example] Next, a more specific operation example using the PWM method and the selective WDR method of the solid-state imaging device 100 will be described with reference to FIGS. 22 to 24. FIG.

[0248] FIG. 22 is a diagram showing an example of timing when the HCG signal and the MCG signal are selected.

[0249] FIG. 23 is a diagram showing an example of timing when the MCG signal and the LCG signal are selected.

[0250] FIG. 24 is a diagram showing an example of timing when the saturation level of the LCG signal and the residual signal are selected.

[0251] 22 to 24 will explain an example of timing of selective WDR using the selective readout operation of Fig. 11 in the case where the logic circuit 4d is shared by multiple pixel circuits 3 (pixel circuits A to D) in Fig. 5. Note that the following explanation can also be applied to the case where a logic circuit 4 is provided for each single pixel circuit 3, as in Fig. 2A to Fig. 4, by focusing on one pixel circuit 3 among the pixel circuits A to D.

[0252] In the following description, it is assumed that when the incident light has low to medium illuminance, the number of initializations N is 0, and when the incident light has high illuminance, the number of initializations N is 1 or more.

[0253] First, a case where the level of the HCG signal does not exceed reference signal 2 (the saturation level of the HCG signal) when the incident light is low in illuminance will be described with reference to Fig. 22. In this case, two signals, the HCG signal and the MCG signal, are selected and combined by the WDR combining circuit 76 of the signal processing unit 70. The LCG signal is not required.

[0254] Between time 102 and time 103, due to low illuminance, the charge in the photodiode PD does not exceed the predetermined threshold value of the overflow element OF during exposure. Therefore, no charge accumulates in the storage capacitor C2, and the detection circuit 52 does not operate. First, after the shutter (SHT) time, the gain control transistors GC1 and TGC are turned on, and the reset component of the LCG signal is sampled and held in the capacitance element CR of the sample and hold circuit 30 by the sample and hold signal SHR. However, since the storage capacitor C2 does not exceed the saturation level during exposure and the detection circuit 52 does not operate, the sampled and held charge is discharged.

[0255] From time 103 to time 104, the gain control transistor GC1 is turned on, and the reset component of the MCG signal is sampled and held in the capacitance element CR of the sample and hold circuit 30 by the sample and hold signal SHR.

[0256] From time 104 to time 106 , the reset component and signal component of the HCG signal are AD converted and stored in the memory 513 .

[0257] 22, it is assumed that the level of the HCG signal does not exceed the saturation level (signal potential FDH) in the selective read operation of FIG. 11 from time 106 to time 107. The case where it does exceed the saturation level will be described with reference to FIG.

[0258] From time 107 to time 108, the gain control transistor GC1 is turned on, and the signal component of the MCG signal is sampled and held in the capacitance element CS of the sample and hold circuit 30 by the sample and hold signal SHS.

[0259] Between time 108 and time 110, AD conversion of the reset component and signal component of the sampled and held MCG signal is not performed because the data of the HCG signal has already been stored in the memory 513.

[0260] The reset component and signal component of the LCG signal are not read out from time 110 to time 112. This is because WDR synthesis can be performed using two signals, the HCG signal and the MCG signal.

[0261] Between time 115 and time 116, the HCG signal data in the memory 513 is transferred to the signal processing unit 70 during the next exposure.

[0262] From time 116 to time 118, the reset component of the MCG signal sampled and held by the sample and hold signal SHR in the capacitance element CR of the sample and hold circuit 30 and the signal component of the MCG signal sampled and held by the sample and hold signal SHS in the capacitance element CS of the sample and hold circuit 30 are AD converted and stored in the memory 513 which is emptied from time 115 to time 116.

[0263] From time 118 to time 119, the data of the MCG signal in the memory 513 is transferred to the signal processing unit 70 during exposure.

[0264] Next, a case where the level of the HCG signal exceeds reference signal 2 (saturation level of the HCG signal) when the incident light is of medium illuminance will be described with reference to Fig. 23. In this case, two signals, the MCG signal and the LCG signal, are selected and combined by the WDR combining circuit 76 of the signal processing unit 70. The HCG signal becomes unnecessary.

[0265] Between time 102 and time 103, the illuminance is medium, so the charge in the photodiode PD exceeds the predetermined threshold of the overflow element OF during exposure. As a result, charge accumulates in the storage capacitor C2, but does not reach a saturation level, and the detection circuit 52 does not operate. First, after the shutter (SHT) time, the gain control transistors GC1 and TGC are turned on, and the reset component of the LCG signal is sampled and held in the capacitance element CR of the sample and hold circuit 30 by the sample and hold signal SHR. However, since the storage capacitor C2 does not exceed the saturation level during exposure and the detection circuit 52 does not operate, the sampled and held charge is discharged.

[0266] From time 103 to time 104, the gain control transistor GC1 is turned on, and the reset component of the MCG signal is sampled and held in the capacitance element CR of the sample and hold circuit 30 by the sample and hold signal SHR.

[0267] From time 104 to time 106 , the reset component and signal component of the HCG signal are AD converted and stored in the memory 513 .

[0268] 23, it is assumed that the level of the HCG signal exceeds the saturation level (signal potential FDH) in the selective read operation of FIG. 11 from time 106 to time 107. Note that the case where it does not exceed the saturation level is as explained in FIG. 22.

[0269] From time 107 to time 108, the gain control transistor GC1 is turned on, and the signal component of the MCG signal is sampled and held in the capacitance element CS of the sample and hold circuit 30 by the sample and hold signal SHS.

[0270] From time 108 to time 110, the reset component and signal component of the sampled and held MCG signal are AD converted and stored in the memory 513. At this time, from time 106 to time 107, the data of the HCG signal in the memory 513 is cleared and becomes empty.

[0271] From time 110 to time 112, the reset component and signal component of the LCG signal are sampled and held by the capacitance elements CR and CS of the sample and hold circuit 30 by the sample and hold signals SHR and SHS.

[0272] Between time 115 and time 116, the data of the MCG signal in the memory 513 is transferred to the signal processing unit 70 during the next exposure.

[0273] From time 116 to time 118, the reset component of the LCG signal sampled and held by the capacitance element CR of the sample and hold circuit 30 using the sample and hold signal SHR, and the LCG signal component sampled and held by the capacitance element CS of the sample and hold circuit 30 using the sample and hold signal SHS are AD converted and stored in the memory 513, which became empty from time 115 to time 116.

[0274] Between time 118 and time 119, the data of the LCG signal in the memory 513 is transferred to the signal processing unit 70 during exposure.

[0275] Next, a case where the number of initializations N is 1 or more when the incident light is high illuminance will be described with reference to Fig. 24. In this case, two signals, the saturation signal Qsat of the LCG signal and the remaining signal of the LCG signal, are selected and combined by the WDR combining circuit 76 of the signal processing unit 70. The HCG signal and the MCG signal are no longer necessary.

[0276] From time 102 to time 103, due to high illuminance, the charge in the photodiode PD exceeds the predetermined threshold of the overflow element OF during exposure. As a result, charge accumulates in the storage capacitor C2, which then exceeds the saturation level, activating the detection circuit 52. Figure 24 shows an example in which the number of initializations N is 2. First, after the shutter (SHT) time, the gain control transistors GC1 and TGC are turned on, and the reset component of the LCG signal is sampled and held by the capacitor CR of the sample and hold circuit 30 using the sample and hold signal SHR. Next, the storage capacitor C2 exceeds the saturation level, activating the detection circuit 52. Next, the charges in the photodiode PD and the storage capacitor C2 are mixed with FD, and the saturation level signal component (saturation signal Qsat) of the LCG signal is sampled and held by the capacitor CS of the sample and hold circuit 30 using the sample and hold signal SHS.

[0277] After initialization, the gain control transistors GC1 and TGC are turned on, and the reset component of the LCG signal is sampled and held by the capacitance element CR of the sample and hold circuit 30 using the sample and hold signal SHR. Next, the storage capacitance C2 exceeds the saturation level, and the detection circuit 52 operates. Next, the charges of the photodiode PD and the storage capacitance C2 are mixed with each other, and the saturated level signal component of the LCG signal (saturation signal Qsat) is sampled and held by the capacitance element CS of the sample and hold circuit 30 using the sample and hold signal SHS. This operation is repeated N times.

[0278] Here, the sample-and-hold circuit 30 does not need to repeatedly accumulate the saturation signal Qsat every time initialization is performed, but may accumulate it only once and continue to hold the saturation signal Qsat accumulated only once during exposure.

[0279] From time 103 to time 104, the reset component of the MCG signal is not sampled and held by the sample and hold circuit 30. This is because charge is accumulated in the sample and hold circuit 30 from time 102 to time 103.

[0280] From time 104 to time 106, the reset component and signal component of the HCG signal are not AD converted and are not stored in the memory 513. This is because the HCG signal is not necessary at high illuminance.

[0281] From time 106 to time 107, processing from time 107 to time 108 is performed regardless of whether the HCG signal level exceeds the saturation level in the selective read operation of FIG.

[0282] From time 107 to time 108, the signal component of the MCG signal is not sampled and held by the sample-and-hold circuit 30. This is because the MCG signal is not necessary at high illuminance.

[0283] Between time 108 and time 110, the saturation signal Qsat of the sampled and held LCG signal (specifically, the reset component and signal component of the saturation signal Qsat) is AD converted and stored in memory 513. Here, the saturation signal Qsat of the LCG signal may be the signal when the number of initializations N is 1 or when the number of initializations N is 2.

[0284] From time 110 to time 112, the charges of the photodiode PD and the storage capacitor C2 are mixed in the FD, and the reset component and signal component of the remaining signal of the LCG signal are sampled and held in the capacitance elements CR and CS of the sample and hold circuit 30 by the sample and hold signals SHR and SHS.

[0285] Between time 115 and time 116, the data of the saturation signal Qsat of the LCG signal stored in the memory 513 is transferred to the signal processing unit 70 during the next exposure.

[0286] From time 116 to time 118, the residual signal of the sampled and held LCG signal (specifically, the reset component and signal component of the residual signal) is AD converted and stored in memory 513, which became empty from time 115 to time 116.

[0287] From time 118 to time 119, data of the remaining LCG signals in the memory 513 is transferred to the signal processing unit 70 during exposure.

[0288] [Dependence of SN on Illuminance of Subject] Next, the dependency of SN on illuminance of subject will be described with reference to FIG.

[0289] 25 is a diagram showing the SN of the saturation signal Qsat (also referred to as linear saturation (Qsat)) of the HCG signal, the MCG signal, and the LCG signal, and the residual signal of the LCG signal. Fig. 25 shows the SN of the HCG signal at low illuminance, the MCG signal at medium illuminance, and the LCG signal at high illuminance, and is obtained by adding the SN of the first signal (linear saturation (Qsat) × N of the LCG signal + residual signal) to (d) of Fig. 7.

[0290] The signal-to-noise ratio at low illumination is good because the HCG signal is directly AD converted by the AD conversion circuit 51. Furthermore, with regard to the maximum subject illumination, as shown in Fig. 25, the conventional method without PWM results in "linear saturation (Qsat)", but the method with PWM of the present disclosure results in "linear saturation (Qsat) x N + residual signal", which allows for a significant expansion of the dynamic range.

[0291] Specifically, the S / N of "linear saturation (Qsat) × N + residual signal" maintains the S / N of the linear saturation (Qsat) of the LCG signal. This is because the S / N of the linear saturation (Qsat) of the LCG signal is determined by the √(linear saturation (Qsat)) of the shot noise, and both the signal S (Signal) and the noise N (Noise) are only digitally multiplied by N initialization times in the signal processing unit 70 and remain unchanged.

[0292] Here, as described above, the SN of "linear saturation (Qsat) × N + residual signal" is equivalently expressed as the SN of "linear saturation (Qsat) + residual signal" because the SN of "linear saturation (Qsat) × N" is equal to the SN of "linear saturation (Qsat)." The signal S (Signal) is "S = (Qsat) + residual signal," and the noise N (Noise) is expressed as the root mean square of each shot noise, so "N = √((√Qsat)^2 + (√residual signal)^2) = √(Qsat + residual signal)." Therefore, "SN = √(Qsat + residual signal)."

[0293] According to the present disclosure, even in the case of a storage capacitor C2 with a small capacity rather than a high density storage capacitor C2, the dynamic range can be expanded.

[0294] It can also be seen that the SN difference at the boundary between the transition regions of the HCG signal, MCG signal, and LCG signal is not large, and ideal characteristics can be achieved.

[0295] Furthermore, when the PWM method is adopted for the photodiode PD disclosed in Patent Document 1, the maximum S / N is determined by the shot noise of the MCG signal of the photodiode PD when it is saturated, and is a constant value. This is because the S / N of the photodiode PD does not change even when it is digitally multiplied by N. However, according to the present disclosure, the maximum S / N is determined by the shot noise of the LCG signal of the photodiode PD and storage capacitor C2 when it is saturated, and therefore the S / N can be improved compared to conventional methods.

[0296] The saturation signal (Qsat) of the LCG signal may be calculated each time initialization is performed by the sample-and-hold circuit 30, or may be calculated by averaging multiple times, which leads to improved accuracy of the saturation signal (Qsat) of the LCG signal.

[0297] It is preferable that the size of the amplifier transistor SF1 be larger than that of the amplifier transistor SF2. By increasing the size of the amplifier transistor SF1 that reads out the signal, noise can be reduced. Furthermore, by decreasing the size of the amplifier transistor SF2 that reads out the detection signal, reduction in the area of ​​the photodiode PD can be suppressed.

[0298] [Image Capturing Apparatus Using Solid-State Image Capturing Device] Next, an image capturing apparatus using the solid-state image capturing device 100 will be described with reference to FIG.

[0299] FIG. 26 is a diagram showing an example of an imaging device 200 to which the solid-state imaging device 100 according to the embodiment is applied.

[0300] The imaging device 200 in the figure is a camera system, and includes the solid-state imaging device 100, an imaging optical system 202 including a lens, a signal processing unit 203, a drive circuit 204, and a system control unit 205. In the imaging device 200, the solid-state imaging device 100 is used.

[0301] The drive circuit 204 receives a control signal corresponding to the drive mode from the system control unit 205 and supplies a drive mode signal to the solid-state imaging device 100. Upon receiving the drive mode signal, the solid-state imaging device 100 generates drive pulses corresponding to the drive mode signal and supplies them to each block within the solid-state imaging device 100.

[0302] The signal processing unit 203 receives the image signal output from the solid-state imaging device 100 and performs various signal processing on the image signal.

[0303] Thus, the imaging device 200 includes the solid-state imaging device 100 , an imaging optical system 202 that guides incident light from a subject to the solid-state imaging device 100 , and a signal processing unit 203 that processes an output signal from the solid-state imaging device 100 .

[0304] [Range Measuring Image Pickup Apparatus Using Solid-State Image Pickup Device] Next, a range finding image pickup apparatus using the solid-state image pickup device 100 will be described with reference to FIG.

[0305] 27 is a diagram showing an example of a distance measuring imaging device 300 to which the solid-state imaging device 100 according to the embodiment is applied. The object of distance measurement is an object 190.

[0306] The distance measuring image pickup device 300 includes a light source driver 150, a light source unit 160, an optical lens 170, a signal processing unit 180, and the solid-state image pickup device 100. In the distance measuring image pickup device 300, the solid-state image pickup device 100 is used.

[0307] The light source driver 150 supplies a drive signal to the light source unit 160 in accordance with a signal from the solid-state imaging device 100 instructing it to emit light.

[0308] The light source unit 160 generates pulsed light for distance measurement in accordance with a drive signal from the light source driver 150 .

[0309] The optical lens 170 is a lens for collecting pulsed light reflected by the object 190 corresponding to the pulsed light from the light source unit 160 .

[0310] The signal processing unit 180 calculates the distance to the object 190 based on the signal received from the solid-state imaging device 100 .

[0311] The solid-state imaging device 100 irradiates an object 190 with near-infrared light from the light source unit 160 in the presence of background light. The light reflected from the object 190 is incident on the pixel array unit 1 via the optical lens 170. The reflected light incident on the pixel array unit 1 forms an image, and the formed optical image is converted into a pixel signal. The output of the solid-state imaging device 100 is converted into distance data by the signal processing unit 180, and may also be converted into a visible distance image or brightness image depending on the application.

[0312] (Other Embodiments) While the solid-state imaging device 100 according to one or more aspects of the present disclosure has been described above based on the embodiments, the present disclosure is not limited to the embodiments. As long as it does not deviate from the spirit of the present disclosure, various modifications conceivable by a person skilled in the art to each embodiment or configurations constructed by combining components of different embodiments may also be included within the scope of one or more aspects of the present disclosure.

[0313] The present disclosure relates to a solid-state imaging device, and an imaging apparatus or a distance measuring imaging apparatus that uses the solid-state imaging device as an imaging device, and is suitable for, for example, a digital camera or a distance measuring system.

[0314] 1 Pixel array section 3, 3a, 3b, 3c Pixel circuit 3d Pixel circuit group 4, 4d Logic circuit 14 Vertical scanning circuit 15 Horizontal scanning line group 19 Input / output signal line 20 Timing control section 27 Reference signal generation section 28 Output circuit 30 Sample and hold circuit 51 AD conversion circuit 52 Detection circuit 61, 62 Local pixel control circuit 70, 180, 203 Signal processing section 71 HCG signal generation circuit 72 MCG signal generation circuit 73 LCG signal generation circuit 74 Interpolation circuit 76 WDR synthesis circuit 77, 513, 515, 523, 525 Memory 80 Count control signal generation section 100 Solid-state imaging device 150 Light source driver 160 Light source section 170 Optical lens 190 Object 200 Imaging device 202 Imaging optical system 204 Driver circuit 205 System control section 271, 272 Reference signal generation section 300 Distance measuring imaging device 511, 521 Comparator 512, 522 Counter circuit 524 Initialization circuit C0, C1, C2 Storage capacitance CR, CS Capacitance element FD0, FD1, FD2 Charge storage section GC1, TGC Gain control transistor OF Overflow element PD Photodiode RS Reset transistor TG Transfer transistor SEL1, SEL2 Selection transistor SF1, SF2 Amplification transistor SW1, SW2 Selection circuit

Claims

1. A pixel circuit that outputs a plurality of pixel signals; A detection circuit; A pixel control circuit for controlling the pixel circuit; A signal processing unit, The pixel circuit includes: A photodiode; a first transfer transistor for reading out a signal from the photodiode to a floating diffusion; a storage capacitor for storing charge overflowing from the photodiode; the detection circuit compares the signal of the storage capacitance with a first reference value, and when the signal of the storage capacitance reaches the first reference value, initializes the photodiode and the storage capacitance via the pixel control circuit, and counts the number of initializations; The signal processing unit calculates a first signal indicating an intensity of incident light based on the number of initializations and a mixed signal of the signal of the photodiode and the signal of the storage capacitance read out to the floating diffusion by the first transfer transistor. Solid-state imaging device.

2. The solid-state imaging device includes: A sample and hold circuit; An AD conversion circuit is provided. The solid-state imaging device according to claim 1 .

3. At least one pixel signal among the plurality of pixel signals is not held by the sample-and-hold circuit, and is directly AD-converted by the AD conversion circuit; At least one other pixel signal among the plurality of pixel signals is held by the sample-and-hold circuit, and the held signal is AD-converted by the AD conversion circuit. The solid-state imaging device according to claim 2 .

4. When the number of initializations is 1 or more, the pixel circuit outputs, as a second signal, a mixed signal of the photodiode and the storage capacitance when the signal of the storage capacitance reaches the first reference value during exposure, and the photodiode and the storage capacitance are initialized; the second signal is held by the sample-and-hold circuit, and the held signal is AD-converted by the AD conversion circuit; the pixel circuit outputs, as a third signal, a mixed signal remaining in the photodiode and the storage capacitor when the signal in the storage capacitor does not reach the first reference value at the end of exposure; The third signal is not held by the sample-and-hold circuit, and is directly AD-converted by the AD conversion circuit. The solid-state imaging device according to claim 2 .

5. The signal processing unit calculates the first signal by calculating a sum of the product of the second signal and the number of initializations and the third signal. The solid-state imaging device according to claim 4 .

6. The sample and hold circuit comprises: a first sample-and-hold capacitance element for a reset component and a second sample-and-hold capacitance element for a signal component; When the number of initializations is 1 or more, During exposure, after the photodiode and the storage capacitance are initialized, a reset component is held in the first sample and hold capacitance element; When the signal of the storage capacitance reaches the first reference value during exposure, the second signal is held as a signal component in the second sample and hold capacitance element; The AD conversion circuit performs AD conversion on the pixel signal level by comparing a pixel signal level obtained by subtracting the reset component from the signal component with a second reference value. The solid-state imaging device according to claim 4 .

7. If the number of initializations is 0, the pixel circuit outputs a fourth signal in a low illuminance mode for low illuminance and outputs a fifth signal in a mode for higher illuminance than the low illuminance mode; the fourth signal is not held by the sample-and-hold circuit, and is directly AD-converted by the AD conversion circuit; The fifth signal is held by the sample-and-hold circuit, and the held signal is AD-converted by the AD conversion circuit. The solid-state imaging device according to claim 2 .

8. The pixel circuit includes: a second transfer transistor that transfers the charge of the storage capacitor to the floating diffusion; a first amplifying transistor that outputs a signal of the photodiode and a signal of the storage capacitor; a first selection transistor connected to the first amplification transistor; a second amplifying transistor connected to the storage capacitor; a second selection transistor connected to the second amplification transistor; the detection circuit is connected to the storage capacitor via the second selection transistor and the second amplification transistor; In the low illuminance mode, the pixel circuit outputs a signal of the photodiode from the first amplification transistor via the first transfer transistor as the fourth signal; the high illuminance mode includes a high illuminance mode in which the pixel circuit outputs a signal of the storage capacitance from the first amplification transistor via the second transfer transistor as a sixth signal; The sixth signal belongs to the fifth signal. The solid-state imaging device according to claim 7 .

9. the pixel circuit includes a reset transistor; The detection circuit controls the reset transistor, the first transfer transistor, and the second transfer transistor via the pixel control circuit based on a comparison result between the signal of the storage capacitance and a first reference value, thereby discharging charges from the photodiode and the storage capacitance and initializing the photodiode and the storage capacitance. The solid-state imaging device according to claim 8 .

10. the pixel circuit includes a gain switching transistor that switches a gain of a signal of the photodiode; the high illuminance mode includes a medium illuminance mode in which the gain switching transistor is controlled so that the pixel circuit outputs a signal of the photodiode from the first amplification transistor as a seventh signal; The seventh signal belongs to the fifth signal. The solid-state imaging device according to claim 8 .

11. When the number of initializations is 1 or more, the pixel circuit outputs, as a second signal, a mixed signal of the photodiode and the storage capacitance when the signal of the storage capacitance reaches the first reference value during exposure, and the photodiode and the storage capacitance are initialized; the second signal is held by the sample-and-hold circuit, and the held signal is AD-converted by the AD conversion circuit; the pixel circuit outputs, as a third signal, a mixed signal remaining in the photodiode and the storage capacitor when the signal in the storage capacitor does not reach the first reference value at the end of exposure; the third signal is not held by the sample-and-hold circuit, and is directly AD-converted by the AD conversion circuit; The sample and hold circuit comprises: a first sample-and-hold capacitance element for a reset component and a second sample-and-hold capacitance element for a signal component; When the number of initializations is 1 or more, During exposure, after the photodiode and the storage capacitance are initialized, a reset component is held in the first sample and hold capacitance element; When the signal of the storage capacitance reaches the first reference value during exposure, the second signal is held as a signal component in the second sample and hold capacitance element; the AD conversion circuit performs AD conversion on the pixel signal level by comparing a pixel signal level obtained by subtracting the reset component from the signal component with a second reference value; The second reference value is a saturation level of the fourth signal. The solid-state imaging device according to claim 7 .

12. The signal processing unit includes a WDR processing unit, The WDR processing unit is generating an output signal from at least the first signal when the initialization count is equal to or greater than one; When the initialization count is 0, an output signal is generated from at least one of the fourth signal and the fifth signal. The solid-state imaging device according to claim 7 .

13. The AD conversion circuit includes a comparator. If the number of initializations is 0, the pixel circuit outputs three or more pixel signals; the comparator compares one pixel signal among the three or more pixel signals with a second reference value after being AD converted, and generates a selection signal that instructs selection of at least two pixel signals among the three or more pixel signals when the one pixel signal reaches the second reference value; The pixel control circuit selects the at least two pixel signals from the three or more pixel signals based on the selection signal. The solid-state imaging device according to claim 2 .

14. the AD conversion circuit and the detection circuit are provided for each of the pixel circuits, The pixel control circuit controls the pixel circuit for each individual pixel circuit. The solid-state imaging device according to claim 2 .

15. the AD conversion circuit and the detection circuit are provided for each of the plurality of pixel circuits, the pixel control circuit controls the pixel circuit for each individual pixel circuit; The detection circuit includes: A signal of the storage capacitance of the pixel circuit is compared with the first reference value while synchronizing the pixel circuit and the pixel control circuit corresponding thereto. The solid-state imaging device according to claim 2 .

16. If the number of initializations is 0, the pixel circuit outputs a fourth signal in a low illuminance mode for low illuminance and outputs a fifth signal in a mode for higher illuminance than the low illuminance mode; the fourth signal is not held by the sample-and-hold circuit, and is directly AD-converted by the AD conversion circuit; the fifth signal is held by the sample-and-hold circuit, and the held signal is AD-converted by the AD conversion circuit; The pixel circuit includes: a second transfer transistor that transfers the charge of the storage capacitor to the floating diffusion; a first amplifying transistor that outputs a signal of the photodiode and a signal of the storage capacitor; a first selection transistor connected to the first amplification transistor; a second amplifying transistor connected to the storage capacitor; a second selection transistor connected to the second amplification transistor; the detection circuit is connected to the storage capacitor via the second selection transistor and the second amplification transistor; In the low illuminance mode, the pixel circuit outputs a signal of the photodiode from the first amplification transistor via the first transfer transistor as the fourth signal; the high illuminance mode includes a high illuminance mode in which the pixel circuit outputs a signal of the storage capacitance from the first amplification transistor via the second transfer transistor as a sixth signal; the sixth signal belongs to the fifth signal, The pixel control circuit synchronizes control of the first selection transistor, the second selection transistor, and the sample-and-hold circuit of the corresponding pixel circuit. The solid-state imaging device according to claim 15.

17. The pixel circuits correspond to pixels of a color filter array, The pixel control circuit performs the same pixel control for the plurality of pixel circuits in accordance with a maximum signal level of the array pixels of the color filter. The solid-state imaging device according to claim 15.

18. The solid-state imaging device includes: a first semiconductor substrate having the pixel circuit; a second semiconductor substrate having the detection circuit and the AD conversion circuit; The first semiconductor substrate and the second semiconductor substrate are stacked. The solid-state imaging device according to claim 2 .

19. The first reference value is a saturation level of the storage capacity. The solid-state imaging device according to any one of claims 1 to 18.

20. A photodiode; a floating diffusion from which a signal from the photodiode is read out; a storage capacitor for storing charge overflowing from the photodiode; a pixel circuit having a reset means for initializing the photodiode, the floating diffusion, and the storage capacitance; a comparator for comparing the signal of the storage capacitance with a first reference value; an initialization circuit for controlling the reset means based on a comparison result of the comparator; Equipped with the pixel circuit is formed on a first semiconductor substrate having one or more semiconductor layers, and the detection circuit is formed on a second semiconductor substrate having one or more semiconductor layers; The first semiconductor substrate and the second semiconductor substrate are stacked. Solid-state imaging device.

21. The pixel circuit includes: a first transfer transistor that reads out a signal from the photodiode to the floating diffusion; a second transfer transistor that transfers the signal of the storage capacitance to the floating diffusion; The solid-state imaging device according to claim 20.

22. The detection circuit includes: A counter function for counting the comparison results of the comparator is provided. The solid-state imaging device according to claim 20.

23. Further, the second semiconductor substrate is formed with an AD conversion function for converting a signal of the floating diffusion into a digital value, The input terminals of the comparator and the AD conversion function are respectively connected to different output terminals of the pixel circuit. The solid-state imaging device according to any one of claims 20 to 22.

24. moreover, an AD conversion function formed on the second semiconductor substrate for converting a signal of the floating diffusion into a digital value; a selection circuit formed on the first semiconductor substrate or the second semiconductor substrate, receiving a signal from the storage capacitor and a signal from the floating diffusion and selecting an output; The output of the selection circuit is input to the AD conversion function, The detection circuit and the AD conversion function share the comparator. The solid-state imaging device according to any one of claims 20 to 22.

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