Semiconductor device

Abstract

Provided is a semiconductor device having a novel configuration. The present invention has: a base die having a first power supply circuit that generates a first voltage; a first die having a second power supply circuit that generates a second voltage due to having the first voltage supplied thereto; and a second die having a functional circuit that operates due to having the second voltage supplied thereto. The first die and the second die have a first through electrode and a second through electrode. The first die is provided on the base die. The second die is provided in contact with the top layer or the bottom layer of the first die. The base die and the first die are electrically connected via the first through electrode. The first die and the second die are electrically connected via the second through electrode.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device or the like.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.

[0003] In recent years, there has been active research and development into a configuration in which multiple dies (e.g., silicon dies) each having circuits with different functions, such as SRAM cells or DRAM cells, are stacked three-dimensionally (e.g., Non-Patent Documents 1 and 2).

[0004] The stacked dies achieve a reduction in wiring load, low power consumption, and high speed (low delay) by using a technology that uses through electrodes such as TSV (Through Silicon Via) or Cu-Cu (Copper-Copper) direct bonding technology, etc. In a semiconductor device formed by stacking dies having different functional circuits, management of clock signals in the Z direction (the direction in which the dies are stacked) and power management are important.

[0005] W. Gomes et al. , ISSCC Dig. Tech. Papers, pp. 42-43, 2022. M. Park et al. , ISSCC Dig. Tech. Papers, pp. 444-445, 2022.

[0006] In a configuration in which a power supply circuit is provided on a base die (a die in which multiple dies are stacked), the voltage drop is large when supplying power to an upper die that is distant from the base die, which can lead to a risk that the uniformity of the voltage supplied by the power supply circuit cannot be maintained in the Z direction.

[0007] An object of one embodiment of the present invention is to provide a semiconductor device having a novel structure in which multiple dies are three-dimensionally stacked on a base die, and in which voltages supplied to functional circuits included in the multiple dies are highly uniform.Another object of one embodiment of the present invention is to provide a semiconductor device having a novel structure in which multiple dies are three-dimensionally stacked on a base die, and in which power consumption in a power supply circuit is reduced.Another object of one embodiment of the present invention is to provide a semiconductor device having a novel structure in which the influence of heat generation in a power supply circuit can be reduced in a structure in which multiple dies are three-dimensionally stacked on a base die.Another object of one embodiment of the present invention is to provide a semiconductor device having a novel structure.

[0008] The problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention solves at least one of the problems listed above and / or other problems.

[0009] One aspect of the present invention is a semiconductor device having a base die having a first power supply circuit that generates a first voltage, a first die having a second power supply circuit that generates a second voltage when the first voltage is supplied, and a second die having a functional circuit that operates when the second voltage is supplied, wherein the first die and the second die have first and second through electrodes, the first die is provided on the base die, the second die is provided in contact with an upper or lower layer of the first die, the base die and the first die are electrically connected via the first through electrode, and the first die and the second die are electrically connected via the second through electrode.

[0010] In one aspect of the present invention, the semiconductor device is preferably such that the first power supply circuit is a switching regulator.

[0011] In one aspect of the present invention, the second power supply circuit is preferably a series regulator.

[0012] In one embodiment of the present invention, the semiconductor device is preferably a semiconductor device in which the functional circuit is a circuit having one or more functions of an arithmetic circuit, a peripheral circuit, a memory circuit, or a driver circuit.

[0013] In one aspect of the present invention, the semiconductor device preferably includes a heat dissipation layer, the heat dissipation layer being provided between the first die and the second die.

[0014] In one aspect of the present invention, the semiconductor device is preferably such that the first through electrode and the second through electrode provided on different dies are electrically connected via a metal bump.

[0015] In one embodiment of the present invention, the semiconductor device preferably includes a layer having a transistor including an oxide semiconductor in a channel formation region, and the layer having the transistor is stacked.

[0016] In one embodiment of the present invention, the oxide semiconductor preferably contains In, Ga, and Zn.

[0017] One aspect of the present invention is a semiconductor device comprising: a base die having a first power supply circuit that generates a first voltage; a first die having a second power supply circuit that generates a second voltage when the first voltage is supplied; and a second die and a third die having functional circuits that operate when the second voltage is supplied; the first die, the second die, and the third die have through electrodes; the first die is provided on the base die; the second die is provided in contact with a lower layer of the first die; and the third die is provided in contact with an upper layer of the first die; the base die and the first die are electrically connected via the first through electrode; and the first die, the second die, and the third die are electrically connected via the second through electrode.

[0018] In one aspect of the present invention, the semiconductor device is preferably such that the first power supply circuit is a switching regulator.

[0019] In one aspect of the present invention, the second power supply circuit is preferably a series regulator.

[0020] In one embodiment of the present invention, the semiconductor device is preferably a semiconductor device in which the functional circuit is a circuit having one or more functions of an arithmetic circuit, a peripheral circuit, a memory circuit, or a driver circuit.

[0021] One aspect of the present invention is a semiconductor device having a heat dissipation layer, the heat dissipation layer being provided between a first die and a second die and between the first die and a third die.

[0022] In one aspect of the present invention, the semiconductor device is preferably such that the first through electrode and the second through electrode provided on different dies are electrically connected via a metal bump.

[0023] In one embodiment of the present invention, the semiconductor device preferably includes a layer including a transistor having an oxide semiconductor in a channel formation region, and the layer including the transistor is stacked.

[0024] In one embodiment of the present invention, the oxide semiconductor preferably contains In, Ga, and Zn.

[0025] Other aspects of the present invention will be described in the following embodiments and in the drawings.

[0026] One embodiment of the present invention can provide a semiconductor device with a novel structure in which multiple dies are three-dimensionally stacked on a base die, and in which voltages supplied to functional circuits included in the multiple dies are highly uniform. Another embodiment of the present invention can provide a semiconductor device with a novel structure in which multiple dies are three-dimensionally stacked on a base die, and in which power consumption in a power supply circuit is reduced. Another embodiment of the present invention can provide a semiconductor device with a novel structure in which the influence of heat generation in a power supply circuit can be reduced in a structure in which multiple dies are three-dimensionally stacked on a base die. Another embodiment of the present invention can provide a semiconductor device with a novel structure.

[0027] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc.

[0028] FIGS. 1A and 1B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 2A and 2B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 3A and 3B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 4A and 4B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 5A and 5B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 6A and 6B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 7A, 7B, and 7C are diagrams illustrating a configuration example of a semiconductor device. FIGS. 8A and 8B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 9A to 9D are diagrams illustrating a configuration example of a semiconductor device. FIGS. 10 are diagrams illustrating a configuration example of a semiconductor device. FIGS. 11A to 11C are diagrams illustrating a configuration example of a semiconductor device. FIG. 12 is a diagram illustrating a configuration example of a memory section. FIG. 13A is a diagram illustrating a configuration example of a memory layer. FIG. 13B is a diagram illustrating an equivalent circuit of the memory layer. FIG. 14 is a diagram illustrating a configuration example of a memory section. FIG. 15A is a diagram illustrating a configuration example of the memory layer. FIG. 15B is a diagram illustrating an equivalent circuit of the memory layer. Fig. 16A and Fig. 16B are diagrams showing an example of an electronic component. Fig. 17A and Fig. 17B are diagrams showing an example of an electronic device, and Fig. 17C to Fig. 17E are diagrams showing an example of a mainframe computer. Fig. 18 is a diagram showing an example of space equipment. Fig. 19 is a diagram showing an example of a storage system applicable to a data center.

[0029] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different forms and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0030] In addition, in the drawings, the size, layer thickness, or area may be exaggerated for clarity, and therefore, are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0031] In this specification and the like, unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0032] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used in an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0033] In this embodiment, a configuration example of a semiconductor device will be described. A semiconductor device described in one embodiment of the present invention functions as a system on a chip (SoC) including a plurality of functional circuits such as a logic circuit, a memory circuit, or a peripheral circuit.

[0034] 1A and 1B are block diagrams illustrating a semiconductor device according to one embodiment of the present invention, and schematic diagrams illustrating a semiconductor device according to one embodiment of the present invention.

[0035] The semiconductor device 10 shown in FIG. 1A has a power supply circuit 21, a power supply circuit 31, and multiple functional circuits 32. The power supply circuit 21, the power supply circuit 31, and multiple functional circuits 32 included in the semiconductor device 10 shown in FIG. 1A are provided on stacked dies. The schematic diagram shown in FIG. 1B shows multiple dies (30_1 to 30_3, for example) provided on a die (hereinafter, referred to as a base die 20). The Z direction in FIG. 1B represents the direction perpendicular to the surface of the base die 20, or the direction in which the dies 30_1 to 30_3 are stacked on the base die 20.

[0036] 1B , the dies stacked on the base die 20 are denoted as 30_1 to 30_3. For example, the die in the nth layer of the dies stacked on the base die 20 can be denoted as die 30_n. In the present embodiment and the like, when describing matters relating to the entire n-layer die consisting of dies 30_1 to 30_n or when indicating matters common to each layer of the die 30, the term "die 30" may be used.

[0037] The power supply circuit 21 generates a constant voltage Vin and a reference voltage Vref based on a base voltage V_BASE. The power supply circuit 21 is provided on the base die 20. The power supply circuit 21 is preferably, for example, a switching regulator. A switching regulator can efficiently generate the constant voltage Vin and the reference voltage Vref based on the reference voltage V_BASE. A switching regulator requires large electronic components such as inductors and capacitors. The base die 20 has a larger area than the dies 30_1 to 30_3, so it can accommodate large electronic components such as external inductors and diodes. The constant voltage Vin and the reference voltage Vref may be referred to as first voltages. The power supply circuit 21 may also be referred to as a first power supply circuit.

[0038] The base die 20 on which the power supply circuit 21 is provided is not limited to the power supply circuit 21, and may have a configuration including functional circuits such as a clock generation circuit, an arithmetic circuit such as a CPU core, and a memory circuit.

[0039] The power supply circuit 31 generates a constant voltage Vout based on a constant voltage Vin and a reference voltage Vref. A plurality of power supply circuits 31 may be provided to generate a plurality of different constant voltages Vout. The power supply circuit 31 is preferably a series regulator such as a low-drop-out regulator (LDO regulator). Because a series regulator can be configured with an amplifier circuit and a transistor for output voltage control, it can be applied to the power supply circuits of the dies 30_1 to 30_3 stacked on the base die 20 without using electronic components such as inductors and diodes. The constant voltage Vout may also be referred to as a second voltage. The power supply circuit 31 may also be referred to as a second power supply circuit. The die 30_2 on which the power supply circuit 31 is provided may also be referred to as a first die.

[0040] In a configuration in which multiple dies (e.g., 30_1 to 30_3) are three-dimensionally stacked on a base die 20, by providing a die 30_2 having a power supply circuit 31, it is possible to supply a constant voltage Vout from the power supply circuit 31 of the die 30_2 that is far from the base die 20 to the functional circuits 32 of the dies 30_1 and 30_3 that are close to the die 30_2. This reduces the effect of voltage drop in the voltage supplied to the functional circuits 32. This makes it easier to ensure uniformity in the voltage supplied by the power supply circuit in power management in the Z direction.

[0041] The base die 20 and the dies 30_1 to 30_3 each have a transistor (Si transistor) in which a semiconductor layer having a channel formation region includes silicon. The inclusion of Si transistors allows for a configuration in which a power supply circuit and a functional circuit are formed using a CMOS circuit (Si CMOS circuit). This configuration allows for the power supply circuit and the functional circuit of the Si CMOS circuit to be arranged on each layer. Because the power supply circuit and the functional circuit can be formed using a CMOS circuit, high-speed operation is possible.

[0042] The semiconductor layer having the channel formation region of the Si transistor can be made of a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like, either singly or in combination. The semiconductor material is not limited to silicon, and can be, for example, germanium. Alternatively, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, or a nitride semiconductor can be used.

[0043] The base die 20 having the Si transistor and the dies 30_1 to 30_3 can be connected to each other as stacked element layers by using a technology using through electrodes such as TSV (Through Silicon Via) or Cu-Cu (copper-copper) direct bonding technology (a technology that achieves electrical conduction by connecting Cu (copper) pads together). The connection between the dies having through electrodes can be made via metal bumps (sometimes called microbumps).

[0044] The supply paths of the constant voltage Vin and the reference voltage Vref from the power supply circuit 21 of the base die 20 to the power supply circuit 31 of the die 30_2 are configured to be via through electrodes 41A provided in multiple dies (e.g., 30_1 to 30_3) on the base die 20. The supply path of the constant voltage Vout from the power supply circuit 31 of the die 30 to the functional circuits 32 of the dies 30_1 and 30_3 is configured to be via through electrodes 41B provided in multiple dies (e.g., 30_1 to 30_3) on the base die 20. With this configuration, the constant voltage Vin and the reference voltage Vref can be supplied to dies distant from the base die, and the power supply circuit 31 that supplies the constant voltage Vout and the functional circuits 32 that receive the constant voltage Vout can be located close to each other.

[0045] The functional circuit 32 is a circuit that functions when supplied with a constant voltage Vout. The functional circuit 32 is preferably a circuit having one or more functions of an arithmetic circuit, a peripheral circuit, a memory circuit, and a drive circuit. By providing synchronous circuits such as an arithmetic circuit, a peripheral circuit, a memory circuit, and a drive circuit on dies 30_1 to 30_3 stacked on the base die 20, multiple synchronous circuits can be arranged in close proximity, facilitating clock signal timing adjustment and reducing the power consumption required for clock signal distribution. Furthermore, multiple functional circuits can be arranged per unit area, thereby enabling the semiconductor device to have higher functionality. The die 30_1 or die 30_3 on which the functional circuit 32 is provided may be referred to as the first die.

[0046] The dies 30_1 and 30_3 having the functional circuits 32 to which the constant voltage Vout is supplied are preferably provided in contact with the upper or lower layer of the die 30_2 having the power supply circuit 31. By adopting this configuration, the functional circuits 32 to which the constant voltage Vout is supplied can be arranged at equal distances from the power supply circuit 31.

[0047] The arithmetic circuit is a functional circuit having an arithmetic function, such as a CPU or a GPU. The memory circuit is a memory circuit having a Si transistor, such as a DRAM or an SRAM, or a memory circuit having a transistor (OS transistor) in which a semiconductor layer having a channel formation region includes an oxide semiconductor, such as a DOSRAM or an NOSRAM described later. The driver circuit is a circuit for driving other circuits such as a memory circuit. The peripheral circuit is a circuit such as a local area network (LAN), a universal serial bus (USB), or a peripheral component interconnect (PCI), which may perform slower processing than the arithmetic circuit. Other circuits that can be used as the functional circuit include an interface circuit, a bridge circuit, and the like.

[0048] As described above, the semiconductor device 10 according to one embodiment of the present invention includes a base die 20 having a power supply circuit 21 that generates a constant voltage Vin and a reference voltage Vref, a die 30_2 having a power supply circuit 31 that generates a constant voltage Vout in response to the supply of the constant voltage Vin and the reference voltage Vref, and dies 30_1 and 30_3 having a functional circuit 32 that operates in response to the supply of the constant voltage Vout. The dies 30_1 to 30_3 have through electrodes 41A and 41B. The die 30_2 is provided on the base die, and the dies 30_1 and 30_3 are provided in contact with the upper or lower layer of the die 30_2. The base die 20 and the die 30_2 are electrically connected via the through electrode 41A. The die 30_2 is electrically connected to the dies 30_1 and 30_3 via the through electrode 41B.

[0049] In a semiconductor device according to one embodiment of the present invention, in a configuration in which multiple dies are three-dimensionally stacked on a base die, it is possible to easily ensure uniformity in the voltage supplied by the power supply circuit in power management in the Z direction. Furthermore, it is possible to supply the voltage required to generate a constant voltage to a die distant from the base die, and to arrange the power supply circuit and the functional circuits close to each other. Furthermore, since multiple functional circuits 32 can be arranged at equal distances from the power supply circuit 31, a semiconductor device with excellent uniformity in the voltage supplied to each functional circuit 32 can be obtained.

[0050] 1B shows a configuration in which the functional circuit 32 is provided on the dies 30_1 and 30_3 above and below the die 30_2 having the power supply circuit 31, but it is also possible to provide only one of them. For example, as in the semiconductor device 10A shown in FIG. 2A, a configuration in which the functional circuit 32 is not provided on the die 30_1 is also possible.

[0051] 1B shows a configuration in which the die 30_2 having the power supply circuit 31 is electrically connected to the functional circuits 32 provided on the upper and lower dies 30_1 and 30_3 via through electrodes 41B, but other configurations are also possible. For example, as shown in FIG. 2B , a semiconductor device 10B may be configured in which the functional circuit 32 provided on the upper die 30_3 is connected to the power supply circuit 31 via through electrodes 41B, and the functional circuit 32 provided on the lower die 30_1 is connected to the power supply circuit 31 via through electrodes 41C. Also, as shown in FIG. 2B , the power supply circuit 31 provided on the die 30_2 may be configured to be provided for each functional circuit 32.

[0052] 2B is also excellent in terms of improving the accuracy of the voltage supplied to the functional circuit 32. An example of the configuration of the power supply circuit 31 and the advantages of arranging the power supply circuit 31 near the functional circuit 32 will be described with reference to FIGS.

[0053] FIG. 3A is a diagram showing the circuit configuration of an LDO regulator applicable to the power supply circuit 31. As described above, in a configuration in which multiple dies are three-dimensionally stacked on a base die, the power supply circuit 31 includes an amplifier circuit 33 and a transistor 34, which is a p-channel Si transistor. The transistor 34 is a transistor for output voltage control. The voltage Vin and the reference voltage Vref are supplied from the power supply circuit 21 of the base die 20, and a constant voltage Vout is supplied. The voltage of the wiring supplying the constant voltage Vout is fed back to the amplifier circuit 33. The amplifier circuit 33 controls the gate voltage of the transistor 34 based on the fed-back voltage, thereby supplying the desired constant voltage Vout. Note that in FIG. 3A and other figures, the constant voltage Vout fed back to the amplifier circuit 33 is input as a voltage divided between the amplifier circuit 33 and the GND potential.

[0054] In the configuration of the power supply circuit in Fig. 3A, in the wiring that supplies the constant voltage Vout to the functional circuit 32 of the upper die 30_3 (or the lower die 30_1), a voltage drop occurs due to a resistor 35A of the through electrode 41B and a resistor 35B of the wiring of the die 30_3 that has the functional circuit 32 (Fig. 3B). Therefore, as shown in Fig. 3B, the constant voltage Vout output by the power supply circuit 31 is a voltage Vout-V ＴＳＶ (V ＴＳＶ is supplied to the functional circuit 32 as a voltage drop across the resistors 35A and 35B. ＴＳＶ There is a risk that the feedback will not be provided.

[0055] In a configuration in which the desired voltage is not fed back to the amplifier circuit 33, the voltage drop becomes more pronounced when the power supply circuit 31 and the functional circuit 32 are far apart. For example, as shown in Figure 4A, in the case of a die 30_N (N is an integer of 2 or more) in which the power supply circuit 31 is provided on the base die 20 and the die 30 having the functional circuit 32 to which the constant voltage Vout is supplied is provided on the top layer, the voltage drop becomes significant due to the resistors 35A and 35B of the through electrodes 41B provided on each of the N dies. Specifically, as shown in Figure 4A, the constant voltage Vout output by the power supply circuit 31 is expressed as the voltage Vout-N x V ＴＳＶ That is, in the power supply circuit 31 of the die 30_2, the amplifier circuit 33 outputs the voltage Vout fed back and the voltage Vout-N×V supplied to the functional circuit 32. ＴＳＶ The difference between and becomes impossible to ignore.

[0056] In one embodiment of the present invention, the die 30_2 having the power supply circuit 31 that generates the constant voltage Vout by receiving the constant voltage Vin and the reference voltage Vref, and the dies 30_1 and 30_3 having the functional circuit 32 that operates by receiving the constant voltage Vout, can be provided close to each other on an upper or lower layer, thereby reducing the difference between the feedback voltage Vout and the voltage supplied to the functional circuit 32.

[0057] 4B , the functional circuit 32 and the input terminal of the amplifier circuit 33 can be arranged close to each other, and a voltage can be fed back to the amplifier circuit 33 via a through electrode 41D that is separate from the through electrode 41B. Although the fed-back voltage has a voltage drop due to the resistance 35C in the through electrode 41D, the voltage drop due to the resistance 35B required for routing the wiring on the die 30_3 is reduced. Therefore, a voltage close to the constant voltage Vout supplied to the functional circuit 32 can be fed back to the amplifier circuit 33.

[0058] Although FIG. 1A shows a power supply circuit 31 that supplies a constant voltage Vout based on a constant voltage Vin and a reference voltage Vref, a configuration may be adopted in which a plurality of power supply circuits 31 are provided and a plurality of constant voltages are supplied to the functional circuit.

[0059] FIG. 5A is a block diagram of a semiconductor device 10C having a power supply circuit 31A that supplies a constant voltage Vout1 to a functional circuit 32A based on a constant voltage Vin and a reference voltage Vref, and a power supply circuit 31B that supplies a constant voltage Vout2 to a functional circuit 32B based on the constant voltage Vin and the reference voltage Vref.

[0060] Each of the components shown in FIG. 5A can be arranged on multiple dies (e.g., 30_1 to 30_6) on the base die 20, as shown in the schematic diagram of FIG. 5B. In the configuration of FIG. 5B, a die 30_2 having a power supply circuit 31A is provided, and the power supply circuit 31 of the die 30_2, which is far from the base die 20, supplies a constant voltage Vout1 to the functional circuits 32A of the dies 30_1 and 30_3, which are close to the die 30_2. Similarly, in the configuration of FIG. 5B, a die 30_5 having a power supply circuit 31B is provided, and the power supply circuit 31 of the die 30_5, which is far from the base die 20, supplies a constant voltage Vout2 to the functional circuits 32B of the dies 30_4 and 30_6, which are close to the die 30_5. The base die 20, die 30_2, and die 30_5 are electrically connected via through electrodes 41A. The die 30_2 is electrically connected to the dies 30_1 and 30_3 via a through electrode 41B_1, and the die 30_5 is electrically connected to the dies 30_4 and 30_6 via a through electrode 41B_2.

[0061] 5A and 5B , in a configuration in which multiple dies are three-dimensionally stacked on a base die, power management in the Z direction can easily ensure uniformity in the voltage supplied by the power supply circuit. Furthermore, the voltage required to generate a constant voltage can be supplied to dies far from the base die, and the power supply circuit and the functional circuits can be located close to each other. Furthermore, since the multiple functional circuits 32A and 32B can be positioned at equal distances from the power supply circuits 31A and 31B, a semiconductor device with excellent uniformity in the voltage supplied to each functional circuit 32A and 32B can be obtained.

[0062] 6A and 6B show an example of an integrated circuit (referred to as an IC chip) having the above-described semiconductor device 10. The semiconductor device 10 can be made into a single IC chip by mounting multiple dies on a package substrate. An example of the configuration is shown in FIGS. 6A and 6B.

[0063] The cross-sectional schematic diagram of an IC chip 100A shown in FIG. 6A illustrates a semiconductor device 10 having a base die 20 on a package substrate 101, with three layers of dies 30_1 to 30_3 stacked on the base die 20 as an example. The package substrate 101 is provided with solder balls 102 for connecting the IC chip 100A to a printed circuit board or the like. The dies 30_1 to 30_3 can be connected to the base die 20 via through-electrodes 41A and 41B that penetrate the dies 30_1 to 30_3. Furthermore, each layer can be electrically connected via metal bumps 42 (also referred to as microbumps) that are provided between the through-electrodes 41A and 41B that penetrate the respective layers.

[0064] The dies 30_1 to 30_3 may be configured without using the metal bumps 42. In this case, the dies may be bonded to each other and the electrodes exposed on the surfaces may be electrically connected. Cu-Cu bonding may be used as a technique for electrically connecting different layers using electrodes exposed on the surfaces. Cu-Cu bonding is a technique for achieving electrical conduction by connecting Cu (copper) pads together.

[0065] As another example, the cross-sectional schematic diagram of IC chip 100B shown in Fig. 6B shows a configuration in which dies 30_1 to 30_3 are stacked as shown in Fig. 6A, with thermal diffusion layers 50 provided between die 30_1 and die 30_2 and between die 30_2 and die 30_3, and with heat dissipation layers 52 provided on the upper layers of dies 30_1 to 30_3. It is preferable to increase thermal conductivity between thermal diffusion layers 50 and heat dissipation layers 52 by connecting them with metal bumps and through electrodes, for example.

[0066] The thermal diffusion layer 50 and the heat dissipation layer 52 are preferably made of a material with excellent thermal conductivity, such as a metal layer or a layer containing an organic material. It is also preferable to provide a heat sink or the like on the heat dissipation layer to enhance heat dissipation. The heat dissipation layer 52 is preferably a layer with excellent adhesion to a heat sink or the like.

[0067] A series regulator applicable to the power supply circuit 31 can be made smaller than a switching regulator, but its conversion efficiency is lower. As a result, heat is easily generated in the process of generating the constant voltage Vout. Therefore, by promoting heat dissipation using the thermal diffusion layer 50 and the heat dissipation layer 52, a semiconductor device and IC chip with excellent reliability can be obtained.

[0068] As described above, one aspect of the present invention makes it easy to ensure uniformity in the voltage supplied by the power supply circuit in the Z direction in a configuration in which multiple dies are three-dimensionally stacked on a base die. Furthermore, the voltage required to generate a constant voltage can be supplied to dies far from the base die, and the power supply circuit and the functional circuits can be located close to each other. Furthermore, since multiple functional circuits can be arranged at equal distances from the power supply circuit, a semiconductor device with excellent uniformity in the voltage supplied to each functional circuit 32 can be obtained.

[0069] This embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0070] Second Embodiment In this embodiment, a modified example of the semiconductor device described in the above embodiment will be described. Note that the same reference numerals will be used to refer to the same components as in the first embodiment, and the description thereof will be omitted.

[0071] Fig. 7A is a cross-sectional view illustrating a modified example of a die that can be stacked on a base die of semiconductor device 10. Figs. 7B and 7C are cross-sectional views of a semiconductor device in which the configuration of Fig. 7A is applied to the cross-sectional view of semiconductor device 10 mounted on an IC chip described in Fig. 6A.

[0072] 7A illustrates a configuration in which element layers 40_1 to 40_4 each having an OS transistor 48 are provided on a base die 20S having a Si transistor 49. Electrodes 47 for electrically connecting the base die 20S and the element layers 40_1 to 40_4 can be provided in the process of manufacturing the Si transistor 49 or the OS transistor 48. In the present embodiment and the like, the number of element layers indicated by the element layers 40_1 to 40_4 is not limited to four, but may be two or more. When describing matters common to the element layers 40_1 to 40_4, the element layers may be simply referred to as "element layer 40."

[0073] 7A , the connection between the base die 20S including the Si transistor 49 and the element layers 40_1 to 40_4 including the OS transistors can be a monolithic configuration without using a through-electrode technique such as a TSV or a Cu-Cu direct bonding technique. The element layers 40_1 to 40_4 on the base die 20S can be configured to use wiring provided together with the OS transistors 48 included in the element layers 40_1 to 40_4 as electrodes 47 for connecting to upper or lower element layers.

[0074] The spacing between the wirings provided together with the OS transistors 48 can be finely processed compared to through electrodes used in TSV or Cu-Cu direct bonding technology. Therefore, in the configuration of the die 30S shown in FIG. 7A , the number of electrodes for connection to upper or lower element layers can be increased. This allows for an increase in the number of wirings (signal lines) between the functional circuits provided in the element layers 40_1 to 40_4 and the functional circuits provided in the base die 20S. In other words, the number of channels between the functional circuits can be increased. This allows for an increase in the transfer rate (bandwidth) of signals transmitted and received between the functional circuits. By increasing the bandwidth, the amount of data transferred per unit time can be increased.

[0075] Examples of metal oxides applicable to OS transistors include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains two or three elements selected from the group consisting of indium, an element M, and zinc. The element M is one or more elements selected from the group consisting of gallium, aluminum, silicon, boron, yttrium, tin, antimony, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. The element M is preferably one or more elements selected from the group consisting of aluminum, gallium, yttrium, and tin.

[0076] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) as the metal oxide. Alternatively, it is preferable to use an oxide containing indium, tin, and zinc (also referred to as ITZO). Alternatively, it is preferable to use an oxide containing indium, gallium, tin, and zinc. Alternatively, it is preferable to use an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO). Alternatively, it is preferable to use an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as IAGZO). Alternatively, it is preferable to use an oxide containing indium (In), gallium (Ga), zinc (Zn), and tin (Sn) (also referred to as IGZTO).

[0077] The metal oxide used in the OS transistor may have two or more metal oxide layers with different compositions. For example, a stacked structure of a first metal oxide layer having an atomic ratio of In:M:Zn=1:3:4 or a composition similar thereto and a second metal oxide layer having an atomic ratio of In:M:Zn=1:1:1 or a composition similar thereto provided over the first metal oxide layer can be preferably used.

[0078] Alternatively, for example, a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO may be used.

[0079] Note that a metal oxide used in an OS transistor preferably has crystallinity. Examples of a crystalline oxide semiconductor include a c-axis-aligned crystalline (CAAC)-OS and a nanocrystalline (nc)-OS. When a crystalline oxide semiconductor is used, a highly reliable semiconductor device can be provided.

[0080] Furthermore, OS transistors operate stably even in high-temperature environments and exhibit little fluctuation in their characteristics. For example, their off-state current hardly increases even in high-temperature environments. Specifically, their off-state current hardly increases even in temperatures above room temperature and below 200° C. Furthermore, their on-state current is unlikely to decrease even in high-temperature environments. Therefore, memory cells including OS transistors operate stably and exhibit high reliability even in high-temperature environments.

[0081] A functional circuit that can be provided in the element layer 40 having an OS transistor is preferably a memory circuit. A memory cell applicable to a memory circuit is preferably an NOSRAM. NOSRAM (registered trademark) is an abbreviation for "Nonvolatile Oxide Semiconductor Random Access Memory (RAM)." The NOSRAM memory cell is a two-transistor (2T) or three-transistor (3T) gain cell.

[0082] An OS transistor has an extremely small leakage current, that is, a current that flows between the source and drain in an off state. NOSRAM can be used as a nonvolatile memory by retaining a charge corresponding to data in a memory cell using its extremely small leakage current characteristic. In particular, NOSRAM can read stored data without destroying it (nondestructive readout), making it suitable for arithmetic processing in which only data read operations are repeated a large number of times.

[0083] FIG. 7B is a schematic cross-sectional view showing an example of the configuration of an IC chip 100C that combines the die 30S of FIG. 7A with the die 30 having the power supply circuit 31 described in the first embodiment.

[0084] In the IC chip 100C shown in Figure 7B, the configuration applied to the dies 30S_1 and 30S_2 is a monolithic configuration that does not use a technology using through electrodes such as TSVs in the element layer or a Cu-Cu direct bonding technology, so that the wiring provided in the element layer can be finely processed. Therefore, in the configuration of the IC chip 100C shown in Figure 7B, the number of electrodes for connecting the dies 30S_1 and 30S_2, in which functional circuits are provided, to the upper or lower element layer can be increased. Therefore, the transfer rate (bandwidth) of signals transmitted and received between the functional circuits can be expanded, and the amount of data transferred per unit time can be increased.

[0085] The configuration of the IC chip shown in FIG. 7B may also be an example of the configuration of the IC chip 100D shown in FIG. 7C. In FIG. 7C, the die 30S_2 provided in the upper layer and the die 30S_1 provided in the lower layer are arranged symmetrically with respect to the die 30. Specifically, the configuration is such that the base die 20S provided in the lower layer (die 30S_1), the element layers 40_1 to 40_4 provided in the lower layer (die 30S_1), the die 30, the element layers 40_1 to 40_4 provided in the upper layer (die 30S_2), and the base die 20S provided in the upper layer (die 30S_2) are stacked in this order. This configuration can improve the uniformity of the voltage supplied by the power supply circuit 31 to the functional circuits of each die 30S_1 and 30S_2.

[0086] Next, a configuration example of a functional circuit 32M that functions as a memory circuit using a NOSRAM that can be applied to the element layers 40_1 to 40_4 including OS transistors will be described.

[0087] 8A includes a memory cell array 60 and a peripheral circuit 65. The peripheral circuit 65 includes a control circuit 61, a row circuit 62, a column circuit 63, and an input / output circuit 64.

[0088] The memory cell array 60 has memory cells 66, word lines RWL, word lines WWL, bit lines RBL, bit lines WBL, source lines SL, and wiring BGL. The word lines RWL may be referred to as read word lines. The word lines WWL may be referred to as write word lines. The bit lines RBL may be referred to as read bit lines. The bit lines WBL may be referred to as write bit lines.

[0089] The control circuit 61 controls writing and reading of data. The control circuit 61 processes command signals (e.g., chip enable signals, write enable signals, etc.) from the outside and generates control signals for other circuits in the peripheral circuit 65.

[0090] The row circuit 62 has a function of selecting a row to be accessed. For example, the row circuit 62 has a row decoder and a word line driver. The column circuit 63 has a function of precharging the bit lines WBL and RBL, a function of writing data to the bit lines WBL, a function of amplifying data on the bit lines RBL, a function of reading data from the bit lines RBL, etc. The input / output circuit 64 has a function of holding write data, a function of holding read data, etc.

[0091] The configuration of the peripheral circuit 65 is changed as appropriate depending on the configuration, read method, write method, etc. of the memory cell array 60. It is also preferable that part of the peripheral circuit 65 is provided on the base die 20S.

[0092] 8B shows an example of a circuit configuration of the memory cell 66. Here, the memory cell 66 is a two-transistor (2T) gain cell. The memory cell 66 includes transistors MW1 and MR1 and a capacitor CS1. The transistor MW1 is a write transistor, and the transistor MR1 is a read transistor. The back gates of the transistors MW1 and MR1 are electrically connected to a wiring BGL.

[0093] Since the write transistor is an OS transistor, the memory cell 66 does not consume power to retain data. Therefore, the memory cell 66 is a low-power memory cell that can retain data for a long period of time, and the functional circuit 32M can be used as a nonvolatile memory device.

[0094] Another example of the configuration of the memory cell will be described with reference to FIGS. 9A to 9D.

[0095] The memory cell 66A shown in FIG. 9A is a 3T-type gain cell and includes transistors MW2, MR2, MS2, and a capacitance element CS2. The transistors MW2, MR2, and MS2 are a write transistor, a read transistor, and a select transistor, respectively. The back gates of the transistors MW2, MR2, and MS2 are electrically connected to a wiring BGL. The memory cell 66A is electrically connected to word lines RWL and WWL, bit lines RBL and WBL, a capacitance line CDL, and a power supply line PL2. For example, a voltage GND (low-level power supply voltage) is input to the capacitance line CDL and the power supply line PL2.

[0096] Another example of the configuration of a 2T gain cell is shown in Fig. 9B. In a memory cell 66B shown in Fig. 9B, the read transistor is an OS transistor without a back gate.

[0097] Another example of the configuration of a 3T-type gain cell is shown in Fig. 9C. In a memory cell 66C shown in Fig. 9C, the read transistor and the select transistor are OS transistors without a back gate.

[0098] In the above gain cell, a bit line that serves as both the bit line RBL and the bit line WBL may be provided.

[0099] Although NOSRAM has been described as an example of a configuration applicable to the memory cell 66, other configurations may be used as long as the memory cell can be formed using OS transistors. For example, DOSRAM, which is a memory circuit having OS transistors, may be used. DOSRAM (registered trademark) is an abbreviation for "Dynamic Oxide Semiconductor RAM" and refers to a RAM having 1T (transistor) 1C (capacitor) type memory cells. DOSRAM is a DRAM formed using OS transistors, and is a memory that temporarily stores information sent from the outside. DOSRAM is a memory that takes advantage of the low off-state current of OS transistors.

[0100] 9D shows an example of a 1T1C (capacitor) type memory cell. A memory cell 66D shown in FIG. 9D is electrically connected to a word line WL, a bit line BL, a capacitor line CDL, and a wiring BGL. The memory cell 66D includes a transistor MW3 and a capacitor CS3. The back gate of the transistor MW3 is electrically connected to the wiring BGL.

[0101] When the memory cell 66 is a NOSRAM or DOSRAM, it is preferable to apply a voltage to the word line WWL connected to the gate of the access transistor (transistor MW1 in FIG. 8B) so that the transistor is turned off, and power-gate the other parts. With this configuration, it is possible to stop the supply of power supply voltage while data is stored in the memory cell 66.

[0102] This embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0103] (Embodiment 3) In this embodiment, a structure of a transistor applicable to the semiconductor device described in the above embodiment will be described. As an example, a structure in which transistors having different electrical characteristics are stacked will be described. By using this structure, the degree of freedom in designing a semiconductor device can be increased. In addition, by stacking transistors having different electrical characteristics, the degree of integration of a semiconductor device can be increased.

[0104] 10 shows a part of a cross-sectional structure of a semiconductor device. The semiconductor device shown in FIG. 10 includes a transistor 550, a transistor 500, and a capacitor 600. FIG. 11A is a cross-sectional view of the transistor 500 in the channel length direction, FIG. 11B is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 11C is a cross-sectional view of the transistor 550 in the channel width direction. For example, the transistor 500 corresponds to the OS transistor described in the above embodiment, and the transistor 550 corresponds to a Si transistor.

[0105] In FIG. 10, the transistor 500 is provided above the transistor 550 , and the capacitor 600 is provided above the transistor 550 and the transistor 500 .

[0106] The transistor 550 is provided over a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 made of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions.

[0107] 11C , in the transistor 550, the top surface and the side surfaces in the channel width direction of the semiconductor region 313 are covered with a conductor 316 via an insulator 315. By forming the transistor 550 as a Fin type in this manner, the effective channel width is increased, thereby improving the on-state characteristics of the transistor 550. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 550.

[0108] The transistor 550 may be either a p-channel type or an n-channel type.

[0109] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or drain region, and the low-resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 550 may be a high electron mobility transistor (HEMT) by using GaAs and GaAlAs, or the like.

[0110] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0111] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material such as silicon containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron, a metal material, an alloy material, or a metal oxide material.

[0112] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a stacked structure, and tungsten is particularly preferable in terms of heat resistance.

[0113] The transistor 550 may be formed using an SOI (Silicon on Insulator) substrate or the like.

[0114] The SOI substrate may be a SIMOX (Separation by Implanted Oxygen) substrate formed by implanting oxygen ions into a mirror-polished wafer and then heating it at a high temperature to form an oxide layer to a certain depth from the surface and eliminate defects that have occurred in the surface layer, or an SOI substrate formed using a Smart Cut method or an ELTRAN method (registered trademark: Epitaxial Layer Transfer) that cleaves a semiconductor substrate by utilizing growth by heat treatment of microvoids formed by hydrogen ion implantation. A transistor formed using a single crystal substrate has a single crystal semiconductor in a channel formation region.

[0115] An insulator 320 , an insulator 322 , an insulator 324 , and an insulator 326 are stacked in this order to cover the transistor 550 .

[0116] The insulators 320, 322, 324, and 326 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0117] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0118] The insulator 322 may function as a planarizing film that planarizes steps caused by the transistor 550 or the like provided thereunder. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0119] The insulator 324 is preferably a film having a barrier property that prevents hydrogen, impurities, and the like from diffusing from the substrate 311 or the transistor 550 to a region where the transistor 500 is provided.

[0120] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, diffusion of hydrogen into a semiconductor element including an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 550. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0121] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, in the TDS analysis, the amount of desorption of hydrogen from the insulator 324 is calculated as 1×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. and the amount of desorption converted into hydrogen atoms is 1×10 １６ atoms / cm ２ Below 5 × 10, preferably １５ atoms / cm ２ The following is fine.

[0122] The insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0123] Furthermore, insulators 320, 322, 324, and 326 are embedded with conductors 328 and 330, which are connected to capacitor 600 or transistor 500. Note that conductors 328 and 330 function as plugs or wiring. Furthermore, for conductors that function as plugs or wiring, the same reference numeral may be used to denote multiple components. Furthermore, in this specification and the like, the wiring and the plug connecting to the wiring may be integrated. That is, there are cases where a portion of a conductor functions as a wiring, and cases where a portion of a conductor functions as a plug.

[0124] As the material for each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single layer or a laminated layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the plug and wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0125] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 10 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring connected to the transistor 550. Note that the conductor 356 can be formed using a material similar to that of the conductors 328 and 330.

[0126] Note that, for example, the insulator 350 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0127] Note that, for example, tantalum nitride or the like is preferably used as a conductor having a barrier property against hydrogen. Furthermore, by stacking tantalum nitride and highly conductive tungsten, diffusion of hydrogen from the transistor 550 can be suppressed while maintaining the conductivity of the wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

[0128] A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 10 , an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. The conductor 366 can be provided using the same material as the conductors 328 and 330.

[0129] Note that, for example, the insulator 360 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0130] A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 10 , an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. A conductor 376 is formed in the insulators 370, 372, and 374. The conductor 376 functions as a plug or a wiring. The conductor 376 can be formed using the same material as the conductors 328 and 330.

[0131] Note that, for example, the insulator 370 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0132] A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 10 , an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. A conductor 386 is formed in the insulators 380, 382, ​​and 384. The conductor 386 functions as a plug or wiring. The conductor 386 can be provided using the same material as the conductors 328 and 330.

[0133] Note that, for example, the insulator 380 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0134] In the above, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 have been described, but the semiconductor device according to this embodiment is not limited to this. There may be three or fewer wiring layers similar to the wiring layer including the conductor 356, or there may be five or more wiring layers similar to the wiring layer including the conductor 356.

[0135] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order over the insulator 384. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably formed using a substance that has a barrier property against oxygen, hydrogen, and the like.

[0136] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property that prevents hydrogen, impurities, and the like from diffusing from the substrate 311 or a region where the transistor 550 is provided to a region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 324 can be used.

[0137] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, diffusion of hydrogen into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, a film that suppresses hydrogen diffusion is preferably used between the transistor 500 and the transistor 550. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0138] As a film having a barrier property against hydrogen, for example, the insulators 510 and 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0139] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0140] For example, the insulator 512 and the insulator 516 can be made of a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, the insulators 512 and 516 can be made of a silicon oxide film or a silicon oxynitride film.

[0141] A conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503), and the like are embedded in the insulators 510, 512, 514, and 516. The conductor 518 functions as a plug or wiring connected to the capacitor 600 or the transistor 550. The conductor 518 can be formed using a material similar to that of the conductors 328 and 330.

[0142] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 550 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0143] Above the insulator 516, the transistor 500 is provided.

[0144] As shown in Figures 11A and 11B, transistor 500 has a conductor 503 arranged so as to be embedded in insulator 514 and insulator 516, an insulator 520 arranged on insulator 516 and conductor 503, an insulator 522 arranged on insulator 520, an insulator 524 arranged on insulator 522, an oxide 530a arranged on insulator 524, an oxide 530b arranged on oxide 530a, conductors 542a and 542b arranged apart from each other on oxide 530b, an insulator 580 arranged on conductors 542a and 542b and having an opening formed therein overlapping with conductors 542a and 542b, an insulator 545 arranged on the bottom and side surfaces of the opening, and a conductor 560 arranged on the surface on which insulator 545 is formed.

[0145] 11A and 11B, it is preferable that an insulator 544 be disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580. It is also preferable that the conductor 560 have a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a. It is also preferable that an insulator 574 be disposed on the insulator 580, the conductor 560, and the insulator 545, as shown in FIG.

[0146] In this specification and other documents, oxide 530a and oxide 530b may be collectively referred to as oxide 530.

[0147] Although the transistor 500 has a two-layer structure of the oxide 530a and the oxide 530b in and around the channel formation region, the present invention is not limited to this structure. For example, the oxide 530b may be a single layer or a stack of three or more layers.

[0148] Although the transistor 500 has a two-layer structure in which the conductor 560 is stacked, the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. The transistor 500 shown in FIGS. 10 and 11A is merely an example and is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like.

[0149] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source electrode and drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductor 560 can be formed without providing an alignment margin, thereby reducing the area occupied by the transistor 500. This allows for miniaturization and high integration of semiconductor devices.

[0150] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. This improves the switching speed of the transistor 500 and provides high frequency characteristics.

[0151] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the threshold voltage of the transistor 500 above 0 V and reduce the off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to not applying a negative potential to the conductor 503.

[0152] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. In this way, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and a channel formation region formed in the oxide 530 can be covered.

[0153] In this specification, etc., a transistor structure in which a channel formation region is electrically surrounded by the electric field of a first gate electrode is called a surrounded channel (S-channel) structure. The S-channel structure disclosed in this specification, etc., is different from a Fin structure and a planar structure. On the other hand, the S-channel structure disclosed in this specification, etc., can also be considered as a type of Fin structure. In this specification, etc., a Fin structure refers to a structure in which a gate electrode is disposed so as to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By employing the Fin structure and the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to obtain a transistor in which the short channel effect is less likely to occur.

[0154] By forming the transistor in the S-channel structure, the channel formation region can be electrically surrounded. Note that the S-channel structure electrically surrounds the channel formation region, and therefore, can be said to be substantially equivalent to a Gate All Around (GAA) structure or a Lateral Gate All Around (LGAA) structure. By forming the transistor in the S-channel structure, the GAA structure, or the LGAA structure, the channel formation region formed at or near the interface between the oxide 530 and the gate insulator can be the entire bulk of the oxide 530. Therefore, the current density flowing through the transistor can be improved, which is expected to improve the on-state current of the transistor or the field-effect mobility of the transistor.

[0155] The conductor 503 has a structure similar to that of the conductor 518, in which the conductor 503a is formed in contact with the inner walls of the openings of the insulators 514 and 516, and the conductor 503b is formed further inside. Note that although the transistor 500 shows a structure in which the conductors 503a and 503b are stacked, the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0156] Here, the conductor 503a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (i.e., the impurities are less likely to permeate). Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate). Note that in this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities and oxygen.

[0157] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, which can suppress the conductor 503b from being oxidized and causing a decrease in conductivity.

[0158] Furthermore, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b be made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Note that, although the conductor 503 is illustrated as a stack of the conductors 503a and 503b in this embodiment, the conductor 503 may have a single-layer structure.

[0159] The insulators 520, 522, and 524 function as a second gate insulating film.

[0160] Here, the insulator 524 in contact with the oxide 530 preferably contains more oxygen than the oxygen required for the stoichiometric composition. The oxygen is easily released from the film by heating. In this specification and elsewhere, oxygen released by heating may be referred to as "excess oxygen." That is, the insulator 524 preferably has a region containing excess oxygen (also referred to as an "excess oxygen region"). By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies (V Ｏ When hydrogen enters an oxygen vacancy in the oxide 530, the defect (hereinafter referred to as V Ｏ H.) may function as a donor and generate electrons as carriers. In addition, some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated. In one embodiment of the present invention, V in the oxide 530 Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. ＯTo obtain an oxide semiconductor in which H is sufficiently reduced, it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (also referred to as "dehydration" or "dehydrogenation treatment") and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (also referred to as "oxygenation treatment"). Ｏ When an oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0161] Specifically, it is preferable to use an oxide material from which part of the oxygen is released by heating as an insulator having an excess oxygen region. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen, converted into oxygen atoms, is 1.0×10 in TDS (Thermal Desorption Spectroscopy) analysis. １８ atoms / cm ３ or more, preferably 1.0 × 10 １９ atoms / cm ３ More preferably, 2.0 × 10 １９ atoms / cm ３ or more, or 3.0 x 10 ２０ atoms / cm ３ The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0162] Alternatively, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By performing such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 that breaks the V−H bond, in other words, the V Ｏ The reaction "H → Vo + H" occurs, and dehydrogenation can be achieved. Some of the hydrogen generated at this time combines with oxygen to form H ２ As O, it may be removed from the oxide 530 or from an insulator near the oxide 530. Also, some of the hydrogen may be gettered to the conductor 542.

[0163] Furthermore, the microwave treatment is preferably performed using, for example, an apparatus having a power supply for generating high-density plasma or an apparatus having a power supply for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using a gas containing oxygen and high-density plasma, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530. The microwave treatment may be performed under a pressure of 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. The gases introduced into the microwave treatment apparatus may be, for example, oxygen and argon, with an oxygen flow ratio (O ２ / (O ２ +Ar)) is preferably 50% or less, and more preferably 10% or more and 30% or less.

[0164] Furthermore, in the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. or higher and 450° C. or lower, more preferably 350° C. or higher and 400° C. or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 530, thereby eliminating oxygen vacancies (V Ｏ ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere in order to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0165] By performing oxygen addition treatment on the oxide 530, oxygen vacancies in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction of "Vo + O → null" can be promoted. Furthermore, the supplied oxygen reacts with hydrogen remaining in the oxide 530, converting the hydrogen into H ２ As a result, hydrogen remaining in the oxide 530 is recombined with the oxygen vacancies to form V. Ｏ The formation of H can be suppressed.

[0166] Furthermore, when the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms, oxygen molecules, etc.) (that is, the insulator 524 is less likely to transmit oxygen).

[0167] The insulator 522 preferably has a function of suppressing diffusion of oxygen, impurities, and the like, which prevents oxygen contained in the oxide 530 from diffusing toward the insulator 520. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524, the oxide 530, and the like can be suppressed.

[0168] The insulator 522 may be, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ), or (Ba,Sr)TiO ３ It is preferable to use an insulator containing a so-called high-k material such as (BST) in a single layer or a multilayer configuration. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to thinner gate insulating films. By using a high-k material as the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0169] In particular, an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material that has the function of suppressing the diffusion of impurities and oxygen (i.e., the oxygen is less likely to permeate), is preferably used. As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 or the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0170] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0171] Furthermore, it is preferable that the insulator 520 be thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Furthermore, by combining a high-k insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 520 having a thermally stable layered structure with a high dielectric constant.

[0172] 11A and 11B , the second gate insulating film has a three-layer structure including the insulators 520, 522, and 524. However, the second gate insulating film may have a single-layer structure, a two-layer structure, or a four- or more-layer structure. In this case, the second gate insulating film is not limited to a stack structure made of the same material, and may have a stack structure made of different materials.

[0173] The transistor 500 uses a metal oxide functioning as an oxide semiconductor for the oxide 530 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (the element M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like) can be used as the oxide 530.

[0174] The metal oxide functioning as an oxide semiconductor may be formed by a sputtering method or an atomic layer deposition (ALD) method. Note that the metal oxide functioning as an oxide semiconductor will be described in detail in another embodiment.

[0175] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap in this manner, the off-state current of the transistor can be reduced.

[0176] By having the oxide 530a below the oxide 530b, the oxide 530 can suppress the diffusion of impurities from components formed below the oxide 530a to the oxide 530b.

[0177] The oxide 530 preferably has a configuration of multiple oxide layers with different atomic ratios of the metal atoms. Specifically, the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530a is preferably larger than the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530b. Furthermore, the atomic ratio of the element M to In in the metal oxide used for the oxide 530a is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Furthermore, the atomic ratio of In to M in the metal oxide used for the oxide 530b is preferably larger than the atomic ratio of In to M in the metal oxide used for the oxide 530a.

[0178] The energy of the conduction band minimum of the oxide 530a is preferably higher than that of the oxide 530b, or in other words, the electron affinity of the oxide 530a is preferably smaller than that of the oxide 530b.

[0179] Here, the energy level of the conduction band minimum changes gradually at the junction between the oxides 530a and 530b. In other words, the energy level of the conduction band minimum at the junction between the oxides 530a and 530b changes continuously or forms a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxides 530a and 530b.

[0180] Specifically, when the oxide 530a and the oxide 530b have a common element (main component) other than oxygen, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In—Ga—Zn oxide, an In—Ga—Zn oxide, a Ga—Zn oxide, or a gallium oxide can be used as the oxide 530a.

[0181] In this case, the oxide 530b serves as the main carrier path. By configuring the oxide 530a as described above, the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.

[0182] Conductors 542a and 542b, which function as a source electrode and a drain electrode, are provided on the oxide 530b. The conductors 542a and 542b are preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or alloys containing the above metal elements or alloys combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen.Furthermore, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen or oxygen.

[0183] 11A shows the conductor 542a and the conductor 542b as a single layer, they may be stacked with two or more layers. For example, a tantalum nitride film and a tungsten film may be stacked. Alternatively, a titanium film and an aluminum film may be stacked. Alternatively, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, or a two-layer structure in which a copper film is stacked on a tungsten film may be used.

[0184] Other examples include a three-layer structure in which a titanium film or titanium nitride film is laminated on the titanium film or titanium nitride film, an aluminum film or copper film is laminated on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, and a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film, an aluminum film or copper film is laminated on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.

[0185] 11A, regions 543a and 543b may be formed as low-resistance regions at and near the interface of the oxide 530 with the conductor 542a (conductor 542b). In this case, the region 543a functions as one of the source and drain regions, and the region 543b functions as the other of the source and drain regions. A channel formation region is formed in the region sandwiched between the regions 543a and 543b.

[0186] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Furthermore, a metal compound layer containing a metal contained in the conductor 542a (conductor 542b) and a component of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier density in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0187] The insulator 544 is provided to cover the conductors 542 a and 542 b and suppresses oxidation of the conductors 542 a and 542 b. In this case, the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0188] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Alternatively, the insulator 544 can be silicon nitride oxide, silicon nitride, or the like.

[0189] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Hafnium aluminate is particularly preferable because it has higher heat resistance than hafnium oxide film. Therefore, it is less likely to crystallize during heat treatment in a later process. Note that if the conductors 542a and 542b are made of a material that is resistant to oxidation or whose conductivity does not decrease significantly even when it absorbs oxygen, the insulator 544 is not an essential component. It may be designed appropriately depending on the desired transistor characteristics.

[0190] The insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b. The insulator 580 can also prevent the conductor 542 from being oxidized by excess oxygen contained in the insulator 580.

[0191] The insulator 545 functions as a first gate insulating film. Like the insulator 524, the insulator 545 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating.

[0192] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0193] By providing an insulator containing excess oxygen as the insulator 545, oxygen can be effectively supplied from the insulator 545 to the channel formation region of the oxide 530b. Similar to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 545 is preferably reduced. The thickness of the insulator 545 is preferably 1 nm to 20 nm.

[0194] Furthermore, a metal oxide may be provided between the insulator 545 and the conductor 560 to efficiently supply excess oxygen contained in the insulator 545 to the oxide 530. The metal oxide preferably suppresses oxygen diffusion from the insulator 545 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed. In other words, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 may be used.

[0195] Note that the insulator 545 may have a layered structure, similar to the second gate insulating film. As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Therefore, by using a layered structure of a high-k material and a thermally stable material as the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Furthermore, a thermally stable layered structure with a high dielectric constant can be achieved.

[0196] The conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in FIGS. 11A and 11B, but may have a single-layer structure or a stacked structure of three or more layers.

[0197] The conductor 560a is a material containing hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２It is preferable to use a conductive material that has the function of suppressing the diffusion of impurities such as copper atoms, etc., or that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). The conductor 560a has the function of suppressing oxygen diffusion, which can suppress the oxidation of the conductor 560b due to the oxygen contained in the insulator 545, thereby preventing a decrease in conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum, tantalum nitride, ruthenium, and ruthenium oxide. An oxide semiconductor that can be used for the oxide 530 can also be used as the conductor 560a. In this case, the conductor 560b can be formed by sputtering, thereby reducing the electrical resistance of the conductor 560a and making it a conductor. This can be called an OC (oxide conductor) electrode.

[0198] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductor 560b also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0199] The insulator 580 is provided over the conductor 542a and the conductor 542b with the insulator 544 interposed therebetween. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or a resin. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Silicon oxide and silicon oxide having voids are particularly preferred because they allow for easy formation of excess oxygen regions in a later step.

[0200] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating, oxygen in the insulator 580 can be efficiently supplied to the oxide 530. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0201] The opening of the insulator 580 is formed to overlap the region between the conductors 542 a and 542 b, so that the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductors 542 a and 542 b.

[0202] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to ensure that the conductivity of the conductor 560 does not decrease. If the film thickness of the conductor 560 is increased for this purpose, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580, and therefore, even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0203] The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 545. By forming the insulator 574 by a sputtering method, excess oxygen regions can be provided in the insulator 545 and the insulator 580. This allows oxygen to be supplied from the excess oxygen regions into the oxide 530.

[0204] For example, the insulator 574 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium.

[0205] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even when it is a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as both an oxygen source and a barrier film against impurities such as hydrogen.

[0206] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0207] Furthermore, conductors 540a and 540b are arranged in openings formed in insulators 581, 574, 580, and 544. Conductor 540a and 540b are arranged opposite each other with conductor 560 interposed therebetween. Conductor 540a and 540b have the same configuration as conductors 546 and 548, which will be described later.

[0208] An insulator 582 is provided over the insulator 581. The insulator 582 is preferably formed using a substance that has a barrier property against oxygen, hydrogen, and the like. Therefore, the insulator 582 can be formed using a material similar to that of the insulator 514. For example, the insulator 582 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0209] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0210] An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.

[0211] Furthermore, conductors 546 and 548 are embedded in insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0212] The conductor 546 and the conductor 548 function as plugs or wirings that connect to the capacitor 600, the transistor 500, or the transistor 550. The conductor 546 and the conductor 548 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0213] After the transistor 500 is formed, an opening may be formed to surround the transistor 500, and an insulator with high barrier properties against hydrogen or water may be formed to cover the opening. By surrounding the transistor 500 with the insulator with high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, multiple transistors 500 may be collectively surrounded by an insulator with high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, it is preferable to form an opening that reaches the insulator 522 or the insulator 514 and form the insulator with high barrier properties in contact with the insulator 522 or the insulator 514, because this can serve as part of the manufacturing process of the transistor 500. For example, the insulator with high barrier properties against hydrogen or water may be made of a material similar to that of the insulator 522 or the insulator 514.

[0214] Subsequently, a capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0215] A conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug or wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.

[0216] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), or the like can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can also be used.

[0217] In this embodiment, the conductor 612 and the conductor 610 have a single-layer structure, but the present invention is not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.

[0218] The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. Note that the conductor 620 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferable. Furthermore, when the conductor 620 is formed simultaneously with other components such as a conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) can be used.

[0219] An insulator 640 is provided over the conductor 620 and the insulator 630. The insulator 640 can be provided using a material similar to that of the insulator 320. The insulator 640 may also function as a planarizing film that covers the uneven shape underneath.

[0220] With this structure, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor.

[0221] Examples of a substrate that can be used for the semiconductor device of one embodiment of the present invention include a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate (e.g., a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, etc.), a semiconductor substrate (e.g., a single crystal semiconductor substrate, a polycrystalline semiconductor substrate, or a compound semiconductor substrate), an SOI (Silicon on Insulator) substrate, and the like. A plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may also be used. Examples of a glass substrate include barium borosilicate glass, aluminosilicate glass, aluminoborosilicate glass, and soda-lime glass. Alternatively, crystallized glass or the like can be used.

[0222] Alternatively, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film can be used as the substrate. Examples of flexible substrates, laminated films, and base films include the following: Plastics, such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Synthetic resins, such as acrylic, can be used. Polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride can be used. Polyamide, polyimide, aramid resin, epoxy resin, inorganic vapor-deposited film, and paper can be used. In particular, by manufacturing transistors using semiconductor substrates, single-crystal substrates, or SOI substrates, transistors with small size, high current capacity, and little variation in characteristics, size, or shape can be manufactured. Constructing a circuit using such transistors can reduce the power consumption of the circuit or increase the circuit integration.

[0223] Alternatively, a flexible substrate may be used as the substrate, and transistors, resistors, and / or capacitors may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistors, resistors, and / or capacitors. The release layer can be used to separate a semiconductor device, after a part or all of the semiconductor device is completed thereon, from the substrate and transfer it to another substrate. In this case, the transistors, resistors, and / or capacitors can be transferred to a substrate with poor heat resistance, a flexible substrate, or the like. The release layer may be, for example, a laminated structure of an inorganic film including a tungsten film and a silicon oxide film, a structure in which an organic resin film such as polyimide is formed on a substrate, or a silicon film containing hydrogen.

[0224] That is, the semiconductor device may be formed on a certain substrate and then transferred to another substrate. Examples of substrates onto which the semiconductor device may be transferred include, in addition to the substrates on which the above-mentioned transistors can be formed, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester), or recycled fibers (acetate, cupra, rayon, recycled polyester)), leather substrates, and rubber substrates. By using these substrates, it is possible to manufacture semiconductor devices that are flexible, durable, heat-resistant, lightweight, or thin.

[0225] By providing a semiconductor device over a flexible substrate, an increase in weight can be suppressed and a semiconductor device that is less likely to be damaged can be provided.

[0226] 10 is just an example and is not limited to the structure thereof, and an appropriate transistor may be used depending on the circuit structure, driving method, etc. For example, when the semiconductor device is a unipolar circuit including only OS transistors (meaning transistors with the same polarity, such as only n-channel transistors), the structure of the transistor 550 may be the same as that of the transistor 500.

[0227] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiment modes and examples.

[0228] Embodiment 4 In this embodiment, examples of cross-sectional structures of semiconductor devices including the OS transistors described in the above embodiments, such as DOSRAM and NOSRAM, will be described.

[0229] 12 shows a cross-sectional configuration example in the case where a DOSRAM circuit configuration is used. In FIG. 12, element layers 700[1] to 700[4] are stacked on a driver circuit layer 701.

[0230] 12 illustrates a transistor 550 included in the driver circuit layer 701. The transistor 550 described in the above embodiment can be used as the transistor 550.

[0231] Note that the transistor 550 illustrated in FIG. 12 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or the driving method.

[0232] A wiring layer provided with an interlayer film, wiring, plugs, and the like may be provided between the driver circuit layer 701 and the element layer 700, or between the kth element layer 700 and the k+1th element layer 700. Note that in this embodiment and the like, the kth element layer 700 may be referred to as element layer 700[k], and the k+1th element layer 700 may be referred to as element layer 700[k+1]. Here, k is an integer of 1 to N. Furthermore, in this embodiment and the like, when "k+α (α is an integer of 1 or more)" or "k-α" is used, the solutions of "k+α" and "k-α" are integers of 1 to N, respectively.

[0233] Furthermore, multiple wiring layers can be provided depending on the design. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0234] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 550. A conductor 328 or the like is embedded in the insulators 320 and 322. A conductor 330 or the like is embedded in the insulators 324 and 326. The conductors 328 and 330 function as contact plugs or wirings.

[0235] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 320 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0236] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 12 , an insulator 350, an insulator 357, an insulator 352, and an insulator 354 are stacked in this order over the insulator 326 and the conductor 330. A conductor 356 is formed in the insulator 350, the insulator 357, and the insulator 352. The conductor 356 functions as a contact plug or a wiring.

[0237] The insulator 514 included in the element layer 700[1] is provided over the insulator 354. A conductor 358 is embedded in the insulator 514 and the insulator 354. The conductor 358 functions as a contact plug or a wiring. For example, the bit line BL and the transistor 550 are electrically connected through the conductor 358, the conductor 356, the conductor 330, and the like.

[0238] Fig. 13A shows an example of the cross-sectional structure of the element layer 700[k]. Fig. 13B shows an equivalent circuit diagram of Fig. 13A. Fig. 13A shows an example in which two memory cells MC are electrically connected to one bit line BL.

[0239] 12 and 13A includes a transistor M1 and a capacitor C. The transistor M1 can be, for example, the transistor 500 described in the above embodiment.

[0240] Note that in this embodiment, the transistor M1 is a modified example of the transistor 500. Specifically, the transistor M1 differs from the transistor 500 in that the conductors 542a and 542b extend beyond the ends of the metal oxide 531.

[0241] 12 and 13A includes a conductor 156 that functions as one terminal of a capacitance element C, an insulator 153 that functions as a dielectric, and a conductor 160 (conductor 160a and conductor 160b) that functions as the other terminal of the capacitance element C. The conductor 156 is electrically connected to a part of the conductor 542b. The conductor 160 is also electrically connected to a wiring PL (not shown in FIG. 13A).

[0242] The capacitor C is formed in an opening provided by removing a part of the insulator 574, the insulator 580, and the insulator 554. The conductor 156, the insulator 153, and the conductor 160a are formed along the side surfaces of the openings, and therefore are preferably formed by an ALD method, a CVD method, or the like.

[0243] The conductor 156 and the conductor 160 may be made of a conductor that can be used for the conductor 505 or the conductor 560. For example, titanium nitride formed by an ALD method may be used as the conductor 156. Titanium nitride formed by an ALD method may be used as the conductor 160a, and tungsten formed by a CVD method may be used as the conductor 160b. Note that if the adhesion of tungsten to the insulator 153 is sufficiently high, a single layer film of tungsten formed by a CVD method may be used as the conductor 160.

[0244] It is preferable to use a high-dielectric-constant (high-k) material (material with a high relative dielectric constant) for the insulator 153. For example, an oxide, oxynitride, oxynitride, or nitride containing one or more metal elements selected from aluminum, hafnium, zirconium, gallium, etc. can be used as the high-dielectric-constant insulator. Silicon may also be contained in the oxide, oxynitride, oxynitride, or nitride. Insulating layers made of the above materials may also be stacked.

[0245] For example, examples of high-dielectric-constant insulators that can be used include aluminum oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, oxides containing silicon and zirconium, oxynitrides containing silicon and zirconium, oxides containing hafnium and zirconium, oxynitrides containing hafnium and zirconium, etc. By using such high-dielectric-constant materials, the insulator 153 can be made thick enough to suppress leakage current, and the capacitance of the capacitance element C can be sufficiently ensured.

[0246] Furthermore, it is preferable to use a laminated insulating layer made of the above materials, and it is preferable to use a laminated structure of a high-dielectric-constant material and a material having a higher dielectric strength than the high-dielectric-constant material. For example, an insulating film formed by laminating zirconium oxide, aluminum oxide, and zirconium oxide in this order can be used as the insulator 153. Alternatively, it is possible to use an insulating film formed by laminating zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, it is possible to use an insulating film formed by laminating hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By using a laminated insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitance element C can be suppressed.

[0247] Fig. 14 shows an example of a cross-sectional configuration when a circuit configuration of a NOSRAM memory cell is used. Fig. 14 is also a modified example of Fig. 12. Fig. 15A shows an example of a cross-sectional structure of an element layer 700[k]. Fig. 15B shows an equivalent circuit diagram of Fig. 15A.

[0248] 14 and 15A has a transistor M1, a transistor M2, and a transistor M3 on an insulator 514. In addition, a conductor 215 is provided on the insulator 514. The conductor 215 can be formed simultaneously with the conductor 505 using the same material and in the same process.

[0249] 14 and 15A share one island-shaped metal oxide 531. In other words, part of the island-shaped metal oxide 531 functions as a channel formation region for the transistor M2, and another part functions as a channel formation region for the transistor M3. The source of the transistor M2 and the drain of the transistor M3, or the drain of the transistor M2 and the source of the transistor M3, are shared. Therefore, the area occupied by the transistors M2 and M3 is smaller than when the transistors M2 and M3 are provided independently.

[0250] 14 and 15A, an insulator 287 is provided on an insulator 581, and a conductor 161 is embedded in the insulator 287. An insulator 514 of an element layer 700[k+1] is provided on the insulator 287 and the conductor 161.

[0251] 14 and 15A, the conductor 215 of the element layer 700[k+1] functions as one terminal of the capacitance element C, the insulator 514 of the element layer 700[k+1] functions as a dielectric of the capacitance element C, and the conductor 161 functions as the other terminal of the capacitance element C. In addition, the other of the source and drain of the transistor M1 is electrically connected to the conductor 161 via a contact plug, and the gate of the transistor M2 is electrically connected to the conductor 161 via another contact plug.

[0252] This embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0253] In this embodiment, a transistor including an oxide semiconductor in a channel formation region (OS transistor) will be described. Note that in the description of the OS transistor, a comparison with a transistor including silicon in a channel formation region (also referred to as a Si transistor) will also be briefly described.

[0254] [OS Transistor] An OS transistor is preferably formed using an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of a channel formation region of an oxide semiconductor is preferably 1×10 １８ cm −３ Below 1 × 10, preferably １７ cm −３ less than 1×10 １６ cm −３ less than 1×10 １３ cm −３ less than 1×10 １０ cm −３ is less than 1×10 −９ cm −３ The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0255] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor may have a low density of trap states due to a low density of defect states. Charges trapped in trap states of the oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0256] Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen and nitrogen. Note that the impurities in the oxide semiconductor refer to, for example, elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0257] Furthermore, when impurities and oxygen vacancies exist in a channel formation region of an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate, and reliability may be reduced. Ｏ H) and generate electrons that become carriers. Ｏ When H is formed, the donor concentration in the channel formation region may increase. As the donor concentration in the channel formation region increases, the threshold voltage may vary. Therefore, if oxygen vacancies are present in the channel formation region of an oxide semiconductor, the transistor is likely to have normally-on characteristics (characteristics in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of an oxide semiconductor, impurities, oxygen vacancies, and V Ｏ It is preferable that H is reduced as much as possible.

[0258] The band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor having a band gap larger than that of silicon, the off-state current (also referred to as Ioff) of the transistor can be reduced.

[0259] Furthermore, as the size of Si transistors is reduced, a short channel effect (also referred to as SCE) occurs. This makes it difficult to reduce the size of Si transistors. One of the reasons for the short channel effect is the small band gap of silicon. On the other hand, an OS transistor uses an oxide semiconductor, which is a semiconductor material with a wide band gap, and therefore the short channel effect can be suppressed. In other words, an OS transistor is a transistor that does not have the short channel effect or has an extremely small short channel effect.

[0260] The short-channel effect is a degradation of electrical characteristics that becomes apparent as transistors are miniaturized (channel lengths are reduced). Specific examples of the short-channel effect include a decrease in threshold voltage, an increase in subthreshold swing (sometimes referred to as S value), and an increase in leakage current. Here, the S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.

[0261] Furthermore, the characteristic length is widely used as an index of resistance to the short channel effect. The characteristic length is an index of how easily the potential in the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to the short channel effect.

[0262] An OS transistor is an accumulation-mode transistor, while a Si transistor is an inversion-mode transistor. Therefore, compared with a Si transistor, an OS transistor has a smaller characteristic length between a source region and a channel formation region and a smaller characteristic length between a drain region and a channel formation region. Therefore, an OS transistor is more resistant to the short-channel effect than a Si transistor. That is, when a transistor with a short channel length is to be manufactured, an OS transistor is more suitable than a Si transistor.

[0263] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region becomes i-type or substantially i-type, the conduction band minimum of the channel formation region in a short-channel transistor is lowered due to the conduction-band-lowering (CBL) effect, and therefore the energy difference between the conduction band minimums of the source or drain region and the channel formation region can be reduced to 0.1 eV or more and 0.2 eV or less. − The source and drain regions are n-type regions. ＋ The region of type n ＋ / n − / n ＋ an accumulation-type junction-less transistor structure, or ＋ / n − / n ＋ This can also be regarded as an accumulation type non-junction transistor structure.

[0264] By using an OS transistor with the above structure, good electrical characteristics can be obtained even when a semiconductor device is miniaturized or highly integrated. For example, good electrical characteristics can be obtained even when the gate length of an OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, or 1 nm or more, 3 nm or more, or 5 nm or more. On the other hand, a Si transistor may have difficulty achieving a gate length of 20 nm or less or 15 nm or less due to the short-channel effect. Therefore, an OS transistor can be suitably used as a transistor having a shorter channel length than a Si transistor. Note that the gate length refers to the length of a gate electrode in the direction in which carriers move inside a channel formation region during transistor operation, and refers to the width of the bottom surface of the gate electrode in a plan view of the transistor.

[0265] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of an OS transistor is within the above range, the cutoff frequency of the transistor can be set to, for example, 50 GHz or higher, preferably 100 GHz or higher, and further preferably 150 GHz or higher at room temperature.

[0266] As described above, compared to Si transistors, OS transistors have excellent advantages such as a smaller off-state current and the ability to be manufactured as transistors with a short channel length.

[0267] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0268] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiments will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0269] [Electronic Component] FIG. 16A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 709 is mounted. The electronic component 709 shown in FIG. 16A has a semiconductor device 710 inside a mold 711. FIG. 16A omits some parts in order to show the interior of the electronic component 709. The electronic component 709 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 710 via wires 714. The electronic component 709 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.

[0270] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0271] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0272] Furthermore, it is preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0273] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0274] 16B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0275] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA).

[0276] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0277] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0278] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0279] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0280] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0281] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0282] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 16B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0283] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0284] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 17A . The electronic device 6500 shown in FIG. 17A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.

[0285] 17B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6611, the control device 6616, and the like. Note that the use of the semiconductor device of one embodiment of the present invention in the control device 6509 and the control device 6616 is preferable because power consumption can be reduced.

[0286] 17C shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 shown in Fig. 17C has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0287] The computer 5620 can have the configuration shown in the perspective view in Fig. 17D, for example. In Fig. 17D, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0288] A PC card 5621 shown in Figure 17E is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. The PC card 5621 includes a board 5622. The board 5622 also includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Figure 17E illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for these semiconductor devices, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 may be referred to.

[0289] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0290] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0291] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0292] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0293] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 709 can be used as the semiconductor device 5628.

[0294] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0295] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as equipment for processing and storing information.

[0296] The semiconductor device of one embodiment of the present invention can include an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space.

[0297] Fig. 18 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 18, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0298] 18 , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0299] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0300] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0301] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0302] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the semiconductor device of one embodiment of the present invention is preferably used for the control device 6807. An OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, an OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0303] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0304] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0305] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0306] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to install storage and servers for storing a huge amount of data, to ensure a stable power supply for maintaining the data, or to ensure cooling equipment required for maintaining the data.

[0307] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0308] Furthermore, the semiconductor device of one embodiment of the present invention consumes less power, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0309] Fig. 19 shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 19 has a plurality of servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0310] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0311] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0312] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0313] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0314] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0315] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0316] <Additional Notes Regarding the Description of the Present Specification, etc.> The following additional notes are provided regarding the above-described embodiments and the explanations of the respective configurations in the embodiments.

[0317] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0318] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or the content (or even a part of the content) described in one or more other embodiments.

[0319] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0320] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0321] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0322] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0323] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.

[0324] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0325] Furthermore, in this specification and the like, the terms voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), then voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0326] In this specification and the like, terms such as "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0327] In this specification, a switch refers to a device that has a function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0328] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between a source and a drain in a region where a channel is formed.

[0329] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0330] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0331] In this specification, "A and B are connected" refers to an electrical connection between A and B. Here, "A and B are electrically connected" refers to a connection in which an electrical signal can be transmitted between A and B when an object (such as a switch, transistor element, or diode, or a circuit including such an object and wiring) is present between A and B. Note that "A and B are electrically connected" also includes a case in which A and B are directly connected. Here, "A and B are directly connected" refers to a connection in which an electrical signal can be transmitted between A and B via wiring (or electrodes) or the like, without passing through the object. In other words, a direct connection refers to a connection that can be regarded as the same circuit diagram when represented by an equivalent circuit.

[0332] 10: semiconductor device, 20: base die, 21: power supply circuit, 30_1: die, 30_2: die, 30_3: die, 30: die, 31: power supply circuit, 32: functional circuit, 33: amplifier circuit, 34: transistor, 40: element layer, 41A: through electrode, 41B: through electrode, 41C: through electrode, 41D: through electrode, 42: metal bump, 47: electrode, 48: OS transistor, 49: Si transistor, 50: thermal diffusion layer, 52: heat dissipation layer

Claims

1. A base die having a first power supply circuit that generates a first voltage, A first die having a second power supply circuit that generates a second voltage when the first voltage is supplied, The present invention comprises a second die having a functional circuit that operates when the second voltage is supplied, The first die and the second die each have a first through electrode and a second through electrode, The first die is provided on the base die, The second die is provided in contact with the upper or lower layer of the first die. The base die and the first die are electrically connected via the first through electrode. A semiconductor device in which the first die and the second die are electrically connected via the second through electrode.

2. In claim 1, The first power supply circuit is a semiconductor device which is a switching regulator.

3. In claim 1, The second power supply circuit is a semiconductor device that is a series regulator.

4. In claim 1, A semiconductor device in which the functional circuit is a circuit having one or more functions of an arithmetic circuit, a peripheral circuit, a memory circuit, and a drive circuit.

5. In claim 1, It has a heat dissipation layer, The heat dissipation layer is provided between the first die and the second die in a semiconductor device.

6. In claim 1, A semiconductor device in which the first through-electrode and the second through-electrode, provided on different dies, are electrically connected via metal bumps.

7. In claim 1, The second die has a layer having a transistor with an oxide semiconductor in the channel formation region, The semiconductor device is provided with layers having the transistors, arranged in a stacked manner.

8. In claim 7, The oxide semiconductor is a semiconductor device having In, Ga, and Zn.

9. A base die having a first power supply circuit that generates a first voltage, A first die having a second power supply circuit that generates a second voltage when the first voltage is supplied, The present invention comprises a second die and a third die, each having a functional circuit that operates when the second voltage is supplied, The first die, the second die, and the third die each have a first through electrode and a second through electrode, The first die is provided on the base die, The second die is provided in contact with the lower layer of the first die, The third die is provided in contact with the upper layer of the first die, The base die and the first die are electrically connected via the first through electrode. A semiconductor device in which the first die, the second die, and the third die are electrically connected via the second through electrode.

10. In claim 9, The first power supply circuit is a semiconductor device which is a switching regulator.

11. In claim 9, The second power supply circuit is a semiconductor device that is a series regulator.

12. In claim 9, A semiconductor device in which the functional circuit is a circuit having one or more functions of an arithmetic circuit, a peripheral circuit, a memory circuit, and a drive circuit.

13. In claim 9, It has a heat dissipation layer, The heat dissipation layer is provided between the first die and the second die, and between the first die and the third die, in a semiconductor device.

14. In claim 9, A semiconductor device in which the first through-electrode and the second through-electrode, provided on different dies, are electrically connected via metal bumps.

15. In claim 9, The second die and the third die each have a layer having a transistor with an oxide semiconductor in the channel formation region. The semiconductor device is provided with layers having the transistors, arranged in a stacked manner.

16. In claim 15, The oxide semiconductor is a semiconductor device having In, Ga, and Zn.