Bias voltage generation circuit and electronic circuit

Abstract

This bias voltage generation circuit comprises: a first constant current source for supplying a first constant current; a second constant current source for supplying a second constant current that is smaller than the first constant current; and a bias voltage generation unit that includes at least one first MOS transistor, and generates a prescribed bias voltage on the basis of the second constant current or the first and second constant currents. The current is supplied by using a current mirror circuit made up of the first MOS transistor and at least one second MOS transistor. The bias voltage generation circuit is such that, on the basis of an operation mode switching control signal, when an electronic circuit is not running, a bias voltage generation unit generates a prescribed bias voltage on the basis of the second constant current, and when the electronic circuit is running, the bias voltage generation unit generates a prescribed bias voltage on the basis of the first and second constant currents or the first constant current.

Description

Bias voltage generating circuit and electronic circuit

[0001] The present invention relates to a bias voltage generating circuit and an electronic circuit including the bias voltage generating circuit.

[0002] It is already known that there is a demand for reducing current consumption in order to use rechargeable batteries for a long period of time. For example, Patent Document 1 discloses a method of selectively switching in response to an operation mode switching control signal so that the current consumption in the sleep mode is reduced compared to the operation mode.

[0003] The low dropout (LDO) regulator disclosed in Patent Document 1 includes: (1) a pass gate that controllably couples a voltage rail to a regulator output in response to a pass gate control signal that is an operation mode switching control signal; and (2) a controllable slew differential amplifier that is switchable between a slew-limited state and a full slew state, receives feedback from the regulator output, and is configured to generate the pass gate control signal at a full slew rate in the full slew state and at a reduced slew rate in the slew-limited state based on a reference voltage and the feedback.

[0004] Next, a specific description will be given using a conventional comparator circuit 100 as an example.

[0005] Fig. 17 is a circuit diagram showing the configuration of a conventional comparator circuit 100. Fig. 18 is a timing chart of signals showing the operation of the comparator circuit 100 of Fig. 17.

[0006] 17, a comparator circuit 100 is configured to include a comparator section 101 and a bias voltage generating section 102. The comparator section 101 is configured as a general comparator by a differential amplifier and an inverter INV1, and here, the differential amplifier is configured to include MOS field effect transistors (hereinafter referred to as MOS transistors) Q1 to Q7.

[0007] In the comparator section 101, MOS transistors Q1, Q2, and Q6 are P-channel MOS transistors, and MOS transistors Q3, Q4, Q5, and Q7 are N-channel MOS transistors. The comparator circuit 100 has a non-inverting input terminal T1, an inverting input terminal T2, a block enable signal input terminal T3, and a comparison result signal output terminal T4. During operation of the comparator section 101, a tail current Itail flows through the MOS transistor Q5. The output voltage of the differential amplifier is output from the connection point of the drains of the MOS transistors Q6 and Q7 via an inverter INV1 to the comparison result signal output terminal T4.

[0008] In the bias voltage generating section 102, the power supply voltage VDD is connected to the sources of the MOS transistors Q1, Q2, and Q6 of the comparator section 101, and is also grounded via a constant current source CI1 that supplies a reference current IREF and switches SW1 and SW2. The junction of the switches SW1 and SW2 generates a bias voltage VNBIAS, which is applied to the drain and gate of the MOS transistor Q8 and the gates of the MOS transistors Q5 and Q7. The sources of the MOS transistors Q8, Q5, and Q7 are grounded.

[0009] A block enable signal BLKEN, which is an operation mode switching control signal input to the block enable signal input terminal T3, is input to the control terminal of switch SW1 and, via inverter INV2, to the control terminal of switch SW2. When a high-level block enable signal BLKEN is input to the block enable signal input terminal T3, switch SW1 is turned on and switch SW2 is turned off. MOS transistors Q5, Q7, and Q8 form a current mirror circuit, in which a current flows through MOS transistor Q8 in response to bias voltage VNBIAS, and a current proportional to this current flows through MOS transistors Q5 and Q7. On the other hand, when a low-level block enable signal BLKEN is input to the block enable signal input terminal T3, switch SW1 is turned off and switch SW2 is turned on.

[0010] 18, in the comparator circuit 100 configured as described above, when the block enable signal BLKEN is switched from L level to H level at time t1, the operating mode is switched from sleep mode to startup mode, and the bias voltage VNBIAS goes through a startup period in which it rises from a pulled-down state to the gate-source voltage Vgs of the MOS transistor Q8, which corresponds to the reference current IREF, and then goes into active mode at time t2. In other words, the comparator circuit 100 cannot demonstrate its inherent capabilities until the startup period from time t1 to t2 has passed. The time required for this depends on the magnitude of the reference current IREF and the parasitic capacitance value in the wiring for the bias voltage VNBIAS.

[0011] Japanese Patent Application Laid-Open No. 2019-053757

[0012] However, while the conventional method of turning on / off a circuit that is always operating as needed can reduce current consumption, it has the side effect of preventing stable operation immediately after startup. For example, Patent Document 1 discloses a configuration in which one side of a parallel-connected current source is turned on / off depending on the operating mode in order to switch the tail current Itail. However, this circuit has the problem of not being able to operate stably immediately after startup.

[0013] An object of the present invention is to solve the above problems and to provide a bias voltage generation circuit for an electronic circuit that can start a desired operation immediately after switching the current consumption in accordance with an operation mode switching control signal, and an electronic circuit that includes the same.

[0014] A bias voltage generation circuit according to a first aspect of the present invention is a bias voltage generation circuit comprising: a first constant current source that supplies a first constant current; a second constant current source that supplies a second constant current smaller than the first constant current; and a bias voltage generation unit that includes at least one first MOS transistor and generates a predetermined bias voltage based on the second constant current or the first and second constant currents, the bias voltage generation circuit being for an electronic circuit to which current is supplied by a current mirror circuit formed by the first MOS transistor and at least one second MOS transistor, the bias voltage generation circuit being configured, based on an operation mode switching control signal, as follows: (1) when the electronic circuit is not operating, the bias voltage generation unit generates the predetermined bias voltage based on the second constant current; and (2) when the electronic circuit is operating, the bias voltage generation unit generates the predetermined bias voltage based on the first and second constant currents or the first constant current.

[0015] Furthermore, a second aspect of the present invention provides an electronic circuit having a bias voltage generation circuit including: a first constant current source that supplies a first constant current; a second constant current source that supplies a second constant current smaller than the first constant current; and a bias voltage generation unit that includes at least one first MOS transistor and generates a predetermined bias voltage based on the second constant current or the first and second constant currents, wherein the bias voltage generation circuit is supplied with current by a current mirror circuit formed by the first MOS transistor and at least one second MOS transistor, and the bias voltage generation circuit is configured, based on an operation mode switching control signal, as follows: (1) when the electronic circuit is not operating, the bias voltage generation unit generates the predetermined bias voltage based on the second constant current; and (2) when the electronic circuit is operating, the bias voltage generation unit generates the predetermined bias voltage based on the first and second constant currents, or the first constant current.

[0016] Therefore, according to the bias voltage generating circuit or electronic circuit of the present invention, the gate voltage of the bias transistor is kept constant even if the amount of current of the current source is reduced in accordance with the operation mode switching control signal in order to reduce current consumption, so that the desired operation can be started immediately after the operation mode switching control signal is switched.

[0017] 1 is a circuit diagram showing an example of the configuration of a comparator circuit 1 according to a first embodiment; FIG. 2 is a timing chart of each signal showing the operation of the comparator circuit 1 of FIG. 1; FIG. 3 is a diagram showing a comparison of the operation of a comparator circuit 100 according to a first comparative example and the comparator circuit 1 according to the embodiment, and is a timing chart of each signal when the bias voltage VNBIAS has sufficiently risen to a predetermined voltage at the time of signal detection; FIG. 4 is a diagram showing a comparison of the operation of a comparator circuit 100 according to a first comparative example and the comparator circuit 1 according to the embodiment, and is a timing chart of each signal when the bias voltage VNBIAS is in the middle of sufficiently rising to a predetermined voltage at the time of signal detection; FIG. 5 is a circuit diagram showing an example of the configuration of a bias voltage generating unit 12A according to a first modified example; FIG. 6 is a circuit diagram showing an example of the configuration of a bias voltage generating unit 12B according to a second modified example; FIG. 7 is a circuit diagram showing an example of the configuration of a bias voltage generating unit 12C according to a third modified example; FIG. 8 is a circuit diagram showing an example of the configuration of a bias voltage generating unit 12D according to a fourth modified example; FIG. 9 is a circuit diagram showing an example of the configuration of a bias voltage generating unit 12E according to a fifth modified example; and FIG. 10 is a circuit diagram showing an example of the configuration of a bias voltage generating unit 12F according to a sixth modified example. 19 is a circuit diagram showing an example of the configuration of a bias voltage generating unit 12G according to Modification 7. FIG. 20 is a circuit diagram showing an example of the configuration of a source follower circuit 3 according to Embodiment 2. FIG. 21 is a circuit diagram showing an example of the configuration of a voltage generating circuit 4 according to Embodiment 3. FIG. 22 is a circuit diagram showing an example of the configuration of a time constant circuit 5 according to Embodiment 4. FIG. 23 is a circuit diagram showing an example of the configuration of a comparator circuit 1A according to Embodiment 5. FIG. 24 is a circuit diagram showing an example of the configuration of a comparator circuit 1B according to Embodiment 6. FIG. 25 is a circuit diagram showing the configuration of a comparator circuit 100 according to a conventional example. FIG. 26 is a timing chart of each signal showing the operation of the comparator circuit 100 of FIG. 17. FIG. 27 is a circuit diagram showing the configuration of a comparator circuit 100A according to Comparative Example 1. FIG. 28 is a timing chart of each signal showing the operation of the comparator circuit 100A of FIG. 19. FIG. 29 is a circuit diagram showing the configuration of a comparator circuit 100B according to Comparative Example 2.

[0018] Hereinafter, comparative examples, embodiments of the present invention, and modifications thereof will be described with reference to the drawings. Note that the same or similar components are designated by the same reference numerals.

[0019] (Inventor's Knowledge) An embodiment of the present invention is characterized in that, when it is desired to reduce circuit current when not necessary, while operating immediately when necessary, the gate voltage of the bias generating transistor is kept constant even when the amount of current of the current source is reduced in order to reduce current consumption.

[0020] (Comparative Example 1) Fig. 19 is a circuit diagram showing an example of the configuration of a comparator circuit 100A according to Comparative Example 1. Fig. 20 is a timing chart of signals showing the operation of the comparator circuit 100A of Fig. 19. The comparator circuit 100A of Fig. 19 differs from the comparator circuit 100 of Fig. 17 in the following respects.

[0021] (1) A comparator section 101A is provided instead of the comparator section 101, and the comparator section 101A further includes constant current sources CI11 and CI12 that generate a standby current Itailp (FIG. 20).

[0022] According to the comparative example configured as described above, in order to facilitate operation immediately after startup, a small standby current Itailp (Figure 20) is supplied from the constant current sources CI11 and CI12, so that the comparator section 101A can be configured to operate even with a small circuit current.

[0023] However, with the small standby current Itailp according to Comparative Example 1, even if the comparator unit 101A tries to operate, it takes the same amount of time as a circuit without countermeasures until the circuit operates as originally expected. In addition, a standby current is required for each target current path, and the more current paths there are, the more the standby current needs to be increased.

[0024] Fig. 21 is a circuit diagram showing the configuration of a comparator circuit 100B according to Comparative Example 2. The comparator circuit 100B in Fig. 21 differs from the comparator circuit 100 in Fig. 17 in the following respects.

[0025] (1) A comparator unit 101B is provided instead of the comparator unit 101. The connection point between the sources of MOS transistors Q3 and Q4 is grounded via switch SW3 and MOS transistor Q5. The drain of MOS transistor Q6 is grounded via switch SW4 and MOS transistor Q7. When the block enable signal BLKEN is at H level, the switches SW3 and SW4 are turned on, while when the block enable signal BLKEN is at L level, the switches SW3 and SW4 are turned off. (2) A bias voltage generator 102B is provided instead of the bias voltage generator 102. Here, the power supply voltage VDD is grounded via a constant current source CI11 and MOS transistor Q8.

[0026] In the comparative example 2 configured as described above, the bias voltage VNBIAS is constantly applied to the gates of the MOS transistors Q5 and Q7, and the current path is cut off to reduce power consumption so that the device can start operating immediately after startup. However, while this allows for both a reduction in circuit current and a countermeasure for startup time, it is not possible to reduce the reference current IREF.

[0027] In the following, embodiments of the present invention will be described with respect to a bias voltage generating circuit that can solve these problems, and an electronic circuit that includes the bias voltage generating circuit.

[0028] 1 is a circuit diagram showing an example of the configuration of a comparator circuit 1 according to embodiment 1. Also, FIG. 2 is a timing chart of each signal showing the operation of the comparator circuit 1 of FIG.

[0029] In FIG. 1, the comparator circuit 1 includes a comparator section 11 and a bias voltage generating section 12. The comparator section 11 is configured with a differential amplifier and an inverter INV1, and further includes switches SW3 and SW4 compared to the comparator section 101 of FIG. 17. The differential amplifier includes MOS transistors Q1 to Q7. The connection point between the sources of MOS transistors Q3 and Q4 is grounded via switch SW3 and MOS transistor Q5. The drain of MOS transistor Q6 is grounded via switch SW4 and MOS transistor Q7.

[0030] In the comparator section 11, MOS transistors Q1, Q2, and Q6 are P-channel MOS transistors, and MOS transistors Q3, Q4, Q5, and Q7 are N-channel MOS transistors. The comparator circuit 1 has a non-inverting input terminal T1, an inverting input terminal T2, a block enable signal input terminal T3, and a comparison result signal output terminal T4. During operation of the comparator section 11, a tail current Itail flows through the MOS transistor Q5. The output voltage of the differential amplifier is output from the connection point of the drains of the MOS transistors Q6 and Q7 via an inverter INV1 to the comparison result signal output terminal T4.

[0031] In the bias voltage generating section 12, the power supply voltage VDD is connected to the sources of the MOS transistors Q1, Q2, and Q6 of the comparator section 11, and is also grounded via a constant current source CI21 that supplies a first reference current IREFL, switches SW1 and SW2, and a MOS transistor Q9. The power supply voltage VDD is also grounded via a constant current source CI22 that supplies a second reference current IREFS (<IREFL), and MOS transistors Q8 and Q9. The junction of switches SW1 and SW2 generates a bias voltage VNBIAS, which is applied to the drain and gate of MOS transistor Q8, the gate of MOS transistor Q9, and the gates of MOS transistors Q5 and Q7. The sources of MOS transistors Q9, Q5, and Q7 are grounded.

[0032] A block enable signal BLKEN, which is an operation mode switching control signal input to the block enable signal input terminal T3, is input to the control terminal of the switch SW1 and the control terminal of the switch SW2. When an H-level block enable signal BLKEN is input to the block enable signal input terminal T3, the switches SW1 and SW2 are turned on. The MOS transistors Q5, Q7, and Q9 form a current mirror circuit, in which a current flows through the MOS transistor Q9 in accordance with the bias voltage VNBIAS, and a current proportional to this current flows through the MOS transistors Q5 and Q7. On the other hand, when an L-level block enable signal BLKEN is input to the block enable signal input terminal T3, the switches SW1 and SW2 are turned off. The gates of the MOS transistors Q1 to Q9 function as control terminals.

[0033] In the comparator circuit 1 configured as described above, as shown in FIG. 2, at time t11, the block enable signal BLKEN is switched from low to high, switching the operating mode from sleep mode to active mode. Here, (1) in sleep mode (when the comparator circuit 1 is not operating), switches SW1 and SW2 are both off, and only constant current source CI22 flows a constant current IREFS through the series circuit of MOS transistors Q8 and Q9. This generates a bias voltage VBIAS corresponding to the constant current IREFS (Itailpe = 0). (2) in active mode (when the comparator circuit 1 is operating), switches SW1 and SW2 are both on, and constant current sources CI21 and CI22 flow constant currents IREFL and IREFS, respectively, through MOS transistor Q9. As a result, a bias voltage VBIAS corresponding to the constant current (IREFL+IREFS) is generated, and a tail current Itail corresponding to the constant current (IREFL+IREFS) flows through the MOS transistor Q5.

[0034] That is, by switching the size of the MOS transistor on the diode-connected side (gate and drain connected) of the current mirror circuit formed by MOS transistors Q8, Q9, Q5, and Q7, the bias voltage VBIAS generated by the constant current IREFS with reduced current in sleep mode is combined with the bias voltage VBIAS generated by the constant current IREFL+IREFS that is originally intended to flow in active mode, and a tail current Itail corresponding to the sum of the two constant currents IREFL and IREFS can be caused to flow immediately at time t11.

[0035] 3 is a diagram showing a comparison of the operation of the comparator circuit 100 according to the first comparative example with that of the comparator circuit 1 according to the embodiment, and is a timing chart of each signal when the bias voltage VNBIAS has risen sufficiently to a predetermined voltage at the time of signal detection. Also, FIG. 4 is a diagram showing a comparison of the operation of the comparator circuit 100 according to the first comparative example with that of the comparator circuit 1 according to the embodiment, and is a timing chart of each signal when the bias voltage VNBIAS is in the middle of rising sufficiently to the predetermined voltage at the time of signal detection.

[0036] As is clear from FIGS. 3 and 4 , in Comparative Example 1, a difference occurs in the detection delay time between when the bias voltage VBIAS is fully raised ( FIG. 3 ) and when it is in the middle of rising ( FIG. 4 ). That is, Ta1 ≠ Tb1. In contrast, in Embodiment 1, a predetermined tail current Itail can be caused to flow immediately after the block enable signal BLKEN rises from L level to H level (time t11). That is, no difference occurs in the detection delay time between these two cases, and Ta2 = Tb2. Furthermore, the current consumption ICe of Embodiment 1 during sleep mode is smaller than the current consumption ICc of Comparative Example 1. As described above, Embodiment 1 has the unique effects described above compared to the comparative examples.

[0037] As described above, according to the first embodiment, the desired comparison operation can be started immediately after switching to the increased current consumption in accordance with the block enable signal BLKEN, which is the operation mode switching control signal.

[0038] (Modification 1) Fig. 5 is a circuit diagram showing an example of the configuration of a bias voltage generating unit 12A according to Modification 1. The bias voltage generating unit 12A in Fig. 5 differs from the bias voltage generating unit 12 in Fig. 1 in the following respects: (1) The gates and drains of both MOS transistors Q8 and Q9 are diode-connected. The comparator unit 11 in Fig. 1 is used.

[0039] The comparator circuit having the bias voltage generating section 12A configured as above operates in the same manner as the comparator circuit 1 of the first embodiment, except for the operational differences in the configuration.

[0040] (Modification 2) FIG. 6 is a circuit diagram showing an example of the configuration of a bias voltage generating unit 12B according to Modification 2. The bias voltage generating unit 12B of FIG. 6 differs from the bias voltage generating unit 12 of FIG. 1 in the following respects: (1) The power supply voltage VDD is grounded via a constant current source CI21 that supplies a constant current IREFL, switches SW1 and SW2, and a MOS transistor Q9a having a threshold value VthS. (2) The power supply voltage VDD is grounded via a constant current source CI22 that supplies a constant current IREFS (<IREFL), the junction of SW1 and SW2, switch SW5, and a MOS transistor Q9b having a threshold value VthL (>VthS). The junction of SW1 and SW2 is connected to the gates of the MOS transistors Q9a and Q9b. (3) The block enable signal BLKEN is applied to the control terminals of the switches SW1 and SW2, and is also applied to the control terminal of the switch SW5 via the inverter INV3, using the comparator unit 11 in FIG.

[0041] In the bias voltage generating unit 12B configured as described above, when an L-level block enable signal BLKEN is input, the switch SW5 is turned on and the switches SW1 and SW2 are turned off. When an H-level block enable signal BLKEN is input, the switch SW5 is turned off and the switches SW1 and SW2 are turned on.

[0042] The comparator circuit having the bias voltage generating section 12B configured as above operates in the same manner as the comparator circuit 1 of the first embodiment, except for the operational differences in the configuration.

[0043] (Modification 3) Fig. 7 is a circuit diagram showing an example of the configuration of a bias voltage generating unit 12C according to Modification 3. The bias voltage generating unit 12C of Fig. 7 differs from the bias voltage generating unit 12 of Fig. 1 in the following respects: (1) A resistor R1 is provided instead of the MOS transistor Q8. Note that the comparator unit 11 of Fig. 1 is used.

[0044] The comparator circuit having the bias voltage generating section 12C configured as above operates in the same manner as the comparator circuit 1 of the first embodiment, except for the operational differences in the configuration.

[0045] (Modification 4) Fig. 8 is a circuit diagram showing an example of the configuration of a bias voltage generating unit 12D according to Modification 4. The bias voltage generating unit 12D of Fig. 8 differs from the bias voltage generating unit 12A of Fig. 5 in the following respects: (1) A resistor R1 is provided instead of the MOS transistor Q8. Note that the comparator unit 11 of Fig. 1 is used.

[0046] The comparator circuit having the bias voltage generating section 12D configured as above operates in the same manner as the comparator circuit of the first modified example, except for the operational differences in the configuration.

[0047] (Modification 5) Fig. 9 is a circuit diagram showing an example of the configuration of a bias voltage generating unit 12E according to Modification 5. The bias voltage generating unit 12E of Fig. 9 differs from the bias voltage generating unit 12C of Fig. 7 in the following respects: (1) A diode D1 is provided instead of the resistor R1. Here, the anode of the diode D1 is connected to the constant current source CI22, and the cathode thereof is connected to the drain and gate of the MOS transistor Q9. Note that the comparator unit 11 of Fig. 1 is used.

[0048] The comparator circuit having the bias voltage generating section 12E configured as above operates in the same manner as the comparator circuit of the third modified example, except for the operational differences in the configuration.

[0049] (Modification 6) Fig. 10 is a circuit diagram showing an example of the configuration of a bias voltage generating unit 12F according to Modification 6. The bias voltage generating unit 12F of Fig. 10 differs from the bias voltage generating unit 12D of Fig. 8 in the following respects: (1) A diode D1 is provided instead of the resistor R1. Here, the anode of the diode D1 is connected to the constant current source CI22, and the cathode thereof is connected to the drain and gate of the MOS transistor Q9. Note that the comparator unit 11 of Fig. 1 is used.

[0050] The comparator circuit having the bias voltage generating section 12F configured as above operates in the same manner as the comparator circuit of the fourth modification, except for the operational differences in the configuration.

[0051] (Variation 7) Figure 11 is a circuit diagram showing an example of the configuration of a bias voltage generating unit 12G according to Variation 7. The bias voltage generating unit 12G of Figure 11 differs from the bias voltage generating unit 12A of Figure 5 in the following respects: (1) A diode D2 is provided instead of the MOS transistor Q9. Here, the anode of the diode D2 is connected to the source of the MOS transistor Q8, and its cathode is grounded. (2) A switch SW2 is connected across the diode D2, and the ends of the diode D2 are short-circuited or open-circuited based on the block enable signal BLKEN. Note that the comparator unit 11 of Figure 1 is used.

[0052] The comparator circuit having the bias voltage generating section 12G configured as above operates in the same manner as the comparator circuit of the first modified example, except for the operational differences in the configuration.

[0053] The MOS transistors, resistors, and diodes used in the first embodiment and the first to seventh modifications can also be arranged on the ground side of the MOS transistor that serves as the reference for the current mirror circuit.

[0054] Second Embodiment FIG. 12 is a circuit diagram showing an example of the configuration of a source follower circuit 3 according to a second embodiment.

[0055] 12, the source follower circuit 3 has an input terminal T11, an output terminal T12, and a block enable signal input terminal T3, and is configured with the bias voltage generating unit 12 of Fig. 1, a MOS transistor Q4, a switch SW5, and a MOS transistor Q10. Here, the MOS transistors Q4 and Q10 are configured as N-channel MOS transistors.

[0056] The power supply voltage VDD is grounded via a MOS transistor Q4, a switch SW5, and a MOS transistor Q10. A bias voltage VBIAS is applied to the gate of the MOS transistor Q10. An input voltage VIN is input to an input terminal T11, and an output voltage Vout, which is a buffered version of the input voltage VIN, is output from an output terminal T12 when the source follower circuit 3 is in operation.

[0057] In the source follower circuit 3 configured as described above, when an L-level block enable signal BLKEN is applied, the switches SW1 and SW2 are turned off and the constant current source CI22 in the bias voltage generating unit 12 operates. When an H-level block enable signal BLKEN is applied, the constant current sources CI21 and CI22 operate, the constant current increases from IREFS to (IREFS+IREFL), and the increased bias voltage VBIAS corresponding to this current is applied to the gate of the MOS transistor Q10.

[0058] In the source follower circuit 3 configured as above, the block enable signal BLKEN is switched from L level to H level, and the operation mode is switched from sleep mode to active mode. At this time, as described above, the constant current sources CI21 and CI22 operate, the constant current increases from IREFS to (IREFS+IREFL), and the increased bias voltage VBIAS corresponding to this current is applied to the gate of the MOS transistor Q10, allowing the source follower circuit 3 to immediately enter an operating state.

[0059] As described above, according to the second embodiment, the desired buffering operation can be started immediately after switching to the increased current consumption in accordance with the block enable signal BLKEN, which is the operation mode switching control signal.

[0060] The bias voltage generating section of FIG. 12 may be configured with the bias voltage generating sections 12A to 12G of the first to seventh modifications of FIGS. 5 to 11 instead of the bias voltage generating section of FIG.

[0061] 13 is a circuit diagram showing an example of the configuration of a voltage generating circuit 4 according to a third embodiment. The voltage generating circuit 4 of FIG. 13 differs from the source follower circuit 3 of FIG. 12 in the following respects: (1) A resistor R2 is provided instead of the MOS transistor Q4.

[0062] The voltage generating circuit 4 configured as above operates when the block enable signal BLKEN at H level is input, and can generate and output from the output terminal T12 a predetermined voltage determined by the resistor R2 and the MOS transistor Q10.

[0063] As described above, according to the third embodiment, a desired voltage generating operation can be started immediately after switching to the increased current consumption in accordance with the block enable signal BLKEN, which is an operation mode switching control signal.

[0064] The voltage generating circuit 4 of FIG. 13 may be configured with the bias voltage generating units 12A to 12G of the first to seventh modifications of FIGS. 5 to 11, instead of the bias voltage generating unit of FIG.

[0065] 14 is a circuit diagram showing an example of the configuration of a time constant circuit 5 according to a fourth embodiment. The time constant circuit 5 in FIG. 14 differs from the voltage generating circuit 4 in FIG. 13 in the following respects: (1) A capacitor C1 is provided instead of the resistor R2.

[0066] The time constant circuit 5 configured as described above operates when an H-level block enable signal BLKEN is input, and can generate and output from the output terminal T12 a voltage that decreases with a predetermined time constant determined by the current values ​​of the capacitor C1 and the MOS transistor Q10.

[0067] As described above, according to the fourth embodiment, a voltage generating operation having a desired time constant can be started immediately after switching to an increased current consumption in accordance with the block enable signal BLKEN, which is an operation mode switching control signal.

[0068] The time constant circuit 5 in FIG. 14 may be configured with the bias voltage generating sections 12A to 12G of the first to seventh modifications in FIGS. 5 to 11, instead of the bias voltage generating section in FIG.

[0069] Fifth Embodiment Fig. 15 is a circuit diagram showing an example of the configuration of a comparator circuit 1A according to a fifth embodiment. The comparator circuit 1A of Fig. 15 differs from the comparator circuit 1 of Fig. 1 in the following respects: (1) MOS transistors Q11 to Q17 are provided instead of MOS transistors Q1 to Q7. Here, MOS transistors Q13 to Q15 and Q17 are P-channel MOS transistors, and MOS transistors Q11 to Q12 and Q16 are N-channel MOS transistors. (2) Switches SW1 to SW4 are provided instead of switches SW11 to SW14.

[0070] As described above, by replacing some of the N-channel MOS transistors with P-channel MOS transistors, the present invention can be used not only as a current source on the ground side but also as a current source on the power supply side. This also applies to the second to fourth embodiments.

[0071] The comparator circuit 1A configured as above operates when the block enable signal BLKEN at H level is input, and can pass a current corresponding to IREFL+IREFS through the MOS transistors Q15 and Q17.

[0072] As described above, according to the fifth embodiment, the desired comparison operation can be started immediately after switching to the increased current consumption in accordance with the block enable signal BLKEN, which is the operation mode switching control signal.

[0073] The bias voltage generating section of FIG. 15 may be configured using the circuits of the first to seventh modifications of FIGS. 5 to 11 instead of the circuit of FIG.

[0074] Sixth Embodiment Figure 16 is a circuit diagram showing an example of the configuration of a comparator circuit 1B according to a sixth embodiment. The comparator circuit 1B of Figure 16 differs from the comparator circuit 1 of Figure 1 in the following respects: (1) A bias voltage generating unit 12H is provided, in which a switch SW11 is inserted between a constant current source CI22 and the drain of a MOS transistor Q8. (2) A block enable signal BLKEN is further input to the control terminal of the switch SW11 via an inverter INV11. That is, the bias voltage generating unit 12H generates a predetermined bias voltage based on a second constant current when the electronic circuit is not operating, and generates another predetermined bias voltage based on the first constant current when the electronic circuit is operating.

[0075] In the comparator circuit 1B configured as above, when the block enable signal BLKEN is at L level, the switch SW11 turns on, allowing a current according to IREFS to flow through the MOS transistors Q8 and Q9.

[0076] As described above, according to the sixth embodiment, the desired comparison operation can be started immediately after switching to the increased current consumption in accordance with the block enable signal BLKEN, which is the operation mode switching control signal.

[0077] (Other Modifications) In the above embodiments and modifications, a comparator circuit, a source follower circuit, a voltage generation circuit, and a time constant circuit are configured, but the present invention is not limited to these, and various other electronic circuits such as a differential amplifier circuit may also be configured.

[0078] As described above in detail, the bias voltage generating circuit or electronic circuit according to the present invention keeps the gate voltage of the bias transistor constant even when the amount of current in the current source is reduced in accordance with the operation mode switching control signal in order to reduce current consumption, so that the desired operation can be started immediately after the operation mode switching control signal is switched.

[0079] 1, 1A, 1B Comparator circuit 3 Source follower circuit 4 Voltage generation circuit 5 Time constant circuit 11 Comparator section 12, 12A to 12H Bias voltage generation section 100, 100A, 100B Comparator circuit 101, 101A, 101B Comparator section 102, 102B Bias voltage generation section C1 Capacitor CI1 to CI32 Constant current source D1, D2 Diode INV1 to INV11 Inverter Q1 to Q17, Q9a, Q9b MOS transistor R1 to R2 Resistor SW1 to SW14 Switch T1 to T12 Terminal

Claims

1. a first constant current source that supplies a first constant current; a second constant current source that supplies a second constant current smaller than the first constant current; A bias voltage generating circuit including at least one first MOS transistor and a bias voltage generating unit that generates a predetermined bias voltage based on the second constant current or the first and second constant currents, the bias voltage generating circuit being for an electronic circuit to which a current is supplied by a current mirror circuit formed of the first MOS transistor and at least one second MOS transistor, The bias voltage generating circuit, based on an operation mode switching control signal, (1) When the electronic circuit is not in operation, the bias voltage generating unit generates a predetermined bias voltage based on the second constant current; (2) during operation of the electronic circuit, the bias voltage generating unit generates a predetermined bias voltage based on the first and second constant currents or the first constant current; A bias voltage generating circuit comprising:

2. the at least one first MOS transistor includes two MOS transistors connected in series with each other, and the control terminals of the two MOS transistors are connected with each other; 2. The bias voltage generating circuit according to claim 1.

3. the at least one first MOS transistor includes two MOS transistors connected in series with each other, and the two MOS transistors are each diode-connected; 2. The bias voltage generating circuit according to claim 1.

4. the at least one first MOS transistor includes two MOS transistors connected in parallel to each other and having different threshold values; 2. The bias voltage generating circuit according to claim 1.

5. the at least one first MOS transistor includes a third MOS transistor connected in series with a first resistor connected to the second constant current source; a control terminal of the third MOS transistor is connected to a connection point between the second constant current source and the resistor; 2. The bias voltage generating circuit according to claim 1.

6. the at least one first MOS transistor includes a third MOS transistor connected in series with a first resistor connected to the second constant current source; the third MOS transistor is diode-connected; 2. The bias voltage generating circuit according to claim 1.

7. the at least one first MOS transistor includes a third MOS transistor connected in series with a first diode connected to the second constant current source; the third MOS transistor is diode-connected; 2. The bias voltage generating circuit according to claim 1.

8. the at least one first MOS transistor is configured by connecting in series a third MOS transistor connected to the second constant current source and a second diode; the third MOS transistor is diode-connected; 2. The bias voltage generating circuit according to claim 1.

9. a first constant current source that supplies a first constant current; a second constant current source that supplies a second constant current smaller than the first constant current; An electronic circuit having a bias voltage generation circuit including at least one first MOS transistor and a bias voltage generation unit that generates a predetermined bias voltage based on the second constant current or the first and second constant currents, a current is supplied to the bias voltage generating circuit by a current mirror circuit formed of the first MOS transistor and at least one second MOS transistor; The bias voltage generating circuit, based on an operation mode switching control signal, (1) When the electronic circuit is not in operation, the bias voltage generating unit generates a predetermined bias voltage based on the second constant current; (2) during operation of the electronic circuit, the bias voltage generating unit generates a predetermined bias voltage based on the first and second constant currents or the first constant current; The electronic circuit that is composed of.

10. the at least one first MOS transistor includes two MOS transistors connected in series with each other, and the control terminals of the two MOS transistors are connected with each other; 10. The electronic circuit of claim 9.

11. the at least one first MOS transistor includes two MOS transistors connected in series with each other, and the two MOS transistors are each diode-connected; 10. The electronic circuit of claim 9.

12. the at least one first MOS transistor includes two MOS transistors connected in parallel to each other and having different threshold values; 10. The electronic circuit of claim 9.

13. the at least one first MOS transistor includes a third MOS transistor connected in series with a first resistor connected to the second constant current source; a control terminal of the third MOS transistor is connected to a connection point between the second constant current source and the resistor; 10. The electronic circuit of claim 9.

14. the at least one first MOS transistor includes a third MOS transistor connected in series with a first resistor connected to the second constant current source; the third MOS transistor is diode-connected; 10. The electronic circuit of claim 9.

15. the at least one first MOS transistor includes a third MOS transistor connected in series with a first diode connected to the second constant current source; the third MOS transistor is diode-connected; 10. The electronic circuit of claim 9.

16. the at least one first MOS transistor is configured by connecting in series a third MOS transistor connected to the second constant current source and a second diode; the third MOS transistor is diode-connected; 10. The electronic circuit of claim 9.

17. The electronic circuit is a comparator circuit, a source follower circuit, a voltage generation circuit, a time constant circuit, or a differential amplifier circuit. An electronic circuit according to any one of claims 9 to 16.