Semiconductor light-emitting element and semiconductor light-emitting device
Patent Information
- Application Number
- JP2024521672
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Filing Date
- 2024-10-07
- Publication Date
- 2025-01-30
AI Technical Summary
Conventional semiconductor light emitting devices face issues with Sn atom diffusion affecting ohmic contact between the p-type semiconductor layer and the lower electrode, leading to impaired contact and reduced reliability.
A semiconductor light emitting device design featuring a contact electrode with a barrier layer that covers the top and side surfaces, suppressing Sn atom diffusion, and a current blocking layer that continuously covers the ridge and side surfaces to maintain ohmic contact and prevent Sn diffusion into the contact electrode.
The solution effectively suppresses Sn atom diffusion, maintaining reliable ohmic contact and reducing the formation of slit-like voids, thereby enhancing the long-term reliability and reducing the threshold current for laser oscillation.
Abstract
Description
Semiconductor light emitting element and semiconductor light emitting device
[0001] The present disclosure relates to a semiconductor light emitting element and a semiconductor light emitting device.
[0002] Conventionally, semiconductor light-emitting elements such as semiconductor laser elements have been known as compact, high-power light sources (see, for example, Patent Document 1). The semiconductor light-emitting element described in Patent Document 1 has a ridge formed in a p-type semiconductor layer, a first electrode disposed on the ridge, and a second electrode made of Au covering the first electrode. The first electrode includes a lower electrode disposed on the ridge and an upper electrode disposed on the lower electrode. The lower electrode is a contact electrode that makes ohmic contact with the p-type semiconductor layer. The second electrode is bonded to a mounting substrate using AuSn solder or the like. During this bonding, Sn atoms contained in the AuSn solder diffuse into the second electrode, but the upper electrode made of Pt or the like prevents the Sn from diffusing into the lower electrode. This is intended to prevent the ohmic contact between the lower electrode and the p-type semiconductor layer from being impaired due to the diffusion of Sn atoms into the lower electrode.
[0003] International Publication No. 2020 / 110783
[0004] However, even in the configuration described in Patent Document 1, for example, Sn atoms may diffuse from between the p-type semiconductor layer and the lower electrode to the lower electrode, which may impair the ohmic contact between the lower electrode and the p-type semiconductor layer.
[0005] The present disclosure is intended to solve such problems, and has an object to provide a semiconductor light emitting device and the like that can suppress the diffusion of Sn atoms into a contact electrode.
[0006] In order to solve the above problems, one aspect of the semiconductor light-emitting device according to the present disclosure is a semiconductor light-emitting device that emits light, comprising: a first semiconductor layer of a first conductivity type; an active layer disposed above the first semiconductor layer; a second semiconductor layer of a second conductivity type different from the first conductivity type, disposed above the active layer; an electrically insulating current blocking layer disposed above the second semiconductor layer; a contact electrode disposed above the second semiconductor layer and in contact with the second semiconductor layer; and a conductive barrier layer that covers an upper surface and a side surface of the contact electrode and suppresses diffusion of Sn atoms into the contact electrode, wherein the second semiconductor layer has a bottom surface that is a part of the upper surface of the second semiconductor layer, and a ridge that protrudes upward from the bottom surface and extends in the propagation direction of the light, the contact electrode is disposed on the upper surface of the ridge, and in a cross section perpendicular to the propagation direction of the light, the width of the contact electrode is smaller than the width of the upper surface of the ridge, and the current blocking layer continuously covers from an end of the barrier layer in the width direction of the ridge to a side surface of the ridge.
[0007] In order to solve the above problem, one aspect of the semiconductor light emitting device according to the present disclosure comprises the above semiconductor light emitting element, a submount on which the semiconductor light emitting element is mounted, and AuSn solder that joins the semiconductor light emitting element and the submount, and the AuSn solder is electrically connected to the contact electrode.
[0008] According to the present disclosure, it is possible to provide a semiconductor light emitting device and the like that can suppress the diffusion of Sn atoms into a contact electrode.
[0009] 1 is a schematic top view showing the overall configuration of a semiconductor light emitting device according to a first embodiment. FIG. 2 is a schematic cross-sectional view showing the overall configuration of a semiconductor light emitting device according to a first embodiment. FIG. 3 is an enlarged view of the vicinity of a ridge in the cross-sectional view shown in FIG. 2. FIG. 4 is an enlarged cross-sectional view of the vicinity of a ridge of a semiconductor light emitting device according to a comparative example. FIG. 5 is a schematic cross-sectional view showing the configuration of a first semiconductor layer according to the first embodiment. FIG. 6 is a schematic cross-sectional view showing the configuration of an active layer according to the first embodiment. FIG. 7 is a schematic cross-sectional view showing the configuration of a second semiconductor layer according to the first embodiment. FIG. 8 is an enlarged view of the vicinity of a ridge of a semiconductor light emitting device according to a comparative example. FIG. 9 is a graph showing the relationship between the distance in the X-axis direction between the end of a contact electrode in the X-axis direction and the lower end of the ridge according to the first embodiment, and the threshold current of laser oscillation of the semiconductor light emitting device. FIG. 10 is a diagram showing the current diffusion in the ridge when L1 / L2<0.7. FIG. 11 is a diagram showing the current diffusion in the ridge when L1 / L2=1.0. FIG. 12 is a diagram showing the current diffusion in the ridge when L1 / L2>2.2. FIG. 13 is a diagram showing the current diffusion in the ridge when L1 / L2>2.2. FIG. 1 is a schematic cross-sectional view showing a second step of the method for manufacturing a semiconductor light-emitting device according to the first embodiment. FIG. 2 is a schematic cross-sectional view showing a contact electrode formation step by normal vapor deposition. FIG. 3 is a schematic cross-sectional view showing a contact electrode formation step by planetary vapor deposition. FIG. 4 is a schematic cross-sectional view showing a third step of the method for manufacturing a semiconductor light-emitting device according to the first embodiment. FIG. 5 is a schematic cross-sectional view showing a fourth step of the method for manufacturing a semiconductor light-emitting device according to the first embodiment. FIG. 6 is a schematic cross-sectional view showing a sixth step of the method for manufacturing a semiconductor light-emitting device according to the first embodiment. FIG. 7 is a schematic cross-sectional view showing a seventh step of the method for manufacturing a semiconductor light-emitting device according to the first embodiment. FIG. 8 is a schematic cross-sectional view showing an eighth step of the method for manufacturing a semiconductor light-emitting device according to the first embodiment. FIG. 9 is a schematic cross-sectional view showing a ninth step of the method for manufacturing a semiconductor light-emitting device according to the first embodiment. FIG. 10 is a schematic cross-sectional view showing a tenth step of the method for manufacturing a semiconductor light-emitting device according to the first embodiment.1 is a schematic top view showing the overall configuration of a semiconductor light emitting device according to a second embodiment. FIG 2 is an enlarged view showing the configuration of a ridge and its vicinity of the semiconductor light emitting device according to a second embodiment.
[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that each of the embodiments described below represents a specific example of the present disclosure. Therefore, the numerical values, shapes, materials, components, and the arrangement and connection of the components shown in the following embodiments are merely examples and are not intended to limit the present disclosure.
[0011] Furthermore, each figure is a schematic diagram and is not necessarily an exact representation. Therefore, the scales and the like do not necessarily match in each figure. In each figure, the same reference numerals are used to denote substantially the same components, and redundant explanations will be omitted or simplified.
[0012] In this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are used not only when two components are arranged with a gap between them and another component is present between the two components, but also when two components are arranged in contact with each other.
[0013] First Embodiment A semiconductor light emitting element and a semiconductor light emitting device according to a first embodiment will be described.
[0014] [1-1. Overall Configuration] First, the overall configuration of the semiconductor light-emitting element and semiconductor light-emitting device according to this embodiment will be described with reference to FIGS. 1 to 4. FIG. 1 is a schematic top view showing the overall configuration of a semiconductor light-emitting element 10 according to this embodiment. FIG. 2 is a schematic cross-sectional view showing the overall configuration of the semiconductor light-emitting element 10 according to this embodiment. FIG. 2 shows a cross-section taken along line II-II in FIG. 1. FIG. 3A is an enlarged view of the vicinity of the ridge 34r in the cross-section shown in FIG. 2. FIG. 3A also shows an enlarged view of the interior of the dashed frame III in FIG. 2. FIG. 4 is a schematic cross-sectional view of a semiconductor light-emitting device 11 according to this embodiment. FIG. 4 shows a cross-section corresponding to line II-II in FIG. 1. Note that each figure shows an X-axis, a Y-axis, and a Z-axis, which are orthogonal to one another. The X-axis, the Y-axis, and the Z-axis represent a right-handed Cartesian coordinate system. The stacking direction of the semiconductor light-emitting element 10 is parallel to the Z-axis, and the main emission direction of light (laser light) is parallel to the Y-axis.
[0015] The semiconductor light-emitting element 10 is an element that emits light. The semiconductor light-emitting element 10 emits light from a facet 10F (see FIG. 1 ) perpendicular to the stacking direction of each semiconductor layer (i.e., the Z-axis direction). In this embodiment, the semiconductor light-emitting element 10 is a semiconductor laser element having two facets 10F and 10R that form a resonator. The facet 10F is a front facet that emits laser light, and the facet 10R is a rear facet that has a higher reflectivity than the facet 10F. The semiconductor light-emitting element 10 also has a waveguide formed between the facets 10F and 10R. In this embodiment, the reflectivities of the facets 10F and 10R are 16% and 95%, respectively. The resonator length of the semiconductor light-emitting element 10 according to this embodiment (i.e., the distance between the facets 10F and 10R) is approximately 1200 μm. The semiconductor light-emitting element 10 emits light having a peak wavelength in the 405 nm band, for example. The semiconductor light emitting element 10 may emit light having a peak wavelength outside the 405 nm band.
[0016] 2, the semiconductor light emitting element 10 includes a substrate 31, a first semiconductor layer 32, an active layer 33, a second semiconductor layer 34, a current blocking layer 21, a contact electrode 22, a barrier layer 23, a cover electrode 24, and an n-side electrode 28. Note that other semiconductor layers may be inserted between the above-mentioned semiconductor layers of the semiconductor light emitting element 10. For example, a buffer layer or the like may be inserted between the substrate 31 and the first semiconductor layer 32.
[0017] The substrate 31 is a plate-like member that serves as a base for the semiconductor light-emitting device 10. In this embodiment, the substrate 31 is an n-type GaN substrate. The thickness of the substrate 31 is, for example, 50 μm or more and 150 μm or less. The substrate 31 is doped with a group IV n-type impurity. The group IV n-type impurity is, for example, Si. The group IV n-type impurity contained in the substrate 31 may be Ge or the like. The impurity concentration (specifically, Si concentration) of the substrate 31 is, for example, 1.4×10 １８ cm －３ is.
[0018] The first semiconductor layer 32 is a semiconductor layer of a first conductivity type disposed above the substrate 31. In this embodiment, the first conductivity type is n-type. An example of the configuration of the first semiconductor layer 32 will be described below with reference to FIG. 5. FIG. 5 is a schematic cross-sectional view showing the configuration of the first semiconductor layer 32 according to this embodiment. Note that FIG. 5 shows an enlarged view of a portion of the cross section taken along line II-II in FIG. 1. The first semiconductor layer 32 includes, for example, an n-type cladding layer 32a made of n-type AlGaN and an n-side guide layer 32b made of n-type GaN.
[0019] The n-type cladding layer 32a is provided between the substrate 31 and the n-side guide layer 32b in contact with each other. The n-type cladding layer 32a is, for example, an AlGaN layer with a film thickness of 3 μm. The Al composition ratio is, for example, 2.6%. The n-type cladding layer 32a is doped with Si, which is an example of a Group IV n-type impurity. The impurity concentration of the n-type cladding layer 32a is lower than the impurity concentration of the substrate 31, for example, 5.0×10 １７ cm －３ is.
[0020] The n-side guide layer 32b is provided between the n-type cladding layer 32a and the active layer 33 in contact with each other. The n-side guide layer 32b is a GaN layer with a film thickness of 127 nm. The n-side guide layer 32b is doped with Si, which is an example of a Group IV n-type impurity. The impurity concentration of the n-side guide layer is the same as the impurity concentration of the n-type cladding layer and is lower than the impurity concentration of the substrate 31, for example, 5.0 × 10 １７ cm －３ is.
[0021] The active layer 33 shown in FIG. 2 is disposed above the first semiconductor layer 32 and is a light-emitting layer that generates light. In this embodiment, the active layer 33 has a multiple quantum well structure. Specifically, the active layer 33 has multiple well layers and multiple barrier layers that are alternately stacked one on top of the other. An example of the configuration of the active layer 33 will be described below with reference to FIG. 6. FIG. 6 is a schematic cross-sectional view showing the configuration of the active layer 33 according to this embodiment. Note that FIG. 6 also shows an enlarged view of a portion of the cross section taken along line II-II in FIG. 1. As shown in FIG. 6, the active layer 33 has two well layers 33b and 33d and three barrier layers 33a, 33c, and 33e. Each of the two well layers 33b and 33d is an undoped InGaN layer with a thickness of 7.5 nm. The In composition ratio of the well layers 33b and 33d is adjusted so that the peak wavelength of light is 405 nm. The three barrier layers 33 a, 33 c, and 33 e are all undoped InGaN layers. The In composition ratio of the three barrier layers 33 a, 33 c, and 33 e is, for example, 0.8%. The film thicknesses of the three barrier layers 33 a, 33 c, and 33 e are, for example, 92 nm, 19 nm, and 18 nm, respectively.
[0022] The second semiconductor layer 34 shown in FIG. 2 is disposed above the active layer 33 and is a semiconductor layer of a second conductivity type different from the first conductivity type. In this embodiment, the second conductivity type is p-type. As shown in FIGS. 1 and 2 , the second semiconductor layer 34 has a bottom surface 34u, which is a part of the upper surface of the second semiconductor layer 34, and a ridge 34r, which protrudes upward from the bottom surface 34u and extends in the light propagation direction (i.e., the Y-axis direction). Two grooves 34t extending in the light propagation direction are formed in the second semiconductor layer 34. The ridge 34r is formed between the two grooves 34t. The bottom of the groove 34t corresponds to the bottom surface 34u. The ridge 34r may have a forward mesa shape as shown in FIG. 2 . That is, the width of the ridge 34r in the X-axis direction may increase as it approaches the active layer 33. The ridge 34r functions as a current confinement structure (i.e., a current confinement structure) and also functions as a waveguide for laser light. A wing portion 34w is formed on the outer side of the groove 34t in the X-axis direction. The wing portion 34w protrudes upward from the bottom surface of the groove 34t. The position of the upper surface of the wing portion 34w in the stacking direction is equal to the position of the upper surface of the ridge 34r in the stacking direction. Note that, although the wing portion 34w is formed in this embodiment, the wing portion 34w does not have to be formed. In other words, a structure may be such that only the ridge 34r protrudes upward from the upper surface of the second semiconductor layer 34. The height of the ridge 34r from the bottom surface 34u is, for example, 0.68 μm.
[0023] An example of the configuration of the second semiconductor layer 34 will be described below with reference to Fig. 7. Fig. 7 is a schematic cross-sectional view showing the configuration of the second semiconductor layer 34 according to this embodiment. Note that Fig. 7 shows an enlarged view of a portion of the cross section taken along line II-II in Fig. 1. As shown in Fig. 7, the second semiconductor layer 34 includes, for example, a p-side guide layer 34a, an electron blocking layer 34b, a p-type cladding layer 34c, and a p-type contact layer 34d.
[0024] The p-side guide layer 34a is provided between the active layer 33 and the electron blocking layer 34b in contact with each other. The p-side guide layer 34a has a stacked structure of, for example, a 40-nm-thick undoped InGaN layer, a 6-nm-thick undoped GaN layer, and a 3-nm-thick p-type GaN layer. The In composition ratio of the undoped InGaN layer is, for example, 0.3%. The p-type GaN layer is an example of a p-type nitride-based semiconductor layer, and is doped with Mg as a p-type impurity. The impurity concentration of the p-type GaN layer is higher than the impurity concentration of the substrate 31, for example, 1.5×10 １９ cm －３ is.
[0025] The electron blocking layer 34b blocks electrons moving from the active layer 33 to the contact electrode 22. The electron blocking layer 34b can improve the efficiency of electron injection into the active layer 33, thereby improving light emission efficiency. The electron blocking layer 34b is provided between and in contact with the p-side guide layer 34a and the p-type cladding layer 34c. The electron blocking layer 34b has, for example, a stacked structure of multiple p-type AlGaN layers. The multiple p-type AlGaN layers differ from one another in film thickness and Al composition ratio. The p-type AlGaN layer (lower layer) in contact with the p-side guide layer has a film thickness of 5 nm, and the Al composition ratio gradually increases from 4% to 36% in the direction from the p-side guide layer 34a to the p-type cladding layer 34c. The p-type AlGaN layer (upper layer) in contact with the p-type cladding layer 34c has a film thickness of 1 nm and an Al composition ratio of 36%. The two p-type AlGaN layers are doped with Mg as a p-type impurity. The impurity concentration of the p-type AlGaN layers is equal to the impurity concentration of the p-type GaN layer of the p-side guide layer, and is, for example, 1.5×10 １９ cm －３ is.
[0026] The p-type cladding layer 34c is provided between and in contact with the electron blocking layer 34b and the p-type contact layer 34d. The p-type cladding layer 34c has, for example, a stacked structure of multiple p-type AlGaN layers. The multiple p-type AlGaN layers have different thicknesses and impurity concentrations. The Al composition ratios of the multiple p-type AlGaN layers are equal to each other, for example, 2.6%. The multiple p-type AlGaN layers are doped with Mg as a p-type impurity. The p-type AlGaN layer (lower layer) in contact with the electron blocking layer 34b has a thickness of 250 nm and an impurity concentration of, for example, 2.00×10 １８ cm －３ The thickness of the p-type AlGaN layer (upper layer) in contact with the p-type contact layer is 409 nm, and the impurity concentration is higher than the impurity concentration of the p-type AlGaN layer in contact with the electron blocking layer 34 b and lower than the impurity concentration of the electron blocking layer 34 b, for example, 1.0×10 １９ cm －３ is.
[0027] The p-type contact layer 34d is provided between the p-type cladding layer 34c and the contact electrode 22 so as to be in contact with each other. The p-type contact layer 34d has, for example, a stacked structure of a plurality of p-type GaN layers. The plurality of p-type GaN layers differ from one another in film thickness and impurity concentration. The plurality of p-type GaN layers are doped with Mg as a p-type impurity. The p-type GaN layer (lower layer) in contact with the p-type cladding layer 34c has a film thickness of 50 nm and an impurity concentration higher than that of the p-type cladding layer 34c, for example, 2.0×10 １９ cm －３ The thickness of the p-type GaN layer (upper layer) in contact with the contact electrode 22 is 10 nm, and the impurity concentration is higher than the impurity concentration of the p-type GaN layer in contact with the p-type cladding layer 34c, for example, 2.0×10 ２０ cm －３ That is, the p-type GaN layer in contact with the contact electrode 22 is heavily doped with p-type impurities.
[0028] 1 to 3A is an electrically insulating layer disposed above the second semiconductor layer 34. As shown in FIG. 1, the current blocking layer 21 is formed in a region of the upper surface of the second semiconductor layer 34 excluding the opening 21a. The opening 21a is formed above the ridge 34r. In this embodiment, as shown in FIG. 3A, the current blocking layer 21 covers the bottom surface 34u of the groove 34t in the second semiconductor layer 34 and the side surface 34rs of the ridge 34r. Furthermore, the current blocking layer 21 continuously covers from the side surface 34rs of the ridge 34r to the upper surface 23t of the barrier layer 23.
[0029] In this embodiment, the current blocking layer 21 is made of SiO ２ The current blocking layer 21 is made of SiO ２ The current blocking layer 21 may be made of a material such as SOG (Spin on Glass), PSG (Phosphorus Silicon Glass), or BPSG (Boron Phosphorus Silicon Glass), or may be made of TiO ２ , Ta ２ O ５ , Al ２ O ３ , ZrO ２ , HfO ２ , CeO ２ , In ２ O ３ , Nd ２ O ５ It may be an oxide other than Si-based oxide such as SiN, Si ３ N ４ The current blocking layer 21 may be made of a nitride such as SiN or an organic material such as polyimide. ２ The same characteristics can be obtained as when using
[0030] The contact electrode 22 shown in FIGS. 1 to 4 is a conductive layer disposed above the second semiconductor layer 34 and in contact with the second semiconductor layer 34. The contact electrode 22 is an ohmic electrode that makes ohmic contact with the second semiconductor layer 34. In this embodiment, as shown in FIG. 3A, the contact electrode 22 is disposed on the upper surface 34rt of the ridge 34r (hereinafter also referred to as the ridge upper surface 34rt). In a cross section perpendicular to the light propagation direction, the width of the contact electrode 22 is smaller than the width of the upper surface 34rt of the ridge 34r. As shown in FIG. 1, the contact electrode 22 is disposed in a region of the upper surface 34rt of the ridge 34r excluding the edge and its vicinity. The contact electrode 22 is made of, for example, Pd, Ag, Ni, or Co.
[0031] The barrier layer 23 is a conductive layer that covers the upper surface 22t and the side surface 22s of the contact electrode 22 and suppresses the diffusion of Sn atoms into the contact electrode 22. The barrier layer 23 is made of, for example, Pt.
[0032] The cover electrode 24 is disposed above the current blocking layer 21 and the barrier layer 23, and is an electrode that covers at least a portion of each of the current blocking layer 21 and the barrier layer 23. In this embodiment, the cover electrode 24 is made of Au.
[0033] The semiconductor light-emitting device 11 shown in FIG. 4 is a device on which a semiconductor light-emitting element 10a is mounted. The semiconductor light-emitting device 11 includes the semiconductor light-emitting element 10a, a submount 13, and AuSn solder 12. The semiconductor light-emitting element 10a includes a cover electrode 24a instead of the cover electrode 24 of the semiconductor light-emitting element 10. The cover electrode 24a differs from the cover electrode 24 in that it contains Sn. The semiconductor light-emitting device 11 is formed by junction-down mounting (in other words, flip-chip mounting) the semiconductor light-emitting element 10 on the submount 13. The cover electrode 24 of the semiconductor light-emitting element 10 is joined to the submount 13 by the AuSn solder 12. The cover electrode 24 becomes the cover electrode 24a by containing Sn diffused from the molten AuSn solder 12.
[0034] The submount 13 is a base on which the semiconductor light emitting element 10 is mounted. The submount 13 functions as a heat sink for the semiconductor light emitting element 10. The configuration of the submount 13 is not particularly limited as long as it is a base having a main surface on which the semiconductor light emitting element 10 is mounted. In this embodiment, as shown in FIG. 4 , the submount 13 includes a metal layer 13 a and a base 13 b. The metal layer 13 a is a layer made of metal. The metal forming the metal layer 13 a is not particularly limited. The metal layer 13 a is, for example, a metal film in which Ti, Pt, and Au are stacked in this order from the base 13 b. The base 13 b is a bulk member that occupies the majority of the submount 13. In this embodiment, the base 13 b has a rectangular parallelepiped shape. The material forming the base 13 b is not particularly limited. In this embodiment, the base 13 b is a polycrystalline SiC substrate. The base 13b may be a Si or AlN substrate, and in order to further improve heat dissipation, a single crystal SiC or diamond substrate may be used.
[0035] The AuSn solder 12 is a conductive joining member that joins the semiconductor light emitting element 10 and the submount 13. The AuSn solder 12 is electrically connected to the contact electrode 22 of the semiconductor light emitting element 10. The AuSn solder 12 is melted when joining the cover electrode 24 of the semiconductor light emitting element 10 and the metal layer 13a of the submount 13. As a result, the cover electrode 24 and the AuSn solder 12 are alloyed. In this embodiment, the cover electrode 24 is made of Au before being joined with the AuSn solder 12. As the cover electrode 24 is joined with the AuSn solder 12, Sn diffuses into the cover electrode 24, turning it into a cover electrode 24a made of Au containing Sn.
[0036] [1-2. Effects] The effects of the semiconductor light emitting element 10 and the semiconductor light emitting device 11 according to the present embodiment will be described. Below, a description will be given of the effects of the semiconductor light emitting element 10 and the semiconductor light emitting device 11 in comparison with a semiconductor light emitting element of a comparative example, with reference to Fig. 3A and Fig. 8. Fig. 8 is an enlarged view of the vicinity of the ridge 34r of the semiconductor light emitting element of the comparative example.
[0037] The semiconductor light-emitting device of the comparative example shown in FIG. 8 differs from the semiconductor light-emitting device 10 of the present embodiment in the configuration of the current blocking layer 921, but is otherwise identical. As shown in FIG. 8 , the current blocking layer 921 of the comparative example does not cover the end of the barrier layer 23. In other words, the barrier layer 23 is located inside the opening 921a of the current blocking layer 921. Therefore, when the cover electrode 24 of the semiconductor light-emitting device of the comparative example is mounted on a submount 13 or the like using AuSn solder 12, Sn atoms diffused into the cover electrode 24 may diffuse into the contact electrode 22 through the interface between the barrier layer 23 and the top surface 34rt of the ridge 34r, as shown by the dashed arrow in FIG. 8 . This may impair the ohmic contact between the contact electrode 22 and the second semiconductor layer 34.
[0038] 3A , in the semiconductor light emitting device 10 according to the present embodiment, the current blocking layer 21 continuously covers the barrier layer 23 from the end of the ridge 34r in the width direction (i.e., the X-axis direction) to the side surface 34rs of the ridge 34r. In this manner, the interface between the barrier layer 23 and the top surface 34rt of the ridge 34r is covered by the current blocking layer 21. This makes it possible to prevent Sn atoms that have diffused into the cover electrode 24 from diffusing into the contact electrode 22 through the interface between the barrier layer 23 and the top surface 34rt of the ridge 34r. This makes it possible to maintain ohmic contact between the contact electrode 22 and the second semiconductor layer 34.
[0039] In this embodiment, the barrier layer 23 continuously covers from the top surface 34rt of the ridge 34r to the side surface 22s of the contact electrode 22. This makes it possible to suppress direct diffusion of Sn atoms toward the contact electrode 22, compared to when the barrier layer 23 does not cover the side surface 22s of the contact electrode 22.
[0040] In this embodiment, the side surface 23s of the barrier layer 23 (hereinafter also referred to as the barrier layer side surface 23s) is continuously connected to the side surface 34rs of the ridge 34r (hereinafter also referred to as the ridge side surface 34rs), thereby suppressing a step in the current blocking layer 21 at the boundary between the barrier layer side surface 23s and the ridge side surface 34rs.
[0041] Here, the problem of forming such a step will be described with reference to FIG. 3B . FIG. 3B is an enlarged cross-sectional view of the vicinity of the ridge of a semiconductor light-emitting device of a comparative example. A cross section similar to that of FIG. 3A is shown in FIG. 3B . The semiconductor light-emitting device of the comparative example differs from the semiconductor light-emitting device 10 of the present embodiment in that the barrier layer side surface 23s is not continuous with the ridge side surface 34rs, but is identical in other respects. In this semiconductor light-emitting device of the comparative example, a step is formed in the current blocking layer 21 at the boundary between the barrier layer side surface 23s and the ridge side surface 34rs. As shown in FIG. 3B , when such a step is formed in the current blocking layer 21, a slit-shaped void 21v as shown in FIG. 3B is likely to be formed in the current blocking layer 21 near the step.
[0042] On the other hand, in the semiconductor light emitting device 10 according to this embodiment, as described above, it is possible to suppress a step in the current blocking layer 21 at the boundary between the barrier layer side surface 23s and the ridge side surface 34rs. This reduces the possibility of a slit-shaped void 21v, as shown in the comparative example of FIG. 3B , being formed in the current blocking layer 21 that continuously covers the barrier layer side surface 23s and the ridge side surface 34rs. This prevents Sn atoms from diffusing through the void to the edge of the interface between the barrier layer 23 and the ridge top surface 34rt, and further prevents Sn atoms from diffusing into the contact electrode 22 through the interface between the barrier layer 23 and the ridge top surface 34rt.
[0043] In this embodiment, the barrier layer 23 is made of a metal, which reduces the electrical resistance of the barrier layer 23 and suppresses the diffusion of Sn atoms into the contact electrode 22.
[0044] Furthermore, in this embodiment, the contact resistance between the barrier layer 23 and the second semiconductor layer 34 is greater than the contact resistance between the contact electrode 22 and the second semiconductor layer 34. The barrier layer 23 having such characteristics is made of, for example, Pt, Cr, W, Ti, TiW, or Mo. This makes it possible to reduce the current flowing from the barrier layer 23 to the ridge 34r even if the barrier layer 23 is in contact with the ridge 34r near the side surface 34rs of the ridge 34r, thereby suppressing current concentration on the side surface 34rs of the ridge 34r.
[0045] The barrier layer 23 may be made of, for example, ZnO:Ga, ZnO:Al, or In. ２ O ３ : Sn and In ｘ Ga ｙ Zn ｚ The conductive oxide may be a conductive oxide containing at least one of O (0<x<2 / 3, 0<y<2 / 3, 0<z<1). Such conductive oxides do not alloy with Sn atoms and therefore have a high barrier property against Sn atoms. Furthermore, the conductivity at the junction between each of the conductive oxides and the p-type GaN constituting the upper surface 34rt of the ridge 34r is determined primarily by a quasi-ohmic contact due to the tunneling effect. That is, because the work function of the conductive oxide is smaller than that of p-type GaN, a Schottky barrier is formed at the junction between the conductive oxide and p-type GaN, but carriers pass through the Schottky barrier by the tunneling effect. For this reason, the contact mode between the conductive oxide and p-type GaN is called a quasi-ohmic contact. Such a quasi-ohmic contact is sometimes used as a p-type electrode, but has a higher electrical resistance than a normal ohmic contact such as Pd. Therefore, even if the barrier layer 23 is in contact with the ridge 34r near the side surface 34rs of the ridge 34r, the current flowing from the barrier layer 23 to the ridge 34r can be reduced, thereby suppressing current concentration on the side surface 34rs of the ridge 34r.
[0046] Furthermore, in this embodiment, the film thickness of the contact electrode 22 becomes thinner as it approaches the end of the ridge 34r in the width direction, and the side surface 22s of the contact electrode 22 has an upwardly convex curved shape. This reduces the step in the underlying barrier layer 23 near the end of the ridge 34r in the width direction of the contact electrode 22. This makes it possible to suppress the formation of slit-shaped voids in the barrier layer 23. This makes it possible to reduce the diffusion of Sn atoms into the contact electrode 22 through the voids.
[0047] Next, the relationship between the position of the end of the contact electrode 22 in the X-axis direction (i.e., the width direction of the ridge 34r) and the height of the ridge 34r according to this embodiment will be described with reference to FIGS. 9 to 11 . FIG. 9 is a graph showing the relationship between the distance L1 in the X-axis direction between the end of the contact electrode 22 in the X-axis direction and the bottom end of the ridge 34r according to this embodiment and the threshold current of laser oscillation of the semiconductor light emitting element 10. FIG. 9 illustrates the relationship when the height L2 of the ridge 34r (i.e., the distance in the stacking direction from the bottom surface 34u of the second semiconductor layer 34 to the top surface 34rt of the ridge 34r) is 0.68 μm. For the definitions of the distance L1 and the height L2, see FIG. 3A . FIGS. 10 , 11 , and 12 are schematic diagrams showing the state of current diffusion in the ridge 34r when L1 / L2<0.7, L1 / L2=1.0, and L1 / L2>2.2, respectively. 10 to 12, the direction of current flow is indicated by dashed arrows.
[0048] In a stripe-type semiconductor laser device, in a cross section perpendicular to the cavity, the width of the contact electrode 22 is significantly narrower than the width of the n-side electrode 28, and the electrical conductivity of the p-type cladding layer 34c is approximately isotropic, so the current flowing inside the ridge 34r spreads at an angle of approximately 45 degrees. As shown in FIG. 11 , when L1 / L2 = 1.0, the current flowing inside the ridge 34r spreads across the entire width of the ridge 34r at the bottom end of the ridge 34r and further spreads at a similar angle below. Therefore, the current does not concentrate on the ridge side surfaces 34rs. Therefore, as shown in FIG. 9 , when the distance L1 and the height L2 are approximately the same (i.e., when the distance L1 is approximately 0.68 μm), the threshold current for laser oscillation of the semiconductor light-emitting device 10 can be kept low.
[0049] On the other hand, as shown in FIG. 10 , when L1 / L2<1, the current flowing inside the ridge 34r flows closer to the ridge side surface 34rs near the ridge top surface 34rt than in the case of FIG. 11 . Furthermore, near the bottom end of the ridge 34r, current diffusion near the ridge side surface 34rs is laterally restricted, which predicts an increase in current density (current concentration) near the ridge side surface 34rs. Because the area near the ridge side surface 34rs is relatively rich in defects due to processing, it is predicted that carrier loss increases, the temperature rises locally, and the threshold current for laser oscillation of the semiconductor light-emitting element 10 tends to increase. In particular, as shown in FIG. 9 , when L1 / L2<0.7 (i.e., when the distance L1 is less than approximately 0.5 μm), the increase in the threshold current for laser oscillation of the semiconductor light-emitting element 10 is significant. Furthermore, current concentration near the ridge side surface 34rs, where crystal defects are relatively numerous, can locally increase the temperature during operation, significantly reducing the long-term reliability of the semiconductor light-emitting element 10.
[0050] Furthermore, as shown in FIG. 12 , when L1 / L2>1, the current flowing inside the ridge 34r is predicted to be such that the ridge width is wider than the diffusion region width near the bottom of the ridge 34r. In other words, the current confinement effect of the ridge 34r is not fully exerted, and the oscillation threshold tends to increase. Furthermore, from the perspective of the ridge width, the area of the contact electrode 22 is too small, and the current density in the contact region between the contact electrode 22 and the ridge top surface 34rt is predicted to increase. In particular, as shown in FIG. 9 , when L1 / L2>2.2 (i.e., when the distance L1 is greater than approximately 1.5 μm), the increase in the threshold current for laser oscillation of the semiconductor light emitting element 10 is significant.
[0051] In this embodiment, the distance L1 in the width direction of the ridge 34r between the end of the ridge 34r of the contact electrode 22 in the width direction and the lower end of the ridge 34r is 70% or more and 220% or less of the ridge height L2, thereby making it possible to suppress the threshold current for laser oscillation of the semiconductor light emitting element 10 and to improve the long-term reliability of the semiconductor light emitting element 10.
[0052] [1-3. Manufacturing Method] Next, a method for manufacturing the semiconductor light emitting element 10 according to this embodiment will be described with reference to Figures 13 to 25. Figures 13, 14, and 17 to 25 are schematic cross-sectional views showing the steps of the method for manufacturing the semiconductor light emitting element 10 according to this embodiment. Figures 15 and 16 are schematic views showing the steps of forming the contact electrode 22 by normal evaporation and planetary evaporation, respectively. Figures 13 to 25 show cross sections at the same positions as in Figure 2.
[0053] 13, first, a substrate 31 is prepared, and a first semiconductor layer 32, an active layer 33, and a second semiconductor layer 34 are formed in this order. Each semiconductor layer is formed by an epitaxial growth method such as MOCVD (Metal Organic Chemical Vapor Deposition) or MBE (Molecular Beam Epitaxy).
[0054] Subsequently, as shown in FIG. 14, a mask 91 is formed on the second semiconductor layer 34 except for a partial region, and a contact electrode 22 is formed on the region where the mask 91 is not formed.
[0055] For example, a photosensitive resist can be used as the mask 91. The mask 91 is patterned by, for example, photolithography. The region where the mask 91 is not formed (i.e., removed by photolithography) is the region where the contact electrode 22 is to be formed and the surrounding region.
[0056] The contact electrode 22 is formed by depositing a metal film on the upper surface of the mask 91 and on an area of the upper surface of the second semiconductor layer 34 where the mask 91 is not formed. As a result, the contact electrode 22 is formed on the area of the upper surface of the second semiconductor layer 34 where the mask 91 is not formed, and a metal film 22M is formed on the mask 91.
[0057] The contact electrode 22 is formed by, for example, a vapor deposition method. In this embodiment, the contact electrode 22 made of Pd is formed by a planetary vapor deposition method. The planetary vapor deposition method will be described below in comparison with a normal vapor deposition method with reference to FIGS. 15 and 16 .
[0058] As shown by the dashed arrow in Fig. 15, when normal evaporation is used, the angle of incidence of the metal on the upper surface of the second semiconductor layer 34 is approximately 90 degrees. In Fig. 15, the dashed arrow indicates the direction of travel of the evaporated particles. Therefore, the width of the contact electrode 22 is approximately the same as the opening of the mask 91, and the film thickness is approximately the same over the entire region.
[0059] In contrast, when using planetary evaporation, the contact electrode 22 is formed while varying the orientation of the substrate 31 relative to the direction of the flow of the evaporated metal. Therefore, as shown in FIG. 16 , the angle of incidence of the metal on the upper surface of the second semiconductor layer 34 periodically varies, for example, within a range of approximately 45 degrees to approximately 80 degrees, as indicated by the dashed arrow in FIG. 16 . This causes the width of the contact electrode 22 to be greater than the width of the opening. Furthermore, the thickness of the contact electrode 22 becomes thinner toward the end of the contact electrode 22, and the shape of the side surface 22s of the contact electrode becomes an upwardly convex curved surface (i.e., the cross-sectional shape of the side surface 22s is curved). As described above, the contact electrode 22 according to this embodiment can be formed by using planetary evaporation.
[0060] Subsequently, as shown in FIG. 17, the mask 91 is removed to lift off the metal film 22M.
[0061] 18 , a barrier layer 23 is formed over the entire surface above the second semiconductor layer 34. In this embodiment, the barrier layer 23 made of Pt is formed using a vapor deposition method or the like. The barrier layer 23 covers the contact electrode 22.
[0062] 19, a mask 92 having a predetermined shape is formed on the upper surface of the barrier layer 23. The mask 92 is formed at positions corresponding to the ridge 34r and wing portions 34w of the semiconductor light emitting element 10 using, for example, photolithography.
[0063] 20, the areas of the barrier layer 23 that are not covered by the mask 92 are removed by etching.
[0064] 21 , a portion of the second semiconductor layer 34 that is not covered by the mask 92 is removed by etching. In other words, a groove 34t is formed. As a result, a ridge 34r and wing portions 34w are formed. After the groove 34t is formed, the mask 92 is removed.
[0065] 22, the barrier layer 23 formed on the wing portion 34w is removed by etching. Specifically, while the ridge 34r is covered with a mask, the barrier layer 23 formed on the wing portion 34w is removed by etching. Thereafter, the mask is removed.
[0066] 23, the current blocking layer 21 is formed over the entire surface above the second semiconductor layer 34. Specifically, a SiO ２ The current blocking layer 21 is formed by a P-CVD (Plasma-Chemical Vapor Deposition) method or the like.
[0067] 24, an opening 21a is formed in the current blocking layer 21. Specifically, the opening 21a is formed above the ridge 34r using photolithography and etching.
[0068] 25 , a cover electrode 24 having a predetermined shape is formed above the current blocking layer 21 and the barrier layer 23. Specifically, for example, after a mask is formed by photolithography, an Au film is formed by evaporation or the like, and the mask is removed to lift off unnecessary Au film. In this way, the cover electrode 24 is formed.
[0069] 2, an n-side electrode 28 is formed on the lower surface of the substrate 31 (i.e., the main surface of the substrate 31 behind the main surface on which the first semiconductor layer 32 is stacked). Specifically, for example, after forming a mask by photolithography, a Ti film, a Pt film, and an Au film are formed in this order by vapor deposition or the like, and the mask is removed to lift off the unnecessary Ti film, Pt film, and Au film. In this way, the n-side electrode 28 is formed.
[0070] The semiconductor light emitting device 10 can be manufactured by the manufacturing method described above.
[0071] (Embodiment 2) A semiconductor light emitting device according to embodiment 2 will be described. The semiconductor light emitting device according to this embodiment differs from the semiconductor light emitting device 10 according to embodiment 1 in the configuration of the current blocking layer, but is the same in other respects. The semiconductor light emitting device according to this embodiment will be described below with reference to FIGS. 26 and 27, focusing on the differences from the semiconductor light emitting device 10 according to embodiment 1.
[0072] Fig. 26 is a schematic top view showing the overall configuration of the semiconductor light emitting device 110 according to this embodiment. Fig. 27 is an enlarged view showing the configuration of the vicinity of the ridge 34r of the semiconductor light emitting device 110 according to this embodiment. Fig. 27 shows a part of the cross section taken along line XXVII-XXVII in Fig. 26.
[0073] As shown in FIGS. 26 and 27, a semiconductor light emitting device 110 according to this embodiment includes a current blocking layer 121 instead of the current blocking layer 21 according to the first embodiment.
[0074] 27, the current blocking layer 121 according to this embodiment continuously covers the region from above the contact electrode 22 to the side surface 34rs of the ridge 34r. In other words, the periphery of the opening 121a of the current blocking layer 121 is located above the contact electrode 22, as shown in Fig. 26. As a result, the current blocking layer 121 covers the end portion of the ridge 34r of the contact electrode 22 in the width direction via the barrier layer 23.
[0075] 27 , the barrier layer 23 continuously covers the upper surface 34rt of the ridge 34r and the widthwise end of the ridge 34r of the contact electrode 22. A step is formed at the boundary between the upper surface 34rt of the ridge 34r and the widthwise end of the ridge 34r of the contact electrode 22. When this step is covered by the barrier layer 23, a slit-shaped void may be formed in a region 23v (the region surrounded by an ellipse in FIG. 27 ) near the step of the barrier layer 23. Therefore, when the cover electrode 24 is in contact with the step of the barrier layer 23, Sn atoms may diffuse from outside the barrier layer 23 to the contact electrode 22 through this void.
[0076] However, since the current blocking layer 121 according to this embodiment continuously covers the region from above the contact electrode 22 to the side surface 34rs of the ridge 34r, the current blocking layer 121 covers the region 23v of the barrier layer 23. Therefore, even if a void is formed in the region 23v of the barrier layer 23, the current blocking layer 121 can suppress the diffusion of Sn atoms into the contact electrode 22.
[0077] (Modifications, etc.) Although the semiconductor light emitting device according to the present disclosure has been described above based on the respective embodiments, the present disclosure is not limited to the above-described respective embodiments.
[0078] For example, in each of the above embodiments, an example was shown in which each semiconductor light-emitting element was a semiconductor laser element, but the semiconductor light-emitting element is not limited to a semiconductor laser element. For example, the semiconductor light-emitting element may be a superluminescent diode.
[0079] In addition, in each of the above embodiments, the side surface 23s of the barrier layer 23 is continuously connected to the side surface 34rs of the ridge 34r, but the side surface 23s of the barrier layer 23 does not have to be continuously connected to the side surface 34rs of the ridge 34r. For example, the side surface 23s of the barrier layer 23 may be located inside the edge of the top surface 34rt of the ridge 34r.
[0080] This disclosure also includes forms obtained by applying various modifications to the above-mentioned embodiments that a person skilled in the art would conceive, and forms realized by arbitrarily combining the components and functions of the above-mentioned embodiments within the scope of the present disclosure.
[0081] The semiconductor light emitting element and semiconductor light emitting device of the present disclosure are particularly useful, for example, in light sources for headlights, which require high reliability.
[0082] 10, 10a, 110 Semiconductor light emitting element 10F, 10R End face 11 Semiconductor light emitting device 12 AuSn solder 13 Submount 13a Metal layer 13b Base 21, 121, 921 Current blocking layer 21a, 121a, 921a Opening 21v Air gap 22 Contact electrode 22M Metal film 22s, 23s, 34rs Side face 22t, 23t, 34rt Top face 23 Barrier layer 23v Region 24, 24a Cover electrode 28 N-side electrode 31 Substrate 32 First semiconductor layer 32a N-type cladding layer 32b N-side guide layer 33 Active layer 33a, 33c, 33e Barrier layer 33b, 33d Well layer 34 Second semiconductor layer 34a p-side guide layer 34b electron block layer 34c p-type cladding layer 34d p-type contact layer 34r ridge 34t groove 34u bottom surface 34w wing portion 91, 92 mask
Claims
1. A semiconductor light emitting device that emits light, A first semiconductor layer of a first conductivity type; an active layer disposed above the first semiconductor layer; a second semiconductor layer of a second conductivity type different from the first conductivity type, the second semiconductor layer being disposed above the active layer; an electrically insulating current blocking layer disposed above the second semiconductor layer; a contact electrode disposed above the second semiconductor layer and in contact with the second semiconductor layer; a conductive barrier layer that covers an upper surface and a side surface of the contact electrode and suppresses diffusion of Sn atoms into the contact electrode; the second semiconductor layer has a bottom surface that is a part of an upper surface of the second semiconductor layer, and a ridge that protrudes upward from the bottom surface and extends in a propagation direction of the light, the contact electrode is disposed on an upper surface of the ridge; In a cross section perpendicular to the propagation direction of the light, a width of the contact electrode is smaller than a width of an upper surface of the ridge, a side surface of the barrier layer is continuously connected to a side surface of the ridge, The current blocking layer continuously covers from the upper surface of the barrier layer to the side surface of the ridge. Semiconductor light emitting element.
2. The barrier layer continuously covers from the top surface of the ridge to the side surface of the contact electrode. The semiconductor light emitting device according to claim 1 .
3. The barrier layer is made of a metal. The semiconductor light emitting device according to claim 1 .
4. The contact resistance between the barrier layer and the second semiconductor layer is greater than the contact resistance between the contact electrode and the second semiconductor layer. The semiconductor light emitting device according to claim 1 .
5. The barrier layer is made of Pt, Cr, W, Ti, TiW, or Mo. The semiconductor light emitting device according to claim 1 .
6. The barrier layer is made of a conductive oxide. The semiconductor light emitting device according to claim 1 .
7. The barrier layer is made of ZnO:Ga, ZnO:Al, In ２ O ３ : Sn and In ｘ G ｙ Contains at least one of ZnO (0<x<2 / 3, 0<y<2 / 3, 0<z<1) The semiconductor light emitting device according to claim 6 .
8. A distance in a width direction of the ridge between an end of the ridge of the contact electrode in the width direction and a lower end of the ridge is 70% or more and 220% or less of a height of the ridge. The semiconductor light emitting device according to claim 1 .
9. The current blocking layer continuously covers an area from above the contact electrode to a side surface of the ridge. The semiconductor light emitting device according to claim 1 .
10. The thickness of the contact electrode becomes thinner toward the end of the ridge in the width direction. The semiconductor light emitting device according to claim 1 .
11. a cover electrode disposed above the current blocking layer and the barrier layer and covering at least a portion of each of the current blocking layer and the barrier layer; The current blocking layer covers the bottom surface and the side surfaces of the ridge. The semiconductor light emitting device according to claim 1 .
12. The semiconductor light emitting device according to claim 1 or 2, a submount on which the semiconductor light emitting device is mounted; AuSn solder is provided to join the semiconductor light emitting element and the submount, The AuSn solder is electrically connected to the contact electrode. Semiconductor light emitting device.