Semiconductor device and switching power supply

Abstract

A semiconductor device 10 comprises, for example, the following: a first driver 163 configured to drive an output element M1 that forms a switch output stage SWO; at least a portion of a bootstrap circuit BST configured to generate a boot voltage Vb that is higher than a switch voltage Vsw output from the switch output stage SWO, and to supply the boot voltage to the first driver 163; a boot voltage detection circuit 20 configured to detect that a differential value (=Vb-Vsw) between the boot voltage Vb and the switch voltage Vsw, when the output element M1 is in an off state, has become less than a lower limit detection value, and to charge the boot voltage Vb; and a controller 161 configured to switch the boot voltage detection circuit 20 between an operating state and a non-operating state.

Description

Semiconductor devices, switching power supplies

[0001] The present disclosure relates to a semiconductor device and a switching power supply using the same, and also to a gate drive circuit.

[0002] Bootstrap circuits are widely used as internal power supply means for driving N-channel output transistors.

[0003] An example of the related prior art is disclosed in Japanese Patent Application Laid-Open No. 2003-222299.

[0004] Further, conventionally, a gate drive circuit is known that drives the gates of a high-side transistor and a low-side transistor that are connected in series.

[0005] In some cases, both the low-side transistor and the high-side transistor are configured with an N-channel metal-oxide-semiconductor field-effect transistor (MOSFET). In this case, a so-called bootstrap is provided to drive the high-side transistor. The bootstrap uses a boot capacitor to turn on the high-side transistor (see, for example, Patent Document 2).

[0006] On the other hand, when the high-side transistor and the low-side transistor are on at the same time, a through current occurs, so a so-called dead time (a period when the high-side transistor and the low-side transistor are off at the same time) may be provided when the high-side transistor and the low-side transistor are switched on and off.

[0007] JP 2018-133916 A JP 2021-158720 A

[0008] However, there is room for improvement in preventing a drop in the boot voltage generated by the bootstrap circuit.

[0009] Furthermore, during dead time, current flows through the body diode of the transistor, causing losses and reducing efficiency, which has been an issue.

[0010] A semiconductor device according to one aspect of the present disclosure includes a first driver configured to drive an output element forming a switch output stage, at least a part of a bootstrap circuit configured to generate a boot voltage higher than a switch voltage output from the switch output stage and supply the generated boot voltage to the first driver, a boot voltage detection circuit configured to detect when a difference value between the boot voltage and the switch voltage becomes lower than a lower limit detection value when the output element is in an off state, and to charge the boot voltage, and a controller configured to switch the boot voltage detection circuit between an operating state and an inoperable state.

[0011] Furthermore, for example, a gate drive circuit according to one aspect of the present disclosure is a gate drive circuit for driving a high-side transistor and a low-side transistor connected in series between an application terminal of an input voltage and an application terminal of a ground potential, and includes: a first level shifter configured to be able to input a low-side gate control signal; a low-side gate signal output unit configured to generate a low-side gate signal for driving a gate of the low-side transistor based on an output of the first level shifter; a second level shifter configured to be able to input the output of the first level shifter; a third level shifter configured to be able to input a high-side gate control signal; and a gate drive circuit configured to be able to input the output of the second level shifter and the output of the third level shifter. and a high-side gate signal output unit configured to generate a high-side gate signal that drives the gate of the high-side transistor based on an output of the first logic gate, wherein the first level shifter is configured to output the input voltage as a high level, the second level shifter and the third level shifter are configured to output, as a high level, a boot voltage generated at a second end of a boot capacitor having a first end connected to a node at which the high-side transistor and the low-side transistor are connected, and the high-side gate signal output unit is configured to be able to apply the boot voltage as the high-side gate signal to the gate of the high-side transistor.

[0012] Still other features, elements, steps, advantages, and characteristics will become more apparent from the detailed description that follows and the accompanying drawings related thereto.

[0013] According to the configuration according to one aspect of the present disclosure, it is possible to provide a semiconductor device that can prevent a drop in the boot voltage generated in a bootstrap circuit, and a switching power supply using the same.

[0014] Furthermore, according to the exemplary gate drive circuit of the present disclosure, it is possible to shorten the dead time in a configuration using a boot capacitor.

[0015] FIG. 1 is a diagram showing the overall configuration of a switching power supply. FIG. 2 is a diagram showing a first embodiment (first comparative example) of the switching power supply. FIG. 3 is a diagram showing a second embodiment (second comparative example) of the switching power supply. FIG. 4 is a diagram showing the switching operation of the second embodiment. FIG. 5 is a diagram showing a third embodiment of the switching power supply. FIG. 6 is a diagram showing the switching operation of the third embodiment. FIG. 7 is a diagram showing an example configuration of a boot voltage detection circuit. FIG. 8 is a diagram showing an example operation of a charge pump. FIG. 9 is a diagram showing the configuration of a DC / DC converter according to a comparative example. FIG. 10 is a diagram showing the configuration of a DC / DC converter according to an exemplary embodiment of the present disclosure. FIG. 11 is a timing chart showing an example operation of a gate drive circuit according to an exemplary embodiment of the present disclosure. FIG. 12 is a diagram showing the configuration of a DC / DC converter according to a modified example.

[0016] <Switching Power Supply> Figure 1 is a diagram showing the overall configuration of a switching power supply. The switching power supply X0 in this configuration example is a step-down DC / DC converter that steps down an input voltage Vin (e.g., 2.7 to 5.5 V) to generate a desired output voltage Vout (e.g., 0.6 to 4.0 V). Specifically, with reference to this diagram, the switching power supply X0 includes a semiconductor device 10 and various discrete components (capacitors C1 and C2, an inductor L1, and resistors R1 and R2) attached externally thereto.

[0017] The semiconductor device 10 is a device (a so-called power supply control integrated circuit) that comprehensively controls the operation of the switching power supply X0. The semiconductor device 10 has a plurality of external terminals (pins 1 to 4 in the figure) as means for establishing electrical connections with the outside of the device.

[0018] Pin 1 is a power supply terminal VIN to which an input voltage Vin is applied, Pin 2 is a switch output terminal SW, Pin 3 is a ground terminal GND, and Pin 4 is a feedback input terminal FB.

[0019] Next, the external connections of the semiconductor device 10 will be described. A first terminal of the capacitor C1 is connected to the power supply terminal VIN. A second terminal of the capacitor C1 is connected to the ground terminal. A first terminal of the inductor L1 is connected to the switch output terminal SW. A second terminal of the inductor L1 and a first terminal of each of the resistor R1 and the capacitor C2 are all connected to the application terminal of the output voltage Vout. A second terminal of the resistor R1 and a first terminal of the resistor R2 are all connected to the feedback input terminal FB (= the application terminal of the feedback voltage Vfb). A second terminal of each of the capacitor C2 and the resistor R2 is all connected to the ground terminal.

[0020] The inductor L1 and the capacitor C2 function as an LC filter that rectifies and smoothes the square-wave switch voltage Vsw to generate the output voltage Vout.

[0021] The resistors R1 and R2 function as a feedback voltage generating circuit (voltage dividing circuit) that outputs a feedback voltage Vfb (= a divided voltage of the output voltage Vout) corresponding to the output voltage Vout from a connection node between them. Although not shown in the figure, a speed-up capacitor may be connected in parallel across the resistor R1 to ensure smooth startup of the switching power supply X0. Furthermore, if the output voltage Vout is within the input dynamic range of the semiconductor device 10, the resistors R1 and R2 may be omitted, and the output voltage Vout may be directly input to the feedback input terminal FB.

[0022] 1, the internal configuration of the semiconductor device 10 will be described in detail. The semiconductor device 10 of this configuration example integrates an error amplifier 11, a comparison circuit 12, an on-time setting circuit 13, a ripple generation circuit 14, an adder circuit 15, a drive control circuit 16, a reference voltage generation circuit 17, a charge pump 18, a zero-cross detection circuit 19, capacitors C3 and C4, a switch BS, an output element M1, and a synchronous rectification element M2.

[0023] The error amplifier 11 generates an error voltage Vc corresponding to the difference between a reference voltage Vref input to the non-inverting input terminal (+) and a feedback voltage Vfb input to the inverting input terminal (-). The error voltage Vc increases when the feedback voltage Vfb is lower than the reference voltage Vref, and decreases when the feedback voltage Vfb is higher than the reference voltage Vref.

[0024] The comparison circuit 12 includes a first comparator 121 and a second comparator 122 .

[0025] The first comparator 121 compares the slope voltage Vslp input to its inverting input terminal (-) with the error voltage Vc input to its non-inverting input terminal (+) to generate a comparison signal Sc1. The comparison signal Sc1 goes high when the slope voltage Vslp is lower than the error voltage Vc, and goes low when the slope voltage Vslp is higher than the error voltage Vc. The first comparator 121 may have a hysteresis characteristic.

[0026] The second comparator 122 compares the feedback voltage Vfb input to its inverting input terminal (-) with the error voltage Vc input to its non-inverting input terminal (+) to generate a comparison signal Sc2. The comparison signal Sc2 goes high when the feedback voltage Vfb is lower than the error voltage Vc, and goes low when the feedback voltage Vfb is higher than the error voltage Vc. The second comparator 122 may have a hysteresis characteristic.

[0027] Furthermore, the timing at which the feedback voltage Vfb falls below the error voltage Vc is earlier than the timing at which the slope voltage Vslp (=Vfb+Vr), which is the sum of the feedback voltage Vfb and the ripple voltage Vr, falls below the error voltage Vc. In other words, the timing at which the comparison signal Sc2 rises to a high level is earlier than the timing at which the comparison signal Sc1 rises to a high level.

[0028] The second comparator 122 may have a lower responsiveness (current output capability) than the first comparator 121 .

[0029] The ON time setting circuit 13 generates the switch control signal S0 so that the output element M1 is maintained in the ON state for the ON time Ton after the comparison signal Sc1 rises to a high level. The ON time setting circuit 13 also has a function of ignoring the logical level of the comparison signal Sc1 for a predetermined mask period (e.g., 100 ns) after the comparison signal Sc2 rises to a high level.

[0030] The ripple generating circuit 14 generates a ripple voltage Vr that simulates the ripple component of the output voltage Vout in synchronization with the switch control signal S0.

[0031] The adder circuit 15 adds the ripple voltage Vr to the feedback voltage Vfb to generate the slope voltage Vslp.

[0032] The drive control circuit 16 includes, as its components, a controller 161 , a level shifter 162 , and drivers 163 and 164 .

[0033] The controller 161 generates gate control signals S1 and S2 as basic output feedback control using a bottom detection type fixed on-time method according to the switch control signal S0 so that the output voltage Vout matches a desired target value.

[0034] The controller 161 also has a function of stopping the switching drive of the output element M1 and the synchronous rectifier element M2 under light load conditions in response to the zero-cross detection signal S9. For example, the controller 161 may turn off the synchronous rectifier element M2 when the zero-cross detection signal S9 rises to a high level while the output element M1 is in an off state and the synchronous rectifier element M2 is in an on state, i.e., when it is detected that the switch voltage Vsw has become higher than a zero-cross detection value (e.g., GND).

[0035] The level shifter 162 shifts the level of the gate control signal S1 to generate the gate control signal S1'. Referring to the figure, the level shifter 162 sets the gate control signal S1' to a high level (=Vb) when the gate control signal S1 is at a high level (=Vin), and sets the gate control signal S1' to a low level (=Vsw) when the gate control signal S1 is at a low level (=GND).

[0036] The driver 163 drives the output element M1 by generating a gate drive signal G1 in response to the gate control signal S1′. For example, the gate drive signal G1 is at a high level (=Vb) when the gate control signal S1′ is at a high level, and is at a low level (=Vsw) when the gate control signal S1′ is at a low level.

[0037] The driver 164 drives the synchronous rectifier element M2 by generating a gate drive signal G2 in response to the gate control signal S2. For example, the gate drive signal G2 is at a high level (=Vin) when the gate control signal S2 is at a high level, and is at a low level (=GND) when the gate control signal S2 is at a low level.

[0038] The reference voltage generating circuit 17 generates a predetermined reference voltage Vref (corresponding to the target value of the feedback voltage Vfb, and therefore the target value of the output voltage Vout).

[0039] The charge pump 18 generates a boosted voltage Vcp higher than the input voltage Vin in response to a charge pump control signal CPON output from the controller 161, and applies this to the application terminal of the boot voltage Vb.

[0040] The charge pump 18 does not always maintain the boot voltage Vb at a voltage value higher than the input voltage Vin, but only needs to have a current capacity sufficient to slightly raise the boot voltage Vb when it drops. Therefore, for example, an existing charge pump provided for the purpose of maintaining the boot voltage Vb when the switch output stage SWO is driven at 100% duty may be used as the charge pump 18.

[0041] When the output element M1 is in the off state and the synchronous rectifier element M2 is in the on state, the zero-crossing detection circuit 19 detects the zero-crossing (reverse flow) of the inductor current IL flowing through the synchronous rectifier element M2 by monitoring the voltage across the synchronous rectifier element M2 (corresponding to the switch voltage Vsw).

[0042] The capacitor C3 serves as a phase compensation means for preventing the error amplifier 11 from oscillating, and is connected between the output terminal of the error amplifier 11 and the ground terminal.

[0043] The output element M1 (for example, an NMOSFET [N-channel type metal oxide semiconductor field effect transistor]) functions as an upper switch of the switch output stage SWO that generates a switch voltage Vsw from the input voltage Vin. The drain of the output element M1 is connected to the power supply terminal VIN. The source of the output element M1 is connected to the switch output terminal SW. The gate of the output element M1 is connected to an application terminal of a gate drive signal G1. The output element M1 is in an ON state when the gate drive signal G1 is at a high level, and in an OFF state when the gate drive signal G1 is at a low level.

[0044] The synchronous rectifier element M2 (e.g., an NMOSFET) functions as a lower switch of the switch output stage SWO. The drain of the synchronous rectifier element M2 is connected to the switch output terminal SW. The source of the synchronous rectifier element M2 is connected to the ground terminal GND. The gate of the synchronous rectifier element M2 is connected to an application terminal of a gate drive signal G2. The synchronous rectifier element M2 is in an ON state when the gate drive signal G2 is at a high level, and in an OFF state when the gate drive signal G2 is at a low level.

[0045] As the rectifying element, instead of the synchronous rectifying element M2, a rectifying diode (for example, a Schottky barrier diode) having a cathode connected to the switch output terminal SW and an anode connected to the ground terminal GND may be used.

[0046] The output element M1 and the synchronous rectifier element M2 may be externally attached to the semiconductor device 10. In that case, instead of the switch output terminal SW, an external input terminal for the switch voltage Vsw and external output terminals for the gate drive signals G1 and G2 are required.

[0047] Furthermore, when a high voltage can be applied to the switch output stage SWO, high-voltage elements such as an IGBT (insulated gate bipolar transistor), a SiC device, or a GaN device may be used as the output element M1 and the synchronous rectifier element M2.

[0048] The switch output stage SWO generates a square-wave switch voltage Vsw that is pulse-driven between the input voltage Vin and the ground voltage PGND by complementarily turning on and off the output element M1 and the synchronous rectifier element M2, which are connected to form a half bridge.

[0049] In this specification, the term "complementary" is used to include cases where the on / off states of the output element M1 and the synchronous rectifier element M2 are completely reversed, as well as cases where a delay is given to the timing of their on / off transitions (i.e., cases where a simultaneous off period is provided).

[0050] A first terminal of the switch BS is connected to the power supply terminal VIN. A second terminal of the switch BS and a first terminal of the capacitor C4 are both connected to a terminal to which the boot voltage Vb is applied. A second terminal of the capacitor C4 is connected to the switch output terminal SW.

[0051] The switch BS and capacitor C4 connected in this manner form a bootstrap circuit BST that generates a boot voltage Vb that is higher than the switch voltage Vsw by the voltage across the capacitor C4 and supplies the boot voltage Vb to the level shifter 162 and the driver 163.

[0052] The operation of the bootstrap circuit BST will be briefly explained. When the output device M1 is in the OFF state and the synchronous rectifier device M2 is in the ON state, the switch BS is in the ON state. Therefore, the capacitor C4 is charged by the current flowing from the application terminal of the input voltage Vin via the switch BS. At this time, the voltage across the capacitor C4 rises until it becomes approximately the same potential as the input voltage Vin.

[0053] On the other hand, when the output device M1 is on and the synchronous rectifier device M2 is off, the switch BS is turned off, and the boot voltage Vb is raised to a potential (≈2Vin) that is higher than the switch voltage Vsw (≈Vin) by the voltage across the capacitor C4 (≈Vin), in accordance with the law of conservation of charge of the capacitor C4.

[0054] The switch BS may be, for example, a PMOSFET (P-channel type MOSFET) configured such that the drain is connected to the power supply terminal VIN and the source is connected to the application terminal of the boot voltage Vb, or a diode configured such that the anode is connected to the power supply terminal VIN and the cathode is connected to the application terminal of the boot voltage Vb.

[0055] Furthermore, in this embodiment, the capacitor C4 is built into the semiconductor device 10. This allows for a reduction in the number of discrete components externally attached to the semiconductor device 10. However, the capacitance value of the capacitor C4 is smaller than when the capacitor C4 is externally attached to the semiconductor device 10. Therefore, it is necessary to consider measures to reduce the boot voltage Vb (details will be described later).

[0056] 2 is a diagram showing a first embodiment of a switching power supply X0 (corresponding to a first comparative example to be compared with the third embodiment described later). The switching power supply X0 of this embodiment is based on the overall configuration described above (FIG. 1) and further includes a boot voltage detection circuit 20.

[0057] The boot voltage detection circuit 20 detects when the divided voltage Vbd of the boot voltage Vb becomes lower than the lower limit detection voltage Vth and generates a boot drop detection signal BU. Referring to the figure, the boot voltage detection circuit 20 includes a comparator CMP and resistors R3 and R4.

[0058] The resistors R3 and R4 are connected in series between the application terminal of the boot voltage Vb and the ground terminal, and a divided voltage Vbd of the boot voltage Vb is output from the connection node between them.

[0059] The comparator CMP compares the divided voltage Vbd input to its inverting input terminal (-) with the lower limit detection voltage Vth input to its non-inverting input terminal (+) to generate a boot low detection signal BU. The boot low detection signal BU goes high when the divided voltage Vbd is lower than the lower limit detection voltage Vth, and goes low when the divided voltage Vbd is higher than the lower limit detection voltage Vth. The comparator CMP may be provided with a hysteresis characteristic.

[0060] During the period when the drive of the switch output stage SWO is stopped (= the period when both the output device M1 and the synchronous rectifier device M2 are off), when the boot voltage drop detection signal BU rises to a high level, the controller 161 turns on the synchronous rectifier device M2 and the switch BS to charge the boot voltage Vb. Therefore, the high level of the gate drive signal G1 can be raised to a potential sufficient to turn on the output device M1.

[0061] However, the boot voltage detection circuit 20 of this embodiment is a constant detection type that uses resistive voltage division, and a circuit current always flows from the application terminal of the boot voltage Vb to the ground terminal, so that the boot voltage Vb is likely to drop during the period when the drive of the switch output stage SWO is stopped.

[0062] In particular, when the capacitor C4 is built into the semiconductor device 10, it is difficult to ensure a sufficient capacitance value for the capacitor C4, and the above problem is likely to become apparent.

[0063] Furthermore, when the temperature of the semiconductor device 10 becomes high (for example, 125° C. or higher), the element leakage increases, and the boot voltage Vb tends to decrease.

[0064] <Switching Power Supply (Second Embodiment)> Fig. 3 is a diagram showing a second embodiment of the switching power supply X0 (corresponding to a second comparative example to be compared with the third embodiment described later). The switching power supply X0 of this embodiment is based on the overall configuration described above (Fig. 1) and has a gate monitoring function added to the controller 161.

[0065] Specifically, the controller 161 of this embodiment has the function of detecting a drop in the boot voltage Vb by monitoring whether the gate drive signal G1 has risen to a potential sufficient to turn on the output element M1 after the gate control signal S1 has risen to a high level.

[0066] For example, the drive control circuit 16 may include a level shifter 165 configured to level-shift the gate drive signal G1 to generate a gate drive signal G1′ and output it to the controller 161, as shown in this figure.

[0067] 4 is a diagram showing the switching operation of the second embodiment, depicting, from top to bottom, the switch voltage Vsw (solid line), the boot voltage Vb (dashed line), the gate control signal S1, the gate feedback signal G1fb, the boot drop detection signal BU, and the gate control signal S2. Note that this diagram shows waveforms of intermittent switching operation under a light load.

[0068] The gate feedback signal G1fb is one of the internal signals of the controller 161. Specifically, the gate feedback signal G1fb goes high when the gate drive signal G1 rises to a potential sufficient to turn on the output element M1 after the gate control signal S1 goes high. In this embodiment, the boot drop detection signal BU can also be understood as one of the internal signals of the controller 161.

[0069] During the period when the switch output stage SWO is not driven (before time t12), the gate control signals S1 and S2 are both at a low level, so that the output element M1 and the synchronous rectifier element M2 are both in an off state. At this time, as shown before time t11, the boot voltage Vb decreases over time. Then, as shown from time t11 to t12, the boot voltage Vb finally decreases to a potential substantially equal to the switch voltage Vsw.

[0070] As mentioned above, when the capacitor C4 is built-in and when the semiconductor device 10 is at a high temperature, the boot voltage Vb is likely to decrease.

[0071] Between times t12 and t13, the gate control signal S1 is raised to a high level. However, as mentioned above, the boot voltage Vb has dropped to approximately the same potential as the switch voltage Vsw, so the gate drive signal G1 does not rise to a potential sufficient to turn on the output device M1. As a result, the output device M1 cannot be properly switched on. At this time, the gate feedback signal G1fb remains at a low level.

[0072] At time t13, since the gate feedback signal G1fb is at a low level, the boot drop detection signal BU is raised to a high level (=the logic level when a drop in the boot voltage Vb is detected).

[0073] If the rising edge of the gate drive signal G1 is not detected and the boot drop detection signal BU is raised to a high level, the gate control signal S2 is raised to a high level and the synchronous rectifier device M2 is switched on, as shown from time t13 to t14. As a result, the capacitor C4 is charged and the boot voltage Vb rises. Therefore, from time t14 to t15, the high-level transition of the gate control signal S1 allows the gate drive signal G1 to be raised to a high level, and the output device M1 is switched on.

[0074] However, because the series of reboot operations described above is performed in response to the gate drive signal G1 not rising sufficiently, the timing at which the output element M1 turns on is delayed. In accordance with this diagram, the output element M1 is not turned on at the first switching event (time t12), but is turned on at the second switching event (time t14).

[0075] If the turn-on timing of the output element M1 is delayed, the output voltage Vout will fall below the bottom detection value, increasing the ripple component of the output voltage Vout. In particular, in a configuration in which the synchronous rectifier element M2 is turned on extra to charge the boot voltage Vb, charge will be discarded from the application terminal of the output voltage Vout. This will increase the amount of drop in the output voltage Vout, and ultimately, the increase in the ripple component may become significant.

[0076] Furthermore, if the synchronous rectifier device M2 is turned on when the boot voltage Vb is insufficient, the gate-source voltage of the output device M1 may rise when the switch voltage Vsw drops due to insufficient performance of the driver 163. As a result, not only the synchronous rectifier device M2 but also the output device M1 may be turned on, which may cause an excessively large through current to flow in the switch output stage SWO.

[0077] The problems of the first embodiment (FIG. 2) and the second embodiment (FIG. 3) described above also apply to the case where diode rectification is adopted in the switch output stage SWO.

[0078] Below, a third embodiment that can solve these problems will be proposed.

[0079] <Switching Power Supply (Third Embodiment)> Fig. 5 is a diagram showing a third embodiment of the switching power supply X0. The switching power supply X0 of this embodiment is based on the first embodiment (Fig. 2) and the second embodiment (Fig. 3) described above, but the configuration and operation of the boot voltage detection circuit 20 are changed.

[0080] The boot voltage detection circuit 20 detects that the difference value (= Vb - Vsw) between the boot voltage Vb and the switch voltage Vsw becomes lower than the lower limit detection value Vdet during the period when the switch output stage SWO is not driven (= the period when both the output element M1 and the synchronous rectification element M2 are off), and generates a boot normal detection signal BOK to charge the boot voltage Vb.

[0081] The boot normal detection signal BOK becomes high level (= the logical level when BOOTUVLO is not detected) when the difference value (Vb-Vsw) is higher than the lower limit detection value Vdet, and becomes low level (= the logical level when BOOTUVLO is detected) when the difference value (Vb-Vsw) is lower than the lower limit detection value Vdet.

[0082] When the boot normal detection signal BOK falls to a low level during a period in which the drive of the switch output stage SWO is stopped, the controller 161 drives the charge pump 18 to charge the boot voltage Vb. Referring to the figure, the charge pump 18 generates a boosted voltage Vcp higher than the input voltage Vin in response to a charge pump control signal CPON output from the controller 161, and applies this to the application terminal of the boot voltage Vb.

[0083] This reboot operation allows the high level of the gate drive signal G1 to be raised to a potential sufficient to turn on the output element M1, thereby enabling the switching operation of the switch output stage SWO to be restarted without any problems.

[0084] Furthermore, if the charge pump 18 is used, it is not necessary to turn on the synchronous rectifier element M2 extra to charge the boot voltage Vb, and therefore the ripple component of the output voltage Vout can be kept small.

[0085] As mentioned above, for example, an existing charge pump provided for the purpose of maintaining the boot voltage Vb when the switch output stage SWO is driven at 100% duty may be used as the charge pump 18. By sharing the circuit in this way, it becomes possible to shrink the chip area of ​​the semiconductor device 10.

[0086] However, if the semiconductor device 10 does not include a charge pump 18, a configuration may be adopted in which the synchronous rectifier element M2 is turned on to charge the boot voltage Vb, as in the second embodiment (see Figures 3 and 4) described above.

[0087] Furthermore, in the switching power supply X0 of this embodiment, the controller 161 has a function of generating a boot detection control signal BUON so as to switch the boot voltage detection circuit 20 between an operating state and a non-operating state.

[0088] In other words, the boot voltage detection circuit 20 is activated only when certain conditions (described in detail below) are satisfied. Therefore, unlike the first embodiment (FIG. 2), a circuit current does not always flow from the application terminal of the boot voltage Vb to the ground terminal, making it possible to suppress a decrease in the boot voltage Vb. This can also contribute to reducing the current consumption of the boot voltage detection circuit 20 (and therefore the semiconductor device 10).

[0089] FIG. 6 is a diagram showing the switching operation of the third embodiment, depicting, from top to bottom, the switch voltage Vsw (solid line), the boot voltage Vb (dashed line), the comparison signals Sc2 and Sc1, the wake signal WAKE, the deep signal DEEP, the boot detection control signal BUON, and the boot normal detection signal BOK.

[0090] First, a basic switching operation will be briefly explained with reference to times t24 to t25. When the output device M1 is in the ON state and the synchronous rectifier device M2 is in the OFF state, the inductor current IL flows from the application terminal of the input voltage Vin through the output device M1 and the inductor L1 toward the application terminal of the output voltage Vout. As a result, the output voltage Vout increases. Furthermore, the switch voltage Vsw becomes high (= Vin - IL × Ron(M1), where Ron(M1) is the ON resistance of the output device M1).

[0091] When the synchronous rectifier M2 is in the OFF state, the switch BS of the bootstrap circuit BST is also in the OFF state, so the boot voltage Vb has a voltage value higher than the switch voltage Vsw by the voltage across the capacitor C4.

[0092] On the other hand, when the output device M1 is in the OFF state and the synchronous rectifier device M2 is in the ON state, the electromotive force induced in the inductor L1 causes the inductor current IL to continue flowing from the ground terminal GND through the synchronous rectifier device M2 and the inductor L1 toward the application terminal of the output voltage Vout. As a result, the output voltage Vout continues to rise. In addition, the switch voltage Vsw becomes low (=GND-IL×Ron(M2), where Ron(M2) is the ON resistance of the synchronous rectifier device M2).

[0093] When the synchronous rectifier M2 is in the ON state, the switch BS of the bootstrap circuit BST is also in the ON state, and therefore the capacitor C4 is charged by the current flowing from the application terminal of the input voltage Vin via the switch BS, and the boot voltage Vb rises.

[0094] Then, at time t25, the electromotive force of inductor L1 becomes weak, and when the zero crossing (reverse flow) of inductor current IL flowing through synchronous rectifier device M2 is detected, synchronous rectifier device M2 is turned off. As a result, both output device M1 and synchronous rectifier device M2 are turned off, and switch output terminal SW is in a high impedance state. At this time, switch voltage Vsw is approximately equal to output voltage Vout.

[0095] When the synchronous rectifier element M2 is turned off, the switch BS of the bootstrap circuit BST is also turned off. Therefore, during the period when the drive of the switch output stage SWO is stopped, the boot voltage Vb becomes a voltage value higher than the switch voltage Vsw by the voltage across the capacitor C4. However, during the period when the drive of the switch output stage SWO is stopped, the boot voltage Vb decreases due to natural discharge or high-temperature leakage.

[0096] Next, the wake signal WAKE and the deep signal DEEP, which are internal signals of the controller 161, will be described.

[0097] The wake signal WAKE is a logic signal indicating whether the switching power supply X0 is in a light load state. Referring to this figure, the wake signal WAKE goes low at the timing of detecting a zero cross of the inductor current IL flowing through the synchronous rectifier element M2 (i.e., the timing when the drive of the switch output stage SWO is stopped), as shown at times t21 and t25. The wake signal WAKE also goes high at the timing when the comparison signal Sc2 rises to a high level (i.e., the start timing of the boot voltage detection period T1), as shown at times t23 and t26. The wake signal WAKE is maintained at a high level unless a zero cross of the inductor current IL is detected.

[0098] The deep signal DEEP is a logic signal that indicates whether the switching power supply X0 is in a no-load state (or an ultra-light load state). Referring to this figure, the deep signal DEEP becomes high level when the wake signal WAKE is maintained at a low level over a no-load determination period T2 after a zero crossing of the inductor current IL flowing through the synchronous rectifier element M2 is detected, as shown from time t21 to t22.

[0099] With respect to the operation modes of the semiconductor device 10, when the wake signal WAKE is at a high level, the semiconductor device 10 is in a normal mode. On the other hand, when the wake signal WAKE is at a low level, the semiconductor device 10 transitions to a light load mode (=sleep mode) in which current consumption is lower than in the normal mode. Furthermore, when the wake signal WAKE is at a low level and the deep signal DEEP is at a high level, the semiconductor device 10 transitions to a no-load mode or an ultra-light load mode (=deep sleep mode) in which current consumption is even lower than in the light load mode.

[0100] Next, a method for setting the boot voltage detection period T1 will be described. As described above, the timing at which the comparison signal Sc2 rises to high level is earlier than the timing at which the comparison signal Sc1 rises to high level.

[0101] Therefore, by utilizing the above-described behavior of the comparison signals Sc1 and Sc2, the controller 161 provides a boot voltage detection period T1 before switching the output element M1 to the on state, thereby activating the boot voltage detection circuit 20. For example, in this figure, as shown from time t23 to t24 or from time t26 to t27, the boot voltage detection period T1 is set to a predetermined length (e.g., 100 ns) after the comparison signal Sc2 rises to a high level, and the boot detection control signal BUON is set to a high level.

[0102] However, the method for setting the boot voltage detection period T1 is not limited to the above. For example, it is also possible to establish a system by providing an appropriate delay to a single comparison signal, rather than forming the comparison circuit 12 with two comparators, the first comparator 121 and the second comparator 122.

[0103] Furthermore, a condition for raising the boot detection control signal BUON to a high level may be added that the wake signal WAKE and the deep signal DEEP are both at a high level. In other words, the controller 161 may set the boot voltage detection period T1 when the comparison signal Sc2 (and therefore the wake signal WAKE) rises to a high level in a state in which the deep signal DEEP has risen to a high level as a result of both the output element M1 and the synchronous rectifier element M2 being in an off state for the no-load determination period T2.

[0104] For example, if the load on the switching power supply X0 becomes heavy and the switching period becomes shorter, the boot voltage Vb will not decrease significantly. In such a situation, the above additional condition is no longer met, and the boot detection control signal BUON remains at a low level even after the comparison signal Sc2 rises to a high level, as shown at time t20. When the above additional condition is not met, it is preferable that the boot normal detection signal BOK be fixed at a high level (= the logic level when BOOTUVLO is not detected). However, the above condition is not essential.

[0105] Next, let's focus on the boot voltage detection operation. During the boot voltage detection period T1 from time t23 to t24, the difference between the boot voltage Vb and the switch voltage Vsw (=Vb-Vsw) exceeds the lower limit detection value Vdet. Therefore, the boot normal detection signal BOK is maintained at a high level, and the charge pump 18 does not perform a charging operation of the boot voltage Vb. Thus, if the amount of decrease in the boot voltage Vb is small, the output device M1 does not fail to turn on even if the charging operation of the boot voltage Vb is not performed.

[0106] Meanwhile, during the boot voltage detection period T1 from time t26 to t27, as the boot voltage Vb decreases while the switch output stage SWO is not driven, the difference between the boot voltage Vb and the switch voltage Vsw (Vb-Vsw) falls below the lower limit detection value Vdet. Therefore, the boot normal detection signal BOK falls to a low level. In this figure, the boot normal detection signal BOK falls to a low level after a predetermined delay time d (≦T1) has elapsed since the boot detection control signal BUON rose to a high level. As a result, the charge pump 18 charges the boot voltage Vb before the output element M1 turns on.

[0107] In this figure, the start of charging the boot voltage Vb is held off until the end of a predetermined boot voltage detection period T1 after the boot success detection signal BOK falls to a low level. However, the timing at which charging of the boot voltage Vb starts is not limited to this. For example, the charging operation of the boot voltage Vb may be started without delay when the boot success detection signal BOK falls to a low level.

[0108] Furthermore, after starting charging of the boot voltage Vb in response to the transition of the boot normal detection signal BOK to low level, the controller 161 may maintain the boot detection control signal BUON at high level at least until the boot voltage Vb exceeds the lower limit detection value Vdet, thereby maintaining the boot voltage detection circuit 20 in an operating state and enabling continuous monitoring of whether the boot voltage Vb has recovered.

[0109] Thereafter, when the boot voltage Vb exceeds the lower limit detection value Vdet, the output element M1 is switched to the ON state at time t28, causing the switching operation of the switch output stage SWO to resume.

[0110] Unlike the second embodiment (FIG. 4), the series of reboot operations described above is not performed after a problem occurs in the ON transition of the output device M1, but is performed when it is detected that the difference value (Vb-Vsw) between the boot voltage Vb and the switch voltage Vsw has fallen below the lower limit detection value Vdet. Therefore, compared to the second embodiment (FIG. 4), the ON timing of the output device M1 is less likely to be delayed, and the amount of decrease in the output voltage Vout is suppressed.

[0111] Furthermore, during the charging period of the boot voltage Vb (time t27 to t28), unlike the second embodiment (time t13 to t14 in FIG. 4), the synchronous rectifier device M2 is not turned on to charge the capacitor C4. Therefore, compared to the second embodiment (FIG. 4), it is possible to further suppress the decrease in the output voltage Vout.

[0112] 7 is a diagram showing an example of the configuration of the boot voltage detection circuit 20. The boot voltage detection circuit 20 of this example configuration includes transistors P1 to P7 (e.g., PMOSFETs), transistors N1 to N7 (e.g., NMOSFETs), inverters INV1 to INV4, and resistors R10 to R13.

[0113] The resistor R10 corresponds to a gate resistor. The resistors R11 and R12 correspond to a first resistor and a second resistor, respectively. The transistors P1 and P2 correspond to a first transistor and a second transistor, respectively. The transistors N1 and N2 correspond to a third transistor and a fourth transistor, respectively.

[0114] A first terminal of the resistor R11 is connected to the node to which the boot voltage Vb is applied. A second terminal of the resistor R11 is connected to the source of the transistor P1. A first terminal of the resistor R10 is connected to the node to which the switch voltage Vsw is applied. A second terminal of the resistor R10 is connected to the gate of the transistor P1. A drain of the transistor P1 is connected to the drain of the transistor N1. A source of the transistor P2 and a gate of the transistor N1 are all connected to the node to which the input voltage Vin is applied. A drain of the transistor P2, a source of the transistor N1, and a first terminal of the resistor R12 are all connected to the node to which the node voltage Vx is applied. A second terminal of the resistor R12 is connected to the drain of the transistor N2. A source of the transistor N2 is connected to the ground node.

[0115] The input terminal of the inverter INV1 is connected to the application terminal of the boot detection control signal BUON. The output terminal of the inverter INV1 is connected to the input terminal of the inverter INV2. The output terminal of the inverter INV2 (= application terminal of the gate voltage GP2) is connected to the input terminal of the inverter INV3 and the gate of the transistor P2. The output terminal of the inverter INV3 is connected to the input terminal of the inverter INV4. The output terminal of the inverter INV4 (= application terminal of the gate voltage GN2) is connected to the gate of the transistor N2.

[0116] The drain and gate of transistor N3 and the sources of transistors P5 to P7 are all connected to the terminal to which the input voltage Vin is applied. The source of transistor N3 and the drain of transistor P6 are all connected to the source of transistor P3. The drain of transistor P3 is connected to the source of transistor P4. The drains of transistors P4 and N4, the gates of transistors N6, N7, and P7, and the first terminal of resistor R13 are all connected to the terminal to which the node voltage Vy is applied. The drain of transistor P5 is connected to the drain of transistor N6. The sources of transistors N4 and N6 are all connected to the drain of transistor N5. The sources of transistors N5 and N7, the gate of transistor P5, and the second terminal of resistor R13 are all connected to the ground terminal. The gates of transistors P3, P4, N4, and N5 are all connected to the terminal to which the node voltage Vx is applied. The gate of transistor P6 and the drains of transistors P7 and N7 are all connected to the terminal to which the boot normal detection signal BOK is applied.

[0117] The controller 161 sets the boot detection control signal BUON to a low level when putting the boot voltage detection circuit 20 into an inactive state. Referring to this figure, when the boot detection control signal BUON is at a low level, both gate voltages GP2 and GN2 are at a low level, so that the transistor P2 is in an on state and the transistor N2 is in an off state.

[0118] At this time, the node voltage Vx is fixed at a high level (≈Vin), so the transistor N1 is also turned off. When the boot detection control signal BUON is at a low level, the current path from the application terminal of the boot voltage Vb to the ground terminal via the resistor R11, the transistor P1, the transistor N1, the resistor R12, and the transistor N2 is cut off. As a result, the decrease in the boot voltage Vb is suppressed.

[0119] Transistors P3 to P5 and N4 to N6 form an inverter with hysteresis. Therefore, when node voltage Vx is fixed at a high level (≈Vin), node voltage Vy, which is the inverted logical level of node voltage Vx, is fixed at a low level (≈GND). As a result, boot success detection signal BOK, which is the further inverted logical level of node voltage Vy, is fixed at a high level (=the logical level when BOOTUVLO is not detected).

[0120] In addition, in a situation where the application terminal of the node voltage Vy may become floating in potential, the resistor R13 functions as a pull-down resistor to fix the node voltage Vy to a low level, and ultimately to fix the boot normal detection signal BOK to a high level.

[0121] On the other hand, the controller 161 sets the boot detection control signal BUON to a high level when activating the boot voltage detection circuit 20. Referring to this figure, when the boot detection control signal BUON is at a high level, both gate voltages GP2 and GN2 are at a high level, so that transistor P2 is in an off state and transistor N2 is in an on state.

[0122] In this way, when the boot detection control signal BUON is at a high level, a current path is opened from the application terminal of the boot voltage Vb through the resistor R11, the transistor P1, the transistor N1, the resistor R12, and the transistor N2 to the ground terminal, thereby starting the detection operation of the boot voltage Vb.

[0123] At this time, the node voltage Vx is determined depending on whether the difference between the boot voltage Vb and the switch voltage Vsw (=Vb-Vsw) is higher or lower than the lower limit detection value Vdet. Specifically, when Vb-Vsw>Vdet, a current I1 flows through the resistor R11, and hence a current I2 flows through the resistor R12. Therefore, the node voltage Vx becomes high level (≈I2×R12). On the other hand, when Vb-Vsw<Vdet, the current I1 does not flow through the resistor R11, and hence the current I2 does not flow through the resistor R12. Therefore, the node voltage Vx becomes low level (≈GND).

[0124] If the on-threshold voltage of the transistor P1 is Vgsp, the lower limit detection value Vdet can be expressed as Vdet = Vgsp + I1 × R11. In this way, by combining the on-threshold voltage Vgsp, which has a negative temperature characteristic, with the resistor R11, which has a positive temperature characteristic, the temperature characteristic of the lower limit detection value Vdet can be adjusted to be flat.

[0125] However, the method for setting the lower limit detection value Vdet is not limited to the above, and for example, the lower limit detection value Vdet may be set by using only the diode connection of the transistor P1.

[0126] When the node voltage Vx is at a high level (≈I2×R12), the node voltage Vy is at a low level, and as a result, the boot success detection signal BOK is at a high level. On the other hand, when the node voltage Vx is at a low level (≈GND), the node voltage Vy is at a high level, and as a result, the boot success detection signal BOK is at a low level (=the logical level when BOOTUVLO is detected).

[0127] As mentioned above, the transistors P3 to P5 and N4 to N6 form an inverter with hysteresis, which prevents the boot success detection signal BOK from returning to a high level the moment the boot success detection signal BOK falls to a low level and the charge pump 18 starts charging the boot voltage Vb.

[0128] Other circuit elements will also be briefly explained. Transistor N1 functions as a voltage protection clamper to limit the node voltage Vx to a predetermined upper limit value (≦Vin−Vgsn, where Vgsn is the on-threshold voltage of transistor N1). Since transistor N1 has a high drain-to-backgate withstand voltage, the backgate is connected to the source (a so-called self-suspended circuit).

[0129] Transistor N3 functions as a voltage protection clamper to limit the drain voltage of transistor P3 to a predetermined upper limit (≦Vin−Vgsn, where Vgsn is the on-threshold voltage of transistor N3). Transistor N3 also requires a self-suspended high-voltage element to match the input range of node voltage Vx.

[0130] The transistor P6 is turned off when the node voltage Vx is at a high level (and thus when the boot normal detection signal BOK is at a high level), while the transistor P6 is turned on when the node voltage Vx is at a low level in order to adjust the input range of the hysteresis inverter that receives the node voltage Vx.

[0131] The resistance value of resistor R12 should be set taking into consideration the leakage characteristics of transistor P1 and the voltage fluctuation time of node voltage Vx. If the resistance value of resistor R12 is set too small, the voltage fluctuation of node voltage Vx will become faster, but the current I1 (=I2=Vx / R12) that flows from the application terminal of boot voltage Vb to the ground terminal when boot voltage detection circuit 20 is in an operating state will become larger.

[0132] Boot voltage detection circuit 20 operates only within a certain temperature range (i.e., a temperature range in which a drop in boot voltage Vb may become a problem due to an increase in leakage current from capacitor C4 built into semiconductor device 10). In this way, boot voltage detection circuit 20 has a limited operating range, making it relatively easy to shrink the circuit area.

[0133] In addition, although this diagram illustrates circuit specifications assuming a low-voltage model, it is also possible to apply it to a high-voltage model.

[0134] <Charge Pump> FIG. 8 is a diagram showing an example of the operation of the charge pump 18, and depicts, from top to bottom, the output voltage Vout, the switch voltage Vsw and the boot voltage Vb, the wake signal WAKE, the deep signal DEEP, the comparison signals Sc2 and Sc1, the boot detection control signal BUON, the boot normal detection signal BOK, the charge pump control signal CPON, and the drive clock signal CLK of the charge pump 18.

[0135] As shown in the figure, at time t31, when the boot normal detection signal BOK falls to a low level, the charge pump control signal CPON rises to a high level without delay, which in turn starts pulse driving of the drive clock signal CLK, and the charge pump 18 starts charging the boot voltage Vb.

[0136] On the other hand, at time t32, when the boot normal detection signal BOK rises to a high level, the charge pump control signal CPON immediately falls to a low level, thereby stopping the pulse driving of the drive clock signal CLK and terminating the charging operation of the charge pump 18 to the boot voltage Vb.

[0137] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0138] <1. Comparative Example> Before describing the embodiments of the present disclosure, a comparative example will be described for comparison, which will clarify the problems with the embodiments of the present disclosure.

[0139] 9 is a diagram showing the configuration of a DC / DC converter X according to a comparative example. The DC / DC converter X shown in FIG. 9 is a step-down DC / DC converter that converts an input voltage PVIN into an output voltage Vout. The DC / DC converter X includes a semiconductor device 1, a boot capacitor Cb, an inductor L, and an output capacitor Cout. The boot capacitor Cb, the inductor L, and the output capacitor Cout are elements provided outside the semiconductor device 1.

[0140] The semiconductor device 1 integrates and incorporates a gate drive circuit 9, a high-side transistor HM, and a low-side transistor LM. The gate drive circuit 9 is a circuit for driving the gate of the high-side transistor HM and the gate of the low-side transistor LM.

[0141] The semiconductor device 1 also includes an input voltage terminal Tin, a boot terminal Tb, a switch terminal Tsw, and a ground terminal Tgnd as external terminals for establishing electrical connection with the outside.

[0142] The gate drive circuit 9 includes a logic unit 2 , a level shifter 3 , a high-side driver 4 , a low-side driver 5 , a switch voltage detection unit 6 , and a boot switch 7 .

[0143] The high-side transistor HM and the low-side transistor LM are both configured as NMOS transistors (N-channel MOSFETs). The drain of the high-side transistor HM is connected to the application terminal of the input voltage PVIN via the input voltage terminal Tin. The source of the high-side transistor HM is connected to the drain of the low-side transistor LM. The source of the low-side transistor LM is connected to the application terminal of the ground potential via the ground terminal Tgnd. In other words, the high-side transistor HM and the low-side transistor LM are connected in series between the input voltage PVIN and the ground potential. The high-side transistor HM and the low-side transistor LM form a so-called half bridge.

[0144] A node Nsw, at which the source of the high-side transistor HM and the drain of the low-side transistor LM are connected, is connected to one end of an inductor L via a switch terminal Tsw. The other end of the inductor L is connected to one end of an output capacitor Cout. The other end of the output capacitor Cout is connected to a terminal to which a ground potential is applied. An output voltage Vout is generated at one end of the output capacitor Cout.

[0145] The logic unit 2 has an AND circuit 21 and an AND circuit 22. A high-side gate control input signal HGCTL_IN is input to a first input terminal of the AND circuit 21. A low-side gate signal LG applied to the gate of the low-side transistor LM is input to a second input terminal of the AND circuit 21 as a low-side feedback signal LGFB. The AND circuit 21 takes a logical AND of the high-side gate control input signal HGCTL_IN and the logical inversion of the low-side feedback signal LGFB, and outputs a high-side gate control signal HGCTL.

[0146] The level shifter 3 converts the level of the high-side gate control signal HGCTL into a level-shifted high-side gate control signal HGCTL_LVS in which the boot voltage BOOT is at a high level and the switch voltage SW is at a low level, and outputs the converted signal. Specifically, when the high-side gate control signal HGCTL is at a high level, the level-shifted high-side gate control signal HGCTL_LVS is at a high level, and when the high-side gate control signal HGCTL is at a low level, the level-shifted high-side gate control signal HGCTL_LVS is at a low level.

[0147] The high-side driver 4 generates a high-side gate signal HG to be applied to the gate of the high-side transistor HM based on the input level-shifted high-side gate control signal HGCTL_LVS. Specifically, when the level-shifted high-side gate control signal HGCTL_LVS is at a high level, a high-side gate signal HG of the boot voltage BOOT is applied to the gate of the high-side transistor HM, turning the high-side transistor HM on. When the level-shifted high-side gate control signal HGCTL_LVS is at a low level, a high-side gate signal HG of the switch voltage SW is applied to the gate of the high-side transistor HM, turning the high-side transistor HM off.

[0148] A bootstrap is formed by the boot capacitor Cb and the boot switch 7. One end of the boot capacitor Cb is connected to the switch terminal Tsw. The other end of the boot capacitor Cb is connected to the boot terminal Tb. The boot switch 7, which can be turned on and off, is connected between the input voltage terminal Tin and the boot terminal Tb.

[0149] When the low-side transistor LM is in the on state, the boot switch 7 is controlled to the on state, and the boot capacitor Cb is charged by the input voltage PVIN. When the low-side transistor LM is in the off state, the boot switch 7 is controlled to the off state. The boot voltage BOOT is higher than the switch voltage SW generated at the switch terminal Tsw. Therefore, by applying a high-side gate signal HG, which has been set to the boot voltage BOOT by the high-side driver 4, to the gate of the high-side transistor HM, the high-side transistor HM can be turned on.

[0150] A low-side gate control input signal LGCTL_IN is input to a first input terminal of the AND circuit 22. A detection signal SWFB output from the switch voltage detection unit 6 is input to a second input terminal of the AND circuit 22. The switch voltage detection unit 6 is a circuit that detects the turn-off of the high-side transistor HM by detecting a switch voltage SW that drops when the high-side transistor HM turns off. The AND circuit 22 takes a logical AND of the low-side gate control input signal LGCTL_IN and the logical inversion of the detection signal SWFB, and outputs a low-side gate control signal LGCTL.

[0151] The low-side driver 5 generates a low-side gate signal LG to be applied to the gate of the low-side transistor LM based on the input low-side gate control signal LGCTL. Specifically, when the low-side gate control signal LGCTL is at a high level, a low-side gate signal LG of the input voltage PVIN is applied to the gate of the low-side transistor LM as a high level, turning the low-side transistor LM on. When the low-side gate control signal LGCTL is at a low level, a low-side gate signal LG of ground potential is applied to the gate of the low-side transistor LM as a low level, turning the low-side transistor LM off.

[0152] With this configuration, the high-side transistor HM and the low-side transistor LM are controlled to switch in a complementary manner. Complementary means that when one is on, the other is off. However, a dead time (a period when they are both off at the same time) is provided during the switching transition.

[0153] Here, an operation will be described when the state transitions from the high-side transistor HM in an OFF state and the low-side transistor LM in an ON state to the high-side transistor HM in an ON state and the low-side transistor LM in an OFF state.

[0154] When the high-side gate control input signal HGCTL_IN switches from low to high and the low-side gate control input signal LGCTL_IN switches from high to low, the low-side gate signal LG drops to low (ground potential), the low-side transistor LM is turned off, and both the high-side transistor HM and the low-side transistor LM are turned off, starting the dead time.

[0155] Because the low-side gate signal LG is at a low level, the high-side gate control signal HGCTL output from the AND circuit 21 switches to a high level, and the high-side gate signal HG goes to a high level, which turns on the high-side transistor HM and ends the dead time.

[0156] However, in this configuration, if the delay time between input and output of the level shifter 3 is td1 and the delay time between input and output of the high-side driver 4 is td4, then the dead time = td1 + td4. Therefore, since the dead time is expressed as the sum of the delay times, there is a problem in that it is difficult to minimize the dead time.

[0157] 10 is a diagram showing a configuration of a DC / DC converter Y according to an exemplary embodiment of the present disclosure. Here, differences between the configuration of the DC / DC converter Y and the configuration of the comparative example ( FIG. 9 ) will be mainly described.

[0158] The DC / DC converter Y includes a semiconductor device 1, an inductor L, and an output capacitor Cout. Unlike the comparative example, the boot capacitor Cb is built into the semiconductor device 1. As a result, the semiconductor device 1 does not include a boot terminal Tb.

[0159] The semiconductor device 1 includes a gate drive circuit 9. The gate drive circuit 9 includes a logic unit 2, a level shifter 3, a high-side driver 4, a low-side driver 5, a switch voltage detection unit 6, a boot switch 7, and a level shifter 8.

[0160] The low-side driver 5 has an AND circuit 51, an inverter 52, and a low-side gate signal output unit 53. A low-side gate control signal LGCTL output from the logic unit 2 is input to a first input terminal of the AND circuit 51. A detection signal SWFB output from the switch voltage detection unit 6 is input to a second input terminal of the AND circuit 51. The AND circuit 51 takes a logical AND of the low-side gate control signal LGCTL and a logically inverted version of the detection signal SWFB, and outputs a low-side input signal LG_IN.

[0161] The inverter 52 inverts the level of the input low-side input signal LG_IN and outputs a low-side feedback signal XLGFB, which has a high level when the input voltage PVIN is high and a low level when the ground potential is low.

[0162] The AND circuit 51 and the inverter 52 constitute a level shifter 5A.

[0163] The low-side gate signal output unit 53 inverts the level of the low-side feedback signal XLGFB and outputs a low-side gate signal LG, which is applied to the gate of the low-side transistor LM.

[0164] The level shifter 8 converts the level of the low-side feedback signal XLGFB into a level-shifted low-side feedback signal XLGFB_LVS having a high level equal to the boot voltage BOOT and a low level equal to the switch voltage SW, and outputs the converted signal. Specifically, when the low-side feedback signal XLGFB is at a high level, the level-shifted low-side feedback signal XLGFB_LVS becomes a high level, and when the low-side feedback signal XLGFB is at a low level, the level-shifted low-side feedback signal XLGFB_LVS becomes a low level.

[0165] The high-side driver 4 includes a logic gate 41 , a high-side gate signal output unit 42 , an AND circuit 43 , and a switch 44 .

[0166] The logic gate 41 is configured by an AND circuit. A level-shifted high-side gate control signal HGCTL_LVS output from the level shifter 3 is input to a first input terminal of the logic gate 41. A level-shifted low-side feedback signal XLGFB_LVS is input to a second input terminal of the logic gate 41. The logic gate 41 outputs a high-side input signal HG_IN. The high-side gate signal output unit 42 generates a high-side gate signal HG based on the input high-side input signal HG_IN. The high-side gate signal HG is applied to the gate of the high-side transistor HM.

[0167] Specifically, when the high-side input signal HG_IN is at a high level, the high-side gate signal HG becomes a boot voltage BOOT at a high level, and when the high-side input signal HG_IN is at a low level, the high-side gate signal HG becomes a switch voltage SW at a low level.

[0168] The AND circuit 43 and the switch 44 are provided for a precharge function, which is a function for charging the gate of the high-side transistor HM with electric charge before the high-side transistor HM is turned on, as will be described later.

[0169] The level-shifted high-side gate control signal HGCTL_LVS is input to a first input terminal of the AND circuit 43. The high-side input signal HG_IN is input to a second input terminal of the AND circuit 43. The AND circuit 43 performs a logical AND operation on the level-shifted high-side gate control signal HGCTL_LVS and the logically inverted high-side input signal HG_IN. The switch 44 is connected between the application terminal of the input voltage PVIN and the gate of the high-side transistor HM. The switch 44 is turned on and off in response to the output of the AND circuit 43.

[0170] The operation of the gate drive circuit 9 configured as described above according to the embodiment of the present disclosure will be described. Here, the operation will be described when the high-side transistor HM transitions from an off state and the low-side transistor LM transitions from an on state to an on state and the low-side transistor LM transitions from an off state to an on state. Figure 11 is a timing chart showing an example of the operation in such a transition state.

[0171] 11 shows, from the top to the bottom, the waveforms of the switch voltage SW, the high-side gate control signal HGCTL, the level-shifted high-side gate control signal HGCTL_LVS, the low-side gate control signal LGCTL, the low-side feedback signal XLGFB, the low-side gate signal LG, the level-shifted low-side feedback signal XLGFB_LVS, the high-side input signal HG_IN, and the high-side gate signal HG.

[0172] First, at timing t1, the high-side gate control signal HGCTL switches from low level to high level, and the low-side gate control signal LGCTL switches from high level to low level.

[0173] As a result, the low-side input signal LG_IN switches to low level, and the low-side feedback signal XLGFB switches to high level. The low-side feedback signal XLGFB rises to high level at timing t2, which is delayed by a delay time td3_1 from timing t1. The delay time td3_1 is the delay time between the input and output of the level shifter 5A.

[0174] Because the low-side feedback signal XLGFB switches to high level, the low-side gate signal LG falls from high level to ground potential (low level). There is a delay of delay time td3_2 from timing t2 when the low-side feedback signal XLGFB switches to high level to timing t3 when the low-side gate signal LG falls to ground potential. The delay time td3_2 is the delay time between the input and output of the low-side gate signal output unit 53.

[0175] This turns off the low-side transistor LM, turning it into an OFF state. Therefore, both the high-side transistor HM and the low-side transistor LM are turned off, and the dead time DT begins at timing t3. At this time, the current flowing through the inductor L to the load side flows through the body diode of the low-side transistor LM, causing the switch voltage SW to drop to a negative voltage.

[0176] On the other hand, when the high-side gate control signal HGCTL rises to a high level, the level-shifted high-side gate control signal HGCTL_LVS rises to a high level. The level-shifted high-side gate control signal HGCTL_LVS rises to a high level at timing t4, which is delayed by a delay time td1 from timing t1. The delay time td1 is the delay time between the input and output of the level shifter 3.

[0177] When the level-shifted high-side gate control signal HGCTL_LVS rises to a high level, the output of the AND circuit 43 switches to a high level because the high-side input signal HG_IN is at a low level. This causes the switch 44 to change from an off state to an on state, and charging of the gate of the high-side transistor HM by the input voltage PVIN begins. As a result, the high-side gate signal HG rises to the input voltage PVIN.

[0178] Here, since the low-side feedback signal XLGFB rises to a high level at timing t2, the level-shifted low-side feedback signal XLGFB_LVS rises to a high level. At this time, the level-shifted low-side feedback signal XLGFB_LVS rises at timing t5, which is delayed by a delay time td2 from timing t2. The delay time td2 is the delay time between the input and output of the level shifter 8.

[0179] Then, the high-side input signal HG_IN rises to a high level at timing t6, which is delayed from timing t5 by the delay time td4_1 in the logic gate 41. Then, the output of the AND circuit 43 becomes a low level, the switch 44 is switched to the off state, and charging by the input voltage PVIN is stopped.

[0180] Meanwhile, the high-side gate signal output unit 42 causes the high-side gate signal HG to rise to the boot voltage BOOT (BOOT = PVIN + PVIN). This turns on the high-side transistor HM, and the switch voltage SW rises to the input voltage PVIN. At this time, the dead time DT ends. Note that the delay time td4_2 from timing t6 to timing t7, at which the high-side gate signal HG reaches the boot voltage BOOT, is the delay time in the high-side gate signal output unit 42.

[0181] From the above, the time TH (timings t1 to t7) from when the high-side gate control signal HGCTL rises to a high level until the high-side gate signal HG rises to the boot voltage BOOT is TH = td3_1 + td2 + td4_1 + td4_2. On the other hand, the time TL (timings t1 to t3) from when the low-side gate control signal LGCTL falls to a low level until the low-side gate signal LG falls to a low level is TL = td3_1 + td3_2.

[0182] Therefore, the dead time DT is expressed by adding and subtracting delay times, as follows: DT = TH - TL = td2 + td4_1 + td4_2 - td3_2. This makes it easy to minimize the dead time DT by configuring the circuit so that td2 + td4_1 + td4_2 - td3_2 ≧ 0.

[0183] Furthermore, the precharge function using the input voltage PVIN charges the gate of the high-side transistor HM before the high-side transistor HM is turned on, thereby suppressing charge loss in the boot capacitor Cb, thereby reducing the capacitance of the boot capacitor Cb and making it suitable for use as a boot capacitor Cb built into the semiconductor device 1.

[0184] Note that the constraint condition for the delay time td1 is that, since precharging starts after the delay time td1 has elapsed, it is necessary to satisfy td3_1+td3_2<td1 in order to prevent the high-side transistor HM and the low-side transistor LM from being turned on simultaneously.

[0185] Furthermore, the timing at which the level-shifted high-side gate control signal HGCTL_LVS rises to high level must occur before the timing at which the level-shifted low-side feedback signal XLGFB_LVS rises to high level, otherwise the precharge function will not function. Therefore, it is necessary to satisfy the relationship td1<td3_1+td2. Here, if td1=td2, then td3_1>0, and the condition is automatically met simply by circuit delay. Therefore, it is preferable that the level shifters 3 and 8 have the same configuration so that td1=td2.

[0186] 12 is a diagram showing the configuration of a DC / DC converter Z according to a modification of the present disclosure. This modification differs from the previously described embodiment ( FIG. 10 ) in that a delay circuit 45 is added to the high-side driver 4. The delay circuit 45 is provided between an AND circuit 43 and a switch 44.

[0187] This allows the switch 44 to be turned on and precharge to begin at a timing delayed by a predetermined delay time after the level-shifted high-side gate control signal HGCTL_LVS rises to high level. This makes it possible to adjust the timing at which precharge begins. If td3_1+td3_2, which determines the timing at which the low-side transistor LM is turned off, becomes longer due to not only element delay but also wiring delay, the function of adjusting the timing at which the switch 44 is turned on becomes useful in order to prevent the high-side transistor HM and the low-side transistor LM from being turned on simultaneously.

[0188] <Supplementary Notes> The various embodiments described above will be generally described below.

[0189] For example, a semiconductor device according to one aspect of the present disclosure is configured (first configuration) to include: a first driver configured to drive an output element forming a switch output stage; at least a part of a bootstrap circuit configured to generate a boot voltage higher than a switch voltage output from the switch output stage and supply the generated boot voltage to the first driver; a boot voltage detection circuit configured to detect when the difference between the boot voltage and the switch voltage becomes lower than a lower limit detection value when the output element is in an off state, and to charge the boot voltage; and a controller configured to switch the boot voltage detection circuit between an operating state and an inoperating state.

[0190] In the semiconductor device according to the first configuration described above, the controller may be configured (second configuration) to set a predetermined boot voltage detection period before switching the output element and rectifier element that form the switch output stage from both their off states to their on states, thereby putting the boot voltage detection circuit into an operating state.

[0191] In the semiconductor device according to the second configuration, the controller may be configured (third configuration) to set the voltage detection period when both the output element and the rectifying element are in an off state for a no-load determination period.

[0192] In a semiconductor device having the second or third configuration described above, the controller may be configured (fourth configuration) to maintain the operating state of the boot voltage detection circuit at least until the boot voltage exceeds the lower limit detection value after charging of the boot voltage is started in accordance with the detection result of the boot voltage detection circuit.

[0193] In the semiconductor device according to any one of the second to fourth configurations, the rectifying element may be a synchronous rectifying element configured to be driven complementarily to the output element (fifth configuration).

[0194] The semiconductor device according to the fifth configuration may further include a second driver configured to drive the synchronous rectifier element, and the controller may be configured (sixth configuration) to drive the output element and the synchronous rectifier element complementarily, and to detect that the switch voltage has become higher than a zero-cross detection value when the output element is in an off state and the synchronous rectifier element is in an on state, and turn off the synchronous rectifier element.

[0195] In a semiconductor device according to the fifth or sixth configuration, the boot voltage detection circuit may be configured (seventh configuration) to detect that the difference value between the boot voltage and the switch voltage has become lower than the lower limit detection value and turn on the synchronous rectification element.

[0196] In a semiconductor device having any of the first to sixth configurations, the boot voltage detection circuit may be configured (eighth configuration) to detect that the difference value between the boot voltage and the switch voltage has become lower than the lower limit detection value, and apply a boosted voltage higher than the input voltage input to the switch output stage to the boot voltage application terminal.

[0197] In the semiconductor device according to any one of the first to eighth configurations, the boot voltage detection circuit includes a first resistor and a second resistor, a gate resistor, a P-channel first transistor and a second transistor, and an N-channel third transistor and a fourth transistor, a first end of the first resistor is connected to an application terminal of the boot voltage, a second end of the first resistor is connected to a source of the first transistor, a first end of the gate resistor is connected to an application terminal of the switch voltage, a second end of the gate resistor is connected to a gate of the first transistor, a drain of the first transistor is connected to a drain of the third transistor, and the source of the second transistor and the gate of the third transistor are both connected to the switch output a drain of the second transistor, a source of the third transistor, and a first end of the second resistor are all connected to an application terminal of a node voltage, a second end of the second resistor is connected to the drain of the fourth transistor, and a source of the fourth transistor is connected to a ground terminal; the boot voltage detection circuit outputs a boot normal detection signal according to the node voltage; and the controller turns the second transistor off and the fourth transistor on when the boot voltage detection circuit is in an operating state, and turns the second transistor on and the fourth transistor off when the boot voltage detection circuit is in an inoperable state (ninth configuration).

[0198] Furthermore, for example, a switching power supply disclosed in this specification includes a semiconductor device having any one of the first to ninth configurations, and is configured to drive the switch output stage to generate a desired output voltage from an input voltage (tenth configuration).

[0199] Furthermore, for example, a gate drive circuit (2) according to one aspect of the present disclosure is a gate drive circuit (10) for driving a high-side transistor (HM) and a low-side transistor (LM) connected in series between an application terminal of an input voltage (PVIN) and an application terminal of a ground potential, and includes a first level shifter (5A) configured to be able to input a low-side gate control signal (LGCTL), a low-side gate signal output unit (53) configured to generate a low-side gate signal (LG) for driving the gate of the low-side transistor based on the output of the first level shifter, a second level shifter (8) configured to be able to input the output of the first level shifter, a third level shifter (3) configured to be able to input the high-side gate control signal (HGCTL), and an output of the second level shifter and an output of the third level shifter. an input terminal of the high-side transistor (11) connected to a node (Nsw) at which the high-side transistor and the low-side transistor are connected; and a high-side gate signal output unit (42) configured to generate a high-side gate signal (HG) that drives the gate of the high-side transistor based on the output of the first logic gate, wherein the first level shifter is configured to output the input voltage as a high level, the second level shifter and the third level shifter are configured to output a boot voltage (BOOT) generated at a second end of a boot capacitor (Cb) having a first end connected to a node (Nsw) at which the high-side transistor and the low-side transistor are connected, as a high level, and the high-side gate signal output unit is configured to be able to apply the boot voltage as the high-side gate signal to the gate of the high-side transistor (11th configuration).

[0200] In addition, in the above-mentioned eleventh configuration, a switch voltage detection unit (6) configured to detect a drop in the switch voltage (SW) occurring at the node (Nsw) may be further provided, and the first level shifter (5A) may have a second logic gate (51) configured to be able to input the low-side gate control signal (LGCTL) and the detection signal (SWFB) of the switch voltage detection unit, and an inverter (52) configured to be able to input the output of the second logic gate (twelfth configuration).

[0201] Furthermore, the eleventh or twelfth configuration may further include a third logic gate (43) configured to be able to input the output of the third level shifter (3) and the output of the first logic gate (41), and a switch (44) connected between an application terminal of a power supply voltage (PVIN) and the gate of the high-side transistor (HM), and configured to be controlled to be turned on and off based on the output of the third logic gate (a thirteenth configuration).

[0202] In the thirteenth configuration, it is preferable that the power supply voltage is the input voltage (PVIN) (fourteenth configuration).

[0203] Furthermore, in the thirteenth or fourteenth configuration, the delay time between input and output in the first level shifter (5A) may be td3_1, the delay time in the low-side gate signal output unit (53) may be td3_2, and the delay time between input and output in the third level shifter (3) may be td1, such that td3_1+td3_2<td1 holds (a fifteenth configuration).

[0204] Furthermore, in any of the above-mentioned thirteenth to fifteenth configurations, the delay time between input and output in the first level shifter (5A) may be td3_1, the delay time between input and output in the third level shifter (3) may be td1, and the delay time between input and output in the second level shifter (8) may be td2, such that td1<td3_1+td2 holds (a sixteenth configuration).

[0205] In the sixteenth configuration, the second level shifter (8) and the third level shifter (3) may have the same configuration (seventeenth configuration).

[0206] In addition, any of the thirteenth to seventeenth configurations may further include a delay circuit (45) connected between the third logic gate (43) and the switch (44) (eighteenth configuration).

[0207] Furthermore, a semiconductor device (1) according to one aspect of the present disclosure has a gate drive circuit (10) of any one of the thirteenth to eighteenth configurations and the boot capacitor (Cb) built in (a nineteenth configuration).

[0208] Moreover, a DC / DC converter (Y) according to one aspect of the present disclosure includes a gate drive circuit (10) of any one of the first to eighth configurations described above, the high-side transistor (HM), the low-side transistor (LM), an inductor (L) having a first end connected to a node (Nsw) at which the high-side transistor and the low-side transistor are connected, and an output capacitor (Cout) connected to a second end of the inductor (20th configuration).

[0209] <Other Modifications> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0210] For example, the present disclosure is not limited to application to DC / DC converters, but can also be applied to driving transistors in inverter circuits that perform DC / AC conversion.

[0211] REFERENCE SIGNS LIST 1 semiconductor device 2 logic section 3 level shifter 4 high-side driver 5 low-side driver 6 switch voltage detection section 7 boot switch 8 level shifter 9 gate drive circuit 10 semiconductor device (power supply control IC) 11 error amplifier 12 comparison circuit 121 first comparator 122 second comparator 13 on-time setting circuit 14 ripple generation circuit 15 adder circuit 16 drive control circuit 161 controller 162, 165 level shifter 163, 164 driver 17 reference voltage generation circuit 18 charge pump 19 zero-cross detection circuit 20 boot voltage detection circuit 21 AND circuit 22 AND circuit 41 logic gate 42 high-side gate signal output section 43 AND circuit 44 switch 45 delay circuit 5A level shifter 51 AND circuit 52 inverter 53 Low-side gate signal output section BS Switch BST Bootstrap circuit C1 to C4 Capacitor Cb Boot capacitor Cout Output capacitor CMP Comparator HM High-side transistor INV1 to INV4 Inverter L1, L Inductor LM Low-side transistor M1 Output element (NMOSFET) M2 Synchronous rectifier element (NMOSFET) N1 to N7 Transistor (NMOSFET) P1 to P7 Transistor (PMOSFET) R1 to R4, R10 to R13 Resistor SWO Switch output stage Tb Boot terminal Tgnd Ground terminal Tin Input voltage terminal Tsw Switch terminal X0 Switching power supply X, Y, Z DC / DC converter

Claims

1. a first driver configured to drive an output element forming a switched output stage; At least a part of a bootstrap circuit configured to generate a boot voltage higher than a switch voltage output from the switch output stage and supply the boot voltage to the first driver; a boot voltage detection circuit configured to detect when a difference between the boot voltage and the switch voltage becomes lower than a lower limit detection value when the output element is in an off state, and to charge the boot voltage; a controller configured to switch the boot voltage detection circuit between an active state and an inactive state; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein the controller provides a predetermined boot voltage detection period before switching the output element from an off state to an on state of the output element and the rectifier element that form the switch output stage, thereby putting the boot voltage detection circuit into an operating state.

3. The semiconductor device according to claim 2 , wherein the controller provides the voltage detection period when both the output element and the rectifier element are in an off state for a no-load determination period.

4. 3. The semiconductor device according to claim 2, wherein the controller maintains the operating state of the boot voltage detection circuit at least until the boot voltage exceeds the lower limit detection value after charging of the boot voltage is started in accordance with a detection result of the boot voltage detection circuit.

5. 3. The semiconductor device according to claim 2, wherein the rectifying element is a synchronous rectifying element configured to be driven complementarily to the output element.

6. a second driver configured to drive the synchronous rectification element; 6. The semiconductor device according to claim 5, wherein the controller drives the output element and the synchronous rectifier element complementarily, and detects that the switch voltage becomes higher than a zero-cross detection value when the output element is in an off state and the synchronous rectifier element is in an on state, and turns off the synchronous rectifier element.

7. 6. The semiconductor device according to claim 5, wherein said boot voltage detection circuit detects that said difference value between said boot voltage and said switch voltage becomes lower than said lower limit detection value, and turns on said synchronous rectification element.

8. 2. The semiconductor device according to claim 1, wherein the boot voltage detection circuit detects that the difference value between the boot voltage and the switch voltage becomes lower than the lower limit detection value and applies a boosted voltage higher than the input voltage input to the switch output stage to the boot voltage application terminal.

9. the boot voltage detection circuit includes first and second resistors, a gate resistor, first and second P-channel transistors, and third and fourth N-channel transistors; a first end of the first resistor is connected to the boot voltage application end; a second end of the first resistor is connected to a source of the first transistor; a first end of the gate resistor is connected to the switch voltage application terminal; a second end of the gate resistor is connected to a gate of the first transistor; a drain of the first transistor is connected to a drain of the third transistor; a source of the second transistor and a gate of the third transistor are both connected to an application terminal of an input voltage input to the switch output stage, a drain of the second transistor, a source of the third transistor, and a first end of the second resistor are all connected to an application terminal of a node voltage, a second end of the second resistor is connected to a drain of the fourth transistor; The source of the fourth transistor is connected to the ground terminal. the boot voltage detection circuit outputs a boot normal detection signal corresponding to the node voltage; 2. The semiconductor device according to claim 1, wherein the controller turns off the second transistor and turns on the fourth transistor when the boot voltage detection circuit is in an operating state, and turns on the second transistor and turns off the fourth transistor when the boot voltage detection circuit is in a non-operating state.

10. 10. A switching power supply comprising the semiconductor device according to claim 1, which drives the switch output stage to generate a desired output voltage from an input voltage.