Signal processing circuit

Abstract

A signal processing circuit according to the present invention comprises: a capacitor that is connected to a signal line that connects to a sensor, the capacitor being connected in series with the sensor; and a variable resistance circuit that is connected in parallel to the capacitor. A high-pass filter through which signals of a cutoff frequency or higher pass is configured by the variable resistance circuit and capacitor, the variable resistance circuit is set to a first resistance value when passing a target signal having a peak component on a time axis, and the cutoff frequency at the first resistance value is 1 / 10 or less in relation to the frequency of the peak component.

Description

signal processing circuit

[0001] The present invention relates to a signal processing circuit that processes a signal output from a sensor.

[0002] Patent Document 1 describes a pressure sensor that includes a piezoelectric element, a circuit unit, and a receiving unit. The receiving unit deforms in response to a pressing operation by a user. The piezoelectric element is attached to the receiving unit. The piezoelectric element deforms in response to the deformation of the receiving unit. The piezoelectric element outputs a charge corresponding to the amount of deformation of the piezoelectric element. The circuit unit converts the charge generated by the piezoelectric element into a voltage. When the circuit unit detects a voltage equal to or greater than a preset threshold, it determines that a pressing operation has been performed on the receiving unit.

[0003] The piezoelectric element in Patent Document 1 generates a positive charge when deformed by a pressing operation. The piezoelectric element is an elastic body. Therefore, after generating a positive charge, the piezoelectric element generates a negative charge of the opposite polarity due to rebound. The circuit unit changes the magnitude of the threshold value to prevent the voltage of the opposite polarity caused by the rebound of the pressing operation from being erroneously detected as a pressing operation.

[0004] International Publication No. 2019 / 069786

[0005] The configuration disclosed in Patent Document 1 cannot handle cases where the bounce described above becomes even larger. Furthermore, the bounce described in Patent Document 1 is not the only factor that can cause reverse polarity components. For example, as shown below, reverse polarity components can occur when a circuit has high-pass characteristics. Figure 1A shows the time domain waveform (voltage waveform) of an input signal after passing through a high-pass filter. Figure 1B shows the time domain waveform (voltage waveform) of an input signal before passing through a high-pass filter.

[0006] When an input signal passes through a high-pass filter, low-frequency components of the input signal are removed. Therefore, the high-pass filter distorts the time-domain waveform of the input signal. For example, as shown in FIG. 1A , a high-pass filter may output a negative voltage component (a negative voltage between time t1 and time t2 in FIG. 1A ) in response to a single-pulse wave-shaped input signal having a peak component on the positive time axis. Furthermore, a high-pass filter may output a positive voltage component (a positive voltage between time t3 and time t4 in FIG. 1A ) in response to a single-pulse wave-shaped input signal having a negative voltage component. Hereinafter, a negative voltage component generated in response to a positive voltage input signal or a positive voltage component generated in response to a negative voltage input signal is referred to as an overshoot.

[0007] An object of the present invention is to provide a signal processing circuit capable of suppressing overshoot.

[0008] A signal processing circuit according to one embodiment of the present invention comprises: a capacitor connected to a signal line connected to a sensor and connected in series with the signal line; and a variable resistance circuit connected in parallel with the signal line, wherein the variable resistance circuit and the capacitor form a high-pass filter that passes signals having a cutoff frequency or higher, and the variable resistance circuit is set to a first resistance value when passing a target signal having a peak component on the time axis, and the cutoff frequency at the first resistance value is 1 / 10 or less of the frequency of the peak component.

[0009] The signal processing circuit according to the present invention can suppress overshoot.

[0010] FIG. 1A is a diagram showing a time domain waveform (voltage waveform) of an input signal after passing through a high-pass filter. FIG. 1B is a diagram showing a time domain waveform (voltage waveform) of an input signal before passing through the high-pass filter. FIG. 2 is a diagram showing an example of the circuit configuration of a sensor system SS1. FIG. 3 is a cross-sectional view of a piezoelectric sensor 1. FIG. 4 is a diagram showing the relationship between the user's pressing amount and the voltage output from a charge-voltage conversion circuit 20. FIG. 5 is a diagram showing the circuit configuration of a high-pass filter 21. FIG. 6 is a diagram showing the relationship between the ratio of the cutoff frequency fc to the signal frequency and the ratio of the overshoot peak voltage OSP to the signal peak voltage SGP. FIG. 7 is a diagram showing a variable resistor circuit 211. FIG. 8 is a diagram showing a reference voltage generation circuit 25a included in a signal processing circuit 2a according to Modification 1. FIG. 9 is a diagram showing an AD conversion circuit 24b included in a signal processing circuit 2b according to Modification 2. FIG. 10 is a diagram showing a high-pass filter 21c included in a signal processing circuit 2c according to Modification 3.

[0011] First Embodiment A signal processing circuit 2 according to one embodiment of the present invention will now be described with reference to the drawings. Fig. 2 is a diagram showing an example of the circuit configuration of a sensor system SS1. Fig. 3 is a cross-sectional view of a piezoelectric sensor 1. Fig. 4 is a diagram showing the relationship between the amount of pressure applied by a user and the voltage output from a charge-voltage conversion circuit 20. Fig. 5 is a diagram showing the circuit configuration of a high-pass filter 21.

[0012] As shown in FIG. 2, the sensor system SS1 includes a piezoelectric sensor 1, a signal processing circuit 2, and an MPU (Micro Processing Unit) 3.

[0013] In this embodiment, the piezoelectric sensor 1 is a pressure sensor that detects a pressure operation. The piezoelectric sensor 1 is attached to, for example, a touch panel display of an electronic device such as a smartphone. The piezoelectric sensor 1 generates an electric charge according to the amount of change in the pressure applied by the user. Specifically, the user presses the touch panel display. The touch panel display deforms in response to the pressure. As a result, the piezoelectric sensor 1 attached to the touch panel display deforms (expands or contracts) in response to the pressure and generates an electric charge.

[0014] As shown in FIG. 3, the piezoelectric sensor 1 includes a first electrode 10, a piezoelectric film 11, and a second electrode 12.

[0015] In the following description, as shown in Figure 3, the vertical direction of the paper surface is defined as the Z-axis direction (thickness direction of the piezoelectric sensor 1), the left-right direction of the paper surface is defined as the X-axis direction, and the direction perpendicular to the Z-axis direction and the X-axis direction is defined as the Y-axis direction.

[0016] As shown in FIG. 3 , the piezoelectric film 11 has a first principal surface SF1 and a second principal surface SF2 aligned in the Z-axis direction. In this embodiment, the piezoelectric film 11 is, for example, a film whose main material is a chiral polymer. The chiral polymer is, for example, polylactic acid (PLA), particularly poly(L-lactic acid) (PLLA) or poly(D-lactic acid) (PDLA). Polylactic acid is a chiral polymer whose main chain has a helical structure. Polylactic acid exhibits piezoelectricity when oriented in a predetermined axial direction. This piezoelectricity is represented by the piezoelectric tensor d14.

[0017] The piezoelectric film 11 is attached to the touch panel display so that the stretching direction forms an angle of approximately 45° with the X-axis and Y-axis directions. As a result, polarization occurs due to expansion and contraction of the touch panel display in the X-axis or Y-axis direction, and an output is generated in the piezoelectric sensor 1. In other words, the piezoelectric film 11 deforms in response to the deformation (expansion or contraction) of the touch panel display, generating an electric charge.

[0018] The extension direction does not necessarily form an angle of exactly 45 degrees with respect to the X-axis direction and the Y-axis direction. For example, the touch panel display may be attached so that the extension direction forms an angle of about 45±10 degrees with respect to the X-axis direction and the Y-axis direction.

[0019] The first electrode 10 is a signal electrode. The first electrode 10 is attached to the first main surface SF1 with an adhesive or the like (not shown). The first electrode 10 covers the first main surface SF1. The first electrode 10 is an organic electrode made of, for example, ITO (indium tin oxide) or ZnO (zinc oxide). Alternatively, the first electrode 10 is a metal film formed by vapor deposition or plating, or a printed electrode film made of silver paste or the like.

[0020] The second electrode 12 is a reference voltage electrode. The second electrode 12 is connected to a reference voltage source. The second electrode 12 is attached to the second main surface SF2 with an adhesive or the like (not shown). The second electrode 12 covers the second main surface SF2. The second electrode 12 is an organic electrode made of, for example, ITO (indium tin oxide) or ZnO (zinc oxide). Alternatively, the second electrode 12 is a metal film formed by vapor deposition or plating, or a printed electrode film made of silver paste or the like.

[0021] 2, the signal processing circuit 2 is disposed between the piezoelectric sensor 1 and the MPU 3. The signal processing circuit 2 converts the charge output from the piezoelectric sensor 1 into a voltage signal and performs various signal processing on the voltage signal obtained by the conversion. As shown in FIG. 2, the signal processing circuit 2 includes a charge-voltage conversion circuit 20, a high-pass filter 21, an amplifier circuit 22, a capacitor 23, an AD conversion circuit 24, and a reference voltage generation circuit 25.

[0022] As shown in Fig. 2, the charge-voltage conversion circuit 20 is disposed between the piezoelectric sensor 1 and the high-pass filter 21. The charge-voltage conversion circuit 20 converts the charge detected by the piezoelectric sensor 1 into a voltage. The magnitude and polarity of the charge generated in the piezoelectric film 11 are proportional to the differential value of the amount of pressure. As shown in Fig. 4, when the user presses the touch panel display, the polarity of the voltage output from the charge-voltage conversion circuit 20 becomes positive. On the other hand, when the user releases the pressure on the touch panel display, the polarity of the voltage output from the charge-voltage conversion circuit 20 becomes negative.

[0023] As shown in FIG. 2 , the high-pass filter 21 is disposed between the charge-voltage conversion circuit 20 and the amplifier circuit 22. As shown in FIG. 5 , the high-pass filter 21 includes a capacitor Cd1 and a variable resistance circuit 211. The capacitor Cd1 is connected in series with the signal line. The capacitor Cd1 has a capacitance value Cc1. The variable resistance circuit 211 is connected in parallel with the signal line. The variable resistance circuit 211 has a resistance value Rc. The high-pass filter 21 passes signals having a cutoff frequency fc or higher, which is determined by the resistance value Rc of the variable resistance circuit 211 and the capacitance value Cc1 of the capacitor Cd1. The cutoff frequency fc of the high-pass filter 21 is expressed as "fc = 1 / (2π × Rc × Cc1)" using the resistance value Rc and the capacitance value Cc1. Therefore, the high-pass filter 21 passes signals having a frequency equal to or higher than "1 / (2π × Rc × Cc1)."

[0024] The high-pass filter 21 receives a single-shot or burst-shaped signal. A single-shot or burst-shaped signal may contain one or more frequency components. In this case, in this embodiment, the frequency of the peak component in the signal over time is defined as follows: the largest frequency component among one or more frequency components contained in the signal that is processed by the high-pass filter 21.

[0025] It should be noted that the signal processed by the high-pass filter 21 may contain a DC component. In such cases, the frequency of the peak component in time in the signal is defined as follows: the largest frequency component among one or more frequency components contained in the signal after the DC component has been removed from the signal processed by the high-pass filter 21.

[0026] 2, the amplifier circuit 22 is connected in series to the signal line. The amplifier circuit 22 amplifies the signal that has passed through the high-pass filter 21. The amplifier circuit 22 outputs the amplified signal to the capacitor 23.

[0027] 2, the capacitor 23 is disposed between the amplifier circuit 22 and the AD conversion circuit 24. The capacitor 23 is a DC-cut capacitor that removes DC components contained in the signal. The capacitor 23 has a capacitance Cc23.

[0028] 2, the AD conversion circuit 24 is disposed between the capacitor 23 and the MPU 3. The AD conversion circuit 24 converts the analog signal output from the capacitor 23 into a digital signal (AD conversion).

[0029] The reference voltage generating circuit 25 generates a reference voltage PV. The reference voltage generating circuit 25 is electrically connected to the piezoelectric sensor 1 and the high-pass filter 21, as shown in FIG.

[0030] The MPU 3 performs various processes, for example, by reading out programs stored in a storage device (not shown) into a work memory (not shown). The various processes include processes for determining whether a user has pressed the touch panel display. The MPU 3 is electrically connected to the AD conversion circuit 24. The MPU 3 receives a signal that has been AD converted from the AD conversion circuit 24. For example, when the MPU 3 detects a signal value equal to or greater than a predetermined threshold value (stored in a storage device, etc.), the MPU 3 determines that a user has pressed the touch panel display. The MPU 3 may be, for example, a CPU (Central Processing Unit) or the like.

[0031] The signal processing circuit 2 according to this embodiment can suppress overshoots occurring in a signal (such as the overshoot shown in FIG. 1A). A detailed description will be given below with reference to the drawings. FIG. 6 is a diagram showing the relationship between the ratio of the cutoff frequency fc to the signal frequency and the ratio of the overshoot peak voltage OSP to the signal peak voltage SGP. In FIG. 6, the horizontal axis represents the ratio of the cutoff frequency fc to the signal frequency. In FIG. 6, the vertical axis represents the ratio of the overshoot peak voltage OSP to the signal peak voltage SGP.

[0032] In this embodiment, the signal peak voltage SGP is defined as "the voltage when the difference DF1 between the voltage (signal) output from the piezoelectric sensor 1 and the reference voltage PV is the largest" (see FIGS. 1A and 1B). Also, the overshoot peak voltage OSP is defined as "the voltage when the difference DF2 between the voltage (signal) and the reference voltage PV is the largest in the overshoot."

[0033] 1B shows an example of a signal input to the high-pass filter 21. When such a signal is subjected to signal processing by the high-pass filter 21, an overshoot as shown in FIG. 1A may occur. In this case, the peak voltage OSP of the overshoot may exceed a predetermined threshold value (the threshold value used by the MPU 3 to determine whether a pressing operation has occurred). As a result, the overshoot may cause the MPU 3 to erroneously determine that a pressing operation has been performed by the user when no pressing operation has been performed by the user.

[0034] The inventors of the present invention therefore investigated the causes of overshoot. As a result, they discovered that "overshoot changes depending on the relationship between the cutoff frequency fc of the high-pass filter 21 and the frequency of the input signal." The high-pass filter 21 removes spectral components with frequencies below the cutoff frequency fc. This distorts the signal waveform on the time axis. Here, in a signal with a peak component on the time axis, the spectral components spread to a frequency band lower than the fundamental frequency. Increasing the cutoff frequency fc increases the amount of low-frequency components removed. This significantly distorts the signal waveform on the time axis. This increases the peak voltage OSP of the overshoot.

[0035] Therefore, the inventors of the present invention considered that it would be sufficient to lower the cutoff frequency fc to a level that would avoid erroneous determination by the MPU 3. Through experiments, the inventors found that erroneous determination by the MPU 3 could be avoided if the ratio of the overshoot peak voltage OSP to the signal peak voltage SGP was 0.2 or less. Furthermore, the inventors of the present invention also found that when the ratio of the cutoff frequency fc to the frequency of the signal peak component was 1 / 10 or less (hereinafter referred to as condition A), the overshoot peak voltage was 0.2 or less relative to the signal peak voltage (see FIG. 6). The cutoff frequency fc of the high-pass filter 21 is fc = 1 / (2π × Rc × Cc1). Therefore, the inventors considered a method of lowering the cutoff frequency fc by increasing the resistance value Rc.

[0036] Therefore, in the present invention, by making the resistance value Rc variable, the overshoot is suppressed and a practical operating time as a sensor is realized. This will be described in detail below with reference to the drawings. Figure 7 shows the variable resistance circuit 211.

[0037] In this embodiment, the variable resistance circuit 211 is a switched capacitor having switches S1 and S2 and a capacitor Cd2, as shown in FIG. 7 . Both the switches S1 and S2 correspond to the first switch in the present invention. The capacitor Cd2 is connected in parallel to the signal line. The capacitor Cd2 has a capacitance value Cc2. The switch S1 is disposed between the signal line and the capacitor Cd2. The switch S2 is connected in parallel to the capacitor Cd2.

[0038] The resistance value Rc of the variable resistance circuit 211 is an equivalent resistance value of the switched capacitor determined based on the switching frequency fs used to switch the switches S1 and S2. Specifically, the equivalent resistance value Rc of the switched capacitor is "Rc = 1 / (fs × Cc2)." Therefore, as the switching frequency fs increases, the equivalent resistance value Rc of the switched capacitor decreases. Note that the on / off switching of the switches S1 and S2 is performed by a processing device (not shown), such as a CPU (Central Processing Unit).

[0039] When the high-pass filter 21 passes a target signal, the variable resistance circuit 211 increases the resistance value Rc (decreases the switching frequency fs). Specifically, the variable resistance circuit 211 increases the resistance value Rc (first resistance value) so that the cutoff frequency fc of the high-pass filter 21 is equal to or less than 1 / 10 of the frequency of the peak component on the signal's time axis (satisfies condition A). In this case, as shown in FIG. 6 , the ratio of the overshoot peak voltage OSP to the signal peak voltage SGP is equal to or less than 0.2. This reduces the possibility that the MPU 3 will erroneously determine that a user pressing operation has been performed when no user pressing operation has been performed due to an overshoot.

[0040] Here, a waiting time of approximately the time constant τ is required from when the sensor system SS1 is started until the high-pass filter 21 can perform the desired operation. Specifically, in order for the circuit of the sensor system SS1 to perform the desired operation, the capacitor Cd1 must be charged to an amount of charge determined by the DC voltage biased across the capacitor Cd1 and the capacitance of the capacitor Cd1. To reach this state, the sensor system SS1 requires a waiting time of approximately "time constant τ = Rc × Cc" after the sensor system SS1 is started. In other words, by reducing the time constant τ, the waiting time during use can be reduced.

[0041] For example, in this embodiment, the capacitance value Cc1 of the capacitor Cd1 is 0.1 μF, and the capacitance value Cc2 of the capacitor Cd2 is 6.5 pF. The switching frequency fs of the switched capacitor is, for example, 5 kHz. In this case, the cutoff frequency fc of the high-pass filter 21 is approximately 0.05 Hz. Therefore, the cutoff frequency fc is 1 / 10 or less of the input signal frequency of 1 Hz. Here, the time constant τ of the high-pass filter 21 is expressed as "τ = 1 / (2π × fc)." Therefore, when the cutoff frequency fc of the high-pass filter 21 is 0.05 Hz, the time constant τ is approximately 3 seconds. In other words, the user must wait at least 3 seconds before using the sensor system SS1 in a manner that allows it to function as desired. This may cause the user to feel uncomfortable when using the sensor system SS1.

[0042] Therefore, the variable resistance circuit 211 sets the resistance value Rc to a second resistance value lower than the first resistance value (increases the switching frequency fs) when the target signal is not being passed through the high-pass filter 21 (when the signal is not being processed). A time when the target signal is not being passed is, for example, when the user turns on the power of an electronic device such as a smartphone (when the sensor system SS1 is started). This makes the time constant τ of the high-pass filter 21 shorter than when the target signal is being passed through the high-pass filter 21.

[0043] For example, if the switching frequency fs of the switched capacitor is 500 kHz, which is 100 times the 5 kHz mentioned above, the time constant τ will be 1 / 100, or approximately 30 msec. Therefore, the time required for a user to start using the sensor system SS1 after activating it will be approximately 30 msec. 30 msec is a time so short that it is almost imperceptible to humans. Therefore, the user is unlikely to feel any discomfort. In other words, the signal processing circuit 2 according to this embodiment can achieve practical operation as the sensor system SS1.

[0044] The variable resistance circuit 211 may have any configuration as long as it can change the resistance value Rc. For example, the variable resistance circuit 211 may be a variable resistor.

[0045] The piezoelectric sensor 1 does not necessarily have to be a pressure sensor.

[0046] 1A and 1B, the signal input to the signal processing circuit 2 is a single-wave signal. However, the signal processing circuit 2 may also input a burst-wave signal containing two or more consecutive waves. In this case, the signal processing circuit 2 can suppress overshoots that occur in the burst-wave input signal.

[0047] The high-pass filter 21 may process a signal having multiple frequencies. In this case, the cutoff frequency fc may be equal to or less than 1 / 10 of the lowest frequency among the multiple frequencies included in the signal. Examples of cases where a signal has multiple frequencies include when the sensor system SS1 includes multiple piezoelectric sensors 1, or when the speed at which the piezoelectric sensors 1 deform changes as the user changes the speed at which they press the touch panel display.

[0048] 1B is an example of the signal input to the high-pass filter 21. Therefore, the signal input to the high-pass filter 21 does not necessarily have to be the same as the signal shown in FIG.

[0049] (Modification 1) A signal processing circuit 2a according to Modification 1 will now be described with reference to the drawings. Fig. 8 is a diagram showing a reference voltage generating circuit 25a provided in the signal processing circuit 2a according to Modification 1.

[0050] In this modification, the signal processing circuit 2a includes a reference voltage generation circuit 25a instead of the reference voltage generation circuit 25. As shown in FIG. 8 , the reference voltage generation circuit 25a includes a reference voltage source Pa, a buffer amplifier Ap1a, and a switch S1a (second switch). The reference voltage source Pa generates a reference voltage. The buffer amplifier Ap1a is disposed between the output of the reference voltage source Pa and a circuit that supplies the reference voltage. For example, the buffer amplifier Ap1a is connected in series with the variable resistance circuit 211 and the reference voltage source Pa. The switch S1a is connected in parallel with the buffer amplifier Ap1a. The buffer amplifier Ap1a increases the current supplied from the reference voltage source Pa.

[0051] As the switching frequency fs increases, the charging rate of the capacitor Cd2 increases. At this time, the charging rate of the capacitor Cd2 may exceed the current supply capacity of the reference voltage source Pa. In this case, it may be impossible to charge the capacitor Cd2 within the target charging time (e.g., 30 msec). In other words, it may be difficult to achieve practical operation of the sensor system SS1. Therefore, when the resistance value Rc of the variable resistance circuit 211 is set to the second resistance value, the buffer amplifier Ap1 is turned on and the switch S1a is turned off. This increases the current supplied from the reference voltage source Pa, reducing the possibility that the charging rate of the capacitor Cd2 will exceed the current supply capacity of the reference voltage source Pa.

[0052] On the other hand, when the resistance value Rc of the variable resistance circuit 211 is set to the first resistance value (when the switching frequency fs is low), the buffer amplifier Ap1a is set to off and the switch S1a is set to on. In other words, when there is no need to increase the current input to the capacitor Cd2, the buffer amplifier Ap1a is set to off. This prevents unnecessary power consumption in the buffer amplifier Ap1a.

[0053] 8 is just an example, and the circuit configuration of the reference voltage generating circuit 25a does not necessarily have to be the circuit configuration shown in FIG.

[0054] (Modification 2) A signal processing circuit 2b according to Modification 2 will now be described with reference to the drawings. Fig. 9 is a diagram showing an AD conversion circuit 24b provided in the signal processing circuit 2b according to Modification 2.

[0055] In this modification, the signal processing circuit 2b includes an AD conversion circuit 24b instead of the AD conversion circuit 24. As shown in FIG. 9, the AD conversion circuit 24b includes a sample-and-hold circuit 24b1 and an integration circuit 24b2.

[0056] The sample-and-hold circuit 24b1 is arranged on the input side of the integrating circuit 24b2. In this modification, the sample-and-hold circuit 24b1 is a switched capacitor (hereinafter referred to as a switched capacitor according to modification 2) having switches S1b, S2b, S3b, and S4b and a capacitor Cd1b. The switches S1b and S3b are connected in series to the signal line. The switches S2b and S4b are connected in parallel to the signal line. The switches S1b and S2b are arranged on the input side of the capacitor Cd1b. The switches S3b and S4b are arranged on the output side of the capacitor Cd1b. The capacitor Cd1b is arranged between the switches S1b and S3b. The capacitor Cd1b has a capacitance value Ccb.

[0057] The sample-and-hold circuit 24b1 performs signal sample-and-hold processing by switching the switches S1b, S2b, S3b, and S4b. Specifically, the sample-and-hold circuit 24b1 turns on the switches S1b and S4b and turns off the switches S2b and S3b. This causes the sample-and-hold circuit 24b1 to charge the capacitor Cd1b and perform sample-and-hold. Then, the sample-and-hold circuit 24b1 turns off the switches S1b and S4b and turns on the switches S2b and S3b. This causes the sample-and-hold signal to be output to the integrating circuit 24b2. The switches S1b, S2b, S3b, and S4b are switched on and off based on the switching frequency fsb.

[0058] The sample-and-hold circuit 24b1 configured as described above is equivalent to connecting the signal line on the output side of the capacitor 23 shown in FIG. 2 in parallel to a reference voltage via a resistor. In other words, the sample-and-hold circuit 24b1 is equivalent to the variable resistor circuit of the present invention, and the sample-and-hold circuit 24b1 and the capacitor 23 form a high-pass filter (hereinafter referred to as the high-pass filter according to Modification 2). In this case, the resistance value Rb of the high-pass filter according to Modification 2 is the equivalent resistance value of a switched capacitor (hereinafter referred to as the switched capacitor according to Modification 2) determined based on the switching frequency fsb used to switch the switches S1b, S2b, S3b, and S4b and the capacitance value Ccb of the capacitor Cd1b. Specifically, the resistance value Rb is "Rb = 1 / (fsb × Ccb)."

[0059] The high-pass filter according to the second modification passes signals with a frequency equal to or higher than a cutoff frequency fcb, which is determined by the equivalent resistance value Rb of the switched capacitor according to the second modification and the capacitance value Ccb of the capacitor Cd1b. Specifically, the cutoff frequency fcb is expressed as "fcb = 1 / (2π × Rb × Ccb)." In this case, similar to the high-pass filter 21, the high-pass filter according to the second modification significantly deforms the signal waveform on the time axis. As a result, the overshoot peak voltage OSP increases. Therefore, when passing a target signal through the high-pass filter according to the second modification, the resistance value Rb is set so that the cutoff frequency fcb is equal to or lower than 1 / 10 of the signal frequency. For example, in this modification, the capacitance value Cc23 of the capacitor 23 is 0.082 pF, and the capacitance value Ccb of the capacitor Cd1b is 3.5 pF. The switching frequency fsb of the switched capacitor according to the second modification is, for example, approximately 5 kHz. In this case, the cutoff frequency fcb of the high-pass filter according to the second modification is approximately 0.034 Hz, which is less than 1 / 10 of the input signal frequency of 1 Hz. Therefore, the ratio of the overshoot peak voltage OSP to the signal peak voltage SGP is 0.2 or less (see FIG. 6). As a result, like the signal processing circuit 2 according to the first embodiment, the signal processing circuit 2b can reduce the possibility of the MPU 3 making an erroneous determination.

[0060] Here, the time constant τb of the high-pass filter according to Modification 2 is expressed as "τb = 1 / (2π × fcb)" and is approximately 4.7 seconds. Therefore, similar to the signal processing circuit 2 according to the first embodiment, the user may feel uncomfortable when starting up the sensor system SS1.

[0061] Therefore, the signal processing circuit 2b sets the switching frequency fsb higher when not passing the target signal than when passing the target signal. For example, the signal processing circuit 2b sets the switching frequency fsb to 500 kHz, which is about 100 times higher. In this case, the time constant τb is about 47 msec, which is 1 / 100 of 4.7 sec. 47 msec is a time so short that it is almost imperceptible to humans. Therefore, the user is unlikely to feel any discomfort. In other words, the signal processing circuit 2b according to the second modification can achieve practical operation as the sensor system SS1.

[0062] The integrating circuit 24b2 includes an amplifier Ap1b and a capacitor Cd2b. In the integrating circuit 24b2, the amplifier Ap1b is arranged between the switch S3b and the MPU 3. The capacitor Cd2b is connected in parallel with the amplifier Ap1b. The amplifier Ap1b and the capacitor Cd2b perform a process of integrating the signal input to the integrating circuit 24b2.

[0063] 9 is an example, and the circuit configuration of the AD conversion circuit 24b does not necessarily have to be the circuit configuration shown in FIG.

[0064] (Modification 3) A signal processing circuit 2c according to Modification 3 will now be described with reference to the drawings. Fig. 10 is a diagram showing a high-pass filter 21c provided in the signal processing circuit 2c according to Modification 3.

[0065] 10, the signal processing circuit 2c has a high-pass filter 21c instead of the high-pass filter 21. The high-pass filter 21c has a variable resistance circuit 211c instead of the variable resistance circuit 211.

[0066] The variable resistance circuit 211c includes a switch S1c, a buffer amplifier Ap1c, and a fixed resistor R1c. The fixed resistor R1c is connected in parallel to the signal line. The switch S1c (third switch) and the buffer amplifier Ap1c are connected in parallel to the fixed resistor R1c. The buffer amplifier Ap1c is connected in series to the switch S1c. The fixed resistor R1c may be a variable resistor, a switched capacitor, or the like.

[0067] In this modification, the variable resistance circuit 211c turns off the switch S1c when the high-pass filter 21c passes the target signal. In this case, the resistance value Rcc of the variable resistance circuit 211c is determined by the resistance value (first resistance value) of the fixed resistor R1c. In this modification, the resistance value of the fixed resistor R1c satisfies condition A (the resistance value when the cutoff frequency of the high-pass filter 21c is 1 / 10 or less of the signal frequency). Therefore, as shown in FIG. 6 , the ratio of the overshoot peak voltage OSP to the signal peak voltage SGP is 0.2 or less. Therefore, similar to the signal processing circuit 2, it is possible to reduce the possibility of the MPU 3 making an erroneous determination.

[0068] On the other hand, the high-pass filter 21c turns on the switch S1c and sets the buffer amplifier Ap1c to on except when passing the target signal. This bypasses the fixed resistor R1c. In this case, the high-pass filter 21c changes the resistance Rcc from a value (first resistance) determined primarily by the resistance of the fixed resistor R1c to a value (second resistance) determined by the actual resistance of the entire circuit including the buffer amplifier Ap1c and wiring. The actual resistance of the entire circuit including the buffer amplifier Ap1c and wiring is lower than the resistance of the fixed resistor R1c. Therefore, the time required to charge the capacitor Cd2 is shorter than when the switch S1c is turned off. In other words, similar to the signal processing circuit 2, the signal processing circuit 2c enables the sensor system SS1 to achieve practical operation.

[0069] The buffer amplifier Ap1c is set to off when the switch S1c is turned off (when the resistance value Rcc is set to the first resistance value), thereby preventing unnecessary power consumption in the buffer amplifier Ap1c.

[0070] It should be noted that the variable resistance circuit 211c does not need to include the buffer amplifier Ap1c if the current supply amount of the reference voltage source is sufficient to achieve a target time constant (for example, 100 msec).

[0071] The variable resistance circuit 211c may have a variable resistor whose resistance value is variable or a switched capacitor instead of the fixed resistor R1c. In this case, the signal processing circuit 2c can achieve the same effect as when it has the fixed resistor R1c.

[0072] The variable resistance circuits 211 and 211c may be set to the second resistance value lower than the first resistance value at any timing other than when the target signal is passed, and therefore may remain at the first resistance value at times other than when the target signal is passed.

[0073] The variable resistance circuits 211 and 211c may be set to a second resistance value lower than the first resistance value at all times except when passing a target signal.

[0074] The configurations of the signal processing circuits 2, 2a to 2c may be combined arbitrarily.

[0075] The present invention has the following structure:

[0076] (1) A signal processing circuit comprising: a capacitor connected to a signal line connected to a sensor and connected in series with the signal line; and a variable resistance circuit connected in parallel with the signal line, wherein the variable resistance circuit and the capacitor form a high-pass filter that passes signals having a frequency equal to or higher than a cutoff frequency, and the variable resistance circuit is set to a first resistance value when passing a target signal having a peak component on a time axis, and the cutoff frequency at the first resistance value is 1 / 10 or less of the frequency of the peak component.

[0077] (2) The signal processing circuit according to (1), wherein the variable resistance circuit is set to a second resistance value lower than the first resistance value at any time when the target signal is not passing through.

[0078] (3) The signal processing circuit according to (1), wherein the variable resistance circuit is always set to a second resistance value lower than the first resistance value except when passing the target signal.

[0079] (4) The signal processing circuit according to (2) or (3), wherein the variable resistance circuit includes a switched capacitor having a capacitor and a first switch, and the variable resistance circuit changes the first resistance value to the second resistance value by increasing a switching frequency of the first switch.

[0080] (5) The signal processing circuit according to (2) or (3), wherein the variable resistance circuit is a variable resistor.

[0081] (6) The signal processing circuit according to (4) or (5), wherein the signal processing circuit includes: a buffer amplifier connected in series with the variable resistance circuit and a reference voltage source; and a second switch connected in parallel with the buffer amplifier; the buffer amplifier is set to off when set to the first resistance value, and is set to on when set to the second resistance value; and the second switch is set to on when set to the first resistance value, and is set to off when set to the second resistance value.

[0082] (7) The signal processing circuit according to (2) or (3), wherein the variable resistance circuit includes a resistor and a third switch connected in parallel to the resistor, and the first resistance value is changed to the second resistance value by turning on the third switch.

[0083] (8) The signal processing circuit according to (7), wherein the variable resistance circuit further includes a buffer amplifier connected in series to the third switch, and the buffer amplifier is set to off when set to the first resistance value, and is set to on when set to the second resistance value.

[0084] (9) The signal processing circuit according to any one of (1) to (8), further comprising: a charge-voltage conversion circuit that converts the charge of the sensor into a voltage; and an amplifier circuit that amplifies the signal; and the capacitor and the variable resistance circuit are disposed between the charge-voltage conversion circuit and the amplifier circuit.

[0085] (10) The signal processing circuit according to any one of (1) to (8), further comprising: an amplifier circuit that amplifies the signal; and an AD conversion circuit having an integrating circuit that AD converts the signal, wherein the variable resistance circuit is disposed on the input side of the integrating circuit.

[0086] (11) The signal processing circuit according to any one of (1) to (10), wherein the sensor is a pressure sensor that detects a pressure operation.

[0087] 1: Piezoelectric sensor 2, 2a, 2b, 2c: Signal processing circuit 20: Charge-voltage conversion circuit 21, 21c: High-pass filter 22: Amplification circuit 23: Capacitor 24, 24b: AD conversion circuit 211, 211c: Variable resistance circuit Cd1, Cd1b, Cd2, Cd2b: Capacitors Rb, Rc, Rcc: Resistance values ​​fc, fcb: Cut-off frequencies fs, fsb: Switching frequencies τ, τb: Time constants

Claims

1. a capacitor connected to a signal line connected to the sensor and connected in series with the signal line; a variable resistance circuit connected in parallel to the signal line; Equipped with a high-pass filter that passes signals having a frequency equal to or higher than a cutoff frequency is formed by the variable resistance circuit and the capacitor; The variable resistance circuit includes: a first resistance value is set when a target signal having a peak component on the time axis is passed; the cutoff frequency at the first resistance value is 1 / 10 or less of the frequency of the peak component; A peak voltage of an overshoot occurring in the target signal is 0.2 or less with respect to a peak voltage of the target signal. Signal processing circuit.

2. the variable resistance circuit is set to a second resistance value lower than the first resistance value whenever the target signal is not passing through; 2. The signal processing circuit according to claim 1.

3. the variable resistance circuit is always set to a second resistance value lower than the first resistance value except when the variable resistance circuit is passing the target signal; 2. The signal processing circuit according to claim 1.

4. the variable resistance circuit includes a switched capacitor having a capacitor and a first switch; the variable resistance circuit changes the first resistance value to the second resistance value by increasing a switching frequency of the first switch; 4. The signal processing circuit according to claim 2.

5. The variable resistance circuit is a variable resistor.

4. The signal processing circuit according to claim 2.

6. The signal processing circuit includes: a buffer amplifier connected in series to the variable resistance circuit and a reference voltage source; A second switch connected in parallel to the buffer amplifier; Contains The buffer amplifier is When set to the first resistance value, it is set to off; When the resistance is set to the second resistance value, the resistance is set to ON. The second switch is When the resistance is set to the first resistance value, the resistance is set to ON; When the resistance is set to the second resistance value, the resistance is set to off.

5. The signal processing circuit according to claim 4.

7. The signal processing circuit includes: a buffer amplifier connected in series to the variable resistance circuit and a reference voltage source; A second switch connected in parallel to the buffer amplifier; Contains The buffer amplifier is When set to the first resistance value, it is set to off; When the resistance is set to the second resistance value, the resistance is set to ON. The second switch is When the resistance is set to the first resistance value, the resistance is set to ON; When the resistance is set to the second resistance value, the resistance is set to off.

6. The signal processing circuit according to claim 5.

8. The variable resistance circuit includes: A resistor; a third switch connected in parallel with the resistor; Contains by turning on the third switch, the first resistance value is changed to the second resistance value; 4. The signal processing circuit according to claim 2.

9. the variable resistance circuit further includes a buffer amplifier connected in series with the third switch, The buffer amplifier is When set to the first resistance value, it is set to off; When the resistance is set to the second resistance value, the resistance is set to ON.

9. The signal processing circuit according to claim 8.

10. The signal processing circuit includes: a charge-voltage conversion circuit for converting the charge of the sensor into a voltage; an amplifier circuit for amplifying the signal; It further comprises: the capacitor and the variable resistance circuit are disposed between the charge-voltage conversion circuit and the amplifier circuit; 4. The signal processing circuit according to claim 1.

11. The signal processing circuit includes: an amplifier circuit for amplifying the signal; an AD conversion circuit having an integration circuit for AD-converting the signal; It further comprises: The variable resistance circuit is disposed on the input side of the integrating circuit.

4. The signal processing circuit according to claim 1.

12. The sensor is a pressure sensor that detects a pressing operation.

4. The signal processing circuit according to claim 1.