Memory device using semiconductor element

Abstract

This memory device includes a page composed of a plurality of memory cells arranged on a substrate in a columnar configuration as seen in a plan view, and hole groups generated by the impact ionization phenomenon are retained inside a channel semiconductor layer by controlling a voltage applied to a first gate conductor layer, a second gate conductor layer, a first impurity region and a second impurity region of each memory cell included in the page. The first impurity layer of the memory cell is connected to a source line, the second impurity layer is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to a word line, the other is connected to a plate line, and a page write operation, a page erase operation, and a page read operation are performed by applying a voltage to the source line, bit line, word line, and plate line. The hole groups formed by the impact ionization phenomenon are retained inside the channel semiconductor layer at a first timing during the page write operation, and a page post-write processing operation of annihilating a surplus hole group among the hole groups is performed at a second timing.

Description

[Technical field]

[0001] The present invention relates to a memory device using a semiconductor element. [Background technology]

[0002] In recent years, in the development of LSI (Large Scale Integration) technology, there is a demand for higher integration and higher performance of memory elements.

[0003] Memory elements are becoming increasingly dense and highly functional. Examples include DRAMs (Dynamic Random Access Memories, see Non-Patent Document 2) that use SGTs (Surrounding Gate Transistors, see Patent Document 1 and Non-Patent Document 1) as selection transistors and connect a capacitor, PCMs (Phase Change Memories, see Non-Patent Document 3) that connect a resistance change element, RRAMs (Resistive Random Access Memories, see Non-Patent Document 4), and MRAMs (Magneto-resistive Random Access Memories, see Non-Patent Document 5) that change resistance by changing the direction of magnetic spins using a current.

[0004] There are also DRAM memory cells (see Patent Document 2, Non-Patent Documents 6 to 10) that are composed of one MOS transistor without a capacitor. For example, a source-drain current of an N-channel MOS transistor generates holes and electrons in a channel by impact ionization, and some or all of the holes are held in the channel to write logical memory data "1". Then, the holes are removed from the channel to write logical memory data "0". In this memory cell, there are random memory cells with "1" written and memory cells with "0" written for a common selected word line. When an on-voltage is applied to a selected word line, the floating body channel voltage of the selected memory cell connected to this selected word line fluctuates greatly due to the capacitive coupling between the gate electrode and the channel. In this memory cell, the issues are to improve the decrease in the operating margin caused by the fluctuation in the floating body channel voltage, and to improve the decrease in data retention characteristics caused by removing some of the holes, which are signal charges stored in the channel.

[0005] There is also a Twin-Transistor MOS transistor memory element in which one memory cell is formed using two MOS transistors in the SOI layer (see, for example, Patent Documents 3 and 4, and Non-Patent Document 11). In these elements, the N + The N layer is formed in contact with the insulating layer on the substrate side. + The floating body channels of the two MOS transistors are electrically separated by the layer. The group of holes, which is the signal charge, is stored only in the floating body channel of one of the MOS transistors. The other MOS transistor acts as a switch to read out the group of holes of the signal stored in the other MOS transistor. In this memory cell, the group of holes, which is the signal charge, is also stored in the channel of one MOS transistor, so as with the memory cell consisting of one MOS transistor mentioned above, the issue is to improve the decrease in operating margin, or to improve the decrease in data retention characteristics caused by removing some of the group of holes, which is the signal charge stored in the channel.

[0006] There is also a memory 111 that does not have a capacitor and is composed of MOS transistors, as shown in FIG. 5 (see Patent Document 5 and Non-Patent Document 12). As shown in FIG. 5(a), a floating body semiconductor body 102 is provided on a SiO2 layer 101 of an SOI substrate. N + N connected to layer 103 and bit line BL + There is a layer 104. And N + a first gate insulating layer 109a connected to the layer 103 and covering the floating body semiconductor body 102; + A second gate insulating layer 109b is connected to the layer 104 and the first gate insulating layer 109a, and covers the floating body semiconductor body 102 via a slit insulating film 110. A first gate conductor layer 105a covers the first gate insulating layer 109a and is connected to a plate line PL, and a second gate conductor layer 105b covers the second gate insulating layer 109b and is connected to a word line WL. An insulating layer 110 is provided between the first gate conductor layer 105a and the second gate conductor layer 105b. This forms a memory cell 111 of a DFM (Dynamic Flash Memory). Note that the source line SL is connected to the N + layer 104, and the bit line BL is + It may be configured to connect to layer 103.

[0007] As shown in FIG. 5(a), for example, N + Zero voltage on layer 103, N +A positive voltage is applied to the layer 104, the first N-channel MOS transistor region made of the floating body semiconductor body 102 covered with the first gate conductor layer 105a is operated in the saturation region, and the second N-channel MOS transistor region made of the floating body semiconductor body 102 covered with the second gate conductor layer 105b is operated in the linear region. As a result, in the second N-channel MOS transistor region, no pinch-off point exists, and an inversion layer 107b is formed over the entire surface. The inversion layer 107b formed under the second gate conductor layer 105b connected to the word line WL acts as a substantial drain of the first N-channel MOS transistor region. As a result, a current between the first N-channel MOS transistor region and the second N-channel MOS transistor region is generated. Semiconductor body The electric field is maximum in the boundary region, and impact ionization occurs in this region. Then, as shown in Fig. 5(b), the electrons among the electron-hole group generated by the impact ionization are removed from the floating body semiconductor body 102, and a part or all of the hole group 106 is retained in the floating body semiconductor body 102, thereby performing a memory write operation. This state becomes logical storage data "1".

[0008] Then, as shown in FIG. 5(c), for example, a positive voltage is applied to the plate line PL, a zero voltage is applied to the word line WL and the bit line BL, and a negative voltage is applied to the source line SL, to remove the hole group 106 from the floating body semiconductor matrix 102, and an erase operation is performed. This state becomes logical storage data "0". Then, in data read, the voltage applied to the first gate conductor layer 105a connected to the plate line PL is set to be higher than the threshold voltage when the logical storage data is "1" and lower than the threshold voltage when the logical storage data is "0", so that a characteristic is obtained in which no current flows even if the voltage of the word line WL is increased when reading logical storage data "0", as shown in FIG. 5(d). This characteristic allows a significant expansion of the operating margin compared to memory cells. In this memory cell, the channels of the first and second N-channel MOS transistor regions, whose gates are the first gate conductor layer 105a connected to the plate line PL and the second gate conductor layer 105b connected to the word line WL, are connected by the floating body semiconductor body 102, so that the voltage fluctuation of the floating body semiconductor body 102 when a selection pulse voltage is applied to the word line WL is greatly suppressed. This greatly improves the problem of the decrease in the operating margin in the memory cell described above, or the decrease in data retention characteristics caused by the removal of a part of the hole group, which is the signal charge accumulated in the channel. Further characteristic improvements are required for this memory element in the future. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 2-188966 [Patent Document 2] Japanese Patent Application Publication No. 3-171768 [Patent Document 3] US2008 / 0137394 A1 [Patent Document 4] US2003 / 0111681 A1 [Patent Document 5] Patent No. 7057032 [Non-patent literature]

[0010]

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[0011] In dynamic flash memory cells, it is required to perform stable page write operations and to eliminate malfunctions of sense amplifier circuits. [Means for solving the problem]

[0012] In order to solve the above problems, a memory device using a semiconductor element according to the present invention comprises: A memory device in which a page is constituted by a plurality of memory cells arranged in a row direction on a substrate in a plan view, and a plurality of pages are arranged in a column direction, The memory cells included in each page include A semiconductor body standing vertically or extending horizontally on the substrate; First electrodes at both ends of the semiconductor body impurity region And the second impurity region and, The first impurity region and the second impurity region a gate insulating layer in contact with a side surface of the semiconductor body between the gate insulating layer and the semiconductor body; a first gate conductor layer covering a part or the whole of the gate insulating layer; a second gate conductor layer adjacent to the first gate conductor layer and in contact with a side surface of the gate insulating layer; the first impurity region, the second impurity region, and the first gate conductor layer; and controlling a voltage applied to the second gate conductor layer to perform a page write operation, a page erase operation, and a page read operation; During the page write operation, at a first time Semiconductor bodya page write post-processing operation is performed at a second time subsequent to the first time to eliminate a surplus hole group among the hole groups. This is characterized by the above (first invention).

[0013] In the first aspect of the present invention, during the page write operation, Semiconductor body The voltage of the first impurity region and the second impurity region a first data-retaining voltage that is higher than one or both of the voltages During the page erase operation, voltages applied to the first impurity region, the second impurity region, the first gate conductor layer, and the second gate conductor layer are controlled to Semiconductor body The hole group of Semiconductor body a second data-retaining voltage lower than the first data-retaining voltage. This is characterized by the above (second aspect of the invention). In the first aspect of the present invention, the first impurity region is connected to a source line, the second impurity region is connected to a bit line, and if one of the first gate conductor layer and the second gate conductor layer is connected to a word line, the other is connected to a plate line; controlling voltages applied to the source line, the bit line, the word line, and the plate line to perform the page write operation, the page erase operation, the page read operation, and the page write post-processing operation; This is characterized by the above (third aspect of the invention).

[0014] In the third aspect of the present invention, applying a pulse voltage to at least one of the source line, the bit line, the word line, and the plate line during a page write post-processing operation; This is characterized by the above (fourth aspect of the invention).

[0015] The above Third In the present invention, during the page write post-processing operation, the same voltages as those during the page read operation are applied to the bit lines, the word lines, and the plate lines. This is characterized by the above (fifth aspect).

[0016] The above Third In the invention, during the page write post-processing operation, a voltage higher than that during the page read operation is applied to at least one of the bit line, the word line, and the plate line. This is characterized by the above (sixth aspect of the invention).

[0017] The above Fourth In the invention, during the page write post-processing operation, the pulse voltage is applied at least once to the selected page. This is characterized by the above (seventh aspect of the invention).

[0018] The above Third In the present invention, the word lines and the plate lines are arranged in parallel in a plan view, the bit lines are disposed in a direction perpendicular to the word lines and the plate lines in a plan view; It is characterized by ( Eighth invention).

[0019] The above Third In the present invention, the first gate conductor layer or the second gate conductor layer and the Semiconductor body A first gate capacitance between the first gate conductor layer or the second gate conductor layer and the Semiconductor body and a second gate capacitance between the first and second gate electrodes. This is characterized by the above (ninth aspect of the invention).

[0020] The above Third In the present invention, in a plan view, the source lines are separated for each of the memory cells arranged in the column direction and are arranged in parallel to the word lines and the plate lines. This is characterized by the above (10th aspect of the invention).

[0021] The above Third In the present invention, in a plan view, the source line is commonly provided to the adjacent pages. This is characterized by the above (11th aspect of the invention).

[0022] The above Third In the present invention, at least two of the plate lines of the adjacent pages are commonly arranged in plan view. It is characterized by ( 12th invention ). In the third invention, the first gate conductor layer is composed of a split gate conductor layer separated into two, and the split gate conductor layers are located on both sides of the second gate conductor layer, performing the page write operation, the page erase operation, the page read operation, and the page write post-processing operation; This is characterized by the above (13th aspect of the invention). In the third invention, the second gate conductor layer is composed of a split gate conductor layer separated into two, and the split gate conductor layers are located on both sides of the first gate conductor layer, performing the page write operation, the page erase operation, the page read operation, and the page write post-processing operation; This is characterized by the above (fourteenth aspect of the invention).

[0023] In the first aspect of the present invention, Semiconductor body is a P-type semiconductor layer, and the first impurity region and the second impurity region are N-type semiconductor layers. It is characterized by ( 15th invention).

[0024] In the first invention, at least two sets of the pages are selectively erased during the page erase operation. It is characterized by ( 16th invention).

[0025] The above Third In the present invention, the word lines and the plate lines are connected to a row decoder circuit, a row address is input to the row decoder circuit, and the page is selected according to the row address. It is characterized by ( 17th invention).

[0026] In the third invention, the bit line is connected to a sense amplifier circuit, the sense amplifier circuit is connected to a column decoder circuit, a column address is input to the column decoder circuit, and the sense amplifier circuit is selectively connected to an input / output circuit according to the column address. It is characterized by ( 18th invention). [Brief description of the drawings]

[0027] [Figure 1] 1 is a structural diagram of a memory device having an SGT according to a first embodiment. [Figure 2A] 4A and 4B are diagrams illustrating a page write operation mechanism of the memory device according to the first embodiment. [Figure 2B] 4A and 4B are diagrams illustrating a page write operation mechanism of the memory device according to the first embodiment. [Figure 3A] 11A and 11B are diagrams illustrating a page write post-processing operation of the memory device according to the first embodiment. [Figure 3B] 11A and 11B are diagrams illustrating a page write post-processing operation of the memory device according to the first embodiment. [Figure 3C] 11A and 11B are diagrams illustrating a page write post-processing operation of the memory device according to the first embodiment. [Figure 4A] 4A to 4C are diagrams illustrating a page erase operation mechanism of the memory device according to the first embodiment. [Figure 4B] 4A to 4C are diagrams illustrating a page erase operation mechanism of the memory device according to the first embodiment. [Figure 4C] 4A to 4C are diagrams illustrating a page erase operation mechanism of the memory device according to the first embodiment. [Figure 4D] 4A to 4C are diagrams illustrating a page erase operation mechanism of the memory device according to the first embodiment. [Figure 4E] 4A to 4C are diagrams illustrating a page erase operation mechanism of the memory device according to the first embodiment. [Diagram 5] FIG. 1 is a diagram for explaining a conventional dynamic flash memory. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a memory device using a semiconductor element (hereinafter, referred to as a dynamic flash memory) according to an embodiment of the present invention will be described with reference to the drawings.

[0029] (First embodiment) The structure and operation mechanism of a dynamic flash memory cell according to a first embodiment of the present invention will be described with reference to Figures 1 to 4. The structure of the dynamic flash memory cell will be described with reference to Figure 1. Then, the page write operation mechanism will be described with reference to Figure 2, the page write post-processing operation will be described with reference to Figure 3, and the page erase operation mechanism will be described with reference to Figure 4.

[0030] 1 shows the structure of a dynamic flash memory cell according to the first embodiment of the present invention. Silicon semiconductor pillars 2 (hereinafter, referred to as "Si pillars") having a P-type or i-type (intrinsic) conductivity type are formed on a substrate (an example of a "semiconductor body" in the claims). N-type semiconductor pillars, one of which serves as a source and the other as a drain, are arranged at upper and lower positions within the pillars. + Layers 3a, 3b (the "first impurity region ", "Second impurity region This is an example of a "source / drain" structure. + The part of the Si pillar 2 between the layers 3a and 3b Semiconductor body 7. This Semiconductor body A first gate insulating layer 4a (one example of the "first gate insulating layer" in the claims) and a second gate insulating layer 4b (one example of the "second gate insulating layer" in the claims) are formed to surround the gate insulating layer 7. The first gate insulating layer 4a and the second gate insulating layer 4b are formed by insulating the N + The first gate insulating layer 4a and the second gate insulating layer 4b are in contact with or adjacent to the layers 3a and 3b, respectively. A first gate conductor layer 5a (one example of the "first gate conductor layer" in the claims) and a second gate conductor layer 5b (one example of the "second gate conductor layer" in the claims) are formed to surround the first gate insulating layer 4a and the second gate insulating layer 4b, respectively. The first gate conductor layer 5a and the second gate conductor layer 5b are separated by an insulating layer 6. + Between layers 3a and 3b Semiconductor body 7 is a first gate insulating layer surrounded by a first gate insulating layer 4a Semiconductor body 7a and the second gate insulating layer 4b. Semiconductor body This results in the formation of the N +layers 3a, 3b, Semiconductor body 7, a dynamic flash memory cell 10 is formed, which is made up of a first gate insulating layer 4a, a second gate insulating layer 4b, a first gate conductor layer 5a, and a second gate conductor layer 5b. + The layer 3a is connected to the source line SL (one example of the "source line" in the claims) and to the N + The layer 3b is connected to a bit line BL (an example of a "bit line" in the claims), the first gate conductor layer 5a is connected to a plate line PL (an example of a "plate line" in the claims), and the second gate conductor layer 5b is connected to a word line WL (an example of a "word line" in the claims). It is desirable to have a structure in which the first gate capacitance (an example of a "first gate capacitance" in the claims) of the first gate conductor layer 5a to which the plate line PL is connected is larger than the second gate capacitance (an example of a "second gate capacitance" in the claims) of the second gate conductor layer 5b to which the word line WL is connected.

[0031] 2A and 2B show a page write operation (one example of the "page write operation" in the claims) of the dynamic flash memory cell according to the first embodiment of the present invention. FIG. 2A(a) shows the mechanism of the write operation, and FIG. 2A(b) shows the bit line BL, source line SL, plate line PL, word line WL, and floating body FB. Semiconductor body 7 shows the operation waveforms of the dynamic flash memory cell 100 at time T0 in the erased state “0”; Semiconductor body The voltage at 7 is V FB The bit line BL, source line SL, and word line WL are connected to Vss, and the plate line PL is connected to V PLL Here, for example, Vss is 0V and V PLL Next, between times T1 and T2, the bit line BL is changed from Vss to V BLH For example, if Vss is 0V, Semiconductor body The voltage at 7 is the bit line BL Semiconductor body 7, V FB "0"+β BL ×VBLH It becomes.

[0032] Next, the write operation of the dynamic flash memory cell will be described with reference to FIG. 2A(a) and FIG. 2A(b). Between times T3 and T4, the word line WL is changed from Vss to V WLH As a result, the second gate conductor layer 5b connected to the word line WL Semiconductor body The threshold voltage of the "0" erase of the second N-channel MOS transistor region surrounding 7 is Vt WL When set to "0", the voltage on the word line WL rises from Vss to Vt WL Up to "0", the word line WL Semiconductor body The second capacitive coupling with 7 Semiconductor body The voltage at 7 is V FB "0"+β BL ×V BLH +β WL ×Vt WL The voltage of the word line WL becomes Vt WL When the temperature rises to "0" or higher, the inner circumference of the second gate conductor layer 5b Semiconductor body A circular inversion layer 12b is formed in the MOSFET 7, and the word line WL and Semiconductor body 7 and interrupts the second capacitive coupling.

[0033] 2A(a) and (b), the write operation of the dynamic flash memory cell will be described. At times T3 to T4, a voltage of, for example, V PLL A fixed voltage of 2V is input, and the second gate conductor layer 5b connected to the word line WL is set to, for example, V WLH As a result, as shown in FIG. 2A(a), the inner circumference of the first gate conductor layer 5a to which the plate line PL is connected Semiconductor body 7, a ring-shaped inversion layer 12a is formed, and a pinch-off point 13 exists in the inversion layer 12a. As a result, the first N-channel MOS transistor region having the first gate conductor layer 5a operates in the saturation region. On the other hand, the second N-channel MOS transistor region having the second gate conductor layer 5b connected to the word line WL operates in the linear region. As a result, the inner circumference of the second gate conductor layer 5b connected to the word line WL Semiconductor body No pinch-off point exists at 7, and an inversion layer 12b is formed over the entire inner circumference of the gate conductor layer 5b. The inversion layer 12b formed over the entire inner circumference of the second gate conductor layer 5b connected to the word line WL acts as a substantial drain of the first N-channel MOS transistor region. As a result, a current is generated between the first N-channel MOS transistor region having the first gate conductor layer 5a and the second N-channel MOS transistor region having the second gate conductor layer 5b connected in series. Semiconductor body The electric field is maximized in the first boundary region of the gate electrode 7, and impact ionization occurs in this region. This region is on the source side as viewed from the second N-channel MOS transistor region having the second gate conductor layer 5b to which the word line WL is connected, and therefore this phenomenon is called source-side impact ionization. This source-side impact ionization phenomenon causes the N + N connected to bit lines from layer 3a + The electrons flow toward the N-type layer 3b. The accelerated electrons collide with the Si lattice atoms, and the kinetic energy of the collision generates electron-hole pairs. Some of the generated electrons flow toward the first gate conductor layer 5a and the second gate conductor layer 5b, but most of them flow toward the N-type layer 3b connected to the bit line BL. + It flows into layer 3b (not shown).

[0034] Then, as shown in FIG. 2A(c), the generated hole group 9 (one example of the “hole group” in the claims) Semiconductor body 7 is the majority carrier, Semiconductor body 7 is charged to a positive bias. N connected to the source line SL + Layer 3a is at 0V, so Semiconductor body 7 is the N connected to the source line SL + Layer 3a and Semiconductor body 7 is charged to the built-in voltage Vb (about 0.7 V) of the PN junction between Semiconductor body When 7 is charged to a positive bias, the threshold voltages of the first N-channel MOS transistor region and the second N-channel MOS transistor region become lower due to the substrate bias effect.

[0035] Next, the write operation of the dynamic flash memory cell will be described with reference to FIG. 2A(b). At times T6 to T7, the voltage of the word line WL is V WLH At that time, the word line WL and Semiconductor body 7, the second capacitive coupling is performed, but the voltage V WLH but, Semiconductor body The threshold voltage Vt of the second N-channel MOS transistor region when the voltage of 7 is Vb WL The inversion layer 12b blocks this second capacitive coupling until the bit line WL becomes equal to or lower than "1". Semiconductor body 7, the effective capacitive coupling is WL Only when it falls below "1" and drops to Vss. Semiconductor body The voltage at 7 is Vb-β WL ×Vt WL "1". Here, Vt WL "1" is the Vt WL Lower than "0", and Semiconductor body Voltage change β of 7 WL ×Vt WL The “1” is suppressed softly.

[0036] Next, the page write operation of the dynamic flash memory cell will be described with reference to FIG. 2A(b). At times T8 to T9, the bit line BL is set to V BLH The bit line BL drops to Vss. Semiconductor body 7 is capacitively coupled, so ultimately Semiconductor body 7 “1” write voltage V FB “1” becomes: V FB "1" = Vb-β WL ×Vt WL “1”-β BL ×V BLH (1) Here, the bit line BL and Semiconductor body Coupling ratio β with 7 BL As a result, as shown in FIG. 2B, the second Semiconductor body The threshold voltage of the second N-channel MOS transistor region 7b is lowered. Semiconductor bodyA memory write operation is performed in which the “1” write state of 7 is set as a first data retention voltage (an example of the “first data retention voltage” in the claims), and the logical memory data is assigned to “1.” Semiconductor body In the “0” erase state of 7, the first Semiconductor body 7a and the second N-channel MOS transistor region connected to the word line WL. Semiconductor body Since the threshold voltage of the second N-channel MOS transistor region 7b becomes high, if the voltage applied to the plate line PL is set to be equal to or lower than the threshold voltage, the cell current Icell does not flow even if the voltage of the word line WL is increased.

[0037] During the write operation, the first boundary area is replaced by the first impurity region 3a and 1st Semiconductor body 7a and the second boundary area, or the second impurity region 3b and the second Semiconductor body In the third boundary region between 7b and 7c, electron-hole pairs are generated by impact ionization, and the generated hole group 9 Semiconductor body You can also charge the 7.

[0038] Furthermore, the above-mentioned voltage conditions applied to the bit line BL, source line SL, word line WL, and plate line PL, and the potential of the floating body are only an example for performing a write operation, and other operating conditions that generate electron-hole pairs due to impact ionization may also be used.

[0039] 3A to 3C show a page write post-processing operation (one example of a "page write post-processing operation" in the claims) after a page write operation of the dynamic flash memory cell according to the first embodiment of the present invention.

[0040] FIG. 3A shows operation waveforms of a word line WL, a plate line PL, a bit line BL, and a source line SL during a page write post-processing operation after a page write operation of a dynamic flash memory cell; Semiconductor body7 and the memory cell current Icell. At time T1, the word line WL and the plate line PL are selected, a first voltage V1 is applied to the word line WL, and a second voltage V2 is applied to the plate line PL, starting a page write operation. At time T2, a third voltage V3 is applied to the bit line BL connected to the memory cell to which the logic "1" of the selected page (an example of a "page" in the claims) is to be written. Here, the first voltage V1, the second voltage V2, and the third voltage V3 are, for example, 1.5V, 1.3V, and 1.0V. As a result, Semiconductor body Impact ionization occurs at 7, generating electron-hole pairs. At this time, the generated electron group flows into the bit line BL, and the generated hole group 9 flows into Semiconductor body 7. Therefore, Semiconductor body The voltage of 7 rises, and this substrate bias effect reduces the threshold voltage of the MOS transistor regions of the word line WL and the plate line PL. Therefore, positive feedback is applied, and the number of holes 9 (Holes) increases from the number of neutral states N1 to N2 at the first time T3 (one example of the "first time" in the claims). Also, the memory cell current Icell increases from I0 to I1. Thereafter, the word line WL, the plate line PL, and the bit line BL return to, for example, the ground voltage Vss, and the page write operation is completed. Semiconductor body The accumulation operation of the hole group 9 in the pixel 7 is temporarily terminated.

[0041] At a time T4 of the second time (which is an example of the "second time" in the claims), a page write operation is performed. Semiconductor bodyA page write post-processing operation is performed to eliminate the surplus hole group (one example of the "surplus hole group" in the claims) among the hole group 9 stored in the memory cell 7. In this page write post-processing operation, a pulse voltage is applied to the word line WL, the plate line PL, and the bit line BL. The applied voltage is increased, for example, from the ground voltage Vss to a fourth voltage V4, a fifth voltage V5, and a sixth voltage V6, respectively. The fourth voltage V4, the fifth voltage V5, and the sixth voltage V6 may be, for example, the same voltage as that in the page read operation. As a result, the surplus hole group is eliminated, the number of the hole group 9 Holes decreases from the number N2 to N3, and the memory cell current Icell decreases from I2 to I3. In the dynamic flash memory cell, it is required to perform a stable page write operation and to eliminate malfunctions of the sense amplifier circuit. For this reason, it is necessary to read the stable memory cell current Icell using the sense amplifier circuit SA (one example of the "sense amplifier circuit" in the claims) shown in Figure 4E. Therefore, even if a page read operation is performed from time T6 to T7 and from time T8 to T9, the number of holes 9 Holes remains constant at N3, and the memory cell current Icell remains constant at I3, making it possible to perform a stable page read operation. In this example, a series of page write operations are performed from time T1 to T5.

[0042] 3B shows an example in which the voltages applied to the word line WL, the plate line PL, and the bit line BL during the page write post-processing operation are increased from the ground voltage Vss to a seventh voltage V7, an eighth voltage V8, and a ninth voltage V9, respectively. These seventh voltage V7, eighth voltage V8, and ninth voltage V9 are higher than the fourth voltage V4, the fifth voltage V5, and the sixth voltage V6 during the page read operation after the page write post-processing operation shown in FIG. 3A. Therefore, the surplus hole group can be efficiently eliminated.

[0043] FIG. 3C shows an example in which the voltages applied to the word line WL, the plate line PL, and the bit line BL during the page write post-processing operation are, for example, the fourth voltage V4, the fifth voltage V5, and the sixth voltage V6, which are the same voltages as those in the page read operation, and two pulse voltages are input. From time T4 to T5, the number of holes 9 Holes decreases from the number N2 to N4, and the memory cell current Icell decreases from I2 to I4. Then, from time T6 to T7, the number of holes 9 Holes decreases from the number N4 to N3, and the memory cell current Icell decreases from I4 to I3. In this way, the sudden disappearance of the surplus holes can be prevented. In this example, the time from T1 to T7 is a series of page write operations.

[0044] The mechanism of a page erase operation (one example of a "page erase operation" in the claims) will be described with reference to FIGS. 4A to 4E.

[0045] FIG. 4A shows a memory block circuit diagram for explaining a page erase operation. Here, nine memory cells C00-C22 in a 3-row x 3-column arrangement are shown in plan view, but the actual memory block is larger than this matrix. When memory cells are arranged in a matrix, one direction of the arrangement is called the "row direction" (or "row-like"), and the direction perpendicular to this is called the "column direction" (or "column-like"). Source lines SL0-SL2, bit lines BL0-BL2, plate lines PL0-PL2, and word lines WL0-WL2 are connected to each memory cell. The source lines SL0-SL2, plate lines PL0-PL2, and word lines WL0-WL2 are arranged in parallel, and bit lines BL0-BL2 are arranged in a direction perpendicular to them. For example, in this block, it is assumed that memory cells C10-C12, to which the plate line PL1, word line WL1, and source line SL1 of an arbitrary page P1 are connected, are selected and a page erase operation is performed.

[0046] FIG. 4B shows an operation waveform diagram of a page erase operation. A page erase operation starts, and for example, a selective erase of page P1 is performed. At a first time T1, the word line WL1 and the plate line PL1 rise from the ground voltage Vss to the first voltage V1 and the second voltage V2, respectively. Here, the ground voltage Vss is, for example, 0V. Also, the first voltage V1 and the second voltage V2 are, for example, 1V each. Next, at a second time T2, the source line SL1 drops from the ground voltage Vss to the third voltage V3. Here, the third voltage V3 is a negative voltage (an example of the "negative voltage" in the claims), for example, -1V. As a result, N + The first layer is impurity region 3a and P layers Semiconductor body The PN junction between 7 and Semiconductor body The hole group 9 stored in the first impurity region Discharge to 3a. Semiconductor body When the discharge of the hole group 9 stored in the transistor 7 is saturated, at a third time T3, the source line SL1 returns from the third voltage V3 to the ground voltage Vss, and at a fourth time T4, the word line WL1 and the plate line PL1 return from the first voltage V1 and the second voltage V2 to the ground voltage Vss, respectively, and the page erase operation is completed. Semiconductor body 7 “0” erased state voltage V FB A page erase operation is performed with "0" as the second data retention voltage (an example of the "second data retention voltage" in the claims), and the logical memory data is assigned to "0".

[0047] Either the word line WL1 or the plate line PL1 may rise from the ground voltage Vss to the first voltage V1 or the second voltage V2 around the first time T1. Also, the source line SL1 may fall from the ground voltage Vss to the third voltage V3 before the first time T1. Also, either the word line WL1 or the plate line PL1 may return from the first voltage V1 or the second voltage V2 to the ground voltage Vss around the fourth time T4. Also, the source line SL1 may return from the third voltage V3 to the ground voltage Vss after the fourth time T4.

[0048] AlsoAt the second time T2, when the source line SL1 drops from the ground voltage Vss to the third voltage V3, a current flows from the bit lines BL0 to BL2 to the source line SL1. + The second layer is impurity region The P layer around 3b Semiconductor body At 7, impact ionization occurs, generating electron-hole pairs. Semiconductor body 7, a group of holes 9 generated, and a first impurity region The number of holes 9 discharged to 3a is balanced, a saturated state is reached, and the page erase operation is completed.

[0049] The state of the semiconductor body during the erase operation will be described with reference to FIG. 4C. In FIG. 4C(a), a group of holes 9 generated by impact ionization before the erase operation is Semiconductor body 7. When a page erase operation begins, the source N + Layer 3a and Semiconductor body The PN junction between transistor 7 and transistor 8 is in a forward bias state, as shown in FIG. 4C(b). Semiconductor body The hole group 9 of 7 is the source N + The resulting mixture is discharged into layer 3a. Semiconductor body Voltage of 7 V FB Source N + Layer 3a and P layer Semiconductor body This is the built-in voltage Vb of the PN junction formed by

[0050] Subsequently, when the word line WL and the plate line PL to be selectively erased are returned from the first voltage V1 and the second voltage V2 to the ground voltage Vss, Semiconductor body Voltage of 7 V FB is a word line WL and a plate line PL, Semiconductor body 7, Vb to V FB This state is shown in Figure 4C(c).

[0051] Note that the above voltage conditions applied to the bit line BL, source line SL, word line WL, and plate line PL, and the floating body potential are examples for performing a page erase operation, and other operating conditions that enable a page erase operation may also be used.

[0052] 4D shows a memory block circuit diagram in which at least two or more plate lines PL of adjacent pages are shared. The plate lines PL of three pages P0 to P2 are shared.

[0053] FIG. 4E shows a memory block diagram including the main circuits. The word lines WL0-WL2 and plate lines PL0-PL2 are connected to a row decoder circuit RDEC (an example of the "row decoder circuit" in the claims), and a row address RAD (an example of the "row address" in the claims) is input to the row decoder circuit, which selects pages P0-P2 according to the row address RAD. The bit lines BL0-BL2 are connected to a sense amplifier circuit SA, and the sense amplifier circuit SA is connected to a column decoder circuit CDEC (an example of the "column decoder circuit" in the claims), and a column address CAD (an example of the "column address" in the claims) is input to the column decoder circuit CDEC, which selectively connects to an input / output circuit IO (an example of the "input / output circuit" in the claims) according to the column address CAD.

[0054] 1, the dynamic flash memory operation described in this embodiment can be performed even if the horizontal cross-sectional shape of the Si pillar 2 is circular, elliptical, or rectangular. Moreover, dynamic flash memory cells of circular, elliptical, and rectangular shapes may be mixed on the same chip.

[0055] 1, the dynamic flash memory element has been described using as an example an SGT having a first gate insulating layer 4a and a second gate insulating layer 4b that surround the entire side surface of a Si pillar 2 standing vertically on a substrate, and a first gate conductor layer 5a and a second gate conductor layer 5b that surround the entire first gate insulating layer 4a and the second gate insulating layer 4b. As shown in the description of this embodiment, in this dynamic flash memory element, a group of holes 9 generated by impact ionization is Semiconductor body Any structure that satisfies the conditions in 7 is acceptable. Semiconductor body7 may have a floating body structure separated from the substrate 1. As a result, even if the semiconductor body is formed horizontally to the substrate 1 (so that the central axis of the semiconductor body is parallel to the substrate) using, for example, GAA (Gate All Around: see, for example, Non-Patent Document 13), which is one type of SGT, or Nanosheet technology (see, for example, Non-Patent Document 14), the dynamic flash memory operation described above can be performed. Alternatively, a structure in which multiple GAA or Nanosheets formed in the horizontal direction are stacked may be used. Alternatively, a device structure using SOI (Silicon On Insulator) may be used (see, for example, Non-Patent Documents 7 to 10). In this device structure, Semiconductor body The bottom of the SOI substrate is in contact with the insulating layer of the SOI substrate, and the other Semiconductor body is surrounded by a gate insulating layer and an element isolation insulating layer. Semiconductor body In this way, the dynamic flash memory device provided by the present embodiment has a floating body structure. Semiconductor body It is sufficient to satisfy the condition that the structure is a floating body structure. Also, even if a Fin transistor (see, for example, Non-Patent Document 15) is formed on an SOI substrate, Semiconductor body If the device has a floating body structure, this dynamic flash operation is possible.

[0056] In the explanation of FIGS. 2A and 2B, the reset voltages of the word line WL, bit line BL, and source line SL are described as Vss, but they may each be a different voltage.

[0057] In addition, in FIG. 4A to FIG. 4E and the description thereof, an example of a page erase operation condition is shown. Semiconductor body The hole group 9 in 7 is + Layer 3a, N +If it is possible to realize a state in which the charge is removed from either or both of the layers 3b, the voltages applied to the source line SL, the plate line PL, the bit line BL, and the word line WL may be changed. In addition, in a page erase operation, a voltage may be applied to the source line SL of a selected page, and the bit line BL may be set to a floating state. In addition, in a page erase operation, a voltage may be applied to the bit line BL of a selected page, and the source line SL may be set to a floating state.

[0058] In addition, in the direction perpendicular to the substrate, in the portion surrounded by the insulating layer 6 in FIG. Semiconductor body 7, the first Semiconductor body 7a, 2nd Semiconductor body The potential distribution of the first Semiconductor body 7a, the second semiconductor body 7b Semiconductor body 7 are connected in the vertical direction in a region surrounded by insulating layer 6, which is an insulating layer.

[0059] Also In FIG. 1, the vertical length of the first gate conductor layer 5a to which the plate line PL is connected is made longer than the vertical length of the second gate conductor layer 5b to which the word line WL is connected. PL >C WL However, it is desirable to add a plate line PL to the word line WL. Semiconductor body 7, the coupling ratio of capacitive coupling (C WL / (C PL +C WL +C BL +C SL As a result, the floating body Semiconductor body 7 potential fluctuation ΔV FB becomes smaller.

[0060] Also This specification In writingIn this context, when it is said that "the gate insulating layer, gate conductor layer, etc. cover the channel, etc.", the meaning of "cover" includes cases where it completely surrounds the channel, such as in SGT and GAA transistors, cases where it surrounds the channel except for a portion, such as in Fin transistors, and cases where it overlaps on a flat surface, such as in planar transistors.

[0061] Also, In FIG. 1, the first gate conductor layer 5a surrounds the entire first gate insulating layer 4a. Alternatively, the first gate conductor layer 5a may surround a part of the first gate insulating layer 4a in a plan view. The first gate conductor layer 5a may be divided into at least two gate conductor layers, each of which may be operated as a plate line PL electrode. Similarly, the second gate conductor layer 5b may be divided into two or more, each of which may be operated synchronously or asynchronously as a word line conductor electrode. This allows dynamic flash memory operation.

[0062] 1, the first gate conductor layer 5a may be connected to a word line WL, and the second gate conductor layer 5b may be connected to a plate line PL, which also enables the dynamic flash memory operation described above.

[0063] This embodiment provides the following features: (Features) The dynamic flash memory cell according to the first embodiment of the present invention is characterized by a page write operation. In the page write operation, the dynamic flash memory cell according to the present invention performs a page write operation at a first time T1 by using the impact ionization phenomenon. Semiconductor Motherboard 7 At the second time T2, a page write post-processing operation is performed to eliminate the excess hole group. This enables a stable page read. In other words, the page write post-processing operation provides a stable memory cell current Icell, allowing accurate data to be read by the sense amplifier circuit SA. In addition, even if a page read operation is performed multiple times after the page write post-processing operation, Semiconductor bodyThere is no change in the number of holes in 7, and the memory cell current of logic "1" data maintains a constant value, making it possible to perform a stable page read operation, thereby providing a highly reliable memory device.

[0064] (Other embodiments) Although the Si pillars are formed in the present invention, the semiconductor pillars may be made of a semiconductor material other than Si. This also applies to the other embodiments of the present invention.

[0065] In addition, in writing "1", electron-hole pairs may be generated by impact ionization using a gate induced drain leakage (GIDL) current described in Non-Patent Document 10, and the floating body FB may be filled with the generated holes. This also applies to other embodiments of the present invention.

[0066] In addition, in FIG. + Dynamic flash memory operation is also possible in a structure in which the polarity of the conductivity types of the layers 3a, 3b, and the P-type Si pillar 2 is reversed. In this case, the majority carriers in the N-type Si pillar 2 are electrons. Therefore, the electron group generated by impact ionization Semiconductor body 7 and the “1” state is set.

[0067] Also, the memory blocks may be formed by arranging the Si pillars of the memory cells two-dimensionally in a square lattice or a diagonal lattice. When the Si pillars are arranged in a diagonal lattice, the Si pillars connected to one word line may be arranged in a zigzag or sawtooth pattern with multiple Si pillars as one side. This is the same in the other embodiments.

[0068] In addition, the present invention allows various embodiments and modifications without departing from the broad spirit and scope of the present invention. Moreover, each of the above-described embodiments is intended to explain one example of the present invention and does not limit the scope of the present invention. The above-described embodiments and modifications can be combined in any manner. Furthermore, even if some of the constituent elements of the above-described embodiments are omitted as necessary, the present invention will still be within the scope of the technical idea of ​​the present invention. [Industrial Applicability]

[0069] According to the memory device using the semiconductor element of the present invention, a dynamic flash memory, which is a high-density and high-performance memory device using SGT, can be obtained. [Explanation of symbols]

[0070] 10: Dynamic Flash Memory Cell 2: Si pillar with p-type or i-type (intrinsic) conductivity 3a, 3b: N + layer 7: Semiconductor body 4a, 4b: Gate insulating layer 5a, 5b: Gate conductor layer 6: An insulating layer to separate the two gate conductor layers 9: Hole BL: Bit line SL: Source line PL: Plate line WL: Word line FB: Floating body T1~T9: Time V1~V9: 1st voltage~9th voltage N1: Number of neutral holes N2~N4: Number of holes I0~I4: Memory cell current C00~C22: Memory cells SL0~SL2, SL01, SL23: Source lines BL0~BL2: Bit lines PL0~PL2: Plate lines WL0~WL2: Word lines RDEC: Row address circuit RAD: Row address SA: Sense amplifier circuit CDEC: Column Decoder Circuit CAD: Column Address IO: Input / Output circuit 111: DRAM memory cell without a capacitor 100: SOI substrate 101: SiO2 film on SOI substrate 102: Floating Body 103: Source N + layer 104: Drain N + layer 105: Gate conductive layer 106: Hole 107: Inversion layer, electron channel 108: Pinch-off point 109: Gate oxide 110: Slit insulating film

Claims

1. A memory device in which a page is constituted by a plurality of memory cells arranged in a row direction on a substrate in a plan view, and a plurality of pages are arranged in a column direction, The memory cells included in each page include A semiconductor body standing vertically or extending horizontally on the substrate; a first impurity region and a second impurity region at both ends of the semiconductor body; a gate insulating layer in contact with a side surface of the semiconductor body between the first impurity region and the second impurity region; a first gate conductor layer covering a part or the whole of the gate insulating layer; a second gate conductor layer adjacent to the first gate conductor layer and in contact with a side surface of the gate insulating layer; Has controlling voltages applied to the first impurity region, the second impurity region, the first gate conductor layer, and the second gate conductor layer to perform a page write operation, a page erase operation, and a page read operation; During the page write operation, a hole group formed by impact ionization is held inside the semiconductor body at a first time, and a page write post-processing operation is performed at a second time subsequent to the first time to eliminate a surplus hole group among the hole group. A memory device using a semiconductor element.

2. During the page write operation, a voltage of the semiconductor body is set to a first data retention voltage that is higher than a voltage of one or both of the first impurity region and the second impurity region; during the page erase operation, voltages applied to the first impurity region, the second impurity region, the first gate conductor layer, and the second gate conductor layer are controlled to eliminate the group of holes in the semiconductor body, and a voltage of the semiconductor body is set to a second data retention voltage lower than the first data retention voltage; 2. A memory device using the semiconductor element according to claim 1.

3. the first impurity region is connected to a source line, the second impurity region is connected to a bit line, and when one of the first gate conductor layer and the second gate conductor layer is connected to a word line, the other is connected to a plate line; controlling voltages applied to the source line, the bit line, the word line, and the plate line to perform the page write operation, the page erase operation, the page read operation, and the page write post-processing operation; 2. A memory device using the semiconductor element according to claim 1.

4. applying a pulse voltage to at least one of the source line, the bit line, the word line, and the plate line during the page write post-processing operation; 4. A memory device using the semiconductor element according to claim 3.

5. during the page write post-processing operation, applying the same voltages to the bit lines, the word lines, and the plate lines as during the page read operation; 4. A memory device using the semiconductor element according to claim 3.

6. during the page write post-processing operation, a voltage higher than that during the page read operation is applied to at least one of the bit line, the word line, and the plate line; 4. A memory device using the semiconductor element according to claim 3.

7. applying the pulse voltage at least once to the selected page during the page write post-processing operation; 5. A memory device using the semiconductor element according to claim 4.

8. In a plan view, the word lines and the plate lines are arranged in parallel, the bit lines are disposed in a direction perpendicular to the word lines and the plate lines in a plan view; 4. A memory device using the semiconductor element according to claim 3.

9. a first gate capacitance between the first gate conductor layer or the second gate conductor layer, to which the plate line is connected, and the semiconductor body, is larger than a second gate capacitance between the first gate conductor layer or the second gate conductor layer, to which the word line is connected, and the semiconductor body; 4. A memory device using the semiconductor element according to claim 3.

10. In a plan view, the source lines are separated for each of the memory cells arranged in the column direction and are arranged in parallel to the word lines and the plate lines.

4. A memory device using the semiconductor element according to claim 3.

11. In a plan view, the source line is commonly provided to the adjacent pages.

4. A memory device using the semiconductor element according to claim 3.

12. In a plan view, at least two of the plate lines of the adjacent pages are commonly arranged.

4. A memory device using the semiconductor element according to claim 3.

13. The first gate conductor layer is composed of two separated split gate conductor layers, and the split gate conductor layers are located on both sides of the second gate conductor layer, performing the page write operation, the page erase operation, the page read operation, and the page write post-processing operation; 2. A memory device using the semiconductor element according to claim 1.

14. The second gate conductor layer is composed of two separated split gate conductor layers, and the split gate conductor layers are located on both sides of the first gate conductor layer, performing the page write operation, the page erase operation, the page read operation, and the page write post-processing operation; 2. A memory device using the semiconductor element according to claim 1.

15. the semiconductor body is a P-type semiconductor layer, and the first impurity region and the second impurity region are N-type semiconductor layers; 2. A memory device using the semiconductor element according to claim 1.

16. During the page erase operation, at least two sets of the pages are selectively erased.

2. A memory device using the semiconductor element according to claim 1.

17. the word lines and the plate lines are connected to a row decoder circuit, a row address is input to the row decoder circuit, and the page is selected in accordance with the row address; 4. A memory device using the semiconductor element according to claim 3.

18. the bit lines are connected to a sense amplifier circuit, the sense amplifier circuit is connected to a column decoder circuit, a column address is input to the column decoder circuit, and the sense amplifier circuit is selectively connected to an input / output circuit in accordance with the column address; 4. A memory device using the semiconductor element according to claim 3.