Display device

Abstract

Provided is a display device having a high display quality. This display device has pixels, a scanning line driving circuit, and a power supply circuit. The pixels each have first and second transistors, and the second transistor has a semiconductor layer provided in a first opening formed in an interlayer insulating layer on a substrate. A first conductive layer that functions as a gate electrode of the first transistor has a region that extends in a first direction, and is electrically connected to the scanning line driving circuit. A second conductive layer that functions as a source electrode or a drain electrode of the second transistor is provided on the interlayer insulating layer and has a second opening overlapping with the first opening. The second conductive layer has a region that extends in a second direction perpendicular to the first direction, and is electrically connected to the power supply circuit. The first conductive layer and the second conductive layer have regions that overlap with each other having therebetween an insulating layer that is provided in a layer between the first conductive layer, and the second conductive layer and the semiconductor layer, and that functions as a gate insulating layer for the first and second transistors.

Description

display device

[0001] 1. Field of the Invention One embodiment of the present invention relates to a display device, a semiconductor device, a memory device, a display module, and an electronic device. 1. Field of the Invention One embodiment of the present invention relates to a method for manufacturing a display device, a semiconductor device, and a memory device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] Semiconductor devices having transistors are widely used in display devices and electronic devices, and there is a demand for higher integration and higher speed of the semiconductor devices. For example, when a semiconductor device is applied to a high-resolution display device, a highly integrated semiconductor device is required. As one means for increasing the integration degree of transistors, the development of fine-sized transistors is underway.

[0004] In recent years, there has been a demand for display devices applicable to virtual reality (VR), augmented reality (AR), substitutional reality (SR), or mixed reality (MR). VR, AR, SR, and MR are collectively referred to as XR (Extended Reality). Display devices for XR are desired to have high resolution and high color reproducibility in order to enhance the sense of realism and immersion. Examples of display devices applicable to such devices include liquid crystal display devices, organic electroluminescence (EL) elements, and light-emitting devices including light-emitting elements (also referred to as light-emitting devices) such as light-emitting diodes (LEDs).

[0005] Patent Document 1 discloses a display device for VR that uses an organic EL element (also called an organic EL device).

[0006] International Publication No. 2018 / 087625

[0007] A power supply potential is supplied to pixels provided in a display device by a power supply circuit. Here, in pixels that are located a long distance from the power supply circuit, the potential supplied as the power supply potential may decrease due to, for example, wiring resistance. This may result in, for example, the pixel not emitting light with the desired brightness, resulting in a decrease in the display quality of the display device.

[0008] Therefore, an object of one embodiment of the present invention is to provide a display device with high display quality. Another object of one embodiment of the present invention is to provide a high-resolution display device and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a display device that operates at high speed and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a display device including a micro-sized transistor and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a display device including a transistor with high on-state current and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a display device with favorable electrical characteristics and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a novel display device, a novel semiconductor device, a novel memory device, and manufacturing methods thereof.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0010] One embodiment of the present invention includes a pixel, a power supply circuit, and a scan line driver circuit. The pixel includes a first transistor, a second transistor, and a first insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer, and a second insulating layer. The first insulating layer is provided over the first conductive layer, and the first insulating layer has a first opening that reaches the first conductive layer. The second conductive layer is provided over the first insulating layer. The second conductive layer has a second opening that overlaps with the first opening. The second conductive layer is electrically connected to a power supply circuit. The first semiconductor layer has a region in contact with the first conductive layer and a region in contact with the second conductive layer and is located inside the first opening and a region inside the second opening. a second insulating layer provided on the first semiconductor layer to have a region located inside the first opening and a region located inside the second opening; a third conductive layer provided on the first semiconductor layer to have a region located inside the first opening and a region located inside the second opening, and to have a region facing the first semiconductor layer with the second insulating layer sandwiched between the second transistor and the third conductive layer; a second transistor having a second insulating layer, a second semiconductor layer below the second insulating layer, and a fourth conductive layer on the second insulating layer, the fourth conductive layer having a region overlapping with the second semiconductor layer, the fourth conductive layer being electrically connected to a scanning line driver circuit, and the fourth conductive layer having a region overlapping with the second conductive layer via the second insulating layer;

[0011] Alternatively, in the above aspect, the second transistor may have a fifth conductive layer in contact with the second semiconductor layer, and the fifth conductive layer may be electrically connected to the third conductive layer.

[0012] Alternatively, in the above embodiment, the display device may include a signal line driver circuit, the second transistor may include a sixth conductive layer in contact with the second semiconductor layer, and the sixth conductive layer may be electrically connected to the signal line driver circuit.

[0013] Alternatively, in the above embodiment, the pixel may include a display element, and a pixel electrode of the display element may be electrically connected to the first conductive layer.

[0014] Alternatively, in the above aspect, the display device includes a reference potential generating circuit, and the pixel includes a third transistor. The third transistor includes a seventh conductive layer, an eighth conductive layer, a ninth conductive layer, a third semiconductor layer, and a second insulating layer. The first insulating layer is provided on the seventh conductive layer, and the first insulating layer has a third opening that reaches the seventh conductive layer. The seventh conductive layer is electrically connected to the reference potential generating circuit. The eighth conductive layer is provided on the first insulating layer, and the eighth conductive layer has a fourth opening that has a region overlapping with the third opening. The eighth conductive layer is electrically connected to the pixel electrode. The third semiconductor layer has a region in contact with the seventh conductive layer and a second insulating layer. the seventh insulating layer may have a region in contact with the conductive layer and a region located inside the third opening and a region located inside the fourth opening; the second insulating layer may be provided on the third semiconductor layer so as to have a region located inside the third opening and a region located inside the fourth opening; the ninth conductive layer may have a region located inside the third opening and a region located inside the fourth opening and may have a region facing the third semiconductor layer with the second insulating layer sandwiched between the ninth conductive layer and the third semiconductor layer; the ninth conductive layer may be electrically connected to a scanning line driver circuit; and the seventh conductive layer may have a region overlapping with the fourth conductive layer and a region overlapping with the ninth conductive layer.

[0015] Alternatively, one embodiment of the present invention includes a pixel, a scan line driver circuit, and a power supply circuit. The pixel includes a first transistor, a second transistor, and a first insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer, and a second insulating layer. The first insulating layer is provided over the first conductive layer, and the first insulating layer has a first opening that reaches the first conductive layer. The second conductive layer is provided over the first insulating layer, and the second conductive layer has a second opening that overlaps with the first opening. The first semiconductor layer , a region in contact with the first conductive layer and a region in contact with the second conductive layer, and is provided so as to have a region located inside the first opening and a region located inside the second opening; the second insulating layer is provided on the first semiconductor layer so as to have a region located inside the first opening and a region located inside the second opening; the third conductive layer has a region located inside the first opening and a region located inside the second opening, and is provided so as to have a region facing the first semiconductor layer with the second insulating layer sandwiched between them; and the third conductive layer the second transistor is electrically connected to a scanning line driver circuit, the second transistor has a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a second semiconductor layer, and a second insulating layer, the first insulating layer is provided on the fourth conductive layer, the first insulating layer has a third opening that reaches the fourth conductive layer, the fifth conductive layer is provided on the first insulating layer, the fifth conductive layer has a fourth opening having a region overlapping with the third opening, the fifth conductive layer is electrically connected to a power supply circuit, the second semiconductor layer has a region in contact with the fourth conductive layer and a region in contact with the fifth conductive layer, the sixth conductive layer has a region located inside the third opening and a region located inside the fourth opening, the second insulating layer is provided on the second semiconductor layer so as to have a region located inside the third opening and a region located inside the fourth opening, the sixth conductive layer has a region located inside the third opening and a region located inside the fourth opening, and is provided so as to have a region facing the second semiconductor layer with the second insulating layer sandwiched between it and the second semiconductor layer, and the fifth conductive layer has a region overlapping with the third conductive layer via the second insulating layer.

[0016] Alternatively, in the above embodiment, the display device may include a signal line driver circuit, the first conductive layer may be electrically connected to the signal line driver circuit, and the first conductive layer may have a region overlapping with the third conductive layer.

[0017] Alternatively, in the above aspect, the second conductive layer may be electrically connected to the sixth conductive layer.

[0018] Alternatively, in the above-described embodiment, the pixel may include a display element, and a pixel electrode of the display element may be electrically connected to the fourth conductive layer.

[0019] Alternatively, in the above aspect, the display device includes a reference potential generating circuit, and the pixel includes a third transistor. The third transistor includes a seventh conductive layer, an eighth conductive layer, a ninth conductive layer, a third semiconductor layer, and a second insulating layer. The first insulating layer is provided on the seventh conductive layer, and the first insulating layer has a fifth opening that reaches the seventh conductive layer. The seventh conductive layer is electrically connected to the reference potential generating circuit. The eighth conductive layer is provided on the first insulating layer, and the eighth conductive layer has a sixth opening that has a region overlapping with the fifth opening. The eighth conductive layer is electrically connected to the pixel electrode. The third semiconductor layer has a region in contact with the seventh conductive layer and a sixth opening that overlaps with the fifth opening. the ninth conductive layer has a region in contact with the conductive layer and is provided so as to have a region located inside the fifth opening and a region located inside the sixth opening; the second insulating layer is provided on the third semiconductor layer so as to have a region located inside the fifth opening and a region located inside the sixth opening; the ninth conductive layer has a region located inside the fifth opening and a region located inside the sixth opening and is provided so as to have a region facing the third semiconductor layer with the second insulating layer sandwiched between it and the third semiconductor layer; the ninth conductive layer is electrically connected to a scanning line driver circuit; and the seventh conductive layer has a region overlapping with the third conductive layer and a region overlapping with the ninth conductive layer.

[0020] Alternatively, in the above-described embodiment, the first to third semiconductor layers may each contain a metal oxide, for example, indium, zinc, and M (wherein M is one or more elements selected from aluminum, titanium, gallium, germanium, tin, yttrium, zirconium, lanthanum, cerium, neodymium, and hafnium).

[0021] According to one embodiment of the present invention, a display device with high display quality can be provided. According to another embodiment of the present invention, a high-resolution display device and a manufacturing method thereof can be provided. According to another embodiment of the present invention, a display device that operates at high speed and a manufacturing method thereof can be provided. According to another embodiment of the present invention, a display device including a micro-sized transistor and a manufacturing method thereof can be provided. According to another embodiment of the present invention, a display device including a transistor with high on-state current and a manufacturing method thereof can be provided. According to another embodiment of the present invention, a display device with favorable electrical characteristics and a manufacturing method thereof can be provided. According to another embodiment of the present invention, a novel display device, a novel semiconductor device, a novel memory device, and manufacturing methods thereof can be provided.

[0022] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0023] FIG. 1A is a block diagram showing an example of the configuration of a display device. FIG. 1B is a plan view showing an example of the configuration of a pixel. FIGS. 1C and 1D are circuit diagrams showing an example of the configuration of a pixel. FIG. 2A is a block diagram showing an example of the configuration of a display device. FIG. 2B is a circuit diagram showing an example of the configuration of a pixel. FIGS. 3A1 to 3A3 are plan views showing an example of the configuration of a display device. FIG. 3B is a cross-sectional view showing an example of the configuration of a display device. FIG. 4A is a plan view showing an example of the configuration of a display device. FIG. 4B is a cross-sectional view showing an example of the configuration of a display device. FIG. 5 is a plan view showing an example of the configuration of a display device. FIG. 6 is a cross-sectional view showing an example of the configuration of a display device. FIGS. 7A and 7B are plan views showing an example of the configuration of a display device. FIGS. 8A to 8D are plan views showing an example of the configuration of a display device. FIGS. 9A to 9C are plan views showing an example of the configuration of a display device. FIG. 10 is a cross-sectional view showing an example of the configuration of a display device. FIGS. 11A and 11B are plan views showing an example of the configuration of a display device. FIG. 12 is a plan view showing an example of the configuration of a display device. FIG. 13 is a cross-sectional view showing an example of the configuration of a display device. FIG. 14 is a plan view showing an example of the configuration of a display device. FIG. 15 is a cross-sectional view showing an example of the configuration of a display device. FIGS. 16A to 16C are plan views showing an example of the configuration of a display device. FIGS. 17A to 17C are plan views showing an example of the configuration of a display device. FIG. 18A is a plan view showing an example of the configuration of a display device. FIG. 18B is a cross-sectional view showing an example of the configuration of a display device. FIG. 19 is a plan view showing an example of the configuration of a display device. FIGS. 20A1 and 20A2 are plan views showing an example of the configuration of a display device. FIG. 20B is a cross-sectional view showing an example of the configuration of a display device. FIGS. 21A and 21B are plan views showing an example of the configuration of a display device. FIG. 22A is a plan view showing an example of the configuration of a display device. FIG. 22B is a cross-sectional view showing an example of the configuration of a display device. FIGS. 23A and 23B are plan views showing an example of the configuration of a display device. FIG. 24A is a plan view showing an example of the configuration of a display device. FIG. 24B is a cross-sectional view showing an example of the configuration of a display device. FIGS. 25A to 25C are plan views showing an example of the configuration of a display device. Fig. 26A is a plan view showing a configuration example of a display device. Fig. 26B is a cross-sectional view showing a configuration example of a display device. Fig. 27 is a plan view showing a configuration example of a display device. Figs. 28A1 and 28A2 are plan views showing configuration examples of a display device.FIG. 28B is a cross-sectional view showing an example of the configuration of a display device. FIGS. 29A and 29B are plan views showing an example of the configuration of a display device. FIG. 30A is a plan view showing an example of the configuration of a display device. FIG. 30B is a cross-sectional view showing an example of the configuration of a display device. FIG. 31A is a plan view showing an example of the configuration of a display device. FIG. 31B is a cross-sectional view showing an example of the configuration of a display device. FIG. 32A is a plan view showing an example of the configuration of a display device. FIG. 32B is a cross-sectional view showing an example of the configuration of a display device. FIG. 33 is a plan view showing an example of the configuration of a display device. FIG. 34A is a plan view showing an example of the configuration of a display device. FIG. 34B is a cross-sectional view showing an example of the configuration of a display device. FIG. 35A is a plan view showing an example of the configuration of a display device. FIG. 35B is a cross-sectional view showing an example of the configuration of a display device. FIG. 36 is a plan view showing an example of the configuration of a display device. FIG. 37 is a plan view showing an example of the configuration of a display device. FIG. 38A is a plan view showing an example of the configuration of a display device. FIG. 38B is a cross-sectional view showing an example of the configuration of a display device. FIG. 39A is a plan view showing an example of the configuration of a display device. FIG. 39B is a cross-sectional view showing an example of the configuration of a display device. 40A and 40B are plan views showing an example of the configuration of a display device. FIG. 41A is a plan view showing an example of the configuration of a display device. FIG. 41B is a cross-sectional view showing an example of the configuration of a display device. FIG. 42A is a plan view showing an example of the configuration of a display device. FIG. 42B is a cross-sectional view showing an example of the configuration of a display device. FIG. 43 is a plan view showing an example of the configuration of a display device. FIG. 44 is a plan view showing an example of the configuration of a display device. FIG. 45 is a plan view showing an example of the configuration of a display device. FIG. 46 is a plan view showing an example of the configuration of a display device. FIG. 47 is a plan view showing an example of the configuration of a display device. FIG. 48 is a plan view showing an example of the configuration of a display device. FIG. 49 is a plan view showing an example of the configuration of a display device. FIG. 50 is a plan view showing an example of the configuration of a display device. FIG. 51 is a plan view showing an example of the configuration of a display device. FIG. 52A is a plan view showing an example of the configuration of a display device. FIG. 52B is a cross-sectional view showing an example of the configuration of a display device. FIG. 53 is a plan view showing an example of the configuration of a display device. FIG. 54A is a plan view showing an example of the configuration of a display device. FIG. 54B is a cross-sectional view showing an example of the configuration of a display device. Fig. 55 is a plan view showing a configuration example of a display device. Fig. 56A is a plan view showing a configuration example of a display device.FIG. 56B is a cross-sectional view showing an example of the configuration of a display device. FIG. 57 is a plan view showing an example of the configuration of a display device. FIG. 58 is a plan view showing an example of the configuration of a display device. FIG. 59 is a plan view showing an example of the configuration of a display device. FIG. 60 is a plan view showing an example of the configuration of a display device. FIG. 61 is a plan view showing an example of the configuration of a display device. FIG. 62A is a plan view showing an example of the configuration of a display device. FIG. 62B is a cross-sectional view showing an example of the configuration of a display device. FIG. 63 is a plan view showing an example of the configuration of a display device. FIG. 64A is a plan view showing an example of the configuration of a display device. FIG. 64B is a cross-sectional view showing an example of the configuration of a display device. FIG. 65 is a plan view showing an example of the configuration of a display device. FIG. 66A is a plan view showing an example of the configuration of a display device. FIG. 66B is a cross-sectional view showing an example of the configuration of a display device. FIG. 67 is a plan view showing an example of the configuration of a display device. FIG. 68A is a plan view showing an example of the configuration of a display device. FIG. 68B is a cross-sectional view showing an example of the configuration of a display device. FIG. 69 is a plan view showing an example of the configuration of a display device. FIG. 70A is a plan view showing an example of the configuration of a display device. FIG. 70B is a cross-sectional view showing an example of the configuration of a display device. FIG. 71 is a plan view showing an example of the configuration of a display device. FIG. 72 is a plan view showing an example of the configuration of a display device. FIG. 73 is a plan view showing an example of the configuration of a display device. FIG. 74A is a plan view showing an example of the configuration of a display device. FIG. 74B is a cross-sectional view showing an example of the configuration of a display device. FIG. 75 is a plan view showing an example of the configuration of a display device. FIG. 76 is a plan view showing an example of the configuration of a display device. FIG. 77 is a plan view showing an example of the configuration of a display device. FIG. 78A is a plan view showing an example of the configuration of a display device. FIG. 78B is a cross-sectional view showing an example of the configuration of a display device. FIG. 79A is a plan view showing an example of the configuration of a display device. FIG. 79B is a cross-sectional view showing an example of the configuration of a display device. FIG. 80 is a plan view showing an example of the configuration of a display device. FIG. 81A is a plan view showing an example of the configuration of a display device. FIG. 81B is a cross-sectional view showing an example of the configuration of a display device. FIG. 82 is a plan view showing an example of the configuration of a display device. FIG. 83A is a plan view showing an example of the configuration of a display device. FIG. 83B is a cross-sectional view showing an example of the configuration of a display device. FIG. 84 is a plan view showing an example of the configuration of a display device. FIG. 85A is a plan view showing an example of the configuration of a display device. FIG. 85B is a cross-sectional view showing an example of the configuration of the display device.FIG. 86 is a plan view showing an example of the configuration of a display device. FIG. 87A is a plan view showing an example of the configuration of a display device. FIG. 87B is a cross-sectional view showing an example of the configuration of a display device. FIG. 88 is a plan view showing an example of the configuration of a display device. FIG. 89 is a plan view showing an example of the configuration of a display device. FIG. 90 is a plan view showing an example of the configuration of a display device. FIG. 91 is a plan view showing an example of the configuration of a display device. FIG. 92 is a plan view showing an example of the configuration of a display device. FIG. 93A is a plan view showing an example of the configuration of a display device. FIG. 93B is a cross-sectional view showing an example of the configuration of a display device. FIG. 94 is a plan view showing an example of the configuration of a display device. FIG. 95 is a plan view showing an example of the configuration of a display device. FIG. 96 is a plan view showing an example of the configuration of a display device. FIG. 97 is a plan view showing an example of the configuration of a display device. FIG. 98 is a plan view showing an example of the configuration of a display device. FIG. 99A is a plan view showing an example of the configuration of a display device. FIG. 99B is a cross-sectional view showing an example of the configuration of a display device. FIG. 100 is a plan view showing an example of the configuration of a display device. FIG. 101 is a plan view showing an example of the configuration of a display device. FIG. 102 is a plan view showing an example of the configuration of a display device. FIG. 103 is a plan view showing a configuration example of a display device. FIG. 104 is a plan view showing a configuration example of a display device. FIGS. 105A to 105C are circuit diagrams showing a configuration example of a pixel. FIG. 106A is a block diagram showing a configuration example of a memory device. FIGS. 106B to 106F are circuit diagrams showing a configuration example of a memory cell. FIGS. 107A to 107C are plan views showing a configuration example of a display device. FIG. 108A is a plan view showing a configuration example of a display device. FIG. 108B is a cross-sectional view showing a configuration example of a display device. FIG. 109A is a plan view showing a configuration example of a display device. FIG. 109B is a cross-sectional view showing a configuration example of a display device. FIG. 110A is a plan view showing a configuration example of a display device. FIGS. 110B to 110D are cross-sectional views showing a configuration example of a display device. FIGS. 111A and 111B are plan views showing a configuration example of a display device. FIGS. 112A and 112B are plan views showing a configuration example of a display device. FIG. 112C is a cross-sectional view showing a configuration example of a display device. Fig. 113A is a plan view showing a configuration example of a display device, Fig. 113B is a cross-sectional view showing a configuration example of a display device, and Fig. 114A is a plan view showing a configuration example of a display device.FIG. 114B is a cross-sectional view showing an example of the configuration of a display device. FIG. 115A is a plan view showing an example of the configuration of a display device. FIG. 115B is a cross-sectional view showing an example of the configuration of a display device. FIGS. 116A and 116B are plan views showing an example of the configuration of a display device. FIG. 116C is a cross-sectional view showing an example of the configuration of a display device. FIG. 117A is a plan view showing an example of the configuration of a display device. FIG. 117B is a cross-sectional view showing an example of the configuration of a display device. FIG. 118A is a plan view showing an example of the configuration of a display device. FIG. 118B is a cross-sectional view showing an example of the configuration of a display device. FIGS. 119A and 119B are plan views showing an example of the configuration of a display device. FIGS. 120A and 120B are plan views showing an example of the configuration of a display device. FIG. 120C is a cross-sectional view showing an example of the configuration of a display device. FIG. 121A is a plan view showing an example of the configuration of a display device. FIGS. 121B and 121C are cross-sectional views showing an example of the configuration of a display device. FIGS. 122A and 122B are cross-sectional views showing an example of the configuration of a display device. 123A and 123B are cross-sectional views showing an example of the configuration of a display device. FIGS. 124A and 124B are cross-sectional views showing an example of the configuration of a display device. FIG. 125A is a plan view showing an example of the configuration of a display device. FIG. 125B is a cross-sectional view showing an example of the configuration of a display device. FIGS. 126A and 126B are plan views showing an example of the configuration of a display device. FIG. 127A is a plan view showing an example of the configuration of a display device. FIG. 127B is a cross-sectional view showing an example of the configuration of a display device. FIGS. 128A to 128C are plan views showing an example of the configuration of a display device. FIGS. 129A to 129C are plan views showing an example of the configuration of a display device. FIGS. 130A and 130B are plan views showing an example of the configuration of a display device. FIG. 131A is a plan view showing an example of the configuration of a display device. FIG. 131B is a cross-sectional view showing an example of the configuration of a display device. FIG. 132A is a plan view showing an example of the configuration of a display device. FIG. 132B is a cross-sectional view showing an example of the configuration of a display device. Fig. 133A1 and Fig. 133A2 are plan views showing a configuration example of a display device. Fig. 133B is a cross-sectional view showing a configuration example of a display device. Fig. 134A1 and Fig. 134A2 are plan views showing a configuration example of a display device. Fig. 134B is a cross-sectional view showing a configuration example of a display device. Figs. 135A to 135C are plan views showing a configuration example of a display device.

[0111] Figs. 136A and 136B are plan views showing an example of the configuration of a display device. Fig. 137A is a plan view showing an example of the configuration of a display device. Fig. 137B is a cross-sectional view showing an example of the configuration of a display device. Figs. 138A and 138B are plan views showing an example of the configuration of a display device. Fig. 138C is a cross-sectional view showing an example of the configuration of a display device. Fig. 139A is a plan view showing an example of the configuration of a display device. Fig. 139B is a cross-sectional view showing an example of the configuration of a display device. Fig. 140A is a plan view showing an example of the configuration of a display device. Fig. 140B is a cross-sectional view showing an example of the configuration of a display device. Fig. 141A is a plan view showing an example of the configuration of a display device. Fig. 141B is a cross-sectional view showing an example of the configuration of a display device. Figs. 142A to 142C are plan views showing an example of the configuration of a display device. Figs. 143A to 143C are plan views showing an example of the configuration of a display device. Figs. 144A and 144B are plan views showing an example of the configuration of a display device. Fig. 145A is a plan view showing an example of the configuration of a display device. FIG. 145B is a cross-sectional view showing an example of the structure of a display device. FIGS. 146A1 and 146B1 are plan views showing an example of a manufacturing method of a display device. FIGS. 146A2 and 146B2 are cross-sectional views showing an example of a manufacturing method of a display device. FIGS. 147A1 and 147B1 are plan views showing an example of a manufacturing method of a display device. FIGS. 147A2 and 147B2 are cross-sectional views showing an example of a manufacturing method of a display device. FIGS. 148A1 and 148B1 are plan views showing an example of a manufacturing method of a display device. FIGS. 148A2 and 148B2 are cross-sectional views showing an example of a manufacturing method of a display device. FIGS. 149A1 and 149B1 are plan views showing an example of a manufacturing method of a display device. FIGS. 149A2 and 149B2 are cross-sectional views showing an example of a manufacturing method of a display device. FIGS. 150A1 and 150B1 are plan views showing an example of a manufacturing method of a display device. Fig. 150A2 and Fig. 150B2 are cross-sectional views showing an example of a manufacturing method of a display device. Fig. 151 is a perspective view showing a structural example of a display device. Fig. 152 is a cross-sectional view showing a structural example of a display device. Fig. 153 is a cross-sectional view showing a structural example of a display device. Fig. 154 is a cross-sectional view showing a structural example of a display device. Fig. 155 is a cross-sectional view showing a structural example of a display device. Fig. 156 is a cross-sectional view showing a structural example of a display device. Fig. 157A is a perspective view showing a structural example of a display device.Fig. 157B is a plan view showing an example of the configuration of a touch sensor. Fig. 158 is a cross-sectional view showing an example of the configuration of a display device. Fig. 159 is a cross-sectional view showing an example of the configuration of a display device. Figs. 160A to 160G are plan views showing an example of the configuration of a pixel. Figs. 161A to 161K are plan views showing an example of the configuration of a pixel. Figs. 162A to 162D are diagrams showing an example of an electronic device. Figs. 163A to 163F are diagrams showing an example of an electronic device. Figs. 164A to 164G are diagrams showing an example of an electronic device.

[0024] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0025] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations are omitted. Also, when similar functions are indicated, the same hatching pattern may be used and no particular reference numeral may be used. Furthermore, multiple layers that can be formed in the same process may be denoted by the same hatching pattern.

[0026] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0027] It should be noted that the terms "film" and "layer" can be interchangeable in some cases or depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0028] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0029] In this specification and the like, a structure in which at least light-emitting layers are separately formed for light-emitting elements with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in selecting materials and configurations and facilitating improvements in brightness and reliability.

[0030] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier block layer (hole block layer and electron block layer). Note that the carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable from each other depending on their cross-sectional shapes, characteristics, etc. In addition, one layer may have two or three functions of the carrier injection layer, carrier transport layer, and carrier block layer.

[0031] In this specification and the like, a light-receiving element (also referred to as a light-receiving device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes.

[0032] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also referred to as the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0033] In this specification, when the side surface of a layer has a tapered shape, the outermost part of the side surface of the layer is referred to as the edge of the layer unless otherwise specified. For example, when the bottom surface edge of a layer is located outward from the top surface edge, the bottom surface edge of the layer is simply referred to as the edge unless otherwise specified.

[0034] Furthermore, in this specification, terms indicating positions such as "upper," "lower," "left," and "right" are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0035] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OS), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor. Note that metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[0036] Embodiment 1 In this embodiment, a display device of one embodiment of the present invention, a manufacturing method thereof, and the like will be described with reference to drawings.

[0037] One embodiment of the present invention relates to a display device including a display portion, a scan line driver circuit, a signal line driver circuit, and a power supply circuit, in which pixels are arranged in a matrix. Each pixel includes a first transistor and a second transistor in addition to a display element (also referred to as a display device). The first transistor can be a transistor in which a first semiconductor layer is provided inside an opening formed in an interlayer insulating layer over a substrate, and the second transistor can be a transistor in which a second semiconductor layer is provided inside an opening formed in the interlayer insulating layer over the substrate, different from the opening. With this structure, the channel length of the transistor can be aligned along a side surface of the interlayer insulating layer in the opening. Therefore, the channel length is not affected by the performance of an exposure device used to fabricate the transistor, and the channel length can be made shorter than the limiting resolution of the exposure device.

[0038] Here, a first conductive layer provided under the opening is used as one of the source electrode or drain electrode of the first transistor. Specifically, an interlayer insulating layer is provided on the first conductive layer, and an opening is provided in the interlayer insulating layer so as to reach the first conductive layer. Then, a first semiconductor layer is provided so as to have a region in contact with the first conductive layer inside the opening. Furthermore, a second conductive layer surrounding the periphery of the opening in a plan view is used as the other of the source electrode or drain electrode of the first transistor. Then, a gate insulating layer is provided on the first semiconductor layer and the second conductive layer, and a third conductive layer functioning as the gate electrode of the first transistor is provided on the gate insulating layer.

[0039] In this specification and the like, a plan view may be referred to as a top view in some cases, and a plan view may be referred to as a top view in some cases.

[0040] The second transistor can have a structure similar to that of the first transistor. A fourth conductive layer provided under the opening is used as one of the source electrode and the drain electrode of the second transistor. A fifth conductive layer surrounding the periphery of the opening in a plan view is used as the other of the source electrode and the drain electrode of the second transistor. The gate insulating layer is also provided on the second semiconductor layer and the fifth conductive layer, and a sixth conductive layer functioning as the gate electrode of the second transistor is provided on the gate insulating layer.

[0041] The first conductive layer or the second conductive layer is electrically connected to a signal line driving circuit. The third conductive layer has a region extending in the row direction and is electrically connected to a scanning line driving circuit. The fifth conductive layer has a region extending in the column direction and is electrically connected to a power supply circuit. Since the third conductive layer has a region extending in the row direction and the fifth conductive layer has a region extending in the column direction, the third conductive layer and the fifth conductive layer have an overlapping region.

[0042] In a display device according to one embodiment of the present invention, the gate insulating layer is provided on the fifth conductive layer in a region where the third conductive layer and the fifth conductive layer overlap, and the third conductive layer is provided thereon. This increases the capacitance of the parasitic capacitance formed by the conductive layer electrically connected to the scan line driver circuit and the conductive layer electrically connected to the power supply circuit, compared to when, for example, an interlayer insulating layer is provided between these conductive layers. This allows charge to be supplied from the parasitic capacitance to the fifth conductive layer electrically connected to the power supply circuit, i.e., the parasitic capacitance functions as a bypass capacitor. Therefore, a voltage drop in the power supply potential generated by the power supply circuit, for example, due to wiring resistance, can be suppressed. Therefore, particularly in pixels that are far from the power supply circuit, a drop in the potential supplied as the power supply potential can be suppressed, preventing the pixel from emitting light with a desired luminance. As described above, the display device according to one embodiment of the present invention can be a display device with high display quality.

[0043] Here, the fourth conductive layer, rather than the fifth conductive layer, may be electrically connected to the power supply circuit, in which case the fourth conductive layer has a region extending in the column direction.

[0044] When the fourth conductive layer is electrically connected to a power supply circuit, the seventh conductive layer is provided so as to have an area overlapping with the fourth conductive layer. Specifically, the seventh conductive layer has an area extending in the column direction, and the area overlaps with an area of ​​the fourth conductive layer extending in the column direction.

[0045] The seventh conductive layer is provided in the same layer as the fifth conductive layer, i.e., between the interlayer insulating layer and the gate insulating layer. The interlayer insulating layer has an opening that reaches the fourth conductive layer, and the fourth conductive layer and the seventh conductive layer are electrically connected within the opening. The power supply circuit is electrically connected to the fourth conductive layer, and the fourth conductive layer is electrically connected to the seventh conductive layer, so that the fourth and seventh conductive layers are electrically connected to the power supply circuit. As described above, not only the fourth conductive layer but also the seventh conductive layer provided in a layer different from the fourth conductive layer can function as wiring for electrically connecting the power supply circuit and the pixel.

[0046] As described above, by electrically connecting multiple conductive layers provided in different layers to a power supply circuit, wiring resistance from the power supply circuit to a pixel can be reduced. Therefore, a voltage drop in the power supply potential generated by the power supply circuit can be suppressed. Therefore, particularly in a pixel that is far from the power supply circuit, a drop in the potential supplied as the power supply potential can be suppressed, preventing the pixel from emitting light with a desired luminance. As described above, the display device of one embodiment of the present invention can be a display device with high display quality.

[0047] 1A is a block diagram showing a structural example of a display device 10, which is a display device of one embodiment of the present invention. The display device 10 includes a display portion 20, a scanning line driver circuit 11, a signal line driver circuit 13, and a power supply circuit 15. The display portion 20 includes a plurality of pixels 21 arranged in a matrix. Note that the power supply circuit 15 may be provided outside the display device 10.

[0048] The scanning line driving circuit 11 is electrically connected to the pixels 21 via wiring 41. The wiring 41 extends, for example, in the row direction of the matrix.

[0049] The signal line driving circuit 13 is electrically connected to the pixels 21 via wiring 43. The wiring 43 extends, for example, in the column direction of the matrix.

[0050] The power supply circuit 15 is electrically connected to the pixels 21 via wiring 45. For example, all of the pixels 21 can be electrically connected to the power supply circuit 15 via the same wiring 45.

[0051] 1A, the wiring 41 and the wiring 43 are shown as straight lines, but one straight line does not necessarily mean one wiring, and multiple wirings may be represented by one straight line. In the block diagrams and circuit diagrams that follow, multiple wirings may also be represented by one straight line. Furthermore, multiple wirings other than the wiring 41 and the wiring 43 may also be represented by one straight line.

[0052] The pixel 21 has a display element, and can display an image on the display unit 20 by using the display element. As the display element, for example, a light-emitting element, specifically an organic EL element, can be used. Alternatively, a liquid crystal element (also called a liquid crystal device) can be used as the display element.

[0053] The scanning line driver circuit 11 has a function of selecting, for example, the pixels 21 to which image data is to be written, row by row. Specifically, the scanning line driver circuit 11 can select the pixels 21 to which image data is to be written by outputting a signal to a wiring 41. Here, the scanning line driver circuit 11 can select all the pixels 21 by outputting the signal to the wiring 41 in the first row, for example, and then to the wiring 41 in the second row, and so on, in order up to the wiring 41 in the final row. Therefore, the signal that the scanning line driver circuit 11 outputs to the wiring 41 is a scanning signal, and the wiring 41 can be called a scanning line.

[0054] The signal line driver circuit 13 has a function of generating image data. The image data is supplied to the pixels 21 via wirings 43. For example, the image data can be written to all the pixels 21 included in the row selected by the scanning line driver circuit 11. Here, the image data can be expressed as a signal (image signal). Therefore, the wirings 43 can be called signal lines.

[0055] The power supply circuit 15 has a function of generating a power supply potential and supplying it to the wiring 45. The power supply circuit 15 has a function of generating, for example, a high power supply potential (hereinafter simply referred to as "high potential" or "VDD") and supplying it to the wiring 45. The power supply circuit 15 may also have a function of generating a low power supply potential (hereinafter simply referred to as "low potential" or "VSS"). Because a power supply potential is supplied to the wiring 45, the wiring 45 can be referred to as a power supply line.

[0056] The wiring 41 and the wiring 45 have an overlapping region with an insulating layer interposed therebetween. As a result, a parasitic capacitance 25 is formed between the wiring 41 and the wiring 45. The charge accumulated in the parasitic capacitance 25 can be supplied to the wiring 45. Therefore, the parasitic capacitance 25 can function as a bypass capacitor. Here, the thinner the insulating layer between the wiring 41 and the wiring 45 is, the larger the capacitance value of the parasitic capacitance 25 becomes.

[0057] The larger the capacitance value of the parasitic capacitance 25, the larger the amount of charge that can be supplied to the wiring 45. Therefore, the larger the capacitance value of the parasitic capacitance 25, the more effectively it is possible to suppress a voltage drop in the power supply potential generated by the power supply circuit 15, for example, due to wiring resistance. Therefore, particularly in pixels 21 that are located a long wiring distance from the power supply circuit 15, it is possible to effectively suppress a drop in the potential supplied as the power supply potential, which would prevent the pixels 21 from being able to emit light with the desired brightness, for example. As a result, the display device 10 can be made into a display device with high display quality.

[0058] FIG. 1B is a plan view showing an example of the configuration of a pixel 21. The pixel 21 can have multiple sub-pixels 23. FIG. 1B illustrates an example in which the pixel 21 has sub-pixels 23R, 23G, and 23B. Here, when the pixel 21 has a light-emitting element as a display element, for example, the planar shape of the sub-pixels shown in FIG. 1B corresponds to the planar shape of the light-emitting region of the light-emitting element. Note that FIG. 1B illustrates the sub-pixels 23R, 23G, and 23B as having the same or approximately the same aperture ratio (which can also be referred to as the size or the size of the light-emitting region), but this is not a limitation of one embodiment of the present invention. The aperture ratios of the sub-pixels 23R, 23G, and 23B can be determined as appropriate. The aperture ratios of the sub-pixels 23R, 23G, and 23B may be different from one another, or two or more of them may be the same or approximately the same.

[0059] In this specification and the like, when describing matters common to, for example, the subpixels 23R, 23G, and 23B, the alphabets that distinguish them may be omitted and they may be referred to as subpixels 23. When describing matters common to other elements that are distinguished by alphabets, they may also be described using symbols without the alphabets.

[0060] 1B, a stripe arrangement is applied as an arrangement method of the sub-pixels 23. Note that an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, a Pentile arrangement, or the like may also be applied as an arrangement method of the sub-pixels 23. For an example of the planar shape of the sub-pixels, the arrangement of the sub-pixels, and the like, refer to the fourth embodiment.

[0061] The sub-pixels 23R, 23G, and 23B each emit light of a different color. Examples of the sub-pixels 23R, 23G, and 23B include sub-pixels of three colors: red (R), green (G), and blue (B), and sub-pixels of three colors: yellow (Y), cyan (C), and magenta (M). The pixel 21 may also include four or more sub-pixels 23. For example, the pixel 21 may include sub-pixels of four colors: R, G, B, and white (W). As described above, the display device 10 can display a full-color image on the display unit 20 by including a plurality of sub-pixels 23 that emit light of different colors in the pixel 21. The pixel 21 may also include sub-pixels of R, G, B, and infrared (IR) light, for example.

[0062] The display unit 20 may be provided with a sensor, for example, a sensor may be provided in the pixel 21. For example, the display unit 20 may have a function as a fingerprint sensor. For example, the display unit 20 may have a function as an optical or ultrasonic fingerprint sensor.

[0063] 1C is a circuit diagram showing an example of the configuration of the sub-pixel 23. The sub-pixel 23 shown in FIG.

[0064] The pixel circuit 40A includes a transistor 51, a transistor 52, and a capacitor 57. That is, the pixel circuit 40A is a 2Tr (transistor) 1C (capacitor) type pixel circuit.

[0065] In the pixel circuit 40A, one of the source and the drain of the transistor 51 is electrically connected to the wiring 43. The other of the source and the drain of the transistor 51 is electrically connected to the gate of the transistor 52. The gate of the transistor 52 is electrically connected to one electrode of the capacitor 57. The gate of the transistor 51 is electrically connected to the wiring 41.

[0066] One of the source and drain of the transistor 52 is electrically connected to the wiring 45. The other of the source and drain of the transistor 52 is electrically connected to the other electrode of the capacitor 57. The other electrode of the capacitor 57 is electrically connected to one electrode of the light-emitting element 60. The other electrode of the light-emitting element 60 is electrically connected to the wiring 47. Here, the one electrode of the light-emitting element 60 is also referred to as a pixel electrode. Furthermore, the wiring 47 can be shared by, for example, all of the sub-pixels 23. Therefore, the other electrode of the light-emitting element 60 can also be referred to as a common electrode.

[0067] As described above, the wiring 41 functions as a scanning line, the wiring 43 functions as a signal line, and the wiring 45 functions as a power supply line. The wiring 47 also functions as a power supply line, and when a high power supply potential is supplied to the wiring 45, a low power supply potential is supplied to the wiring 47. The wiring 47 can be electrically connected to the power supply circuit 15, for example.

[0068] The transistor 51 functions as a switch and is also referred to as a selection transistor. The transistor 51 controls conduction and non-conduction between the wiring 43 and the gate of the transistor 52 based on the potential of the wiring 41. Image data is written to the pixel circuit 40A by turning on the transistor 51, and the written image data is held by turning off the transistor 51.

[0069] The transistor 52 has a function of controlling the amount of current flowing through the light-emitting element 60 and is also referred to as a driving transistor. The capacitor 57 has a function of holding the gate potential of the transistor 52. The light emission luminance of the light-emitting element 60 is controlled in accordance with a potential corresponding to image data that is supplied to the gate of the transistor 52. Specifically, when a high power supply potential is supplied to the wiring 45 and a low power supply potential is supplied to the wiring 47, the amount of current flowing from the wiring 45 to the wiring 47 is controlled in accordance with the gate potential of the transistor 52. This controls the light emission luminance of the light-emitting element 60.

[0070] OS transistors are preferably used as the transistors 51 and 52. OS transistors have higher field-effect mobility than, for example, transistors using amorphous silicon. Therefore, by using OS transistors as the transistors 51 and 52, the display device 10 can be driven at high speed.

[0071] Furthermore, an OS transistor has an extremely small source-drain leakage current (also referred to as off-state current) in an off state. Therefore, by using an OS transistor as the transistor 51, charge stored in the capacitor 57 can be held for a long period of time. This allows image data written to the subpixel 23 to be held for a long period of time, thereby reducing the frequency of refresh operations (rewriting image data to the subpixel 23). As a result, the power consumption of the display device 10 can be reduced.

[0072] Here, to increase the emission luminance of the light-emitting element 60, it is necessary to increase the amount of current flowing through the light-emitting element 60. To achieve this, it is necessary to increase the source-drain voltage of the transistor 52, which is a driving transistor. Because an OS transistor has a higher withstand voltage between the source and drain than a transistor using silicon (also referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the transistor 52, it is possible to increase the amount of current flowing through the light-emitting element 60 and increase the emission luminance of the light-emitting element 60.

[0073] An OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as the transistor 52, the current flowing between the source and drain can be precisely controlled by changing the gate-source voltage. This allows for precise control of the amount of current flowing through the light-emitting element 60. This allows for precise control of the luminance of light emitted by the subpixel 23. This increases the number of gray levels that can be expressed by the subpixel 23.

[0074] In terms of saturation characteristics of the current that flows when a transistor operates in a saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as the transistor 52, a stable current can be passed through the light-emitting element 60, even when the current-voltage characteristics of each light-emitting element 60 vary from one light-emitting element 60 to another. In other words, when an OS transistor operates in a saturation region, the source-drain current hardly changes even when the source-drain voltage increases, and thus the light-emitting luminance of the light-emitting element 60 can be stabilized.

[0075] As described above, by using an OS transistor for the transistor 52, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," and "suppression of variation in light emission luminance of each light-emitting element 60," etc.

[0076] 1C, the transistors 51 and 52 are n-channel transistors, but one or both of the transistors 51 and 52 may be p-channel transistors. The same applies to other transistors described in this specification.

[0077] It is preferable to use, for example, an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode) as the light-emitting element 60. Examples of the light-emitting material contained in the light-emitting element 60 include a fluorescent material (fluorescent material), a phosphorescent material (phosphorescent material), a material that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF material), and an inorganic compound (e.g., a quantum dot material). Furthermore, an LED such as a micro LED (light-emitting diode) can also be used as the light-emitting element 60.

[0078] 1D is a circuit diagram showing an example of the configuration of the sub-pixel 23. The sub-pixel 23 shown in FIG.

[0079] The pixel circuit 40B includes a transistor 51 and a capacitor 57. That is, the pixel circuit 40B is a 1Tr1C type pixel circuit.

[0080] In the pixel circuit 40B, one of the source and drain of the transistor 51 is electrically connected to a wiring 43. The other of the source and drain of the transistor 51 is electrically connected to one electrode of a capacitor 57. One electrode of the capacitor 57 is electrically connected to one electrode of a liquid crystal element 69. The gate of the transistor 51 is electrically connected to a wiring 41. The other electrode of the capacitor 57 and the other electrode of the liquid crystal element 69 are electrically connected to a wiring 45. Here, the one electrode of the liquid crystal element 69 is also referred to as a pixel electrode. The other electrode of the liquid crystal element 69 may also be referred to as a common electrode. In the pixel circuit 40B, a ground potential, for example, can be supplied to the wiring 45.

[0081] In the pixel circuit 40B, the transistor 51 functions as a switch and controls electrical continuity or non-conduction between the wiring 43 and one electrode of the liquid crystal element 69 based on the potential of the wiring 41. When the transistor 51 is turned on, image data is written to the pixel circuit 40B, and when the transistor 51 is turned off, the written image data is held.

[0082] The capacitor 57 has a function of holding the potential of one electrode of the liquid crystal element 69. The alignment state of the liquid crystal molecules of the liquid crystal element 69 is controlled in accordance with the potential corresponding to image data that is supplied to one electrode of the liquid crystal element 69.

[0083] The modes of the liquid crystal element 69 include, for example, TN (Twisted Nematic) mode, STN (Super-Twisted Nematic) mode, VA (Vertical Alignment) mode, ASM (Axially Symmetric Aligned Micro-cell) mode, OCB (Opticaly Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti-Ferroelectric Liquid Crystal) mode, MVA (Multidomain Vertical Alignment) mode, and PVA (Patterned Vertical Alignment mode, In Plane Switching (IPS) mode, Fringe Field Switching (FFS) mode, or Transverse Bend Alignment (TBA) mode may be used. Other examples include Electrically Controlled Birefringence (ECB) mode, Polymer Dispersed Liquid Crystal (PDLC) mode, Polymer Network Liquid Crystal (PNLC) mode, and Guest-Host mode. However, the present invention is not limited to these, and various other modes may be used.

[0084] 2A is a block diagram showing an example of the configuration of a display device 10, which is a modified example of the display device 10 shown in Fig. 1A. The display device 10 shown in Fig. 2A differs from the display device 10 shown in Fig. 1A in that it has wiring 41a and wiring 41b as wiring 41 and is provided with a reference potential generating circuit 17. In the example shown in Fig. 2A, parasitic capacitance 25 is formed between wiring 41a and wiring 45, and between wiring 41b and wiring 45.

[0085] The reference potential generating circuit 17 is electrically connected to the pixels 21 via the wiring 48. For example, all of the pixels 21 can be electrically connected to the reference potential generating circuit 17 via the same wiring 48. The reference potential generating circuit 17 has a function of generating a reference potential to correct variations in the gate-source potential of each transistor 52, for example, and supplying the reference potential to the wiring 48. Since the potential of the wiring 48 serves as the reference potential, the wiring 48 can be referred to as a reference potential line. The reference potential generating circuit 17 may also be referred to as a power supply circuit. Furthermore, the power supply circuit 15 and the reference potential generating circuit 17 may be integrated into a single circuit. For example, the reference potential generating circuit 17 may be included in the power supply circuit 15.

[0086] Fig. 2B is a circuit diagram showing an example configuration of the sub-pixel 23 included in the pixel 21 shown in Fig. 2A. The sub-pixel 23 shown in Fig. 2B includes a pixel circuit 40C and a light-emitting element 60. The pixel circuit 40C has a configuration in which a transistor 53 is added to the pixel circuit 40A. The pixel circuit 40C is a 3Tr1C type pixel circuit.

[0087] In the pixel circuit 40C, the gate of the transistor 51 is electrically connected to a wiring 41a. One of the source and the drain of the transistor 53 is electrically connected to the other of the source and the drain of the transistor 52, the other electrode of the capacitor 57, and one electrode of the light-emitting element 60. The other of the source and the drain of the transistor 53 is electrically connected to a wiring 48. The gate of the transistor 53 is electrically connected to a wiring 41b.

[0088] The transistor 53 functions as a switch and controls, based on the potential of the wiring 41 b, whether the wiring 48 is electrically connected or disconnected from one electrode of the light-emitting element 60. For example, a reference potential is supplied to the wiring 48. The reference potential of the wiring 48 supplied via the transistor 53 can suppress variations in the gate-source potential of each transistor 52.

[0089] Furthermore, a current value that can be used to set pixel parameters can be obtained based on the current value of the wiring 48. More specifically, the wiring 48 can function as a monitor line for outputting the current flowing through the transistor 52 or the current flowing through the light-emitting element 60 to the outside of the pixel 21. The current output to the wiring 48 can be converted into a potential by, for example, a source follower circuit, or into a digital signal by, for example, an A-D converter. Note that when the wiring 48 functions as a monitor line, the display device 10 does not need to include the reference potential generating circuit 17. Furthermore, when the wiring 48 functions as a monitor line, the pixels 21 can be electrically connected to different wirings 48 for each column.

[0090] An OS transistor is preferably used as the transistor 53. As described above, an OS transistor has higher field-effect mobility than, for example, a transistor using amorphous silicon. Therefore, by using an OS transistor as the transistor 53, the display device 10 can be driven at high speed.

[0091] <Structure Example of Semiconductor Device> Figure 3A1 is a plan view illustrating a structure example of a semiconductor device included in a display device of one embodiment of the present invention, specifically, a plan view illustrating a structure example of a transistor 50, which is a transistor included in the display device of one embodiment of the present invention, and its surroundings. Figure 3B is a cross-sectional view along dashed dotted line A1-A2 in Figure 3A1. Note that some components of the transistor 50, such as an insulating layer, are omitted in Figure 3A1. In the plan views of the transistor, some components, such as an insulating layer, are also omitted in the subsequent drawings.

[0092] The transistor 50 can be applied to, for example, a transistor included in the pixel 21. For example, the transistor 50 can be applied to transistors 51 to 54 and transistors 61 to 66. The transistor 50 may also be applied to at least some of the transistors included in the scan line driver circuit 11, the signal line driver circuit 13, the power supply circuit 15, and the reference potential generation circuit 17.

[0093] The transistor 50 is provided over a substrate 101. The transistor 50 includes a conductive layer 111, a conductive layer 112, a semiconductor layer 113, an insulating layer 105, and a conductive layer 115. In FIG. 3A1, the conductive layer 112 extends in a direction parallel to the conductive layer 111 and in a direction perpendicular to the conductive layer 115.

[0094] 3A1 and 3B, as shown on the coordinate axes, the direction in which the conductive layer 112 extends is the X direction. Furthermore, the direction perpendicular to the X direction and parallel to, for example, the upper surface of the substrate 101 (also referred to as the surface of the substrate 101) is the Y direction, and the direction perpendicular to the upper surface of the substrate 101 is the Z direction. In the following drawings, the definitions of the X direction, Y direction, and Z direction are also shown on the coordinate axes, but these definitions may be the same as or different from those in FIGS. 3A1 and 3B. In any definition, the X direction, Y direction, and Z direction can be perpendicular to each other. Furthermore, the X direction and Y direction can be parallel to the upper surface of the substrate (also referred to as the surface of the substrate), and the Z direction can be perpendicular to the upper surface of the substrate.

[0095] The conductive layer 111 functions as one of a source electrode and a drain electrode of the transistor 50. The conductive layer 112 functions as the other of the source electrode and the drain electrode of the transistor 50. The insulating layer 105 functions as a gate insulating layer of the transistor 50. The conductive layer 115 functions as a gate electrode of the transistor 50.

[0096] In the semiconductor layer 113, an entire region that overlaps with the gate electrode between the source electrode and the drain electrode via the gate insulating layer functions as a channel formation region. In addition, in the semiconductor layer 113, a region in contact with the source electrode functions as a source region, and a region in contact with the drain electrode functions as a drain region.

[0097] A conductive layer 111 is provided over a substrate 101, an insulating layer 103 is provided over the substrate 101 and the conductive layer 111, and a conductive layer 112 is provided over the insulating layer 103. The insulating layer 103 can function as an interlayer insulating layer. The conductive layers 111 and 112 overlap each other through the insulating layer 103. The thickness of the insulating layer 103, which functions as an interlayer insulating layer, can be thicker than the thickness of the insulating layer 105, which functions as a gate insulating layer of the transistor 50.

[0098] The insulating layer 103 has an opening 121 that reaches the conductive layer 111. The conductive layer 112 has an opening 123 that reaches the opening 121. That is, the opening 123 has a region that overlaps with the opening 121. The opening 123 also has a region that overlaps with the conductive layer 111. Here, it is preferable that the conductive layer 112 is not provided inside the opening 121. That is, it is preferable that the conductive layer 112 is not in contact with the side surface of the insulating layer 103 on the opening 121 side.

[0099] 3A1 shows conductive layers 111, 112, semiconductor layers 113, conductive layers 115, openings 121, and 123 as components of the transistor 50. Here, FIG. 3A2 shows a configuration example in which the conductive layer 115 is omitted from the components shown in FIG. 3A1. That is, FIG. 3A2 shows the conductive layers 111, 112, semiconductor layers 113, openings 121, and 123. Furthermore, FIG. 3A3 shows a configuration example in which the semiconductor layer 113 is further omitted from the components shown in FIG. 3A2. That is, FIG. 3A3 shows the conductive layers 111, 112, openings 121, and 123.

[0100] 3A3 and 3B , the conductive layer 112 has an opening 123 in a region overlapping with the conductive layer 111. As shown in Fig. 3A3 , the conductive layer 112 can be configured to cover the entire outer periphery of the opening 121 in a plan view. Here, it is preferable that the conductive layer 112 is not provided inside the opening 121. In other words, it is preferable that the conductive layer 112 not be in contact with the side surface of the insulating layer 103 on the opening 121 side.

[0101] 3A1, 3A2, and 3A3 show examples in which the openings 121 and 123 are each circular in plan view. By making the planar shapes of the openings 121 and 123 circular, the processing accuracy when forming the openings 121 and 123 can be improved, and the openings 121 and 123 can be formed with finer sizes. Note that in this specification, a circle is not limited to a perfect circle. The planar shapes of the openings 121 and 123 may also be, for example, elliptical.

[0102] 3B shows an example in which the end of the conductive layer 112 on the opening 123 side coincides with or roughly coincides with the end of the insulating layer 103 on the opening 121 side. It can also be said that the planar shape of the opening 123 coincides with or roughly coincides with the planar shape of the opening 121. Note that in this specification, the end of the conductive layer 112 on the opening 123 side and the end of the opening 123 refer to the end of the lower surface of the conductive layer 112 on the opening 123 side. The lower surface of the conductive layer 112 refers to the surface on the insulating layer 103 side. The end of the insulating layer 103 on the opening 121 side and the end of the opening 121 refer to the end of the upper surface of the insulating layer 103 on the opening 121 side. The upper surface of the insulating layer 103 refers to the surface on the conductive layer 112 side. Furthermore, the planar shape of the opening 123 refers to the planar shape of the end of the lower surface of the conductive layer 112 on the opening 123 side. The planar shape of the opening 121 refers to the planar shape of the upper surface edge of the insulating layer 103 on the opening 121 side.

[0103] Incidentally, "the edges coincide or approximately coincide" can also be said to mean that the edges are aligned or approximately aligned. When the edges are aligned or approximately aligned, and when the planar shapes are aligned or approximately aligned, it can be said that at least a portion of the contours of the stacked layers overlap in a planar view. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or partially the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer. In these cases, it is also said that the edges are approximately aligned or the planar shapes are approximately aligned.

[0104] The opening 121 can be formed, for example, by using the resist mask used to form the opening 123. Specifically, after the conductive layer 111 is first formed over the substrate 101, the insulating layer 103, a conductive film that will become the conductive layer 112 in a later step over the insulating layer 103, and a resist mask over the conductive film are formed over the substrate 101 and the conductive layer 111. Then, the opening 123 is formed in the conductive film using the resist mask, and then the opening 121 is formed in the insulating layer 103 using the resist mask. This allows the edge of the opening 121 to coincide or approximately coincide with the edge of the opening 123. This structure can simplify the process.

[0105] The semiconductor layer 113 is provided to cover the openings 121 and 123 and to have regions located inside the openings 121 and 123. The semiconductor layer 113 has a shape that follows the shapes of the upper surface and side surfaces of the conductive layer 112, the side surfaces of the insulating layer 103, and the upper surface of the conductive layer 111. The semiconductor layer 113 has regions that are in contact with, for example, the upper surface and side surfaces of the conductive layer 112, the side surfaces of the insulating layer 103, and the upper surface of the conductive layer 111.

[0106] The semiconductor layer 113 preferably covers the end of the conductive layer 112 on the opening 123 side. For example, FIG. 3B shows a structure in which the end of the semiconductor layer 113 is located on the conductive layer 112. It can also be said that the end of the semiconductor layer 113 is in contact with the top surface of the conductive layer 112.

[0107] 3B shows the semiconductor layer 113 having a single-layer structure, one embodiment of the present invention is not limited thereto, and the semiconductor layer 113 may have a stacked structure of two or more layers.

[0108] The insulating layer 105, which functions as a gate insulating layer of the transistor 50, is provided to cover the openings 121 and 123 and to have regions located inside the openings 121 and 123. The insulating layer 105 is provided over the semiconductor layer 113, the conductive layer 112, and the insulating layer 103. The insulating layer 105 can have regions in contact with the top surface and side surfaces of the semiconductor layer 113, the top surface and side surfaces of the conductive layer 112, and the top surface of the insulating layer 103. The insulating layer 105 has a shape that follows the shapes of the top surface of the insulating layer 103, the top surface and side surfaces of the conductive layer 112, and the top surface and side surfaces of the semiconductor layer 113.

[0109] The conductive layer 115 functioning as the gate electrode of the transistor 50 is provided over the insulating layer 105 and can have a region in contact with the top surface of the insulating layer 105. The conductive layer 115 has a region overlapping with the semiconductor layer 113 with the insulating layer 105 interposed therebetween.

[0110] For example, as shown in FIG. 3B , the conductive layer 115 is provided so as to have a region located inside the opening 121 and a region located inside the opening 123, and also to have a region facing the semiconductor layer 113 with the insulating layer 105 sandwiched therebetween. In the example shown in FIG. 3B , the conductive layer 115 has regions overlapping with the conductive layer 111 and the conductive layer 112 via the insulating layer 105 and the semiconductor layer 113. The conductive layer 115 also covers the entire semiconductor layer 113. With this structure, a gate electric field can be applied to the entire semiconductor layer 113, thereby improving the electrical characteristics of the transistor 50 and increasing, for example, the on-state current of the transistor. Furthermore, by providing the insulating layer 103 between the conductive layer 111 and the conductive layer 115 in addition to the insulating layer 105 functioning as a gate insulating layer, the parasitic capacitance formed by the conductive layer 111 and the conductive layer 115 is reduced compared to when, for example, the insulating layer 103 is the only insulating layer provided between the conductive layer 111 and the conductive layer 115.

[0111] The transistor 50 is a so-called top-gate transistor having a gate electrode above the semiconductor layer 113. Furthermore, since the bottom surface of the semiconductor layer 113 has a region in contact with the source electrode and the drain electrode, the transistor 50 can be called a TGBC (Top Gate Bottom Contact) transistor.

[0112] The channel length and channel width of the transistor 50 will now be described with reference to FIGS. 4A and 4B. FIG. 4A is an enlarged plan view showing an example of the configuration of the transistor 50 and its periphery shown in FIG. 3A1. FIG. 4B is a cross-sectional view taken along dashed line A1-A2 shown in FIG. 4A.

[0113] In the semiconductor layer 113, a region in contact with the conductive layer 111 functions as one of a source region and a drain region, a region in contact with the conductive layer 112 functions as the other of the source region and the drain region, and a region between the source region and the drain region functions as a channel formation region.

[0114] The channel length of the transistor 50 is the distance between the source region and the drain region. In Figure 4B, the channel length L50 of the transistor 50 is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length L50 is the distance between the edge of the region where the semiconductor layer 113 and the conductive layer 111 contact each other and the edge of the region where the semiconductor layer 113 and the conductive layer 112 contact each other.

[0115] Here, the channel length L50 of the transistor 50 corresponds to the length of the side surface of the insulating layer 103 on the opening 121 side when viewed from the XZ plane. In other words, the channel length L50 is determined by the film thickness T103 of the insulating layer 103 and the angle θ103 between the side surface of the insulating layer 103 on the opening 121 side and the surface on which the insulating layer 103 is to be formed (here, the top surface of the conductive layer 111), and is not affected by the performance of the exposure device used to fabricate the transistor. Therefore, the channel length L50 can be made smaller than the resolution limit of the exposure device, and a transistor with a fine size can be realized. For example, the channel length L50 is preferably 0.01 μm or more and less than 3.0 μm, more preferably 0.05 μm or more and less than 3.0 μm, even more preferably 0.10 μm or more and less than 3.0 μm, even more preferably 0.15 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 2.5 μm, even more preferably 0.20 μm or more and less than 2.0 μm, even more preferably 0.20 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and 1.0 μm or less, and even more preferably 0.50 μm or more and 1.0 μm or less. In FIG. 4B, the thickness T103 of the insulating layer 103 is indicated by a dashed line with a double-headed arrow.

[0116] The reduction in the channel length L50 can increase the on-state current of the transistor 50. Therefore, by using the transistor 50 as a transistor included in the display device 10, for example, as a transistor included in the pixel 21, the display device 10 can be driven at high speed.

[0117] By adjusting the thickness T103 and angle θ103 of the insulating layer 103, the channel length L50 can be controlled.

[0118] The film thickness T103 of the insulating layer 103 is preferably 0.01 μm or more and less than 3.0 μm, more preferably 0.05 μm or more and less than 3.0 μm, even more preferably 0.10 μm or more and less than 3.0 μm, even more preferably 0.15 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 2.5 μm, even more preferably 0.20 μm or more and less than 2.0 μm, even more preferably 0.20 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and less than 1.2 μm, even more preferably 0.40 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and less than 1.0 μm, even more preferably 0.50 μm or more and less than 1.0 μm.

[0119] The side surface of the insulating layer 103 on the opening 121 side is preferably tapered. The angle θ103 formed between the side surface of the insulating layer 103 on the opening 121 side and the surface on which the insulating layer 103 is to be formed (here, the top surface of the conductive layer 111) is preferably less than 90 degrees. By reducing the angle θ103, the coverage of a layer (e.g., the semiconductor layer 113) provided on the insulating layer 103 can be improved. However, reducing the angle θ103 reduces the contact area between the semiconductor layer 113 and the conductive layer 111, which may increase the contact resistance between the semiconductor layer 113 and the conductive layer 111. The angle θ103 is preferably 45 degrees or more and less than 90 degrees, more preferably 50 degrees or more and less than 90 degrees, even more preferably 55 degrees or more and less than 90 degrees, even more preferably 60 degrees or more and less than 90 degrees, even more preferably 60 degrees or more and less than 85 degrees, even more preferably 65 degrees or more and less than 85 degrees, even more preferably 65 degrees or more and less than 80 degrees, and even more preferably 70 degrees or more and less than 80 degrees. By setting the angle θ103 within the above range, the channel length of the transistor 50 can be shortened while improving the coverage of the conductive layer 111 and the layer (e.g., the semiconductor layer 113) formed on the insulating layer 103, and defects such as discontinuities or voids in the layer can be suppressed. Furthermore, the contact resistance between the semiconductor layer 113 and the conductive layer 111 can be reduced.

[0120] In this specification and the like, the term "step discontinuity" refers to a phenomenon in which a layer, film, or electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0121] 4B shows a cross-sectional view in which the side surface of the insulating layer 103 on the opening 121 side has a straight line shape, but one embodiment of the present invention is not limited to this. In the cross-sectional view, the side surface of the insulating layer 103 on the opening 121 side may have a curved line shape, or the side surface may have both a straight line region and a curved line region.

[0122] The channel width of the transistor 50 is the width of the source region or the width of the drain region in a direction perpendicular to the channel length direction. That is, the channel width is the width of the region where the semiconductor layer 113 and the conductive layer 111 contact each other or the width of the region where the semiconductor layer 113 and the conductive layer 112 contact each other in a direction perpendicular to the channel length direction. Here, the channel width of the transistor 50 is described as the width of the region where the semiconductor layer 113 and the conductive layer 112 contact each other in a direction perpendicular to the channel length direction. In Figures 4A and 4B, the channel width W50 of the transistor 50 is indicated by a solid double-headed arrow. The channel width W50 is the length of the bottom end of the conductive layer 112 on the opening 123 side in a plan view.

[0123] The channel width W50 is determined by the planar shape of the opening 123. In Figures 4A and 4B, the width D123 of the opening 123 is indicated by a two-dot chain line with a double arrow. The width D123 indicates the short side of the smallest rectangle circumscribing the opening 123 in a planar view. When the opening 123 is formed using photolithography, the width D123 of the opening 123 is equal to or greater than the resolution limit of the exposure device. The width D123 is, for example, preferably 0.20 μm or more and less than 5.0 μm, more preferably 0.20 μm or more and less than 4.5 μm, even more preferably 0.20 μm or more and less than 4.0 μm, even more preferably 0.20 μm or more and less than 3.5 μm, even more preferably 0.20 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 2.5 μm, even more preferably 0.20 μm or more and less than 2.0 μm, even more preferably 0.20 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and 1.0 μm or less, and even more preferably 0.50 μm or more and 1.0 μm or less. When the planar shape of the opening 123 is circular, the width D123 corresponds to the diameter of the opening 123, and the channel width W50 can be made equal to the outer periphery of the opening 123 in a planar view, and can be calculated as "D123 x π".

[0124] <Pixel Configuration Example 1> Fig. 5 is a plan view showing a configuration example of the pixel circuit 40A shown in Fig. 1C. Fig. 6 is a cross-sectional view taken along dashed dotted line B1-B2 shown in Fig. 5. Fig. 5 shows two rows and two columns of pixel circuits 40A (pixel circuit 40A[i,j], pixel circuit 40A[i,j+1], pixel circuit 40A[i+1,j], and pixel circuit 40A[i+1,j+1]). Here, i and j are integers equal to or greater than 1.

[0125] 5 and 6 , the structures of the transistor 51 and the transistor 52 are the same as the structure of the transistor 50 shown in FIGS. 3A1 and 3B . Here, the conductive layer 111, the conductive layer 112, the semiconductor layer 113, and the conductive layer 115 included in the transistor 51 are referred to as the conductive layer 111a, the conductive layer 112a, the semiconductor layer 113a, and the conductive layer 115a, respectively. The conductive layer 111, the conductive layer 112, the semiconductor layer 113, and the conductive layer 115 included in the transistor 52 are referred to as the conductive layer 111b, the conductive layer 112b, the semiconductor layer 113b, and the conductive layer 115b, respectively. Furthermore, the openings 121 and 123 provided in the transistor 51 are referred to as the openings 121a and 123a, respectively, and the openings 121 and 123 provided in the transistor 52 are referred to as the openings 121b and 123b, respectively.

[0126] Fig. 7A shows a plan view in which the conductive layers 115a and 115b shown in Fig. 5 are shown without hatching patterns and with two-dot chain lines. Fig. 7B shows a plan view in which the semiconductor layers 113a and 113b are shown without hatching patterns and with two-dot chain lines, which is an addition to the plan view shown in Fig. 7A. Figs. 7A and 7B show an example configuration of one pixel circuit 40A.

[0127] 5 and 6 includes a conductive layer 117 over the insulating layer 103, an insulating layer 105 over the conductive layer 117, and a conductive layer 115b that is provided over the insulating layer 105 and has a region that overlaps with the conductive layer 117. Here, the conductive layer 117 can be provided in the same layer as the conductive layer 112. Therefore, the conductive layer 117 can have the same material as the conductive layer 112 and can be formed in the same process. For example, the conductive layer 112 and the conductive layer 117 can be formed by processing the same conductive film.

[0128] The insulating layer 105 has an opening 125a that reaches the conductive layer 112a, and the conductive layer 112a and the conductive layer 115b are electrically connected inside the opening 125a. Specifically, for example, the opening 125a has a region where the conductive layer 112a and the conductive layer 115b are in contact with each other. The insulating layer 103 has an opening 125b that reaches the conductive layer 111b, and the conductive layer 111b and the conductive layer 117 are electrically connected inside the opening 125b. Specifically, for example, the opening 125b has a region where the conductive layer 111b and the conductive layer 117 are in contact with each other.

[0129] In Figures 5, 7A, and 7B, the shapes of openings 125a and 125b in a plan view are circular, but one embodiment of the present invention is not limited to this and can be the same shape as the shape that opening 121 can take, or the same shape as the shape that opening 123 can take.

[0130] At least a part of the conductive layer 111a functions as a wiring 43 that functions as a signal line and is electrically connected to the signal line driver circuit 13 shown in Fig. 1A. At least a part of the conductive layer 112b functions as a wiring 45 that functions as a power supply line and is electrically connected to the power supply circuit 15 shown in Fig. 1A. At least a part of the conductive layer 115a functions as a wiring 41 that functions as a scan line and is electrically connected to the scan line driver circuit 11 shown in Fig. 1A.

[0131] The conductive layer 115a has a region extending in the X direction. Furthermore, the conductive layer 111a and the conductive layer 112b have regions extending in the Y direction. The conductive layer 115a has a region overlapping with the conductive layer 111a and a region overlapping with the conductive layer 112b. Specifically, a portion of the region of the conductive layer 115a extending in the X direction overlaps a portion of the region of the conductive layer 111a extending in the Y direction. Furthermore, a portion of the region of the conductive layer 115a extending in the X direction overlaps a portion of the region of the conductive layer 112b extending in the Y direction.

[0132] Here, it may be said that the region of the conductive layer 115a extending in the X direction functions as the wiring 41, or that the entire conductive layer 115a functions as the wiring 41. It may also be said that the region of the conductive layer 111a extending in the Y direction functions as the wiring 43, or that the entire conductive layer 111a functions as the wiring 43. It may also be said that the region of the conductive layer 112b extending in the Y direction functions as the wiring 45, or that the entire conductive layer 112b functions as the wiring 45. Unless otherwise specified, the above also applies to other conductive layers having a region that functions as the wiring 41, the wiring 43, or the wiring 45.

[0133] 5 and 6 , in a region where the conductive layer 111a and the conductive layer 115a overlap, the insulating layer 103 is provided over the conductive layer 111a, the insulating layer 105 is provided over the insulating layer 103, and the conductive layer 115a is provided over the insulating layer 105. That is, in a region where the conductive layer 111a and the conductive layer 115a overlap, the insulating layer 103 and the insulating layer 105 are provided between the conductive layer 111a and the conductive layer 115a. Furthermore, in a region where the conductive layer 112b and the conductive layer 115a overlap, the insulating layer 105 is provided over the conductive layer 112b, and the conductive layer 115a is provided over the insulating layer 105. That is, in a region where the conductive layer that functions as the wiring 41 that functions as a scan line and the conductive layer that functions as the wiring 45 that functions as a power supply line overlap, the insulating layer 105 is provided between these conductive layers, but the insulating layer 103 is not provided.

[0134] In a capacitance where an insulating layer serving as a dielectric is provided between a pair of electrodes, the thinner the insulating layer, the larger the capacitance value of the capacitance. Therefore, when the insulating layer 105 is provided between a conductive layer functioning as wiring 41 and a conductive layer functioning as wiring 45 but the insulating layer 103 is not provided, the capacitance value of the parasitic capacitance 25 formed by these conductive layers is larger than when both the insulating layer 103 and the insulating layer 105 are provided. As a result, charge is supplied from the parasitic capacitance 25 to the wiring 45, that is, the parasitic capacitance 25 functions as a bypass capacitor. Therefore, a voltage drop in the power supply potential generated by the power supply circuit 15, for example, due to wiring resistance, can be suppressed. Therefore, particularly in a pixel 21 that is far from the power supply circuit 15, a drop in the potential supplied as the power supply potential can be suppressed, preventing the pixel 21 from emitting light with a desired luminance, for example. As described above, the display device of one embodiment of the present invention can be a display device with high display quality.

[0135] 8A is an enlarged plan view of a portion of the conductive layer 115a functioning as the wiring 41, a portion of the conductive layer 111a functioning as the wiring 43, and a portion of the conductive layer 112b functioning as the wiring 45, shown in FIG. 8A shows an enlarged view of the region of the conductive layer 115a extending in the X direction, the region of the conductive layer 111a extending in the Y direction, and the region of the conductive layer 112b extending in the Y direction, extracted from FIG.

[0136] In Figure 8A, the distance in the X direction in a plan view between a region of the conductive layer 111a extending in the Y direction and a region of the conductive layer 112b extending in the Y direction is defined as space S1. For example, the shortest distance among these distances can be defined as space S1. Space S1 is the space between the wiring 43 and the wiring 45. Here, the subpixel electrically connected to the wiring 43 shown in Figure 8A and the subpixel electrically connected to the wiring 45 can be subpixels in adjacent columns. For example, when the wiring 45 shown in Figure 8A is electrically connected to the subpixel in the jth column, the wiring 43 shown in Figure 8A can be electrically connected to the subpixel in the j+1th column.

[0137] The widths of the conductive layers 111a and 112b in the regions extending in the Y direction, i.e., the lengths in the X direction, are defined as wiring width L1 and wiring width L2, respectively. Wiring width L1 is the width of the wiring 43. Wiring width L2 is the width of the wiring 45.

[0138] The wiring 43 and the wiring 45 are provided in different layers. Therefore, the space S1 can be made smaller than when the wiring 43 and the wiring 45 are provided in the same layer. For example, as shown in FIG. 8A, the space S1 can be made smaller than the wiring width L1 and also smaller than the wiring width L2.

[0139] Fig. 8B is a modified example of the configuration shown in Fig. 8A, in which the end of the conductive layer 111a overlaps with the conductive layer 112b. In the example shown in Fig. 8B, the space S1 is set to 0.

[0140] 8C is a plan view showing an example configuration in which a conductive layer 111b is added to FIG. 8A . In FIG. 8C , the distance between the conductive layer 111a and the conductive layer 111b in a plan view is defined as a space S2. For example, the shortest distance between the conductive layer 111a and the conductive layer 111b in the X direction or the Y direction in a plan view can be defined as the space S2. The space S2 is the space between the conductive layer 111a and the conductive layer 111b. Here, the conductive layer 111b shown in FIG. 8C can be electrically connected to a subpixel in the same column as the subpixel to which the conductive layer 111a shown in FIG. 8C is electrically connected.

[0141] The conductive layers 111a and 111b are provided on the same layer, and the conductive layers 111a and 112b are provided on different layers. Therefore, the space S1 can be made smaller than the space S2.

[0142] 8D is a plan view showing an example configuration in which a conductive layer 112a is added to FIG. 8A . In FIG. 8D , the distance between the conductive layer 112a and the conductive layer 112b in a planar view is defined as a space S3. For example, the shortest distance between the conductive layer 112a and the conductive layer 112b in the X direction or the Y direction in a planar view can be defined as the space S3. The space S3 is the space between the conductive layer 112a and the conductive layer 112b. Here, the conductive layer 112a shown in FIG. 8D can be electrically connected to a subpixel in the same column as the subpixel to which the conductive layer 112b shown in FIG. 8D is electrically connected.

[0143] The conductive layer 111a and the conductive layer 112a are provided on different layers, and the conductive layer 112a and the conductive layer 112b are provided on the same layer. Therefore, the space S1 can be made smaller than the space S3.

[0144] As described above, in the display device of one embodiment of the present invention, the space S1 can be made small, for example, smaller than the wiring width L1, the wiring width L2, the space S2, and the space S3. Therefore, pixels can be miniaturized, and the display device of one embodiment of the present invention can be a high-definition display device.

[0145] Figures 9A, 10, 11A, and 11B are modifications of the configurations shown in Figures 5, 6, 7A, and 7B, respectively. In the following, descriptions of parts that overlap with Figures 5, 6, 7A, and 7B will be omitted as appropriate.

[0146] 9A , 10 , 11A, and 11B , the capacitor 57 includes a conductive layer 112b on the insulating layer 103, an insulating layer 105 on the conductive layer 112b, and a conductive layer 115b provided on the insulating layer 105 and having a region overlapping with the conductive layer 112b. A portion of the region of the conductive layer 115a extending in the X direction overlaps a portion of the region of the conductive layer 111b extending in the Y direction. It may be said that the region of the conductive layer 111b extending in the Y direction functions as the wiring 45, or that the entire conductive layer 111b functions as the wiring 45.

[0147] The conductive layer 136 is provided so as to have a region overlapping with the conductive layer 111b. Specifically, the conductive layer 136 has a region extending in the Y direction, and this region has a region overlapping with the region of the conductive layer 111b extending in the Y direction.

[0148] The conductive layer 136 is provided between the insulating layer 103 and the insulating layer 105. That is, the conductive layer 136 is provided in the same layer as the conductive layer 112. Therefore, the conductive layer 136 can have the same material as the conductive layer 112 and can be formed in the same process. For example, the conductive layer 112 and the conductive layer 136 can be formed by processing the same conductive film.

[0149] The insulating layer 103 has an opening 126 that reaches the conductive layer 111b, and the conductive layer 111b and the conductive layer 136 are electrically connected inside the opening 126. Specifically, for example, the opening 126 has a region where the conductive layer 111b and the conductive layer 136 are in contact with each other. Note that although the opening 126 has a circular shape in a plan view in FIGS. 9A , 11A, and 11B, one embodiment of the present invention is not limited thereto, and the opening 126 can have the same shape as at least one of the openings 121, 123, and 125.

[0150] 1A. As described above, the conductive layer 136 is electrically connected to the conductive layer 111b that functions as the wiring 45, and therefore the conductive layer 136 also functions as the wiring 45. As described above, the wiring 45 is electrically connected to the power supply circuit 15 shown in FIG. 1A. As described above, the conductive layer 136 is electrically connected to the power supply circuit 15.

[0151] For example, by making not only the conductive layer 111b but also the conductive layer 136 function as the wiring 45, the resistance of the wiring 45 can be reduced compared to when only the conductive layer 111b functions as the wiring 45. Therefore, a voltage drop in the power supply potential generated by the power supply circuit 15 can be suppressed. Therefore, particularly in the pixel 21 that is far from the power supply circuit 15, a drop in the potential supplied as the power supply potential can be suppressed, which can prevent the pixel 21 from being able to emit light with a desired luminance. As described above, the display device of one embodiment of the present invention can be a display device with high display quality.

[0152] 9A and 10 , in a region where the conductive layer 111b and the conductive layer 115a overlap, the insulating layer 103 is provided on the conductive layer 111b, the conductive layer 136 is provided on the insulating layer 103, the insulating layer 105 is provided on the conductive layer 136, and the conductive layer 115a is provided on the insulating layer 105. That is, in a region where the conductive layer 115a functioning as the wiring 41 functioning as a scan line and the conductive layer 136, which is an upper layer of the conductive layer functioning as the wiring 45 functioning as a power supply line, overlap, the insulating layer 105 is provided between these layers but the insulating layer 103 is not provided. On the other hand, the insulating layer 103 is provided between the conductive layer functioning as the wiring 41 and the conductive layer 111b, which is a lower layer of the conductive layer functioning as the wiring 45. Here, in a capacitance in which an insulating layer serving as a dielectric is provided between a pair of electrodes, the thinner the film thickness of the insulating layer, the larger the capacitance value of the capacitance.

[0153] As described above, by providing the conductive layer 136 as the wiring 45, the capacitance value of the parasitic capacitance 25 formed in the region where the wiring 41 and the wiring 45 overlap is larger than when the conductive layer 136 is not provided. As a result, charge is supplied from the parasitic capacitance 25 to the wiring 45, that is, the parasitic capacitance 25 functions as a bypass capacitor. Therefore, a voltage drop in the power supply potential generated by the power supply circuit 15 can be suppressed. Therefore, particularly in the pixel 21 that is far from the power supply circuit 15, a drop in the potential supplied as the power supply potential can be suppressed, which can prevent the pixel 21 from being able to emit light with a desired luminance. As described above, the display device of one embodiment of the present invention can be a display device with high display quality.

[0154] 9B is an enlarged plan view of a portion of the conductive layer 111b and the conductive layer 136 that function as the wiring 45 shown in FIG. 9A. In FIG. 9B, the widths of the conductive layer 111b and the conductive layer 136 in the regions extending in the Y direction, that is, the lengths in the X direction, are defined as wiring width L3 and wiring width L4, respectively. As shown in FIG. 9B, wiring width L3 can be made larger than wiring width L4.

[0155] 9C is a modified example of the configuration shown in FIG. 9B, in which the wiring width L3 is smaller than the wiring width L4. Note that the wiring width L3 and the wiring width L4 may be equal or approximately equal.

[0156] Fig. 12 shows a configuration example in which a pixel electrode 311 of a light emitting element 60 is added to the plan view shown in Fig. 5. Fig. 13 is a cross-sectional view taken along the dashed dotted line B1-B2 shown in Fig. 12.

[0157] An insulating layer 218 and an insulating layer 235 over the insulating layer 218 are provided so as to cover the transistor 51, the transistor 52, and the capacitor 57. A light-emitting element 60 is provided over the insulating layer 235, and a protective layer 331 is provided so as to cover the light-emitting element 60. A substrate 152 is attached to the protective layer 331 with an adhesive layer 142.

[0158] The light-emitting element 60 includes a pixel electrode 311 over the insulating layer 235, an island-shaped layer 313 over the pixel electrode 311, and a common electrode 315 over the island-shaped layer 313. The layer 313 includes at least a light-emitting layer. The layer 313 can be referred to as an EL layer. The common electrode is also referred to as a counter electrode.

[0159] In this specification, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like light-emitting layer refers to a state in which the light-emitting layer is physically separated from an adjacent light-emitting layer.

[0160] The insulating layer 105, the insulating layer 218, and the insulating layer 235 have an opening 129 that reaches the conductive layer 117. A pixel electrode 311 is provided to cover the opening 129. The pixel electrode 311 has a shape that follows the upper and side surfaces of the insulating layer 235, the side surfaces of the insulating layer 218, the side surfaces of the insulating layer 105, and the upper surface of the conductive layer 117. The pixel electrode 311 has regions that contact, for example, the upper and side surfaces of the insulating layer 235, the side surfaces of the insulating layer 218, the side surfaces of the insulating layer 105, and the upper surface of the conductive layer 117. The pixel electrode 311 can be electrically connected to the conductive layer 117 inside the opening 129.

[0161] In Figure 12, the shape of the opening 129 in a planar view is circular, but one embodiment of the present invention is not limited to this, and the opening 129 can have a shape similar to the shape that at least one of the openings 121, 123, and 125 can have.

[0162] 13, an insulating layer 237 can be provided so as to cover the upper end portion of the pixel electrode 311. The insulating layer 237 functions as a partition wall (also referred to as a bank, a spacer, or a partition wall). By providing the insulating layer 237, it is possible to prevent the pixel electrode 311 and the common electrode 315 from coming into contact with each other, thereby preventing the light-emitting element 60 from shorting out.

[0163] A recess is formed in the pixel electrode 311 so as to cover the opening 129, and the recess is filled with an insulating layer 237. For example, after forming the insulating layer 237 that covers the upper surface end of the pixel electrode 311 and the opening 129, the layer 313 can be formed using a fine metal mask (FMM).

[0164] The pixel electrode 311 may have a region overlapping with a region of the conductive layer 111a extending in the Y direction, a region overlapping with a region of the conductive layer 112b extending in the Y direction, or a region overlapping with a region of the conductive layer 115a extending in the X direction. This can increase the aperture ratio of the pixel. On the other hand, since the pixel electrode 311 does not overlap with the region of the conductive layer 111a extending in the Y direction, the region of the conductive layer 112b extending in the Y direction, or the region of the conductive layer 115a extending in the X direction, noise caused by signals supplied to the conductive layer 111a, noise caused by the potential of the conductive layer 112b, and noise caused by signals supplied to the conductive layer 115a can be suppressed from being propagated to the pixel electrode 311.

[0165] A light-shielding layer 317 may be provided on the surface of the substrate 152 on the adhesive layer 142 side. The light-shielding layer 317 can be provided between adjacent light-emitting elements 60. By providing the light-shielding layer 317, reflection of external light into the display portion can be suppressed, thereby improving the display quality of the display device of one embodiment of the present invention. Note that a structure without the light-shielding layer 317 is also possible. In this case, the light extraction efficiency from the light-emitting element 60 can be improved.

[0166] Fig. 14 shows a configuration example in which a pixel electrode 311 of a light-emitting element 60 is added to the plan view shown in Fig. 9A. Fig. 15 is a cross-sectional view taken along dashed dotted line B1-B2 shown in Fig. 14. In the following, descriptions of parts that overlap with Figs. 12 and 13 will be omitted as appropriate.

[0167] The insulating layer 105, the insulating layer 218, and the insulating layer 235 have an opening 129 that reaches the conductive layer 112b. A pixel electrode 311 is provided to cover the opening 129. The pixel electrode 311 has a shape that follows the upper and side surfaces of the insulating layer 235, the side surfaces of the insulating layer 218, the side surfaces of the insulating layer 105, and the upper surface of the conductive layer 112b. The pixel electrode 311 has regions that contact, for example, the upper and side surfaces of the insulating layer 235, the side surfaces of the insulating layer 218, the side surfaces of the insulating layer 105, and the upper surface of the conductive layer 112b. The pixel electrode 311 can be electrically connected to the conductive layer 112b inside the opening 129.

[0168] The pixel electrode 311 may have a region overlapping with a region of the conductive layer 111a extending in the Y direction, a region overlapping with a region of the conductive layer 136 extending in the Y direction, or a region overlapping with a region of the conductive layer 115a extending in the X direction. This can increase the aperture ratio of the pixel. On the other hand, since the pixel electrode 311 does not overlap with the region of the conductive layer 111a extending in the Y direction, the region of the conductive layer 136 extending in the Y direction, or the region of the conductive layer 115a extending in the X direction, noise caused by the signal supplied to the conductive layer 111a, noise caused by the potential of the conductive layer 136, and noise caused by the signal supplied to the conductive layer 115a can be suppressed from being propagated to the pixel electrode 311.

[0169] <Pixel Configuration Example 2> Below, a description will be given of a configuration example of a pixel circuit that is partially different from the configurations of Figures 5 to 7B and Figures 9A to 15. Note that below, descriptions of parts that overlap with Figures 5 to 7B and Figures 9A to 15 will be omitted as appropriate.

[0170] 5, and illustrates an example in which at least a portion of a transistor 51 is provided in a region where the wiring 41 and the wiring 43 overlap, and at least a portion of a transistor 52 is provided in a region where the wiring 45 extends in the Y direction. Specifically, Fig. 16A illustrates an example in which a semiconductor layer 113a, an opening 121a, and an opening 123a are provided in a region where the wiring 41 and the wiring 43 overlap, and a semiconductor layer 113b, an opening 121b, and an opening 123b are provided in a region where the wiring 45 extends in the Y direction. Fig. 16A also illustrates an example in which the semiconductor layer 113a, the opening 121a, and the opening 123a overlap with a region of the conductive layer 111a extending in the Y direction and a region of the conductive layer 115a extending in the X direction. Furthermore, FIG. 16A shows an example in which the semiconductor layer 113b, the opening 121b, and the opening 123b overlap with the region of the conductive layer 112b that extends in the Y direction.

[0171] Fig. 16B is a plan view in which the conductive layers 115a and 115b shown in Fig. 16A are shown by dashed double-dashed lines without hatching patterns. Fig. 16C is a plan view in which the semiconductor layers 113a and 113b shown in Fig. 16B are shown by dashed double-dashed lines without hatching patterns. Fig. 16A shows an example of the configuration of a pixel circuit 40A with two rows and two columns. On the other hand, Figs. 16B and 16C show an example of the configuration of one pixel circuit 40A.

[0172] By configuring the pixel circuit 40A as shown in Fig. 16A, it is possible to miniaturize the pixel while ensuring the area of ​​the capacitor 57, compared to when the pixel circuit 40A has the configuration shown in Fig. 5. On the other hand, by configuring the pixel circuit 40A as shown in Fig. 5, it is possible to increase the degree of freedom in the layout of the pixel circuit 40A, compared to when the pixel circuit 40A has the configuration shown in Fig. 16A.

[0173] 17A is a modification of the configuration shown in Fig. 9A and illustrates an example in which at least a part of the transistor 51 is provided in a region where the wiring 41 and the wiring 43 overlap. Specifically, Fig. 17A illustrates an example in which the semiconductor layer 113a, the opening 121a, and the opening 123a are provided in the region where the wiring 41 and the wiring 43 overlap. Fig. 17A also illustrates an example in which the semiconductor layer 113a, the opening 121a, and the opening 123a overlap with a region of the conductive layer 111a extending in the Y direction and a region of the conductive layer 115a extending in the X direction.

[0174] Fig. 17B is a plan view in which the conductive layers 115a and 115b shown in Fig. 17A are shown by dashed double-dashed lines without hatching patterns. Fig. 17C is a plan view in which the semiconductor layers 113a and 113b shown in Fig. 17B are shown by dashed double-dashed lines without hatching patterns. Fig. 17A shows an example of the configuration of two-row and two-column pixel circuits 40A. On the other hand, Figs. 17B and 17C show an example of the configuration of one pixel circuit 40A.

[0175] By configuring pixel circuit 40A as shown in Fig. 17A, it is possible to miniaturize the pixel while ensuring the area of ​​capacitor 57, compared to when pixel circuit 40A has the configuration shown in Fig. 9A. On the other hand, by configuring pixel circuit 40A as shown in Fig. 9A, it is possible to increase the degree of freedom in the layout of pixel circuit 40A, compared to when pixel circuit 40A has the configuration shown in Fig. 17A.

[0176] 18A is a modification of the structure shown in FIG. 5 and illustrates an example in which the conductive layer 117 and the conductive layer 111b are electrically connected to each other through the conductive layer 119. FIG. 18B is a cross-sectional view taken along dashed dotted line B3-B4 in FIG. 18A and illustrates the conductive layer 117, the conductive layer 119, and, for example, the transistor 52. In the examples shown in FIGS. 18A and 18B, the conductive layer 119 is provided in the same layer as the conductive layer 115. Therefore, the conductive layer 119 can be made of the same material as the conductive layer 115 and can be formed in the same process. For example, the conductive layer 115 and the conductive layer 119 can be formed by processing the same conductive film.

[0177] 18B , an opening 125b1 reaching the conductive layer 117 is provided in the insulating layer 105, and the conductive layer 117 and the conductive layer 119 are electrically connected inside the opening 125b1. Specifically, for example, the opening 125b1 has a region where the conductive layer 117 and the conductive layer 119 are in contact with each other. Furthermore, an opening 125b2 reaching the conductive layer 111b is provided in the insulating layer 103 and the insulating layer 105, and the conductive layer 111b and the conductive layer 119 are electrically connected inside the opening 125b2. Specifically, for example, the opening 125b2 has a region where the conductive layer 111b and the conductive layer 119 are in contact with each other.

[0178] As a result, the conductive layer 117 and the conductive layer 111b can be electrically connected to each other through the conductive layer 119. By configuring the display device of one embodiment of the present invention in this manner, the opening 125b (the opening 125b1 and the opening 125b2) can be formed in parallel with the opening 125a. Here, the conductive layer 119 is also referred to as a connection electrode for electrically connecting the conductive layer 117 and the conductive layer 111b, for example.

[0179] 19 is a modified example of the configuration shown in Fig. 18A, and shows an example in which at least a part of a transistor 51 is provided in a region where a wiring 41 and a wiring 43 overlap. Also, this shows an example in which at least a part of a transistor 52 is provided in a region where a wiring 45 extends in the Y direction.

[0180] 20A1 and 20A2 are modified examples of the configuration shown in Fig. 18A , showing an example in which the conductive layer 117 and the conductive layer 111b are electrically connected via a pixel electrode 311. In Fig. 20A1 , the pixel electrode 311 is shown by a two-dot chain line without a hatching pattern, while in Fig. 20A2 , the pixel electrode 311 is shown by a solid line with a hatching pattern. Fig. 20B is a cross-sectional view taken along the dashed dot line B3-B4 shown in Fig. 20A1 and Fig. 20A2 .

[0181] 20B , an opening 129 reaching the conductive layer 117 is provided in the insulating layer 105, the insulating layer 218, and the insulating layer 235, and the conductive layer 117 and the pixel electrode 311 are electrically connected inside the opening 129. Specifically, for example, the opening 129 has a region where the conductive layer 117 and the pixel electrode 311 are in contact with each other. Furthermore, an opening 125b reaching the conductive layer 111b is provided in the insulating layer 103, the insulating layer 105, the insulating layer 218, and the insulating layer 235, and the conductive layer 111b and the pixel electrode 311 are electrically connected inside the opening 125b. Specifically, for example, the opening 125b has a region where the conductive layer 111b and the pixel electrode 311 are in contact with each other.

[0182] As a result, the conductive layer 117 and the conductive layer 111b can be electrically connected via the pixel electrode 311. Here, the opening 125b and the opening 129 can be formed in parallel.

[0183] 21A and 21B are modified examples of the configurations shown in Fig. 20A1 and 20A2, respectively, and show an example in which at least a part of a transistor 51 is provided in a region where a wiring 41 and a wiring 43 overlap. Also, an example in which at least a part of a transistor 52 is provided in a region where a wiring 45 extends in the Y direction is shown.

[0184] Fig. 22A is a plan view showing a configuration example of pixel circuit 40C shown in Fig. 2B. Fig. 22B is a cross-sectional view taken along dashed dotted line B5-B6 shown in Fig. 22A, showing a configuration example of transistor 53, capacitor 57, etc. The configurations shown in Figs. 22A and 22B can be considered modified versions of the configurations shown in Figs. 5 and 6, respectively. Below, descriptions of parts that overlap with Figs. 5 and 6 will be omitted as appropriate.

[0185] 22A and 22B , the structures of the transistor 51, the transistor 52, and the transistor 53 are similar to those shown in FIGS. 3A1 and 3B . Here, the conductive layer 111, the conductive layer 112, the semiconductor layer 113, and the conductive layer 115 included in the transistor 53 are defined as a conductive layer 111c, a conductive layer 112c, a semiconductor layer 113c, and a conductive layer 115c, respectively. Furthermore, the openings 121 and 123 provided in the transistor 53 are defined as an opening 121c and an opening 123c, respectively.

[0186] Fig. 23A shows a plan view in which the conductive layers 115a, 115b, and 115c shown in Fig. 22A are shown without hatching patterns and with two-dot chain lines. Fig. 23B shows a plan view in which the semiconductor layers 113a, 113b, and 113c are shown without hatching patterns and with two-dot chain lines, which is an addition to the plan view shown in Fig. 23A. Figs. 23A and 23B show an example configuration of one pixel circuit 40C.

[0187] The conductive layer 111c functions as one of the source electrode and the drain electrode of the transistor 53, and the conductive layer 112c functions as the other of the source electrode and the drain electrode of the transistor 53. Here, Figures 22A, 23A, and 23B show an example in which the same conductive layer 112c is used for the other of the source electrode and the drain electrode of the transistor 53 and the other electrode of the capacitor 57.

[0188] 22A and 22B, the conductive layer 115a functions as the wiring 41a, and the conductive layer 115c functions as the wiring 41b. In the example shown in FIGS. 22A and 22B, the conductive layer 111c functions as the wiring 48. The conductive layer 111c is electrically connected to the reference potential generating circuit 17 shown in FIG. 2A. The conductive layer 111c can have a region overlapping with the conductive layer 112b.

[0189] The conductive layers 115a and 115c have regions extending in the X direction. The conductive layers 111a, 112b, and 111c have regions extending in the Y direction. The conductive layers 115a and 115c have regions overlapping with the conductive layers 111a, 112b, and 111c. Specifically, a portion of the region of the conductive layer 115a extending in the X direction overlaps with a portion of the region of the conductive layers 111a, 112b, and 111c extending in the Y direction. Furthermore, a portion of the region of the conductive layer 115c extending in the X direction overlaps with a portion of the region of the conductive layers 111a, 112b, and 111c extending in the Y direction.

[0190] Here, it may be said that the region of the conductive layer 115a extending in the X direction functions as the wiring 41a, or that the entire conductive layer 115a functions as the wiring 41a. It may also be said that the region of the conductive layer 115c extending in the X direction functions as the wiring 41b, or that the entire conductive layer 115c functions as the wiring 41b. It may also be said that the region of the conductive layer 111c extending in the Y direction functions as the wiring 48, or that the entire conductive layer 111c functions as the wiring 48. Unless otherwise specified, the above also applies to other conductive layers having a region that functions as the wiring 41a, the wiring 41b, or the wiring 48.

[0191] Fig. 24A is a configuration example in which a pixel electrode 311 of a light-emitting element 60 is added to the plan view shown in Fig. 22A. Fig. 24B is a cross-sectional view taken along dashed line B5-B6 shown in Fig. 24A. The following mainly describes configurations that are different from Figs. 12 and 13, and descriptions of similar configurations will be omitted as appropriate. Note that in Fig. 24A, some of the reference numerals shown in Fig. 22A have been omitted. Some of the reference numerals may also be omitted in subsequent drawings.

[0192] The insulating layer 105, the insulating layer 218, and the insulating layer 235 have an opening 129 that reaches the conductive layer 112c. A pixel electrode 311 is provided to cover the opening 129. The pixel electrode 311 has a shape that follows the upper and side surfaces of the insulating layer 235, the side surfaces of the insulating layer 218, the side surfaces of the insulating layer 105, and the upper surface of the conductive layer 112c. The pixel electrode 311 has regions that contact, for example, the upper and side surfaces of the insulating layer 235, the side surfaces of the insulating layer 218, the side surfaces of the insulating layer 105, and the upper surface of the conductive layer 112c. The pixel electrode 311 can be electrically connected to the conductive layer 112c inside the opening 129.

[0193] The pixel electrode 311 may have a region that overlaps with at least one of the region of the conductive layer 115a extending in the X direction, the region of the conductive layer 115c extending in the X direction, the region of the conductive layer 111a extending in the Y direction, the region of the conductive layer 112b extending in the Y direction, and the region of the conductive layer 111c extending in the Y direction, thereby increasing the aperture ratio of the pixel. On the other hand, since the pixel electrode 311 does not overlap with the region of the conductive layer 115a extending in the X direction, the region of the conductive layer 115c extending in the X direction, the region of the conductive layer 111a extending in the Y direction, the region of the conductive layer 112b extending in the Y direction, and the region of the conductive layer 111c extending in the Y direction, it is possible to suppress propagation of noise caused by signals supplied to the conductive layer 115a, noise caused by signals supplied to the conductive layer 115c, noise caused by signals supplied to the conductive layer 111a, noise caused by the potential of the conductive layer 112b, and noise caused by the potential of the conductive layer 111c to the pixel electrode 311.

[0194] FIG. 25A is a modified example of the configuration shown in FIG. 22A , showing an example in which at least a portion of a transistor 51 is provided in a region where the wiring 41a and the wiring 43 overlap. Also, FIG. 25A shows an example in which at least a portion of a transistor 52 is provided in a region where the wiring 45 extends in the Y direction. Also, FIG. 25A shows an example in which at least a portion of a transistor 53 is provided in a region where the wiring 41b extends in the X direction. Specifically, FIG. 25A shows an example in which a semiconductor layer 113a, an opening 121a, and an opening 123a are provided in a region where the wiring 41a and the wiring 43 overlap. Also, FIG. 25A shows an example in which a semiconductor layer 113b, an opening 121b, and an opening 123b are provided in a region where the wiring 45 extends in the Y direction. Also, FIG. 25A shows an example in which a semiconductor layer 113c, an opening 121c, and an opening 123c are provided in a region where the wiring 41b extends in the X direction. 25A also shows an example in which the semiconductor layer 113a, the opening 121a, and the opening 123a overlap with the region of the conductive layer 111a extending in the Y direction and the region of the conductive layer 115a extending in the X direction. Also, FIG. 25A also shows an example in which the semiconductor layer 113b, the opening 121b, and the opening 123b overlap with the region of the conductive layer 112b extending in the Y direction. Also, FIG. 25A also shows an example in which the semiconductor layer 113c, the opening 121c, and the opening 123c overlap with the region of the conductive layer 115c extending in the X direction. Also, FIG. 25A also shows an example in which the opening 125b overlaps with the conductive layer 115b.

[0195] Fig. 25B is a plan view in which the conductive layers 115a, 115b, and 115c shown in Fig. 25A are shown with dashed double-dashed lines without hatching patterns. Fig. 25C is a plan view further showing the semiconductor layers 113a, 113b, and 113c from the plan view shown in Fig. 25B without hatching patterns and shown with dashed double-dashed lines. Fig. 25A shows an example configuration of a pixel circuit 40C with two rows and two columns. On the other hand, Figs. 25B and 25C show an example configuration of one pixel circuit 40C.

[0196] 25A, the pixel circuit 40C can be miniaturized while ensuring the area of ​​the capacitor 57, compared to when the pixel circuit 40C has the configuration shown in Fig. 22A. On the other hand, when the pixel circuit 40C has the configuration shown in Fig. 22A, the degree of freedom in the layout of the pixel circuit 40C can be increased, compared to when the pixel circuit 40C has the configuration shown in Fig. 25A.

[0197] 26A is a modified example of the configuration shown in FIG. 22A , in which a conductive layer 117, which can be provided in the same layer as the conductive layer 112, functions as the other electrode of the capacitor 57, and the conductive layer 117, the conductive layer 111b, and the conductive layer 112c are electrically connected via a conductive layer 119. FIG. 26B is a cross-sectional view taken along the dashed dotted line B5-B6 shown in FIG. 26A . In the examples shown in FIGS. 26A and 26B , the conductive layer 119 is provided in the same layer as the conductive layer 115. Therefore, the conductive layer 119 can be made of the same material as the conductive layer 115 and can be formed in the same process. For example, the conductive layer 115 and the conductive layer 119 can be formed by processing the same conductive film.

[0198] In the example shown in FIG. 26B , an opening 125b1 reaching the conductive layer 117 is provided in the insulating layer 105, and the conductive layer 117 and the conductive layer 119 are electrically connected inside the opening 125b1. Specifically, for example, the conductive layer 117 and the conductive layer 119 have a contact area inside the opening 125b1. Furthermore, an opening 125b2 reaching the conductive layer 111b is provided in the insulating layer 103 and the insulating layer 105, and the conductive layer 111b and the conductive layer 119 are electrically connected inside the opening 125b2. Specifically, for example, the conductive layer 111b and the conductive layer 119 have a contact area inside the opening 125b2. Furthermore, an opening 125c reaching the conductive layer 112c is provided in the insulating layer 105, and the conductive layer 112c and the conductive layer 119 are electrically connected inside the opening 125c. Specifically, for example, inside the opening 125c, there is a region where the conductive layer 112c and the conductive layer 119 are in contact with each other.

[0199] As a result, the conductive layers 117, 111b, and 112c can be electrically connected to each other through the conductive layer 119. By configuring the display device of one embodiment of the present invention in this manner, the opening 125b (the openings 125b1 and 125b2) and the opening 125c can be formed in parallel with the opening 125a. Here, in the examples shown in Figures 26A and 26B, for example, the conductive layer 119 is also referred to as a connection electrode for electrically connecting the conductive layers 117, 111b, and 112c to each other.

[0200] 27 is a modified example of the configuration shown in Fig. 26A, and shows an example in which at least a part of a transistor 51 is provided in a region where a wiring 41a and a wiring 43 overlap. Also, an example in which at least a part of a transistor 52 is provided in a region where a wiring 45 extends in the Y direction. Furthermore, an example in which at least a part of a transistor 53 is provided in a region where a wiring 41b extends in the X direction is shown.

[0201] 28A1 and 28A2 are modifications of the configuration shown in Fig. 26A , and show an example in which conductive layer 117, conductive layer 111b, and conductive layer 112c are electrically connected via pixel electrode 311. In Fig. 28A1, pixel electrode 311 is shown by a two-dot chain line without a hatching pattern, while in Fig. 28A2, pixel electrode 311 is shown by a solid line with a hatching pattern. Fig. 28B is a cross-sectional view taken along dashed line B5-B6 shown in Figs. 28A1 and 28A2.

[0202] 28B , an opening 125b1 reaching the conductive layer 117 is provided in the insulating layer 105, the insulating layer 218, and the insulating layer 235, and the conductive layer 117 and the pixel electrode 311 are electrically connected inside the opening 125b1. Specifically, for example, the opening 125b1 has a region where the conductive layer 117 and the pixel electrode 311 are in contact with each other. Furthermore, an opening 125b2 reaching the conductive layer 111b is provided in the insulating layer 103, the insulating layer 105, the insulating layer 218, and the insulating layer 235, and the conductive layer 111b and the pixel electrode 311 are electrically connected inside the opening 125b2. Specifically, for example, the opening 125b2 has a region where the conductive layer 111b and the pixel electrode 311 are in contact with each other. Furthermore, an opening 125c reaching the conductive layer 112c is provided in the insulating layer 105, the insulating layer 218, and the insulating layer 235, and the conductive layer 112c and the pixel electrode 311 are electrically connected inside the opening 125c. Specifically, for example, the opening 125c has a region where the conductive layer 112c and the pixel electrode 311 are in contact with each other.

[0203] As a result, the conductive layer 117, the conductive layer 111b, and the conductive layer 112c can be electrically connected via the pixel electrode 311. Here, the openings 125b1, 125b2, and 125c can be formed in parallel.

[0204] 29A and 29B are modifications of the configurations shown in Fig. 28A1 and Fig. 28A2, respectively, and show an example in which at least a part of a transistor 51 is provided in a region where a wiring 41a and a wiring 43 overlap. Also, an example in which at least a part of a transistor 52 is provided in a region where a wiring 45 extends in the Y direction is shown. Furthermore, an example in which at least a part of a transistor 53 is provided in a region where a wiring 41b extends in the X direction is shown.

[0205] 30A is a modification of the configuration shown in FIG. 22A , showing an example in which the wiring 48 is a conductive layer 133 provided in the same layer as the conductive layer 112. FIG. 30B is a cross-sectional view taken along dashed dotted line B5-B6 shown in FIG. 30A . In the examples shown in FIGS. 30A and 30B , the conductive layer 133 can be made of the same material as the conductive layer 112 and can be formed in the same process. For example, the conductive layer 112 and the conductive layer 133 can be formed by processing the same conductive film.

[0206] 30A and 30B , the insulating layer 103 has an opening 125c that reaches the conductive layer 111c, and the conductive layer 111c and the conductive layer 117 are electrically connected inside the opening 125c. Specifically, for example, the opening 125c has a region where the conductive layer 111c and the conductive layer 117 are in contact with each other.

[0207] 30A and 30B includes a conductive layer 131 having a region overlapping with the conductive layer 112c, a region overlapping with the conductive layer 112b, and a region overlapping with the conductive layer 133. In the example shown in FIGS. 30A and 30B , the conductive layer 131 is provided in the same layer as the conductive layer 115. Therefore, the conductive layer 131 can be made of the same material as the conductive layer 115 and can be formed in the same process. For example, the conductive layer 115 and the conductive layer 131 can be formed by processing the same conductive film.

[0208] The insulating layer 105 has an opening 125d1 that reaches the conductive layer 112c and an opening 125d2 that reaches the conductive layer 133. Inside the opening 125d1, the conductive layer 112c and the conductive layer 131 are electrically connected. Also, inside the opening 125d2, the conductive layer 133 and the conductive layer 131 are electrically connected. Specifically, for example, inside the opening 125d1, there is a region where the conductive layer 112c and the conductive layer 131 contact each other. Also, for example, inside the opening 125d2, there is a region where the conductive layer 133 and the conductive layer 131 contact each other. As described above, the conductive layer 112c and the conductive layer 133 can be electrically connected via the conductive layer 131. By electrically connecting the conductive layer 112c and the conductive layer 133 via the conductive layer 131, it is possible to prevent the conductive layer 112c from contacting the conductive layer 112b and causing a short circuit. Here, the conductive layer 131 is also referred to as a connection electrode for electrically connecting the conductive layer 112c and the conductive layer 133, for example.

[0209] In Figure 30A, the shape of opening 125d (opening 125d1 and opening 125d2) in a planar view is circular, but one embodiment of the present invention is not limited to this, and opening 125d can have a shape similar to the shape that at least one of opening 125a, opening 125b, and opening 125c can have.

[0210] The conductive layer 133 functioning as the wiring 48 has a region extending in the Y direction, and a part of this region overlaps with a region of the conductive layer 115a extending in the X direction and a region of the conductive layer 115c extending in the X direction. Here, it may be said that the region of the conductive layer 133 extending in the Y direction functions as the wiring 48, or that the entire conductive layer 133 functions as the wiring 48.

[0211] In the example shown in FIG. 30A , the conductive layer 133 functioning as the wiring 48 is provided in a different layer from the conductive layer 111a functioning as the wiring 43. Therefore, the distance in the X direction in a plan view between the region of the conductive layer 111a extending in the Y direction and the region of the conductive layer 133 extending in the Y direction can be shorter than the distance in the X direction in a plan view between the region of the conductive layer 112b extending in the Y direction and the region of the conductive layer 133 extending in the Y direction. That is, in a plan view, the space between the wiring 48 and the wiring 43 can be smaller than the space between the wiring 48 and the wiring 45. On the other hand, in the example shown in FIG. 22A , the conductive layer 111c functioning as the wiring 48 is provided in a different layer from the conductive layer 112b functioning as the wiring 45. Therefore, in a plan view, the space between the wiring 48 and the wiring 45 can be smaller than the space between the wiring 48 and the wiring 43.

[0212] 31A is a modified example of the configuration shown in FIG. 30A , and shows an example in which at least a part of transistor 51 is provided in a region where wiring 41 a and wiring 43 overlap. Also, an example in which at least a part of transistor 52 is provided in a region where wiring 45 extends in the Y direction. Furthermore, an example in which at least a part of transistor 53 is provided in a region where wiring 41 b extends in the X direction. FIG. 31B is a cross-sectional view taken along dashed line B7-B8 shown in FIG. 31A .

[0213] 31A and 31B, pixel circuit 40C does not have conductive layer 131, which is a connection electrode, and conductive layer 111c and conductive layer 133 are electrically connected inside opening 125d. Opening 125d is provided in insulating layer 103 so as to reach conductive layer 111c. For example, opening 125d has a region where conductive layer 111c and conductive layer 133 are in contact with each other.

[0214] 32A is a modification of the structure shown in FIG. 30A , and illustrates an example in which the conductive layer 117, the conductive layer 111b, and the conductive layer 111c are electrically connected via the conductive layer 119. FIG. 32B is a cross-sectional view taken along the dashed dotted line B5-B6 in FIG. 32A . In the examples shown in FIGS. 32A and 32B , the conductive layer 119 is provided in the same layer as the conductive layer 115. Therefore, the conductive layer 119 can be made of the same material as the conductive layer 115 and can be formed in the same process. For example, the conductive layer 115 and the conductive layer 119 can be formed by processing the same conductive film.

[0215] In the example shown in FIG. 32B , an opening 125b1 reaching the conductive layer 117 is provided in the insulating layer 105, and the conductive layer 117 and the conductive layer 119 are electrically connected inside the opening 125b1. Specifically, for example, the conductive layer 117 and the conductive layer 119 have a region in contact inside the opening 125b1. Furthermore, an opening 125b2 reaching the conductive layer 111b is provided in the insulating layer 103 and the insulating layer 105, and the conductive layer 111b and the conductive layer 119 are electrically connected inside the opening 125b2. Specifically, for example, the conductive layer 111b and the conductive layer 119 have a region in contact inside the opening 125b2. Furthermore, an opening 125c reaching the conductive layer 111c is provided in the insulating layer 103 and the insulating layer 105, and the conductive layer 111c and the conductive layer 119 are electrically connected inside the opening 125c. Specifically, for example, inside the opening 125c, there is a region where the conductive layer 111c and the conductive layer 119 are in contact with each other.

[0216] As a result, the conductive layer 117, the conductive layer 111b, and the conductive layer 111c can be electrically connected to each other through the conductive layer 119. By configuring the display device of one embodiment of the present invention in this manner, the opening 125b (opening 125b1 and opening 125b2) and the opening 125c can be formed in parallel with the opening 125a and the opening 125d (opening 125d1 and opening 125d2). Here, in the example illustrated in FIGS. 32A and 32B , for example, the conductive layer 119 is also referred to as a connection electrode for electrically connecting the conductive layer 117, the conductive layer 111b, and the conductive layer 111c to each other.

[0217] 33 is a modification of the configuration shown in FIG. 32A , and illustrates an example in which at least a portion of a transistor 51 is provided in a region where a wiring 41 a overlaps with a wiring 43. Also, an example in which at least a portion of a transistor 52 is provided in a region of a wiring 45 extending in the Y direction. Furthermore, an example in which at least a portion of a transistor 53 is provided in a region of a wiring 41 b extending in the X direction. In the example shown in FIG. 33 , similar to the examples shown in FIGS. 31A and 31B , a pixel circuit 40C does not include a conductive layer 131, and the conductive layer 111 c and the conductive layer 133 are electrically connected inside an opening 125 d.

[0218] 34A is a modified example of the configuration shown in FIG. 30A , showing an example in which the conductive layer 131 is provided in the same layer as the conductive layer 111. FIG. 34B is a cross-sectional view taken along dashed dotted line B5-B6 shown in FIG. 34A . In the examples shown in FIGS. 34A and 34B , the conductive layer 131 can be made of the same material as the conductive layer 111 and can be formed in the same process. For example, the conductive layer 111 and the conductive layer 131 can be formed by processing the same conductive film.

[0219] 30A and 30B , the conductive layer 112c and the conductive layer 131 are electrically connected inside the opening 125d1, and the conductive layer 133 and the conductive layer 131 are electrically connected inside the opening 125d2. Therefore, the conductive layer 112c and the conductive layer 133 can be electrically connected via the conductive layer 131.

[0220] 35A is a modification of the configuration shown in FIG. 30A , showing an example in which the conductive layer 131 is provided in the same layer as the pixel electrode 311. FIG. 35B is a cross-sectional view taken along dashed dotted line B5-B6 shown in FIG. 35A . In the examples shown in FIGS. 35A and 35B , the conductive layer 131 can be made of the same material as the pixel electrode 311 and can be formed in the same process. For example, the pixel electrode 311 and the conductive layer 131 can be formed by processing the same conductive film.

[0221] 30A and 30B , the conductive layer 112c and the conductive layer 131 are electrically connected inside the opening 125d1, and the conductive layer 133 and the conductive layer 131 are electrically connected inside the opening 125d2. Therefore, the conductive layer 112c and the conductive layer 133 can be electrically connected via the conductive layer 131.

[0222] 36 and 37 are modifications of the configurations shown in FIGS. 22A and 25 , respectively, and show an example in which the conductive layer 111c functioning as the wiring 48 is shared by two adjacent pixel circuits 40C. FIGS. 36 and 37 show an example in which the conductive layer 111c is shared by the jth column pixel circuit 40C and the j+1th column pixel circuit 40C. Also, FIGS. 36 and 37 show an example in which a region of the conductive layer 111c extending in the Y direction is provided between a region of the conductive layer 112b electrically connected to the transistor 52 provided in the jth column pixel circuit 40C, which extends in the Y direction, and a region of the conductive layer 112b electrically connected to the transistor 52 provided in the j+1th column pixel circuit 40C, which extends in the Y direction.

[0223] 36 and 37, the number of conductive layers 111c provided in the display device of one embodiment of the present invention can be reduced compared to the examples shown in Fig. 22A and 25, thereby realizing a high-definition display device. On the other hand, the load of the conductive layers 111c can be reduced compared to the examples shown in Fig. 36 and 37. Therefore, a display device that can be driven at high speed can be realized.

[0224] Fig. 38A is a modified example of the configuration shown in Fig. 22A, and shows an example in which a conductive layer 112b functioning as a wiring 45 is shared by two adjacent columns of pixel circuits 40C. Fig. 38B is a cross-sectional view taken along dashed dotted line B5-B6 shown in Fig. 38A.

[0225] 38A shows an example in which the conductive layer 112b is shared by the jth column pixel circuit 40C and the j+1th column pixel circuit 40C. Also, Fig. 38A shows an example in which a region of the conductive layer 112b extending in the Y direction is provided between a region of the conductive layer 111c electrically connected to the transistor 53 provided in the jth column pixel circuit 40C, which extends in the Y direction, and a region of the conductive layer 111c electrically connected to the transistor 53 provided in the j+1th column pixel circuit 40C, which extends in the Y direction.

[0226] 38A and 38B, the number of conductive layers 112b provided in the display device of one embodiment of the present invention can be reduced compared to the example shown in Fig. 22A and 22B, thereby realizing a high-resolution display device. On the other hand, the load of the conductive layers 112b can be reduced compared to the example shown in Fig. 38A and 38B. Therefore, a display device that can be driven at high speed can be realized.

[0227] As described above, the conductive layer 111c can have an overlapping region with the conductive layer 112b. Fig. 38A shows an example in which the region of the conductive layer 112b extending in the X direction has an overlapping region with the region of the conductive layer 111c extending in the Y direction.

[0228] Fig. 39A is a plan view showing a configuration example of pixel circuit 40C shown in Fig. 2B. Fig. 39B is a cross-sectional view taken along dashed dotted line B5-B6 in Fig. 39A, showing a configuration example of transistor 53, capacitor 57, etc. The configurations shown in Figs. 39A and 39B can also be considered modified versions of the configurations shown in Figs. 9A and 10, respectively. Below, descriptions of parts that overlap with Figs. 9A and 10 will be omitted as appropriate.

[0229] In the example shown in FIGS. 39A and 39B, the configurations of the transistor 51, the transistor 52, and the transistor 53 are the same as those shown in FIGS. 3A1 and 3B.

[0230] Fig. 40A shows a plan view in which the conductive layers 115a, 115b, and 115c shown in Fig. 39A are shown without hatching patterns and with two-dot chain lines. Fig. 40B shows a plan view in which the semiconductor layers 113a, 113b, and 113c are shown without hatching patterns and with two-dot chain lines, which is an addition to the plan view shown in Fig. 40A. Figs. 40A and 40B show an example configuration of one pixel circuit 40C.

[0231] The conductive layer 111c functions as one of the source electrode and the drain electrode of the transistor 53. Here, Figures 39A, 40A, and 40B show an example in which the same conductive layer 112b is used for the other of the source electrode and the drain electrode of the transistor 52, the other of the source electrode and the drain electrode of the transistor 53, and the other electrode of the capacitor 57.

[0232] 39A and 39B, the conductive layer 115a functions as the wiring 41a, and the conductive layer 115c functions as the wiring 41b. The conductive layer 138 is shown as the wiring 48, and is electrically connected to the reference potential generating circuit 17 shown in FIG. 2A.

[0233] The insulating layer 103 and the insulating layer 105 have an opening 125d1 that reaches the conductive layer 111c and an opening 125d2 that reaches the conductive layer 138. The opening 125d1 electrically connects the conductive layer 111c to the conductive layer 119. The opening 125d2 electrically connects the conductive layer 138 to the conductive layer 119. Specifically, for example, the opening 125d1 has a region where the conductive layer 111c and the conductive layer 119 contact each other. The opening 125d2 has a region where the conductive layer 138 and the conductive layer 119 contact each other. As a result, the conductive layer 111c and the conductive layer 138 can be electrically connected via the conductive layer 119. By electrically connecting the conductive layer 111c and the conductive layer 138 via the conductive layer 119, it is possible to prevent the conductive layer 111c from contacting the conductive layer 111b and causing a short circuit.

[0234] The conductive layer 138 can be provided in the same layer as the conductive layer 111. Furthermore, the conductive layer 119 can be provided in the same layer as the conductive layer 115. Therefore, the conductive layer 138 can have the same material as the conductive layer 111 and can be formed in the same process. Furthermore, the conductive layer 119 can have the same material as the conductive layer 115 and can be formed in the same process. For example, the conductive layer 111 and the conductive layer 138 can be formed by processing the same conductive film. Furthermore, the conductive layer 115 and the conductive layer 119 can be formed by processing the same conductive film.

[0235] In Figures 39A, 40A, and 40B, the shapes of openings 125a, 125d1, and 125d2 in a planar view are circular, but one embodiment of the present invention is not limited to this and can be the same shape as opening 121 or the same shape as opening 123.

[0236] The conductive layer 115a and the conductive layer 115c have regions extending in the X direction. The conductive layer 111a, the conductive layer 111b, the conductive layer 136, and the conductive layer 138 have regions extending in the Y direction. The conductive layer 115a and the conductive layer 115c have regions overlapping with the conductive layer 111a, the conductive layer 111b, the conductive layer 136, and the conductive layer 138. Specifically, a portion of the region of the conductive layer 115a extending in the X direction overlaps with a portion of the region of the conductive layer 111a, the conductive layer 111b, the conductive layer 136, and the conductive layer 138 extending in the Y direction. Furthermore, a portion of the region of the conductive layer 115c extending in the X direction overlaps with a portion of the region of the conductive layer 111a, the conductive layer 111b, the conductive layer 136, and the conductive layer 138 extending in the Y direction.

[0237] Here, it may be said that the region of the conductive layer 138 extending in the Y direction functions as the wiring 48, or that the entire conductive layer 138 functions as the wiring 48. The same applies to conductive layers other than the conductive layer 138 that have a region that functions as the wiring 48.

[0238] Fig. 41A is a configuration example in which a pixel electrode 311 of a light-emitting element 60 is added to the plan view shown in Fig. 39A. Fig. 41B is a cross-sectional view taken along dashed line B5-B6 shown in Fig. 41A. The following mainly describes configurations that are different from Figs. 14 and 15, and descriptions of similar configurations will be omitted as appropriate. Note that in Fig. 41A, some of the reference numerals shown in Fig. 39A have been omitted. Some of the reference numerals may also be omitted in subsequent drawings.

[0239] The insulating layer 105, the insulating layer 218, and the insulating layer 235 have an opening 129 that reaches the conductive layer 112b. A pixel electrode 311 is provided to cover the opening 129. The pixel electrode 311 has a shape that follows the upper and side surfaces of the insulating layer 235, the side surfaces of the insulating layer 218, the side surfaces of the insulating layer 105, and the upper surface of the conductive layer 112b. The pixel electrode 311 has regions that contact, for example, the upper and side surfaces of the insulating layer 235, the side surfaces of the insulating layer 218, the side surfaces of the insulating layer 105, and the upper surface of the conductive layer 112b. The pixel electrode 311 can be electrically connected to the conductive layer 112b inside the opening 129.

[0240] The pixel electrode 311 may have a region that overlaps with at least one of the region of the conductive layer 115a extending in the X direction, the region of the conductive layer 115c extending in the X direction, the region of the conductive layer 111a extending in the Y direction, the region of the conductive layer 136 extending in the Y direction, and the region of the conductive layer 138 extending in the Y direction, thereby increasing the aperture ratio of the pixel. On the other hand, since the pixel electrode 311 does not overlap with the region of the conductive layer 115a extending in the X direction, the region of the conductive layer 115c extending in the X direction, the region of the conductive layer 111a extending in the Y direction, the region of the conductive layer 136 extending in the Y direction, and the region of the conductive layer 138 extending in the Y direction, it is possible to suppress the propagation of noise caused by signals supplied to the conductive layer 115a, noise caused by signals supplied to the conductive layer 115c, noise caused by signals supplied to the conductive layer 111a, noise caused by the potential of the conductive layer 136, and noise caused by the potential of the conductive layer 138 to the pixel electrode 311.

[0241] Fig. 42A is a modified example of the configuration shown in Fig. 5, and shows an example in which the conductive layer 112a is used as the wiring 43. Fig. 42B shows a cross-sectional view taken along the dashed dotted line B9-B10 shown in Fig. 42A. Fig. 42B shows an example configuration of a transistor 51 and a capacitor 57.

[0242] Figure 43 is a modified example of the configuration shown in Figure 42A, and shows an example in which at least a part of transistor 51 is provided in the area where wiring 41 and wiring 43 overlap, and at least a part of transistor 52 is provided in the area where wiring 45 extends in the Y direction.

[0243] 44, 45, and 46 are modifications of the configurations shown in FIGS. 18A, 19, and 22A, respectively, and show examples in which the conductive layer 112a is used as the wiring 43.

[0244] In the example shown in FIG. 46 , the wiring 48 is provided in a layer different from not only the wiring 45 but also the wiring 43. Meanwhile, in the example shown in FIG. 22A , the wiring 48 is provided in a layer different from the wiring 45 but in the same layer as the wiring 43. Therefore, in the example shown in FIG. 46 , the space between the wiring 48 and the wiring 43 can be made smaller than in the example shown in FIG. 22A . Therefore, pixels can be miniaturized, and the display device of one embodiment of the present invention can be a high-resolution display device. Meanwhile, in the example shown in FIG. 22A , in a region where the wiring 41 a and the wiring 43 overlap, not only the insulating layer 105 but also the insulating layer 103 is provided between the wiring 41 a and the wiring 43. Furthermore, in a region where the wiring 41 b and the wiring 43 overlap, not only the insulating layer 105 but also the insulating layer 103 is provided between the wiring 41 b and the wiring 43. 22A can reduce the parasitic capacitance between the wiring 41a and the wiring 43 and the parasitic capacitance between the wiring 41b and the wiring 43 compared to the example shown in FIG. 46. This reduces the time from when the scan line driver circuit 11 outputs a signal to the wiring 41a or 41b until the signal is supplied to the pixel circuit 40C. Therefore, the display device of one embodiment of the present invention can be driven at high speed.

[0245] 47 is a modification of the configuration shown in Fig. 46, and shows an example in which at least a part of a transistor 51 is provided in a region where a wiring 41a and a wiring 43 overlap. Also, an example in which at least a part of a transistor 52 is provided in a region where a wiring 45 extends in the Y direction. Furthermore, an example in which at least a part of a transistor 53 is provided in a region where a wiring 41b extends in the X direction is shown.

[0246] 48, 49, 50, and 51 are modifications of the configurations shown in Figures 30A, 31A, 32A, and 33, respectively, and show examples in which conductive layer 112a is used as wiring 43. In the examples shown in Figures 48, 49, 50, and 51, wiring 43, wiring 45, and wiring 48, each having a region extending in the Y direction, are provided in the same layer.

[0247] Fig. 52A is a modified example of the configuration shown in Fig. 9A, and shows an example in which the conductive layer 112a is used as the wiring 43. Fig. 52B is a cross-sectional view taken along the dashed dotted line B9-B10 shown in Fig. 52A. Fig. 52B shows an example of the configuration of a transistor 51 and a capacitor 57.

[0248] FIG. 53 is a modification of the configuration shown in FIG. 52A, and illustrates an example in which at least a part of a transistor 51 is provided in a region where a wiring 41 and a wiring 43 overlap.

[0249] Fig. 54A is a modification of the configuration shown in Fig. 9A, and shows an example in which conductive layer 136a is provided so as to overlap conductive layer 111a, and conductive layer 136b is provided so as to overlap conductive layer 111b. Here, conductive layer 136b corresponds to conductive layer 136 shown in Fig. 9A. Fig. 54B is a cross-sectional view taken along dashed dotted line B9-B10 shown in Fig. 54A.

[0250] 54A, conductive layer 136a has a region extending in the Y direction, and this region overlaps with a region of conductive layer 111a extending in the Y direction. Conductive layer 136b has a region extending in the Y direction, and this region overlaps with a region of conductive layer 111b extending in the Y direction.

[0251] The conductive layer 136a and the conductive layer 136b are provided between the insulating layer 103 and the insulating layer 105. That is, the conductive layer 136a and the conductive layer 136b are provided in the same layer as the conductive layer 112. Therefore, the conductive layer 136a and the conductive layer 136b can have the same material as the conductive layer 112 and can be formed in the same process. For example, the conductive layer 112, the conductive layer 136a, and the conductive layer 136b can be formed by processing the same conductive film.

[0252] The insulating layer 103 has an opening 126a that reaches the conductive layer 111a and an opening 126b that reaches the conductive layer 111b. The conductive layer 111a and the conductive layer 136a are electrically connected inside the opening 126a, and the conductive layer 111b and the conductive layer 136b are electrically connected inside the opening 126b. Specifically, for example, the opening 126a has a region where the conductive layer 111a and the conductive layer 136a contact each other, and the opening 126b has a region where the conductive layer 111b and the conductive layer 136b contact each other. Here, the opening 126b shown in FIG. 54A corresponds to the opening 126 shown in FIG. 9A.

[0253] 54A , the openings 126a and 126b have circular shapes in a plan view; however, one embodiment of the present invention is not limited thereto and can have a shape similar to that of the opening 126 shown in FIG. 9A , for example. Note that the openings 126a and 126b may be collectively referred to as the opening 126. Furthermore, the conductive layers 136a and 136b may be collectively referred to as the conductive layer 136.

[0254] Since the conductive layer 136a is electrically connected to the conductive layer 111a functioning as the wiring 43, the conductive layer 136a also functions as the wiring 43. As described above, the wiring 43 is electrically connected to the signal line driver circuit 13 shown in FIG. 1A. As described above, the conductive layer 136a is electrically connected to the signal line driver circuit 13. Furthermore, since the conductive layer 136b is electrically connected to the conductive layer 111b functioning as the wiring 45, the conductive layer 136b also functions as the wiring 45. As described above, the wiring 45 is electrically connected to the power supply circuit 15. As described above, the conductive layer 136b is electrically connected to the power supply circuit 15.

[0255] 55 is a modification of the configuration shown in Fig. 54A and shows an example in which at least a part of the transistor 51 is provided in a region extending in the X direction of the wiring 41. Specifically, Fig. 55 shows an example in which a semiconductor layer 113a, an opening 121a, and an opening 123a are provided in a region extending in the X direction of the wiring 41. Fig. 55 also shows an example in which the semiconductor layer 113a, the opening 121a, and the opening 123a overlap with a region extending in the X direction of the conductive layer 115a.

[0256] By configuring pixel circuit 40A as shown in Fig. 55, it is possible to miniaturize the pixel while ensuring the area of ​​capacitor 57, compared to when pixel circuit 40A has the configuration shown in Fig. 54A. On the other hand, by configuring pixel circuit 40A as shown in Fig. 54A, it is possible to increase the degree of freedom in the layout of pixel circuit 40A, compared to when pixel circuit 40A has the configuration shown in Fig. 55.

[0257] 56A is a modification of the structure shown in FIG. 9A , illustrating an example in which the conductive layer 111b and the conductive layer 136 are electrically connected via the conductive layer 139. FIG. 56B is a cross-sectional view taken along dashed dotted line B3-B4 in FIG. 56A , illustrating the conductive layer 136, the conductive layer 139, and, for example, the transistor 52. In the examples shown in FIGS. 56A and 56B , the conductive layer 139 is provided in the same layer as the conductive layer 115. Therefore, the conductive layer 139 can be made of the same material as the conductive layer 115 and can be formed in the same process. For example, the conductive layer 115 and the conductive layer 139 can be formed by processing the same conductive film.

[0258] 56B , an opening 126_1 reaching the conductive layer 111b is provided in the insulating layer 103 and the insulating layer 105, and the conductive layer 111b and the conductive layer 139 are electrically connected inside the opening 126_1. Specifically, for example, the opening 126_1 has a region where the conductive layer 111b and the conductive layer 139 are in contact with each other. Furthermore, an opening 126_2 reaching the conductive layer 136 is provided in the insulating layer 105, and the conductive layer 136 and the conductive layer 139 are electrically connected inside the opening 126_2. Specifically, for example, the opening 126_2 has a region where the conductive layer 136 and the conductive layer 139 are in contact with each other.

[0259] As a result, the conductive layer 111b and the conductive layer 136 can be electrically connected to each other through the conductive layer 139. By configuring the display device of one embodiment of the present invention in this manner, the opening 126 (the opening 126_1 and the opening 126_2) can be formed in parallel with the opening 125a. Here, the conductive layer 139 is also referred to as a connection electrode for electrically connecting the conductive layer 111b and the conductive layer 136, for example.

[0260] FIG. 57 is a modification of the configuration shown in FIG. 56A, in which at least a part of the transistor 51 is provided in a region where the wiring 41 and the wiring 43 overlap.

[0261] 58 is a modification of the configuration shown in Fig. 56A and illustrates an example in which the conductive layer 112a is used as the wiring 43. Fig. 59 is a modification of the configuration shown in Fig. 58 and illustrates an example in which at least a part of the transistor 51 is provided in a region where the wiring 41 and the wiring 43 overlap. Fig. 60 is a modification of the configuration shown in Fig. 56A and illustrates an example in which the conductive layer 136a is provided to overlap with the conductive layer 111a and the conductive layer 136b is provided to overlap with the conductive layer 111b, as shown in Fig. 54A.

[0262] In the example shown in FIG. 60 , the conductive layer 111a and the conductive layer 136a are electrically connected through the conductive layer 139a. The conductive layer 111b and the conductive layer 136b are electrically connected through the conductive layer 139b. The conductive layer 139a and the conductive layer 139b are provided in the same layer as the conductive layer 115. Therefore, the conductive layer 139a and the conductive layer 139b can have the same material as the conductive layer 115 and can be formed in the same process. For example, the conductive layer 115, the conductive layer 139a, and the conductive layer 139b can be formed by processing the same conductive film. The conductive layer 139a and the conductive layer 139b may be collectively referred to as the conductive layer 139.

[0263] 60 , an opening 126a1 reaching the conductive layer 111a and an opening 126b1 reaching the conductive layer 111b are provided in the insulating layer 103 and the insulating layer 105. The conductive layer 111a and the conductive layer 139a are electrically connected inside the opening 126a1, and the conductive layer 111b and the conductive layer 139b are electrically connected inside the opening 126b1. Specifically, for example, the conductive layer 111a and the conductive layer 139a have a region in contact inside the opening 126a1, and the conductive layer 111b and the conductive layer 139b have a region in contact inside the opening 126b1. Furthermore, in the example shown in FIG. 60 , an opening 126a2 reaching the conductive layer 136a and an opening 126b2 reaching the conductive layer 136b are provided in the insulating layer 105. Conductive layer 136a and conductive layer 139a are electrically connected inside opening 126a2, and conductive layer 136b and conductive layer 139b are electrically connected inside opening 126b2. Specifically, for example, opening 126a2 has a region where conductive layer 136a and conductive layer 139a are in contact, and opening 126b2 has a region where conductive layer 136b and conductive layer 139b are in contact. Note that insulating layer 103 and insulating layer 105 are not shown in FIG.

[0264] As a result, the conductive layer 111a and the conductive layer 136a can be electrically connected through the conductive layer 139a, and the conductive layer 111b and the conductive layer 136b can be electrically connected through the conductive layer 139b. By configuring the display device of one embodiment of the present invention in this manner, the opening 126a (openings 126a1 and 126a2) and the opening 126b (openings 126b1 and 126b2) can be formed in parallel with the opening 125a. Here, the conductive layer 139a is also referred to as, for example, a connection electrode for electrically connecting the conductive layer 111a and the conductive layer 136a. The conductive layer 139b is also referred to as, for example, a connection electrode for electrically connecting the conductive layer 111b and the conductive layer 136b.

[0265] FIG. 61 shows a modification of the configuration shown in FIG. 60, in which at least a part of a transistor 51 is provided in a region of a conductive layer 115a functioning as a wiring 41 that extends in the X direction.

[0266] Fig. 62A is a modified example of the configuration shown in Fig. 42A , showing an example in which a pixel is provided with a conductive layer 135. Fig. 62B is a cross-sectional view taken along dashed dotted line C1-C2 shown in Fig. 62A , showing an example of the configuration of, for example, a transistor 52 in addition to the conductive layer 135.

[0267] The conductive layer 135 has a region extending in the X direction, and can be provided so as to have, for example, a region located between the region of the conductive layer 115a extending in the X direction and the conductive layer 115b. The conductive layer 135 also has regions overlapping with the conductive layer 112a and the conductive layer 112b. The conductive layer 135 can be provided in the same layer as the conductive layer 111. Therefore, the conductive layer 135 can have the same material as the conductive layer 111 and can be formed in the same process. For example, the conductive layer 111 and the conductive layer 135 can be formed by processing the same conductive film.

[0268] 62B , an opening 127 reaching the conductive layer 135 is provided in the insulating layer 103, and the conductive layer 135 and the conductive layer 112b are electrically connected inside the opening 127. Specifically, for example, the inside of the opening 127 has a region where the conductive layer 135 and the conductive layer 112b are in contact with each other.

[0269] In Figure 62A, the shape of opening 127 in a planar view is circular, but one embodiment of the present invention is not limited to this, and the opening 127 can have a shape similar to the shape that at least one of openings 121, opening 123, and opening 125 can have.

[0270] 62A , not only the conductive layer 112b having a region extending in the Y direction but also the conductive layer 135 having a region extending in the X direction function as the wiring 45 that functions as a power supply line. Therefore, the power supply circuit 15 shown in FIG. 1A can supply a power supply potential to the transistor 52 not only through the conductive layer 112b but also through the conductive layer 135. This can prevent the power supply potential generated by the power supply circuit 15 from dropping before being supplied to the pixel circuit 40A. In particular, it can preferably prevent the power supply potential generated by the power supply circuit 15 from dropping before being supplied to the pixel circuit 40A, which is located a long wiring distance from the power supply circuit 15. Meanwhile, the display device of one embodiment of the present invention with the structure shown in FIG. 42A can miniaturize pixels more than the display device with the structure shown in FIG. 62A .

[0271] Figure 63 is a modified example of the configuration shown in Figure 62A, and shows an example in which at least a part of transistor 51 is provided in the region where wiring 41 and wiring 43 overlap, and at least a part of transistor 52 is provided in the region where wiring 45 extends in the Y direction.

[0272] Fig. 64A is a modified example of the configuration shown in Fig. 48 , showing an example in which a conductive layer 135 is provided. Fig. 64B is a cross-sectional view taken along dashed dotted line C3-C4 shown in Fig. 64A , showing an example of the configuration of, for example, a transistor 53 in addition to the conductive layer 135.

[0273] The conductive layer 135 has a region extending in the X direction, and can be provided so as to have a region located between the region of the conductive layer 115a extending in the X direction and the region of the conductive layer 115c extending in the X direction. The conductive layer 135 also has regions overlapping with the conductive layer 112a, the conductive layer 112b, and the conductive layer 133. As described above, the conductive layer 135 can be provided in the same layer as the conductive layer 111.

[0274] 64B , similar to the example shown in Fig. 62B , an opening 127 reaching conductive layer 135 is provided in insulating layer 103, and conductive layer 135 and conductive layer 112b are electrically connected inside opening 127. Specifically, for example, inside opening 127, there is a region where conductive layer 135 and conductive layer 112b are in contact with each other.

[0275] 64A , the power supply potential generated by the power supply circuit 15 shown in FIG. 2A can be prevented from dropping before being supplied to the pixel circuit 40C. In particular, the power supply potential generated by the power supply circuit 15 can be preferably prevented from dropping before being supplied to the pixel circuit 40C, which is located a long wiring distance from the power supply circuit 15. On the other hand, the display device of one embodiment of the present invention has the structure shown in FIG. 48 , which allows pixels to be miniaturized more than the display device with the structure shown in FIG. 64A .

[0276] 65 is a modification of the configuration shown in FIG. 64A , and shows an example in which at least a part of transistor 51 is provided in a region where wiring 41 a and wiring 43 overlap. Also, an example in which at least a part of transistor 52 is provided in a region where wiring 45 extends in the Y direction. Furthermore, an example in which at least a part of transistor 53 is provided in a region where wiring 41 b extends in the X direction. In the example shown in FIG. 65 , similar to the example shown in FIG. 31A , pixel circuit 40C does not have conductive layer 131, which is a connection electrode, and conductive layer 111 c and conductive layer 133 are electrically connected by opening 125 d.

[0277] Fig. 66A is a modification of the configuration shown in Fig. 62A , and shows an example in which conductive layer 112b and conductive layer 135 are electrically connected via conductive layer 137 provided in the same layer as conductive layer 115. Fig. 66B is a cross-sectional view taken along dashed dotted line C1-C2 shown in Fig. 66A . In the examples shown in Figs. 66A and 66B , conductive layer 137 is provided in the same layer as conductive layer 115.

[0278] In the example shown in FIG. 66B , an opening 127a reaching conductive layer 112b is provided in insulating layer 105, and conductive layer 112b and conductive layer 137 are electrically connected inside opening 127a. Specifically, for example, inside opening 127a, there is a region where conductive layer 112b and conductive layer 137 are in contact. Furthermore, opening 127b reaching conductive layer 135 is provided in insulating layer 103 and insulating layer 105, and conductive layer 135 and conductive layer 137 are electrically connected inside opening 127b. Specifically, for example, inside opening 127b, there is a region where conductive layer 135 and conductive layer 137 are in contact.

[0279] As a result, the conductive layer 112b and the conductive layer 135 can be electrically connected to each other through the conductive layer 137. By configuring the display device of one embodiment of the present invention in this manner, the opening 127 (the opening 127a and the opening 127b) can be formed in parallel with the opening 125a. Here, for example, the conductive layer 137 is also referred to as a connection electrode for electrically connecting the conductive layer 112b and the conductive layer 135.

[0280] 66A and 66B , similarly to the example shown in FIGS. 18A and 18B , the conductive layer 117 and the conductive layer 111b are electrically connected via the conductive layer 119. Like the conductive layer 137, the conductive layer 119 can be provided in the same layer as the conductive layer 115. Therefore, the conductive layer 119 and the conductive layer 137 can have the same material as the conductive layer 115 and can be formed in the same process. For example, the conductive layer 115, the conductive layer 119, and the conductive layer 137 can be formed by processing the same conductive film. Here, the opening 125b1 provided in the insulating layer 105 to electrically connect the conductive layer 117 and the conductive layer 119, and the opening 125b2 provided in the insulating layer 103 and the insulating layer 105 to electrically connect the conductive layer 111b and the conductive layer 119, can be formed in parallel with the opening 127.

[0281] Figure 67 is a modified example of the configuration shown in Figure 66A, and shows an example in which at least a part of transistor 51 is provided in the region where wiring 41 and wiring 43 overlap, and at least a part of transistor 52 is provided in the region where wiring 45 extends in the Y direction.

[0282] Fig. 68A is a modification of the configuration shown in Fig. 64A , and shows an example in which conductive layer 112b and conductive layer 135 are electrically connected via conductive layer 137 provided in the same layer as conductive layer 115. Fig. 68B is a cross-sectional view taken along dashed dotted line C3-C4 shown in Fig. 68A . In the examples shown in Figs. 68A and 68B , conductive layer 137 is provided in the same layer as conductive layer 115.

[0283] 68B , similar to the example shown in Fig. 66B , an opening 127a reaching conductive layer 112b is provided in insulating layer 105, and conductive layer 112b is electrically connected to conductive layer 137 inside opening 127a. Also, an opening 127b reaching conductive layer 135 is provided in insulating layer 103 and insulating layer 105, and conductive layer 135 is electrically connected to conductive layer 137 inside opening 127b.

[0284] 68A and 68B , similarly to the example shown in FIGS. 32A and 32B , the conductive layer 117, the conductive layer 111b, and the conductive layer 111c are electrically connected to each other through the conductive layer 119. Like the conductive layer 137, the conductive layer 119 can be provided in the same layer as the conductive layer 115. Therefore, the conductive layer 119 and the conductive layer 137 can have the same material as the conductive layer 115 and can be formed in the same process. For example, the conductive layer 115, the conductive layer 119, and the conductive layer 137 can be formed by processing the same conductive film. Here, opening 125b1 provided in insulating layer 105 to electrically connect conductive layer 117 and conductive layer 119, opening 125b2 provided in insulating layer 103 and insulating layer 105 to electrically connect conductive layer 111b and conductive layer 119, and opening 125c provided in insulating layer 103 and insulating layer 105 to electrically connect conductive layer 111c and conductive layer 119 can be formed in parallel with opening 127.

[0285] 69 is a modification of the configuration shown in FIG. 68A , and illustrates an example in which at least a portion of transistor 51 is provided in a region where wiring 41 a and wiring 43 overlap. Also, an example in which at least a portion of transistor 52 is provided in a region where wiring 45 extends in the Y direction. Furthermore, an example in which at least a portion of transistor 53 is provided in a region where wiring 41 b extends in the X direction. In the example shown in FIG. 69 , similar to the examples shown in FIGS. 31A and 31B , pixel circuit 40C does not include conductive layer 131, and conductive layer 111 c and conductive layer 133 are electrically connected inside opening 125 d.

[0286] 42 to 69 , the opening 125a is provided in the insulating layer 103 and the insulating layer 105 so as to reach the conductive layer 111a. The conductive layer 111a and the conductive layer 115b are electrically connected inside the opening 125a. Specifically, for example, the opening 125a has a region where the conductive layer 111a and the conductive layer 115b are in contact with each other.

[0287] Fig. 70A is a modification of the configuration shown in Fig. 62A, and shows an example in which conductive layer 135 is provided in the same layer as conductive layer 115. Fig. 70B is a cross-sectional view taken along dashed dotted line C1-C2 shown in Fig. 70A.

[0288] 70B , an opening 127 reaching conductive layer 112b is provided in insulating layer 105, and conductive layer 112b and conductive layer 135 are electrically connected inside opening 127. Specifically, for example, inside opening 127, there is a region where conductive layer 112b and conductive layer 135 are in contact with each other.

[0289] In the example shown in FIGS. 70A and 70B , at least a part of the conductive layer 111a functions as the wiring 43 that functions as a signal line, similar to the example shown in FIGS. 18A and 18B . The conductive layer 112a is electrically connected to one electrode of the capacitor 57 and the conductive layer 115b that functions as the gate electrode of the transistor 52. The conductive layer 117 and the conductive layer 111b are electrically connected through the conductive layer 119. Like the conductive layer 135, the conductive layer 119 can be provided in the same layer as the conductive layer 115. Therefore, the conductive layer 119 and the conductive layer 135 can be made of the same material as the conductive layer 115 and can be formed in the same process. For example, the conductive layer 115, the conductive layer 119, and the conductive layer 135 can be formed by processing the same conductive film. Here, the openings 125b1 and 125b2 can be formed in parallel with the opening 127.

[0290] Figure 71 is a modified example of the configuration shown in Figure 70A, and shows an example in which at least a part of transistor 51 is provided in the region where wiring 41 and wiring 43 overlap, and at least a part of transistor 52 is provided in the region where wiring 45 extends in the Y direction.

[0291] 70A , at least a part of the conductive layer 112a functions as a wiring 43 that functions as a signal line. In the example shown in Fig. 72 , the conductive layer 111a is electrically connected to one electrode of the capacitor 57 and a conductive layer 115b that functions as a gate electrode of the transistor 52. Specifically, an opening 125a is provided in the insulating layer 103 and the insulating layer 105, and the conductive layer 111a and the conductive layer 115b are electrically connected inside the opening 125a.

[0292] Figure 73 is a modified example of the configuration shown in Figure 72, in which at least a portion of transistor 51 is provided in the region where wiring 41 and wiring 43 overlap, and at least a portion of transistor 52 is provided in the region where wiring 45 extends in the Y direction.

[0293] 74A is a modification of the configuration shown in FIG. 66A , showing an example in which conductive layer 137 is provided in the same layer as conductive layer 111. FIG. 74B is a cross-sectional view taken along dashed dotted line C1-C2 shown in FIG. 74A . In the examples shown in FIGS. 74A and 74B , conductive layer 137 can be made of the same material as conductive layer 111 and can be formed in the same process. For example, conductive layer 111 and conductive layer 137 can be formed by processing the same conductive film.

[0294] In the example shown in Figures 74A and 74B, an opening 127a reaching the conductive layer 137 is provided in the insulating layer 103, and the conductive layer 137 and the conductive layer 112b are electrically connected inside the opening 127a. Specifically, for example, the conductive layer 137 and the conductive layer 112b have a contact area inside the opening 127a. Furthermore, an opening 127b reaching the conductive layer 137 is provided in the insulating layer 103 and the insulating layer 105, and the conductive layer 137 and the conductive layer 135 are electrically connected inside the opening 127b. Specifically, for example, the conductive layer 137 and the conductive layer 135 have a contact area inside the opening 127b. As a result, the conductive layer 112b and the conductive layer 135 can be electrically connected via the conductive layer 137.

[0295] 74A and 74B, similar to the examples shown in FIGS. 5 and 6, conductive layer 111b and conductive layer 117 are electrically connected inside opening 125b without going through conductive layer 119, which is a connecting electrode. This allows opening 125b to be formed in parallel with opening 127a. Also, opening 125a can be formed in parallel with opening 127b.

[0296] Figure 75 is a modified example of the configuration shown in Figure 74A, and shows an example in which at least a part of transistor 51 is provided in the region where wiring 41 and wiring 43 overlap, and at least a part of transistor 52 is provided in the region where wiring 45 extends in the Y direction.

[0297] 74A, at least a part of the conductive layer 112a functions as a wiring 43 that functions as a signal line. In the example shown in Fig. 76, the conductive layer 111a is electrically connected to the conductive layer 115b, similar to the example shown in Fig. 72.

[0298] Figure 77 is a modified example of the configuration shown in Figure 76, in which at least a portion of transistor 51 is provided in the region where wiring 41 and wiring 43 overlap, and at least a portion of transistor 52 is provided in the region where wiring 45 extends in the Y direction.

[0299] FIG. 78A is a modified example of the structure shown in FIG. 66A , and shows a different layer in which the conductive layer 137 is provided. FIG. 78A shows a pixel electrode 311, and shows an example in which the conductive layer 137 is provided in the same layer as the pixel electrode 311. Therefore, in the example shown in FIG. 78A , the conductive layer 137 can be made of the same material as the pixel electrode 311 and can be formed in the same process. For example, the pixel electrode 311 and the conductive layer 137 can be formed by processing the same conductive film. FIG. 78B is a cross-sectional view taken along dashed line C1-C2 shown in FIG. 78A . FIG. 78B also shows an example of the structure of layers above the transistor 52, for example.

[0300] An insulating layer 218 and an insulating layer 235 over the insulating layer 218 are provided to cover the transistor 51, the transistor 52, and the capacitor 57. The insulating layer 105, the insulating layer 218, and the insulating layer 235 have an opening 129 that reaches the conductive layer 117. For a description of elements provided above the insulating layer 235 and a description of the opening 129, see, for example, the description in FIG. 13 .

[0301] 78B , openings 127a reaching conductive layer 112b are provided in insulating layer 105, insulating layer 218, and insulating layer 235. Also, openings 127b reaching conductive layer 135 are provided in insulating layer 103, insulating layer 105, insulating layer 218, and insulating layer 235. Here, openings 127a and 127b can be formed in parallel with opening 129.

[0302] The conductive layer 137 is provided to cover the opening 127a and the opening 127b. The conductive layer 137 has a shape that conforms to the upper and side surfaces of the insulating layer 235, the side surfaces of the insulating layer 218, the side surfaces of the insulating layer 105, the side surfaces of the insulating layer 103, the upper surface of the conductive layer 112b, and the upper surface of the conductive layer 135. The conductive layer 137 has regions that contact, for example, the upper and side surfaces of the insulating layer 235, the side surfaces of the insulating layer 218, the side surfaces of the insulating layer 105, the side surfaces of the insulating layer 103, the upper surface of the conductive layer 112b, and the upper surface of the conductive layer 135. The conductive layer 137 can be electrically connected to the conductive layer 112b inside the opening 127a and can be electrically connected to the conductive layer 135 inside the opening 127b. This allows the conductive layer 112b and the conductive layer 135 to be electrically connected via the conductive layer 137.

[0303] An insulating layer 237 can be provided so as to cover the upper surface end portion of the conductive layer 137. By providing the insulating layer 237, for example, the conductive layer 137 can be prevented from coming into contact with the pixel electrode 311 and causing a short circuit.

[0304] A recess is formed in the conductive layer 137 so as to cover the opening 127a, and another recess is formed so as to cover the opening 127b. An insulating layer 237 is filled in these recesses.

[0305] 78A and 78B can also be applied to the openings 127a, 127b, and conductive layers 137 shown in other layers than those shown in FIGS. 66A and 66B. For example, the conductive layer 137 shown in other layers than those shown in FIGS. 66A and 66B can be provided in the same layer as the pixel electrode, and the opening 127a reaching the conductive layer 112b and the opening 127b reaching the conductive layer 135 can be provided in the insulating layer 218 and the insulating layer 235. Furthermore, the structure of the conductive layer 137 shown in FIGS. 78A and 78B can also be applied to the conductive layer 119 and the conductive layer 131. For example, the conductive layer 119 and the conductive layer 131 can be provided in the same layer as the pixel electrode. 78A and 78B, specifically, the configuration in which openings are provided in insulating layer 218 and insulating layer 235, for example, can also be applied to opening 125. For example, the configurations of opening 127a and opening 127b shown in Figures 78A and 78B can be applied to opening 125b1, opening 125b2, and opening 125c when conductive layer 119 is provided in the same layer as the pixel electrode, and can be applied to opening 125d1 and opening 125d2 when conductive layer 131 is provided in the same layer as the pixel electrode.

[0306] Fig. 79A is a modified example of the configuration shown in Fig. 9A , showing an example in which the conductive layer 136 has a region extending in the X direction. Fig. 79B is a cross-sectional view taken along dashed dotted line C1-C2 shown in Fig. 79A , showing an example of the configuration of the conductive layer 136 as well as, for example, the transistor 52.

[0307] 79A , the region of conductive layer 136 extending in the X direction can be provided so as to have a region located between, for example, the region of conductive layer 115a extending in the X direction and conductive layer 115b. Furthermore, for example, the region of conductive layer 136 extending in the X direction has a region overlapping with the region of conductive layer 111a functioning as wiring 43 extending in the Y direction. Here, the area of ​​the region where conductive layer 111b and conductive layer 136 overlap is larger than the area of ​​the region where conductive layer 111a and conductive layer 136 overlap.

[0308] 79A , the resistance of the wiring 45 can be reduced compared to the case of the display device of one embodiment of the present invention having the structure shown in FIG. 9A . Therefore, a drop in the power supply potential generated by the power supply circuit 15 before it is supplied to the pixel circuit 40A can be suppressed. In particular, a drop in the power supply potential generated by the power supply circuit 15 before it is supplied to the pixel circuit 40A, which is located a long wiring distance from the power supply circuit 15, can be suppressed favorably. Meanwhile, the display device of one embodiment of the present invention having the structure shown in FIG. 9A can miniaturize pixels compared to the case of the structure shown in FIG. 79A .

[0309] FIG. 80 shows a modification of the configuration shown in FIG. 79A, in which at least a part of the transistor 51 is provided in a region where the wiring 41 and the wiring 43 overlap.

[0310] Fig. 81A is a modified example of the configuration shown in Fig. 79A, and shows an example in which, similar to the example shown in Fig. 56A, conductive layer 111b and conductive layer 136 are electrically connected via conductive layer 139. Fig. 81B is a cross-sectional view taken along dashed dotted line C1-C2 shown in Fig. 81A.

[0311] FIG. 82 shows a modification of the configuration shown in FIG. 81A, in which at least a part of the transistor 51 is provided in a region where the wiring 41 and the wiring 43 overlap.

[0312] Fig. 83A is a modification of the configuration shown in Fig. 52A, showing an example in which conductive layer 111b has a region extending in the X direction. Fig. 83B is a cross-sectional view taken along dashed dotted line C1-C2 shown in Fig. 83A.

[0313] 83A , the region of conductive layer 111b extending in the X direction can be provided so as to have a region located between, for example, the region of conductive layer 115a extending in the X direction and conductive layer 115b. Also, for example, the region of conductive layer 111b extending in the X direction has a region overlapping with a region of conductive layer 112a functioning as wiring 43 extending in the Y direction. Here, the area of ​​the region where conductive layer 111b and conductive layer 136 overlap is larger than the area of ​​the region where conductive layer 111b and conductive layer 112a overlap.

[0314] 83A , the resistance of the wiring 45 can be reduced compared to the case of the display device having the structure shown in FIG. 52A . Therefore, a voltage drop in the power supply potential generated by the power supply circuit 15 can be suppressed. On the other hand, the pixel can be miniaturized compared to the case of the display device having the structure shown in FIG. 83A .

[0315] FIG. 84 shows a modification of the configuration shown in FIG. 83A, in which at least a part of the transistor 51 is provided in a region where the wiring 41 and the wiring 43 overlap.

[0316] Fig. 85A is a modification of the configuration shown in Fig. 83A, and shows an example in which, similar to the example shown in Fig. 56A, conductive layer 111b and conductive layer 136 are electrically connected via conductive layer 139. Fig. 85B is a cross-sectional view taken along dashed dotted line C1-C2 shown in Fig. 85A.

[0317] FIG. 86 shows a modification of the configuration shown in FIG. 85A, in which at least a part of the transistor 51 is provided in a region where the wiring 41 and the wiring 43 overlap.

[0318] Fig. 87A is a modification of the configuration shown in Fig. 9A, showing an example in which a pixel is provided with a conductive layer 135. Fig. 87B is a cross-sectional view taken along dashed line C1-C2 shown in Fig. 87A.

[0319] The conductive layer 135 has a region extending in the X direction, and can be provided so as to have, for example, a region located between the region of the conductive layer 115a extending in the X direction and the conductive layer 115b. The conductive layer 135 also has regions overlapping with the conductive layer 111a, the conductive layer 111b, and the conductive layer 136. The conductive layer 135 can be provided in the same layer as the conductive layer 115. Therefore, the conductive layer 135 can have the same material as the conductive layer 115 and can be formed in the same process. For example, the conductive layer 115 and the conductive layer 135 can be formed by processing the same conductive film.

[0320] 87B , an opening 127 reaching the conductive layer 136 is provided in the insulating layer 105, and the conductive layer 136 and the conductive layer 135 are electrically connected inside the opening 127. Specifically, for example, inside the opening 127, there is a region where the conductive layer 136 and the conductive layer 135 are in contact with each other.

[0321] In Figure 87A, the shape of opening 127 in a planar view is circular, but one aspect of the present invention is not limited to this, and the opening 127 can have a shape similar to the shape that at least one of openings 121, opening 123, opening 125, and opening 126 can have.

[0322] 87A , not only the conductive layer 111b and the conductive layer 136 having a region extending in the Y direction but also the conductive layer 135 having a region extending in the X direction function as the wiring 45 that functions as a power supply line. Therefore, the power supply circuit 15 shown in FIG. 1A can supply a power supply potential to the transistor 52 not only through the conductive layer 111b and the conductive layer 136 but also through the conductive layer 135. This can reduce the resistance of the wiring 45. Therefore, a voltage drop in the power supply potential generated by the power supply circuit 15 can be suppressed. Meanwhile, the display device of one embodiment of the present invention having the structure shown in FIG. 9A can miniaturize pixels more than the display device with the structure shown in FIG. 87A .

[0323] FIG. 88 shows a modification of the configuration shown in FIG. 87A, in which at least a part of the transistor 51 is provided in a region where the wiring 41 and the wiring 43 overlap.

[0324] 89, 90, 91, and 92 are modified examples of the configurations shown in FIGS. 52A, 53, 54A, and 55, respectively, and show examples in which the conductive layer 135 has a region extending in the X direction, similar to the example shown in FIG. 87A.

[0325] 93A and 93B are modified examples of the configurations shown in FIGS. 87A and 87B, respectively, and show an example in which an opening 126 reaching conductive layer 111b is provided not only in insulating layer 103 but also in insulating layer 105. In the examples shown in FIGS. 93A and 93B, conductive layer 111b and conductive layer 135 are electrically connected inside opening 126. Specifically, for example, inside opening 126, there is a region where conductive layer 111b and conductive layer 135 are in contact.

[0326] As described above, the conductive layer 111b and the conductive layer 136 can be electrically connected to each other through the conductive layer 135. By configuring the display device of one embodiment of the present invention in this manner, the opening 126 and the opening 127 can be formed in parallel with the opening 125a.

[0327] FIG. 94 is a modification of the configuration shown in FIG. 93A, and shows an example in which at least a part of the transistor 51 is provided in a region where the wiring 41 and the wiring 43 overlap.

[0328] 95, 96, 97, and 98 are modifications of the configurations shown in Figures 58, 59, 60, and 61, respectively, and show an example in which, similar to the example shown in Figure 87A, conductive layer 111b and conductive layer 136 are electrically connected via conductive layer 135. In the examples shown in Figures 97 and 98, opening 126 reaching conductive layer 111b is opening 126b, and conductive layer 111b and conductive layer 135 are electrically connected inside opening 126b.

[0329] FIG. 99A is a modification of the structure shown in FIG. 87A , illustrating an example in which the conductive layer 111b, the conductive layer 136, and the conductive layer 135 are electrically connected via the conductive layer 139. FIG. 99A also illustrates a pixel electrode 311, illustrating an example in which the conductive layer 139 is provided in the same layer as the pixel electrode 311. Therefore, in the example shown in FIG. 99A , the conductive layer 139 can be made of the same material as the pixel electrode 311 and can be formed in the same process. For example, the pixel electrode 311 and the conductive layer 139 can be formed by processing the same conductive film. FIG. 99B is a cross-sectional view taken along the dashed dotted line C1-C2 in FIG. 99A . FIG. 99B also illustrates an example of a configuration of layers above the transistor 52, for example.

[0330] An insulating layer 218 and an insulating layer 235 over the insulating layer 218 are provided to cover the transistor 51, the transistor 52, and the capacitor 57. The insulating layer 105, the insulating layer 218, and the insulating layer 235 have an opening 129 that reaches the conductive layer 112b. For a description of elements provided above the insulating layer 235 and a description of the opening 129, see, for example, the description in FIG. 15 .

[0331] 99B , an opening 126_1 reaching the conductive layer 111b is provided in the insulating layer 103, the insulating layer 105, the insulating layer 218, and the insulating layer 235. An opening 126_2 reaching the conductive layer 136 is provided in the insulating layer 105, the insulating layer 218, and the insulating layer 235. An opening 127 reaching the conductive layer 135 is provided in the insulating layer 218 and the insulating layer 235. Here, the openings 126_1, 126_2, and 127 can be formed in parallel with the opening 129.

[0332] The conductive layer 139 is provided to cover the opening 126_1, the opening 126_2, and the opening 127. The conductive layer 139 has a shape that follows the top surface and side surface of the insulating layer 235, the side surface of the insulating layer 218, the side surface of the insulating layer 105, the side surface of the insulating layer 103, the top surface of the conductive layer 111b, the top surface of the conductive layer 136, and the top surface of the conductive layer 135. The conductive layer 139 has regions that are in contact with, for example, the top surface and side surface of the insulating layer 235, the side surface of the insulating layer 218, the side surface of the insulating layer 105, the side surface of the insulating layer 103, the top surface of the conductive layer 111b, the top surface of the conductive layer 136, and the top surface of the conductive layer 135. The conductive layer 139 can be electrically connected to the conductive layer 111b inside the opening 126_1, can be electrically connected to the conductive layer 136 inside the opening 126_2, and can be electrically connected to the conductive layer 135 inside the opening 127. This allows the conductive layer 111 b , the conductive layer 136 , and the conductive layer 135 to be electrically connected via the conductive layer 139 .

[0333] An insulating layer 237 can be provided so as to cover the upper surface end portion of the conductive layer 139. By providing the insulating layer 237, for example, the conductive layer 139 can be prevented from coming into contact with the pixel electrode 311 and causing a short circuit.

[0334] In the conductive layer 139, a recess is formed so as to cover the opening 126_1, a recess is formed so as to cover the opening 126_2, and a recess is formed so as to cover the opening 127. An insulating layer 237 is buried in these recesses.

[0335] 99A and 99B may be provided in the same layer as the pixel electrode 311. In this case, the opening 126 is also provided in the insulating layer 218 and the insulating layer 235. Furthermore, for example, the conductive layer 119 shown in FIGS. 39A and 39B may be provided in the same layer as the pixel electrode 311. In this case, the opening 125b is also provided in the insulating layer 218 and the insulating layer 235.

[0336] FIG. 100 shows a modification of the configuration shown in FIG. 99A, in which at least a part of the transistor 51 is provided in a region where the wiring 41 and the wiring 43 overlap.

[0337] 101, 102, 103, and 104 are modifications of the structures shown in FIGS. 95, 96, 97, and 98, respectively. Similar to the example shown in FIG. 99A, FIGS. 101 to 104 show an example in which the conductive layer 111b, the conductive layer 136, and the conductive layer 135 are electrically connected via a conductive layer 139 provided in the same layer as the pixel electrode 311. Note that FIGS. 101 to 104 show the pixel electrode 311. In the examples shown in FIGS. 103 and 104, the conductive layer 139b, the opening 126b1, and the opening 126b2 correspond to the conductive layer 139, the opening 126_1, and the opening 126_2 shown in FIG. 99A, respectively.

[0338] <Components of Display Device> Components included in the display device of this embodiment will be described below.

[0339] [Semiconductor Layer 113] The semiconductor material that can be used for the semiconductor layer 113 is not particularly limited. For example, an elemental semiconductor or a compound semiconductor can be used. Examples of elemental semiconductors that can be used include silicon or germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Examples of compound semiconductors that can be used include organic substances having semiconductor properties or metal oxides having semiconductor properties. Note that these semiconductor materials may contain impurities as dopants.

[0340] The crystallinity of the semiconductor material used for the semiconductor layer 113 is not particularly limited, and any of an amorphous semiconductor and a crystalline semiconductor (a single-crystalline semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0341] Silicon can be used for the semiconductor layer 113. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS).

[0342] A transistor using amorphous silicon for the semiconductor layer 113 can be formed over a large glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon for the semiconductor layer 113 has high field-effect mobility and can operate at high speed. A transistor using microcrystalline silicon for the semiconductor layer 113 has higher field-effect mobility than a transistor using amorphous silicon and can operate at high speed.

[0343] The semiconductor layer 113 preferably includes a metal oxide (oxide semiconductor). Examples of metal oxides that can be used for the semiconductor layer 113 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably includes at least indium (In) or zinc (Zn). The metal oxide preferably includes two or three elements selected from indium, an element M, and zinc. The element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. In particular, the element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin.

[0344] For the semiconductor layer 113, for example, indium oxide, indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), indium tin zinc oxide (In—Sn—Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide), or indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, indium tin oxide containing silicon can be used. Alternatively, the above oxides having an amorphous structure can be used, such as indium oxide having an amorphous structure or indium tin oxide having an amorphous structure.

[0345] The element M is preferably one or more elements selected from the group consisting of gallium, aluminum, yttrium, and tin, and is particularly preferably gallium.

[0346] Here, the composition of the metal oxide in the semiconductor layer 113 greatly affects the electrical characteristics and reliability of the transistor 50 .

[0347] For example, by increasing the content of indium in the metal oxide, a transistor with a large on-state current can be realized.

[0348] When an In—Zn oxide is used for the semiconductor layer 113, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc. For example, a metal oxide in which the atomic ratio of metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, In:Zn=10:1, or a ratio close to these can be used.

[0349] When an In—Sn oxide is used for the semiconductor layer 113, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of tin. For example, a metal oxide in which the atomic ratio of metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, In:Sn=10:1, or a ratio close to these can be used.

[0350] When an In-M-Zn oxide is used for the semiconductor layer 113, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of the element M can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M. For example, the semiconductor layer 113 may have atomic ratios of metal elements of In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1 :6, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, or metal oxides thereof having a similar structure can be used.

[0351] When a plurality of metal elements are contained as the element M, the sum of the atomic ratios of the metal elements can be taken as the atomic ratio of the element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as the element M, the sum of the atomic ratio of gallium and the atomic ratio of aluminum can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned ranges.

[0352] It is preferable to use a metal oxide in which the ratio of the number of indium atoms to the number of atoms of metal elements contained in the metal oxide is 30 atomic % or more and 100 atomic % or less, preferably 30 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 90 atomic % or less, more preferably 40 atomic % or more and 90 atomic % or less, more preferably 45 atomic % or more and 90 atomic % or less, more preferably 50 atomic % or more and 80 atomic % or less, more preferably 60 atomic % or more and 80 atomic % or less, and more preferably 70 atomic % or more and 80 atomic % or less. For example, when an In—Ga—Zn oxide is used for the semiconductor layer 113, it is preferable that the ratio of the number of indium atoms to the total number of atoms of indium, the element M, and zinc be in the above-mentioned range.

[0353] In this specification and the like, the ratio of the number of indium atoms to the number of atoms of the contained metal element may be referred to as the indium content. The same applies to other metal elements.

[0354] By increasing the indium content of the metal oxide, a transistor with a large on-state current can be obtained. By applying the transistor to a transistor that is required to have a high on-state current, a display device with excellent electrical characteristics can be provided.

[0355] The composition of the metal oxide can be analyzed by, for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for the analysis. For elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0356] In this specification, a "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, when an atomic ratio is described as In:M:Zn = 4:2:3 or a composition near there, this includes a case where, when the atomic ratio of indium is 4, the atomic ratio of M is 1 to 3 and the atomic ratio of zinc is 2 to 4. Furthermore, when an atomic ratio is described as In:M:Zn = 5:1:6 or a composition near there, this includes a case where, when the atomic ratio of indium is 5, the atomic ratio of M is greater than 0.1 and less than 2 and the atomic ratio of zinc is greater than 5 and less than 7. Furthermore, when an atomic ratio is described as In:M:Zn = 1:1:1 or a composition near there, this includes a case where, when the atomic ratio of indium is 1, the atomic ratio of M is greater than 0.1 and less than 2 and the atomic ratio of zinc is greater than 0.1 and less than 2.

[0357] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). When forming a metal oxide by sputtering, the atomic ratio of the target may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc in the metal oxide may be approximately 40% to 90% of the atomic ratio of zinc contained in the target.

[0358] Here, the reliability of a transistor will be described. One of the indicators for evaluating the reliability of a transistor is a Gate Bias Temperature (GBT) stress test, in which the transistor is held in a state in which an electric field is applied to the gate. Among these, a test in which a positive potential (positive bias) is applied to the gate with respect to the source potential and the drain potential and the transistor is held at a high temperature is called a Positive Bias Temperature (PBTS) test, and a test in which a negative potential (negative bias) is applied to the gate and the transistor is held at a high temperature is called a Negative Bias Temperature (NBTS) test. The PBTS test and the NBTS test performed under light irradiation are called a PBTIS (Positive Bias Temperature Illumination Stress) test and a NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0359] In an n-type transistor, a positive potential is applied to the gate when the transistor is turned on (a state in which current flows). Therefore, the amount of variation in threshold voltage in the PBTS test is one of the important items to be noted as an index of the reliability of the transistor.

[0360] By using a metal oxide that does not contain gallium or has a low gallium content for the semiconductor layer 113, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of fluctuation in threshold voltage in a PBTS test can be obtained. Furthermore, when a metal oxide containing gallium is used, it is preferable to make the gallium content lower than the indium content. This allows a highly reliable transistor to be realized.

[0361] One of the factors that causes the threshold voltage to fluctuate in the PBTS test is defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The higher the defect level density, the more significant the degradation in the PBTS test. By reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer, the generation of the defect levels can be suppressed.

[0362] The following is a possible reason why using a metal oxide containing no gallium or with a low gallium content for the semiconductor layer can suppress fluctuations in threshold voltage in the PBTS test. Gallium contained in metal oxides has the property of attracting oxygen more easily than other metal elements (e.g., indium or zinc). Therefore, it is presumed that gallium combines with excess oxygen in the gate insulating layer at the interface between the gallium-rich metal oxide and the gate insulating layer, making it easier to generate carrier (here, electron) trap sites. Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, which is thought to cause fluctuations in threshold voltage.

[0363] More specifically, when an In—Ga—Zn oxide is used for the semiconductor layer 113, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of gallium can be used for the semiconductor layer 113. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium. In other words, it is preferable to use a metal oxide in which the atomic ratios of metal elements satisfy In>Ga and Zn>Ga for the semiconductor layer 113.

[0364] For example, the semiconductor layer 113 has an atomic ratio of metal elements of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn=6:1 :6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10, or metal oxides thereof can be used.

[0365] The semiconductor layer 113 preferably uses a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal element is greater than 0 atomic % and less than 50 atomic %, preferably 0.1 atomic % to 40 atomic %, more preferably 0.1 atomic % to 35 atomic %, more preferably 0.1 atomic % to 30 atomic %, more preferably 0.1 atomic % to 25 atomic %, more preferably 0.1 atomic % to 20 atomic %, more preferably 0.1 atomic % to 15 atomic %, and more preferably 0.1 atomic % to 10 atomic %. By reducing the gallium content in the semiconductor layer, a transistor with high resistance to the PBTS test can be obtained. Note that by including gallium in the metal oxide, oxygen deficiency (V Ｏ This has the effect of making oxygen vacancy less likely to occur.

[0366] A metal oxide that does not contain gallium may be used for the semiconductor layer 113. For example, In—Zn oxide may be used for the semiconductor layer 113. In this case, increasing the atomic ratio of indium to the atomic number of metal elements contained in the metal oxide can increase the field-effect mobility of the transistor. On the other hand, increasing the atomic ratio of zinc to the atomic number of metal elements contained in the metal oxide can result in a metal oxide with high crystallinity, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving reliability. Alternatively, a metal oxide that does not contain gallium or zinc, such as indium oxide, may be used for the semiconductor layer 113. Using a metal oxide that does not contain gallium can significantly reduce fluctuations in threshold voltage, particularly in a PBTS test.

[0367] For example, an oxide containing indium and zinc can be used for the semiconductor layer 113. In this case, a metal oxide having an atomic ratio of metal elements of, for example, In:Zn=2:3, In:Zn=4:1, or a ratio close to these can be used.

[0368] Although gallium has been used as a representative example in the description, the present invention can also be applied to a case where the element M is used instead of gallium. For the semiconductor layer 113, it is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of the element M. It is also preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M.

[0369] A transistor having high reliability when a positive bias is applied can be obtained by using a metal oxide having a low content of the element M for the semiconductor layer 113. When the transistor is used as a transistor that is required to have high reliability when a positive bias is applied, a display device having high reliability can be obtained.

[0370] Next, the reliability of the transistor against light will be described.

[0371] Light incident on a transistor may cause fluctuations in the electrical characteristics of the transistor. In particular, it is preferable that a transistor applied to a region where light may be incident exhibits small fluctuations in electrical characteristics under light irradiation and has high reliability against light. The reliability against light can be evaluated, for example, by the amount of fluctuation in threshold voltage in an NBTIS test.

[0372] Increasing the content of the element M in the metal oxide can provide a transistor with high reliability against light. That is, a transistor with a small variation in threshold voltage in an NBTIS test can be provided. Specifically, a metal oxide in which the atomic ratio of the element M is equal to or greater than the atomic ratio of indium has a larger band gap, and can reduce the variation in threshold voltage of the transistor in an NBTIS test. The band gap of the metal oxide in the semiconductor layer 113 is preferably 2.0 eV or more, more preferably 2.5 eV or more, even more preferably 3.0 eV or more, still more preferably 3.2 eV or more, even more preferably 3.3 eV or more, still more preferably 3.4 eV or more, and even more preferably 3.5 eV or more.

[0373] For example, the semiconductor layer 113 can use metal oxides having an atomic ratio of metal elements of In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or similar ratios thereof.

[0374] The semiconductor layer 113 can suitably use a metal oxide in which the ratio of the number of atoms of element M to the number of atoms of the contained metal element is 20 atomic % or more and 70 atomic % or less, preferably 30 atomic % or more and 70 atomic % or less, more preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less.

[0375] When an In—Ga—Zn oxide is used for the semiconductor layer 113, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is equal to or less than the atomic ratio of gallium can be used. For example, a metal oxide in which the atomic ratio of the metal element is In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:3, In:Ga:Zn=1:3:4, or a ratio close to these can be used.

[0376] The semiconductor layer 113 can suitably use a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal elements is 20 atomic % or more and 60 atomic % or less, preferably 20 atomic % or more and 50 atomic % or less, more preferably 30 atomic % or more and 50 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less.

[0377] A transistor with high reliability to light can be obtained by using a metal oxide having a high content of element M for the semiconductor layer 113. By using the transistor as a transistor that is required to have high reliability to light, a display device with high reliability can be obtained.

[0378] As described above, the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used for the semiconductor layer 113. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a display device that has both excellent electrical characteristics and high reliability can be obtained.

[0379] The semiconductor layer 113 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 113 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs.

[0380] The two or more metal oxide layers included in the semiconductor layer 113 may have different compositions. For example, a stacked structure of a first metal oxide layer having an atomic ratio of In:M:Zn=1:3:4 or a composition similar thereto and a second metal oxide layer having an atomic ratio of In:M:Zn=1:1:1 or a composition similar thereto provided on the first metal oxide layer can be preferably used. Furthermore, it is particularly preferable to use gallium or aluminum as the element M. For example, a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) can be used.

[0381] A crystalline metal oxide layer is preferably used for the semiconductor layer 113. For example, a metal oxide layer having a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a nanocrystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 113, the density of defect states in the semiconductor layer 113 can be reduced, and a highly reliable display device can be realized.

[0382] The higher the crystallinity of the metal oxide layer used for the semiconductor layer 113, the more the density of defect states in the semiconductor layer 113 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0383] When a metal oxide layer is formed by a sputtering method, the higher the substrate temperature (stage temperature) during formation, the higher the crystallinity of the formed metal oxide layer.Furthermore, the higher the ratio of the flow rate of oxygen gas to the total deposition gas used during formation (also referred to as the oxygen flow rate ratio), the higher the crystallinity of the formed metal oxide layer.

[0384] The semiconductor layer 113 may have a stacked structure of two or more metal oxide layers with different crystallinity. For example, the semiconductor layer 113 may have a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, where the second metal oxide layer has a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer. The two or more metal oxide layers included in the semiconductor layer 113 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form the layers, thereby reducing manufacturing costs. For example, by using the same sputtering target and varying the oxygen flow rate, a stacked structure of two or more metal oxide layers with different crystallinity can be formed. Note that the two or more metal oxide layers included in the semiconductor layer 113 may have different compositions.

[0385] The thickness of the semiconductor layer 113 is preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, even more preferably 10 nm or more and 100 nm or less, even more preferably 10 nm or more and 70 nm or less, even more preferably 15 nm or more and 70 nm or less, even more preferably 15 nm or more and 50 nm or less, even more preferably 20 nm or more and 50 nm or less, even more preferably 20 nm or more and 40 nm or less, even more preferably 25 nm or more and 40 nm or less.

[0386] The substrate temperature during the formation of the semiconductor layer 113 is preferably from room temperature (25° C.) to 200° C., more preferably from room temperature to 130° C. By setting the substrate temperature within the above range, bending or distortion of the substrate can be suppressed when a large-area glass substrate is used.

[0387] Here, oxygen vacancies that can be formed in the semiconductor layer 113 will be described.

[0388] When an oxide semiconductor is used for the semiconductor layer 113, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, and oxygen vacancies (V Ｏ In addition, defects in which hydrogen enters oxygen vacancies (hereinafter referred to as V ＯHydrogen atoms (H) may function as donors and generate electrons as carriers. Furthermore, some of the hydrogen atoms may bond with oxygen atoms that are bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced.

[0389] V Ｏ H can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in an oxide semiconductor, evaluation is sometimes performed using the carrier concentration rather than the donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the oxide semiconductor, rather than the donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as the "donor concentration."

[0390] From the above, when an oxide semiconductor is used for the semiconductor layer 113, V in the semiconductor layer 113 Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain an oxide semiconductor in which H is sufficiently reduced, impurities such as water and hydrogen in the oxide semiconductor are removed (this may be referred to as dehydration or dehydrogenation treatment), and oxygen vacancies (V Ｏ It is important to repair the Ｏ By using an oxide semiconductor in which impurities such as H are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0391] In the case where an oxide semiconductor is used for the semiconductor layer 113, the carrier concentration of the oxide semiconductor in a region functioning as a channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm−３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ The lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, but is preferably, for example, 1×10 −９ cm −３ It can be said that:

[0392] The semiconductor layer 113 may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0393] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２), zirconium sulfide (typically ZrS ２ ), and zirconium selenide (typically ZrSe ２ ) etc.

[0394] [Insulating Layer 103] An inorganic insulating material or an organic insulating material can be used for the insulating layer 103. The insulating layer 103 may have a stacked structure of an inorganic insulating material and an organic insulating material.

[0395] An inorganic insulating material can be suitably used for the insulating layer 103. Examples of the inorganic insulating material that can be used include one or more of oxide, oxynitride, nitride oxide, and nitride. For example, the insulating layer 103 can include one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, silicon nitride, silicon nitride oxide, and aluminum nitride.

[0396] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0397] The oxygen and nitrogen contents can be analyzed using, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 1 atomic% or less, or 0.5 atomic% or less). When comparing the element contents, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0398] The insulating layer 103 may have a stacked structure of two or more layers. In the cross-sectional view illustrating the example of the structure of the transistor 50 described above, the insulating layer 103 has a stacked structure of an insulating layer 103a and an insulating layer 103b over the insulating layer 103a. The insulating layer 103a and the insulating layer 103b can each be made of the same material as that used for the insulating layer 103. Note that the insulating layer 103a and the insulating layer 103b may be made of the same material or different materials. Note that the insulating layer 103a may have a stacked structure of two or more layers. The insulating layer 103b may have a stacked structure of two or more layers.

[0399] The insulating layer 103a can be thicker than the insulating layer 103b. The deposition rate (also referred to as deposition rate) of the insulating layer 103a is preferably fast, for example, faster than the deposition rate of the insulating layer 103b. In particular, when the insulating layer 103a is thick, the deposition rate of the insulating layer 103a is preferably fast. By increasing the deposition rate of the insulating layer 103a, productivity can be increased. For example, the deposition rate can be increased by increasing the power used in forming the insulating layer 103a.

[0400] The insulating layer 103a preferably has a small stress. If the insulating layer 103a is made thick, the stress of the insulating layer 103a increases, which may cause warping of the substrate. By reducing the stress of the insulating layer 103a, it is possible to prevent problems during processing that are caused by stress, such as warping of the substrate.

[0401] The insulating layer 103b functions as a blocking layer that suppresses gas desorption from the insulating layer 103a. The insulating layer 103b is preferably made of a material that does not easily diffuse gas. The insulating layer 103b preferably has a region with a higher film density than the insulating layer 103a. Increasing the film density of the insulating layer 103b can improve the blocking property. For example, the insulating layer 103b can be made of a material that has a higher nitrogen content than the insulating layer 103a. Increasing the nitrogen content of the insulating layer 103b can improve the blocking property.

[0402] The insulating layer 103b may have any thickness that functions as a blocking layer for preventing gas from being released from the insulating layer 103a, and may be thinner than the insulating layer 103a. The deposition rate of the insulating layer 103b is preferably slow, for example, slower than the deposition rate of the insulating layer 103a. By slowing the deposition rate of the insulating layer 103b, the film density of the insulating layer 103b can be increased, thereby improving the blocking property. Furthermore, by increasing the substrate temperature during deposition of the insulating layer 103b, the film density of the insulating layer 103b can be increased, thereby improving the blocking property.

[0403] The film density can be evaluated using, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflection (XRR). Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a darker (darker) transmission electron (TE) image, whereas a low film density results in a lighter (brighter) transmission electron (TE) image. Therefore, the insulating layer 103b may appear darker (darker) in the transmission electron (TE) image than the insulating layer 103a. Even when the insulating layer 103a and the insulating layer 103b are made of the same material, the film density is different, and therefore the boundary between them can sometimes be observed as a difference in contrast in a cross-sectional TEM image.

[0404] The insulating layer 103b may have a region where the hydrogen concentration in the film is lower than that in the insulating layer 103a. The difference in hydrogen concentration between the insulating layer 103a and the insulating layer 103b can be evaluated by, for example, secondary ion mass spectrometry (SIMS).

[0405] Here, the insulating layer 103 will be specifically described using an example in which a metal oxide is used for the semiconductor layer 113.

[0406] When an oxide semiconductor is used for the semiconductor layer 113, an inorganic insulating material can be suitably used for each of the insulating layers 103a and 103b.

[0407] The insulating layer 103a is preferably formed using an oxide or an oxynitride. The insulating layer 103a is preferably formed using a film that releases oxygen by heating. For example, silicon oxide or silicon oxynitride can be suitably used for the insulating layer 103a.

[0408] When the insulating layer 103a releases oxygen, oxygen can be supplied from the insulating layer 103a to the semiconductor layer 113. When oxygen is supplied from the insulating layer 103a to the semiconductor layer 113, particularly to the channel formation region of the semiconductor layer 113, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, the transistor 50 can have favorable electrical characteristics and high reliability. The insulating layer 103a preferably has a high oxygen diffusion coefficient. By increasing the oxygen diffusion coefficient of the insulating layer 103a, oxygen can be easily diffused in the insulating layer 103a, and oxygen can be efficiently supplied from the insulating layer 103a to the semiconductor layer 113. Other treatments for supplying oxygen to the semiconductor layer 113 include heat treatment in an atmosphere containing oxygen and plasma treatment in an atmosphere containing oxygen.

[0409] The insulating layer 103a preferably releases little impurities (for example, water and hydrogen) from itself. Reducing the release of impurities from the insulating layer 103a suppresses the impurities from diffusing into the semiconductor layer 113. Therefore, the transistor 50 can have favorable electrical characteristics and high reliability.

[0410] For example, silicon oxide or silicon oxynitride formed by plasma enhanced chemical vapor deposition (PECVD) can be suitably used for the insulating layer 103a. In this case, a mixed gas of a silicon-containing gas and an oxygen-containing gas is preferably used as the source gas. As the silicon-containing gas, for example, one or more of silane, disilane, trisilane, and silane fluoride can be used. As the oxygen-containing gas, for example, oxygen (O ２ ), ozone (O ３ ), nitrous oxide (N ２O), nitric oxide (NO), or nitrogen dioxide (NO ２ Note that by increasing the power used in forming the insulating layer 103a, the amount of impurities (for example, water and hydrogen) released from the insulating layer 103a can be reduced.

[0411] The insulating layer 103b is preferably impermeable to oxygen. The insulating layer 103b functions as a blocking layer that suppresses oxygen from being released from the insulating layer 103a. Furthermore, the insulating layer 103b is preferably impermeable to hydrogen. The insulating layer 103b functions as a blocking layer that suppresses hydrogen from diffusing from the outside of the transistor to the semiconductor layer 113 through the insulating layer 103. The insulating layer 103b preferably has a high film density. Increasing the film density of the insulating layer 103b can improve the blocking property of oxygen and hydrogen. The film density of the insulating layer 103b is preferably higher than that of the insulating layer 103a. When silicon oxide or silicon oxynitride is used for the insulating layer 103a, the insulating layer 103b can be preferably made of, for example, silicon nitride, silicon nitride oxide, or aluminum oxide. The insulating layer 103b preferably has a region with a higher nitrogen content than the insulating layer 103a, for example. The insulating layer 103b can be formed using, for example, a material having a higher nitrogen content than the insulating layer 103a. The insulating layer 103b is preferably formed using a nitride or a nitride oxide. For example, silicon nitride or silicon nitride oxide can be suitably used for the insulating layer 103b.

[0412] When oxygen contained in the insulating layer 103a diffuses upward from a region of the insulating layer 103a that is not in contact with the semiconductor layer 113 (for example, the upper surface of the insulating layer 103a), the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 may decrease. By providing the insulating layer 103b on the insulating layer 103a, it is possible to prevent the oxygen contained in the insulating layer 103a from diffusing from a region of the insulating layer 103a that is not in contact with the semiconductor layer 113. Therefore, the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 increases, and oxygen vacancies (V Ｏ ) and V ＯH can be reduced. Therefore, the transistor 50 can have favorable electrical characteristics and high reliability.

[0413] The conductive layer 112 may be oxidized by the oxygen contained in the insulating layer 103a, resulting in an increase in resistance. Furthermore, the conductive layer 112 may be oxidized by the oxygen contained in the insulating layer 103a, resulting in a decrease in the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113. By providing the insulating layer 103b on the insulating layer 103a, it is possible to prevent the conductive layer 112 from being oxidized and the resistance from increasing. At the same time, the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 increases, resulting in an oxygen deficiency (V Ｏ ) and V Ｏ H can be reduced. Therefore, the transistor 50 can have favorable electrical characteristics and high reliability.

[0414] When hydrogen diffuses into the semiconductor layer 113, it reacts with oxygen atoms contained in the oxide semiconductor to form water, and oxygen vacancies (V Ｏ ) may be formed. Ｏ By providing the insulating layer 103b on the insulating layer 103a, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, the transistor 50 can have favorable electrical characteristics and high reliability.

[0415] The insulating layer 103b preferably has a thickness that functions as a blocking layer for oxygen and hydrogen. If the insulating layer 103b is too thin, its function as a blocking layer may be reduced. On the other hand, if the insulating layer 103b is too thick, the region of the semiconductor layer 113 in contact with the insulating layer 103a may be narrowed, and the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 may be reduced. The insulating layer 103b may have a thickness thinner than that of the insulating layer 103a. The insulating layer 103b has a thickness preferably from 5 nm to 100 nm, more preferably from 5 nm to 70 nm, further preferably from 10 nm to 70 nm, further preferably from 10 nm to 50 nm, further preferably from 20 nm to 50 nm, and further preferably from 20 nm to 40 nm. By setting the thickness of the insulating layer 103b within the above range, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, the transistor 50 can have favorable electrical characteristics and high reliability.

[0416] The insulating layer 103b preferably releases less impurities (for example, water and hydrogen) from itself. Reducing the release of impurities from the insulating layer 103b suppresses the impurities from diffusing into the semiconductor layer 113. Therefore, the transistor 50 can have favorable electrical characteristics and high reliability.

[0417] In the transistor 50, a region of the semiconductor layer 113 in contact with the insulating layer 103 can function as a channel formation region. That is, oxygen is selectively supplied to the channel formation region, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, the transistor 50 can have favorable electrical characteristics and high reliability.

[0418] [Conductive Layer 111, Conductive Layer 112, and Conductive Layer 115] The conductive layers 111 and 112 functioning as source and drain electrodes, and the conductive layer 115 functioning as a gate electrode can be formed using one or more of chromium, copper, aluminum, magnesium, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or an alloy containing one or more of the above metals. The conductive layers 111, 112, and 115 can be formed using a low-resistance conductive material containing one or more of copper, silver, gold, and aluminum. Copper and aluminum are particularly preferred because of their excellent mass productivity.

[0419] A metal oxide (also referred to as an oxide conductor) can be used for the conductive layer 111, the conductive layer 112, and the conductive layer 115. Examples of the oxide conductor (OC) include In—Sn oxide (ITO), In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Zn oxide, In—Sn—Si oxide (ITSO), and In—Ga—Zn oxide.

[0420] Here, oxide conductors (OC) will be explained. For example, when oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes more conductive and becomes an electric conductor. A metal oxide that has become an electric conductor can be called an oxide conductor.

[0421] The conductive layers 111, 112, and 115 may each have a stacked structure of a conductive layer containing the oxide conductor (metal oxide) and a conductive layer containing a metal or an alloy. By using a conductive layer containing a metal or an alloy, wiring resistance can be reduced.

[0422] A Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be used for the conductive layer 111, the conductive layer 112, and the conductive layer 115. By using a Cu-X alloy, processing can be performed by a wet etching process, which makes it possible to reduce manufacturing costs.

[0423] Note that the conductive layers 111, 112, and 115 may be formed using the same material or different materials.

[0424] Here, the conductive layer 111 and the conductive layer 112 will be specifically described using an example in which a metal oxide is used for the semiconductor layer 113 .

[0425] When an oxide semiconductor is used for the semiconductor layer 113, the conductive layers 111 and 112 are oxidized by oxygen contained in the semiconductor layer 113, which may increase the resistance. The conductive layers 111 and 112 are oxidized by oxygen contained in the insulating layer 103a, which may increase the resistance. Furthermore, the conductive layers 111 and 112 are oxidized by oxygen contained in the semiconductor layer 113, which may increase the oxygen vacancy (V Ｏ When the conductive layers 111 and 112 are oxidized by oxygen contained in the insulating layer 103a, the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 may decrease.

[0426] The conductive layers 111 and 112 are preferably made of a material that is resistant to oxidation. The conductive layers 111 and 112 are preferably made of an oxide conductor. For example, In—Sn oxide (ITO) or In—Sn—Si oxide (ITSO) can be suitably used. The conductive layers 111 and 112 may each be made of a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layers 111 and 112 may have a stacked structure of the above-mentioned materials.

[0427] By using a material that is difficult to oxidize for the conductive layer 111 and the conductive layer 112, it is possible to prevent the conductive layer 111 and the conductive layer 112 from being oxidized by oxygen contained in the semiconductor layer 113 or oxygen contained in the insulating layer 103a, which can prevent the resistance from increasing. Ｏ ) in the semiconductor layer 113 can be suppressed, and the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 can be increased. Ｏ ) and V ＯH can be reduced. Therefore, the transistor 50 can have favorable electrical characteristics and high reliability. Note that the conductive layers 111 and 112 may be made of the same material or different materials.

[0428] [Insulating Layer 105] The insulating layer 105 functioning as a gate insulating layer preferably has a low defect density. A low defect density in the insulating layer 105 enables the transistor to exhibit favorable electrical characteristics. Furthermore, the insulating layer 105 preferably has a high withstand voltage. A high withstand voltage of the insulating layer 105 enables the transistor 50 to have high reliability.

[0429] The insulating layer 105 can be formed using, for example, one or more of an oxide, an oxynitride, a nitride oxide, and a nitride having insulating properties. The insulating layer 105 can be formed using, for example, one or more of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide. The insulating layer 105 can be formed as a single layer or a stacked layer. The insulating layer 105 can have, for example, a stacked structure of an oxide and a nitride.

[0430] In a miniaturized transistor, a thin gate insulating layer may result in a large leakage current. By using a material with a high relative dielectric constant (also referred to as a high-k material) for the gate insulating layer, a low voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0431] The insulating layer 105 preferably releases little impurities (for example, water and hydrogen) from itself. The small amount of impurities released from the insulating layer 105 suppresses the impurities from diffusing into the semiconductor layer 113. Therefore, the transistor 50 can have favorable electrical characteristics and high reliability.

[0432] Since the insulating layer 105 is formed over the semiconductor layer 113, it is preferable that the insulating layer 105 be formed under conditions that cause little damage to the semiconductor layer 113. For example, it is preferable that the insulating layer 105 be formed under conditions that cause a sufficiently slow deposition rate, specifically, under conditions that cause a slower deposition rate than that of the insulating layer 103b. For example, when the insulating layer 105 is formed by a PECVD method, damage to the semiconductor layer 113 can be reduced by forming the insulating layer 105 under low power conditions.

[0433] Here, the insulating layer 105 will be specifically described using an example in which a metal oxide is used for the semiconductor layer 113 .

[0434] In order to improve the interface characteristics with the semiconductor layer 113, it is preferable to use an oxide for the insulating layer 105. For example, one or more of silicon oxide and silicon oxynitride can be suitably used for the insulating layer 105. It is more preferable to use a film that releases oxygen by heating for the insulating layer 105.

[0435] Note that the insulating layer 105 may have a stacked structure. The insulating layer 105 can have a stacked structure of an oxide film on a side in contact with the semiconductor layer 113 and a nitride film on a side in contact with the conductive layer 115. For example, one or more of silicon oxide and silicon oxynitride can be preferably used as the oxide film. For the nitride film, silicon nitride can be preferably used. When the insulating layer 105 has a stacked structure, it is preferable to use an oxide on at least the side of the insulating layer 105 in contact with the semiconductor layer 113 because the interface characteristics with the semiconductor layer 113 can be improved.

[0436] [Substrate 101] For example, there are no significant limitations on the material of the substrate 101, but it must have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate may be used as the substrate 101. Furthermore, any of these substrates on which semiconductor elements are provided may also be used as the substrate 101. Furthermore, a printed circuit board may also be used as the substrate 101. The shape of the semiconductor substrate and the insulating substrate may be circular or rectangular.

[0437] A flexible substrate may be used as the substrate 101, and the transistor 50, for example, may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 101 and the transistor 50, etc. The peeling layer can be used to separate a display device, after a part or the whole of the display device is completed thereon, from the substrate 101 and transfer the display device to another substrate. In this case, for example, the transistor 50 can be transferred to a substrate with poor heat resistance or a flexible substrate.

[0438] [Insulating Layer 218] The insulating layer 218 is preferably made of a material that does not easily diffuse impurities. Thus, the insulating layer 218 functions as a blocking layer that prevents impurities from diffusing from the outside into the transistor. Examples of impurities include water and hydrogen. Providing the insulating layer 218 can improve the reliability of the display device.

[0439] The insulating layer 218 can be an insulating layer containing an inorganic material or an insulating layer containing an organic material. For example, an inorganic material such as an oxide or a nitride can be suitably used for the insulating layer 218. More specifically, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. For example, silicon nitride oxide is suitable for use as the insulating layer 218 because it emits little impurities (e.g., water and hydrogen) from itself and can function as a blocking layer that suppresses impurity diffusion from above the transistor to the transistor. For example, one or more of an acrylic resin and a polyimide resin can be used as the organic material. A photosensitive material may be used as the organic material. Two or more of the above insulating films may be stacked. The insulating layer 218 may have a stacked structure of an insulating layer containing an inorganic material and an insulating layer containing an organic material.

[0440] [Insulating Layer 235] The insulating layer 235 has a function of reducing unevenness caused by the transistor 51, the transistor 52, the capacitor 57, and the like. In this specification and the like, the insulating layer 235 may be referred to as a planarizing layer.

[0441] An insulating layer containing an organic material can be suitably used for the insulating layer 235. As the organic material, a photosensitive organic resin is preferably used, and for example, a photosensitive resin composition containing an acrylic resin is preferably used. Note that in this specification and the like, the term "acrylic resin" does not refer only to polymethacrylic acid ester or methacrylic resin, but may refer to all acrylic polymers in a broad sense.

[0442] The insulating layer 235 may be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, or precursors of these resins. The insulating layer 235 may also be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin. A photoresist may also be used as the photosensitive resin. Either a positive-type material or a negative-type material may be used as the photosensitive organic resin.

[0443] The insulating layer 235 may have a laminated structure of an organic insulating layer and an inorganic insulating layer. For example, the insulating layer 235 may have a laminated structure of an organic insulating layer and an inorganic insulating layer on the organic insulating layer. By providing an inorganic insulating layer on the outermost surface of the insulating layer 235, the inorganic insulating layer can function as an etching protection layer. This prevents a portion of the insulating layer 235 from being etched when the pixel electrode 311 is formed, thereby preventing the insulating layer 235 from becoming less flat.

[0444] If the top surface of the insulating layer 235, on which the light-emitting element 60 is formed, is not flat, for example, a connection failure due to a step disconnection of the common electrode 315 may occur. Furthermore, if the top surface of the insulating layer 235 is not flat, the film thickness of the common electrode 315 may become locally thin, resulting in an increase in electrical resistance. Furthermore, if the top surface of the insulating layer 235 is not flat, the processing accuracy of layers formed on the insulating layer 235 may decrease. By flattening the top surface of the insulating layer 235, for example, the processing accuracy of the light-emitting element 60 provided on the insulating layer 235 can be improved, thereby realizing a display device with high resolution. Furthermore, it is possible to suppress the occurrence of a connection failure due to a step disconnection of the common electrode 315 and the increase in electrical resistance due to a local thinning of the film thickness of the common electrode 315, thereby realizing a display device with high display quality.

[0445] Note that a part of the insulating layer 235 may be removed when forming the pixel electrode 311. The insulating layer 235 may have a recess in a region that does not overlap with the pixel electrode 311.

[0446] [Pixel Electrode 311 and Common Electrode 315] A material highly transparent to visible light can be used for one or both of the pixel electrode 311 and the common electrode 315. Alternatively, a material that reflects visible light can be used for one of the pixel electrode 311 and the common electrode 315, and a material highly transparent to visible light can be used for the other of the pixel electrode 311 and the common electrode 315. Examples of materials that can be used for the pixel electrode 311 and the common electrode 315 include metals, alloys, electrically conductive compounds, and mixtures thereof. Specific examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys containing appropriate combinations of these metals. Examples of the material include indium tin oxide (In—Sn oxide, also referred to as ITO), In—Si—Sn oxide (also referred to as ITSO), indium zinc oxide (In—Zn oxide), and In—W—Zn oxide. Examples of the material include aluminum alloys (aluminum alloys) such as an alloy of aluminum, nickel, and lanthanum (Al—Ni—La), and silver alloys such as an alloy of silver and magnesium and an alloy of silver, palladium, and copper (Ag—Pd—Cu, also referred to as APC). Other examples of the material include elements belonging to Group 1 or Group 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium), rare earth metals such as europium and ytterbium, and alloys containing appropriate combinations of these elements, as well as graphene.

[0447] [Insulating Layer 237] The insulating layer 237 can be an insulating layer containing an organic material, and for example, a material that can be used for the insulating layer 235 can be used. The insulating layer 237 can also be an insulating layer containing an inorganic material, and for example, a material that can be used for the insulating layer 218 can be used. Furthermore, the insulating layer 237 may have a stacked structure of an insulating layer containing an inorganic material and an insulating layer containing an organic material.

[0448] [Protective Layer 331] The protective layer 331 may have a single-layer structure or a stacked structure of two or more layers. The conductivity of the protective layer 331 does not matter. The protective layer 331 can be made of at least one of an insulating film, a semiconductor film, and a conductive film.

[0449] The protective layer 331 having an inorganic film can prevent the common electrode 315 from being oxidized and prevent impurities (such as moisture and oxygen) from entering the light-emitting element 60. This prevents deterioration of the light-emitting element 60 and improves the reliability of the display device.

[0450] The protective layer 331 can be an insulating layer containing an inorganic material. For example, an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used for the protective layer 331. The protective layer 331 may have a single-layer structure or a stacked-layer structure. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film and an aluminum oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. In particular, the protective layer 331 preferably includes a nitride insulating film or a nitride oxide insulating film, and more preferably includes a nitride insulating film.

[0451] The protective layer 331 may be an inorganic film containing In—Sn oxide (ITO), In—Zn oxide, Ga—Zn oxide, Al—Zn oxide, In—Ga—Zn oxide (IGZO), or the like. The inorganic film preferably has high resistance, specifically, preferably has higher resistance than the common electrode 315. The inorganic film may further contain nitrogen.

[0452] When light emitted from the light-emitting element 60 is extracted through the protective layer 331, it is preferable that the protective layer 331 has high transparency to visible light. For example, ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.

[0453] For example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a stacked structure of an aluminum oxide film and an IGZO film on the aluminum oxide film, can be used for the protective layer 331. By using such a stacked structure, impurities (water, oxygen, etc.) can be prevented from entering the EL layer side.

[0454] The protective layer 331 may be made of an organic material. For example, the protective layer 331 may be made of an acrylic resin, a polyimide resin, an epoxy resin, an imide resin, a polyamide resin, a polyimideamide resin, a silicone resin, a siloxane resin, a benzocyclobutene-based resin, a phenolic resin, or a precursor of any of these resins. The protective layer 331 may also be made of an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or an alcohol-soluble polyamide resin. The protective layer 331 may also contain both inorganic and organic materials.

[0455] The protective layer 331 may have a two-layer structure formed by using different film formation methods. Specifically, the first layer of the protective layer 331 may be formed by the ALD method, and the second layer of the protective layer 331 may be formed by the sputtering method.

[0456] [Substrate 152] The substrate 152 can be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting element 60 is extracted. Furthermore, using a flexible material for the substrate 152 can increase the flexibility of the display device. A polarizing plate may also be used as the substrate 152. Furthermore, a lamination film or a base film may also be used as the substrate 152.

[0457] The substrate 152 may be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, or the like), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, or the like. The substrate 152 may also be made of glass having a thickness sufficient to provide flexibility.

[0458] When a film is used as a substrate, the film may absorb water, which may cause changes in shape, such as wrinkles, in the display device. Therefore, it is preferable to use a film with low water absorption for the substrate. For example, it is preferable to use a film with a water absorption rate of 1% or less, more preferably 0.1% or less, and even more preferably 0.01% or less.

[0459] Various optical members can be disposed on the outside of the substrate 152. Examples of optical members include a polarizing plate (e.g., a circular polarizing plate), a retardation plate, a light diffusion layer (e.g., a diffusion film), an anti-reflection layer, and a light-collecting film. In addition, a surface protection layer such as an anti-static film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, or an impact absorbing layer may be disposed on the outside of the substrate 152. For example, a glass layer or a silica layer (SiO ｘ The surface protection layer can be preferably formed of a material such as DLC (diamond-like carbon), aluminum oxide (AlO ｘ ), polyester-based materials, polycarbonate-based materials, etc. may be used for the surface protection layer. It is preferable to use a material with high transmittance to visible light for the surface protection layer. It is also preferable to use a material with high hardness for the surface protection layer.

[0460] When a circularly polarizing plate is superimposed on a display device, it is preferable to use a substrate with high optical isotropy as the substrate of the display device. A substrate with high optical isotropy can also be said to have small birefringence (small amount of birefringence).

[0461] The absolute value of the retardation (phase difference) of a substrate having high optical isotropy is preferably 30 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less.

[0462] Examples of films with high optical isotropy include triacetyl cellulose (TAC, also called cellulose triacetate) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic films.

[0463] [Adhesive Layer 142] Various curable adhesives can be used for the adhesive layer 142, such as photo-curable adhesives such as ultraviolet curable adhesives, reactive curable adhesives, thermosetting adhesives, or anaerobic adhesives. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Materials with low moisture permeability, such as epoxy resin, are particularly preferred. Two-component resins may also be used. Alternatively, an adhesive sheet may be used, for example.

[0464] [Light-shielding layer 317] Examples of materials that can be used for the light-shielding layer 317 include carbon black, titanium black, metals, metal oxides, and composite oxides including solid solutions of multiple metal oxides. The light-shielding layer 317 can also be configured by stacking multiple layers containing the materials of the colored layers. For example, the light-shielding layer 317 can have a stacked structure of a layer containing the material used for a colored layer that transmits light of a certain color and a layer containing the material used for a colored layer that transmits light of another color.

[0465] The above is a description of the components.

[0466] <Circuit Configuration Examples> Circuits to which one embodiment of the present invention can be applied, other than those having the configurations shown in FIGS. 1C, 1D, and 2B, will be described below.

[0467] 105A, 105B, and 105C are circuit diagrams showing an example configuration of the sub-pixel 23 included in the pixel 21 shown in Fig. 2A. The sub-pixel 23 shown in Fig. 105A includes a pixel circuit 40D and a light-emitting element 60. The pixel circuit 40D has a configuration in which a transistor 54 and a capacitor 58 are added to the pixel circuit 40C. The pixel circuit 40D is a 4Tr2C type pixel circuit.

[0468] In the pixel circuit 40D, one of the source and the drain of the transistor 52 is electrically connected to one of the source and the drain of the transistor 54. The other of the source and the drain of the transistor 54 is electrically connected to a wiring 45. The gate of the transistor 54 is electrically connected to a wiring 41c. One electrode of the capacitor 58 is electrically connected to the other of the source and the drain of the transistor 52, one of the source and the drain of the transistor 53, the other electrode of the capacitor 57, and one electrode of the light-emitting element 60.

[0469] The wiring 41c is electrically connected to the scanning line driving circuit 11. In other words, when the sub-pixel 23 of the pixel 21 has the configuration shown in FIG. 105A, the wiring 41 includes wirings 41a, 41b, and 41c in the display device 10.

[0470] The transistor 54 functions as a switch and controls conduction and non-conduction between the wiring 45 and one of the source and the drain of the transistor 52 based on the potential of the wiring 41c.

[0471] By turning on the transistor 54, a current having a magnitude corresponding to the gate potential of the transistor 52 flows, for example, from the wiring 45 to the wiring 47. This causes the light-emitting element 60 to emit light with a luminance corresponding to the gate potential of the transistor 52. On the other hand, by turning off the transistor 54, no current flows through the light-emitting element 60, and therefore the light-emitting element 60 does not emit light.

[0472] An OS transistor is preferably used as the transistor 54. As described above, an OS transistor has higher field-effect mobility than, for example, a transistor using amorphous silicon. Therefore, by using an OS transistor as the transistor 54, the display device 10 can be driven at high speed.

[0473] 105B includes a pixel circuit 40E and a light-emitting element 60. The pixel circuit 40E has a configuration in which a transistor 54 is added to the pixel circuit 40C. The pixel circuit 40E is a 4Tr1C type pixel circuit.

[0474] In the pixel circuit 40E, one of the source and the drain of the transistor 54 is electrically connected to the other of the source and the drain of the transistor 51, the gate of the transistor 52, and one electrode of the capacitor 57. The other of the source and the drain of the transistor 54 is electrically connected to a wiring 49. The gate of the transistor 54 is electrically connected to a wiring 41c. When the subpixel 23 has the structure shown in FIG. 105B , wirings 41a, 41b, and 41c are provided as the wiring 41 in the display device 10.

[0475] By turning on the transistor 54, the gate potential of the transistor 52 can be set to the potential of the wiring 49. Here, for example, a low potential can be supplied to the wiring 49. As a result, for example, no current flows through the light-emitting element 60, and the light-emitting element 60 does not emit light.

[0476] The sub-pixel 23 shown in FIG. 105C includes a pixel circuit 40F and a light-emitting element 60.

[0477] The pixel circuit 40F includes a transistor 61, a transistor 62, a transistor 63, a transistor 64, a transistor 65, a transistor 66, a capacitor 67, and a capacitor 68. That is, the pixel circuit 40F is a 6Tr2C type pixel circuit.

[0478] In the pixel circuit 40F, one of the source and the drain of the transistor 61 is electrically connected to a wiring 45. The other of the source and the drain of the transistor 61 is electrically connected to one of the source and the drain of the transistor 62. The one of the source and the drain of the transistor 62 is electrically connected to one of the source and the drain of the transistor 63. The gate of the transistor 61 is electrically connected to a wiring 41d.

[0479] The other of the source and the drain of the transistor 62 is electrically connected to the gate of the transistor 63. The gate of the transistor 63 is electrically connected to one electrode of the capacitor 67. The gate of the transistor 62 is electrically connected to the wiring 41e.

[0480] One of the source and the drain of the transistor 64 is electrically connected to the wiring 43. The other of the source and the drain of the transistor 64 is electrically connected to the other of the source and the drain of the transistor 63. The other of the source and the drain of the transistor 63 is electrically connected to the one of the source and the drain of the transistor 65. The gate of the transistor 64 is electrically connected to the wiring 41f.

[0481] The other of the source and the drain of the transistor 65 is electrically connected to one of the source and the drain of the transistor 66. The other of the source and the drain of the transistor 66 is electrically connected to the other electrode of the capacitor 67. The other electrode of the capacitor 67 is electrically connected to one electrode of the capacitor 68. One electrode of the capacitor 68 is electrically connected to one electrode of the light-emitting element 60. The gate of the transistor 65 is electrically connected to a wiring 41g.

[0482] The other of the source and the drain of the transistor 66 is electrically connected to the wiring 48. The gate of the transistor 66 is electrically connected to the wiring 41e.

[0483] The other electrode of the capacitor 68 is electrically connected to the wiring 41 f. The other electrode of the light emitting element 60 is electrically connected to the wiring 47 .

[0484] The wiring 41d, the wiring 41e, the wiring 41f, and the wiring 41g are electrically connected to the scanning line driving circuit 11. That is, when the subpixel 23 of the pixel 21 has the configuration shown in Fig. 105C, the wiring 41d, the wiring 41e, the wiring 41f, and the wiring 41g are provided in the display device 10.

[0485] The transistors 61, 62, 64, 65, and 66 function as switches. The transistor 61 controls conduction and non-conduction between the wiring 45 and one of the source or drain of the transistor 62 and one of the source or drain of the transistor 63, based on the potential of the wiring 41d. The transistor 62 controls conduction and non-conduction between the other of the source or drain of the transistor 61, one of the source or drain of the transistor 63, the gate of the transistor 63, and one electrode of the capacitor 67, based on the potential of the wiring 41e. The transistor 64 controls conduction and non-conduction between the wiring 43, the other of the source or drain of the transistor 63, and one of the source or drain of the transistor 65, based on the potential of the wiring 41f. The transistor 65 has a function of controlling, based on the potential of the wiring 41g, electrical continuity and non-conduction between the other of the source or the drain of the transistor 63 and the other of the source or the drain of the transistor 64 and one electrode of the light-emitting element 60. The transistor 66 has a function of controlling, based on the potential of the wiring 41e, electrical continuity and non-conduction between the wiring 48 and one electrode of the light-emitting element 60.

[0486] OS transistors are preferably used as the transistors 61 to 66. OS transistors have higher field-effect mobility than, for example, transistors using amorphous silicon. Therefore, by using OS transistors as the transistors 61 to 66, the display device 10 can be driven at high speed.

[0487] [Memory Cell] One embodiment of the present invention can be applied not only to a display device but also to a memory device. FIG. 106A is a block diagram showing a configuration example of a memory device 70 to which one embodiment of the present invention can be applied. The memory device 70 includes a memory portion 80, a word line driver circuit 71, a bit line driver circuit 73, and a power supply circuit 75. The memory portion 80 includes a plurality of memory cells 81 arranged in a matrix. Note that the power supply circuit 75 may be provided outside the memory device 70.

[0488] The word line driving circuit 71 is electrically connected to the memory cells 81 via the wiring 41. For example, similar to the display device 10 shown in FIG. 1A, the wiring 41 extends in the row direction of the matrix. In the memory device 70, the wiring 41 functions as a word line.

[0489] The bit line driving circuit 73 is electrically connected to the memory cells 81 via the wiring 43. For example, similar to the display device 10 shown in FIG. 1A, the wiring 43 extends in the column direction of the matrix. In the memory device 70, the wiring 41 functions as a bit line.

[0490] The power supply circuit 75 is electrically connected to the memory cells 81 via the wiring 45. For example, all the memory cells 81 can be electrically connected to the power supply circuit 75 via the same wiring 45. The wiring 45 functions as a power supply line.

[0491] The word line driver circuit 71 has a function of selecting, for each row, a memory cell 81 to which data is to be written. The word line driver circuit 71 also has a function of selecting, for each row, a memory cell 81 from which data is to be read. Specifically, the word line driver circuit 71 can select a memory cell 81 to which data is to be written or a memory cell 81 from which data is to be read by outputting a signal to the wiring 41.

[0492] The bit line driver circuit 73 has a function of writing data to the memory cell 81 selected by the word line driver circuit 71 via the wiring 43. The bit line driver circuit 73 also has a function of amplifying the data output from the memory cell 81 to the wiring 43 and outputting the amplified data to, for example, the outside of the memory device 70, thereby reading out the data held in the memory cell 81. The bit line driver circuit 73 also has a function of precharging the wiring 43 before reading out data from the memory cell 81.

[0493] The power supply circuit 75 has a function of generating a power supply potential and supplying it to the wiring 45. The power supply circuit 75 has a function of generating, for example, a high potential or a low potential and supplying it to the wiring 45.

[0494] 106B, 106C, 106D, 106E, and 106F are circuit diagrams showing configuration examples of memory cells 81. Here, the memory cells 81 shown in Figures 106B, 106C, 106D, 106E, and 106F are respectively referred to as memory cell 81A, memory cell 81B, memory cell 81C, memory cell 81D, and memory cell 81E.

[0495] The memory cell 81A includes a transistor 51 and a capacitor 57. That is, the memory cell 81A is a 1Tr1C type memory cell.

[0496] In the memory cell 81A, one of the source and the drain of the transistor 51 is electrically connected to the wiring 43. The other of the source and the drain of the transistor 51 is electrically connected to one electrode of the capacitor 57. The gate of the transistor 51 is electrically connected to the wiring 41. The other electrode of the capacitor 57 is electrically connected to the wiring 45.

[0497] In the memory cell 81A, data is written to the memory cell 81A through the wiring 43 by turning on the transistor 51, and the written data is held by turning off the transistor 51. Furthermore, by turning on the transistor 51, the data held in the memory cell 81A can be output to the wiring 43, and the bit line driver circuit 73 can read the data.

[0498] The memory cell 81B includes a transistor 51, a transistor 52, and a capacitor 57. That is, the memory cell 81B is a 2Tr1C type memory cell.

[0499] The memory cell 81B is electrically connected to wirings 41a and 41h as wirings 41, and to wirings 43a and 43b as wirings 43. Specifically, one of the source or drain of the transistor 51 is electrically connected to the wiring 43a. The other of the source or drain of the transistor 51 is electrically connected to one electrode of a capacitor 57. One electrode of the capacitor 57 is electrically connected to the gate of the transistor 52. The gate of the transistor 51 is electrically connected to the wiring 41a. The other electrode of the capacitor 57 is electrically connected to the wiring 41h. One of the source or drain of the transistor 52 is electrically connected to the wiring 43b. The other of the source or drain of the transistor 52 is electrically connected to the wiring 45.

[0500] In the memory cell 81B, data is written to the memory cell 81B through the wiring 43a by turning on the transistor 51, and the written data is retained by turning off the transistor 51. Therefore, in the memory cell 81B, the wiring 41a can be referred to as a write word line, and the wiring 43a can be referred to as a write bit line. Furthermore, by controlling the potential of the wiring 41h, the gate potential of the transistor 52 can be changed by capacitive coupling, and the potential of the wiring 43b can be set to a potential corresponding to the data retained in the memory cell 81B. This allows the bit line driver circuit 73 to read the data retained in the memory cell 81B. Therefore, in the memory cell 81B, the wiring 41h can be referred to as a read word line, and the wiring 43b can be referred to as a read bit line.

[0501] The memory cell 81C is a modified example of the memory cell 81B, and shows an example in which the other of the source and the drain of the transistor 52 is electrically connected to the wiring 41h, and the other electrode of the capacitor 57 is electrically connected to the wiring 45. The word line driver circuit 71 controls the potential of the other of the source and the drain of the transistor 52, so that the memory cell 81C can output data held in the memory cell 81C to the wiring 43b.

[0502] The memory cell 81D is a modified example of the memory cell 81C, and differs from the memory cell 81C in that it includes a transistor 53. The memory cell 81D is a 3Tr1C type memory cell.

[0503] The memory cell 81D is electrically connected to wirings 41a and 41b as wirings 41. Specifically, the gate of the transistor 53 is electrically connected to the wiring 41b. One of the source and the drain of the transistor 52 is electrically connected to the source and the drain of the transistor 53. The other of the source and the drain of the transistor 52 is electrically connected to the wiring 45. The other of the source and the drain of the transistor 53 is electrically connected to the wiring 43b.

[0504] The transistor 53 functions as a switch and controls the conduction or non-conduction state between the wiring 43b and one of the source and drain of the transistor 52 based on the potential of the wiring 41b. By turning on the transistor 53, the potential of the wiring 43b can be set to a potential corresponding to the data stored in the memory cell 81D. This allows the bit line driver circuit 73 to read the data stored in the memory cell 81D. As described above, in the memory cell 81D, the wiring 41b can be considered a read word line.

[0505] The memory cell 81E is a modification of the memory cell 81D and differs from the memory cell 81D in that it does not include the capacitor 57. In the memory cell 81E, the wiring 45 is electrically connected to the other of the source and the drain of the transistor 52.

[0506] For example, if the parasitic capacitance of the gate capacitance of the transistor 52 is sufficiently large, data can be held in the memory cell without providing the capacitor 57 .

[0507] An OS transistor is preferably used as the transistor 51 included in the memory cells 81A to 81E. As described above, an OS transistor has an extremely low off-state current. Therefore, by using an OS transistor as the transistor 51, the charge stored in the capacitor 57 can be held for a long period of ...

Claims

1. The device comprises a pixel having a first transistor, a second transistor, a capacitor, and a light-emitting element. Either the source or the drain of the first transistor is electrically connected to the first wiring. The gate of the first transistor is electrically connected to the second wiring. The source or drain of the first transistor, the other of which is electrically connected to the gate of the second transistor, The first electrode of the capacitance is electrically connected to the gate of the second transistor. The source or drain of the second transistor is electrically connected to the light-emitting element. The source or drain of the second transistor, the other of which is electrically connected to the third wiring, The second electrode of the capacitance is electrically connected to the light-emitting element in a display device, It comprises a first conductive layer, a second conductive layer, a first insulating layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a first semiconductor layer, a second semiconductor layer, a second insulating layer, a sixth conductive layer, and a seventh conductive layer. The first conductive layer has the function of being either the source electrode or the drain electrode of the first transistor, and the function of being the first wiring. The second conductive layer functions as either the source electrode or the drain electrode of the second transistor. The first insulating layer has a region located above the first conductive layer, a region located above the second conductive layer, a first opening reaching the first conductive layer, a second opening reaching the second conductive layer, and a third opening reaching the second conductive layer. The third conductive layer has a region positioned above the first insulating layer and a fourth opening that overlaps with the first opening. The third conductive layer functions as the other of the source electrode or drain electrode of the first transistor. The fourth conductive layer has a region positioned above the first insulating layer and a fifth opening that overlaps with the second opening. The fourth conductive layer has the function of being the other of the source electrode or drain electrode of the second transistor, and the function of being the third wiring. The fifth conductive layer has a region positioned above the first insulating layer and a region in contact with the second conductive layer at the third opening. The fifth conductive layer functions as the second electrode of the capacitance, The first semiconductor layer has a region that is in contact with the first conductive layer at the first opening, It has a region located inside the first opening and a region in the third conductive layer that is in contact with the side surface of the fourth opening, The first semiconductor layer has a channel formation region for the first transistor, The second semiconductor layer has a region that is in contact with the second conductive layer at the second opening, It has a region located inside the second opening and a region in the fourth conductive layer that is in contact with the side surface of the fifth opening, The second semiconductor layer has a channel formation region for the second transistor. The second insulating layer has a region located above the first insulating layer, a region located above the third conductive layer, a region located above the first semiconductor layer, a region located above the fifth conductive layer, a region located above the fourth conductive layer, a region located above the second semiconductor layer, and a sixth opening that reaches the third conductive layer. The sixth conductive layer has a region disposed inside the first opening, a region that overlaps with the first conductive layer via the first insulating layer and the second insulating layer, and a region that overlaps with the fourth conductive layer via the second insulating layer without passing through the first insulating layer. The sixth conductive layer has the function of being the gate electrode of the first transistor and the function of being the second wiring. The seventh conductive layer has a region in contact with the third conductive layer at the sixth opening, a region located inside the second opening, and a region that overlaps with the fifth conductive layer via the second insulating layer without passing through the first insulating layer. The seventh conductive layer has the function of being the gate electrode of the second transistor and the function of being the first electrode of the capacitor. In a plan view of the pixel, the first wiring is arranged to extend along the first direction. In the plan view, the second wiring is arranged to extend along a second direction intersecting the first direction. In the plan view, the third wiring is arranged to extend along the first direction, in a display device.

2. In claim 1, The first semiconductor layer and the second semiconductor layer are a display device having a metal oxide.

3. In claim 1, The first semiconductor layer and the second semiconductor layer are indium oxide in the display device.