Semiconductor device and method for producing semiconductor device

Abstract

The present invention provides a semiconductor device that comprises: an insulating first film which is formed along the side wall of an element isolation trench, and which has a first portion that is formed along the bottom wall and the side wall of the element isolation trench and a second portion that is led out from the first portion along the bottom wall and has an opening through which the bottom wall is exposed; a second film which contains a material that has an etching selectivity with respect to the first film, and which is formed along the upper surface region of the second portion and the first portion of the first film; and a conductive buried body that is buried in the element isolation trench.

Description

Semiconductor device and method for manufacturing the same Related Applications

[0001] This application corresponds to Patent Application No. 2022-154064 filed with the Japan Patent Office on September 27, 2022, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

[0003] For example, Patent Document 1 discloses a semiconductor device including a semiconductor layer, an element isolation portion formed in the semiconductor layer and partitioning an element region in the semiconductor layer, and a first contact formed in a line shape along the element isolation portion in a planar view and electrically connected to the element isolation portion.

[0004] International Publication No. 2021 / 182225

[0005] An embodiment of the present disclosure provides a semiconductor device that suppresses a decrease in breakdown voltage on the sidewall of an isolation trench.

[0006] A semiconductor device according to one embodiment of the present disclosure includes: a chip having a main surface; an isolation trench having sidewalls and a bottom wall, which defines an element region on the main surface side of the chip; an insulating first film formed along the sidewall of the isolation trench, the first film having a first portion formed from the bottom wall of the element isolation trench along the sidewall; and a second portion extending from the first portion along the bottom wall of the element isolation trench and having an opening that exposes the bottom wall of the element isolation trench; a second film containing a material having an etching selectivity with respect to the first film, the second film being formed from an upper surface region of the second portion of the first film along the first portion; and a conductive filling body embedded in the element isolation trench.

[0007] According to the semiconductor device according to the embodiment of the present disclosure, it is possible to suppress a decrease in breakdown voltage on the sidewall of the element isolation trench.

[0008] FIG. 1 is a schematic perspective view of a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a schematic plan view of the semiconductor device showing the first element region of FIG. 1. FIG. 3 is a cross-sectional view showing a cross section taken along III-III in FIG. 2. FIG. 4 is a cross-sectional view showing a cross section taken along IV-IV in FIG. 2. FIG. 5 is an enlarged view of a main portion of the element isolation portion (first embodiment) of FIGS. 3 and 4, illustrating a first shape of the element isolation film. FIG. 6 is an enlarged view of a portion surrounded by dashed line VI in FIG. 5. FIG. 7 is a view illustrating a modified example of the element isolation film of FIG. 6. FIG. 8 is an enlarged view of a main portion of the element isolation portion of FIGS. 3 and 4, illustrating a second shape of the element isolation film. FIG. 9 is an enlarged view of a portion surrounded by dashed line IX in FIG. 8. FIG. 10 is a view illustrating a modified example of the second protrusion of FIG. 9. FIG. 11 is an enlarged view of a main portion of the element isolation portion of FIGS. 3 and 4, illustrating a third shape of the element isolation film. FIG. 12A is a view illustrating a process related to the formation of the element isolation portion according to the first embodiment. FIG. 12B is a diagram showing a step subsequent to FIG. 12A. FIG. 12C is a diagram showing a step subsequent to FIG. 12B. FIG. 12D is a diagram showing a step subsequent to FIG. 12C. FIG. 12E is a diagram showing a step subsequent to FIG. 12D. FIG. 12F is a diagram showing a step subsequent to FIG. 12E. FIG. 12G is a diagram showing a step subsequent to FIG. 12F. FIG. 12H is a diagram showing a step subsequent to FIG. 12G. FIG. 13 is an enlarged view of a main part of an element isolation portion according to a second embodiment of the semiconductor device. FIG. 14A is a diagram showing a step related to the formation of an element isolation portion according to the second embodiment. FIG. 14B is a diagram showing a step subsequent to FIG. 14A. FIG. 14C is a diagram showing a step subsequent to FIG. 14B. FIG. 14D is a diagram showing a step subsequent to FIG. 14C. FIG. 14E is a diagram showing a step subsequent to FIG. 14D. FIG. 14F is a diagram showing a step subsequent to FIG. 14E. FIG. 14G is a diagram showing a step subsequent to FIG. 14F. FIG. 14H is a diagram showing a step subsequent to FIG. 14G.

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0010] <<Overall Configuration of Semiconductor Device 1>> FIG. 1 is a schematic perspective view of a semiconductor device 1 according to an embodiment of the present disclosure.

[0011] 1, the semiconductor device 1 includes, for example, a chip-shaped integrated circuit (IC) device. The semiconductor device 1 may be called an SSI (Small Scale IC), an MSI (Middle Scale IC), an LSI (Large Scale IC), a VLSI (Very Large Scale IC), or an ULSI (Ultra Large Scale IC) based on the number of circuit elements integrated therein.

[0012] The semiconductor device 1 has a plurality of element regions 2 and 3 in which circuit elements are formed. The element regions 2 and 3 are formed in a common semiconductor layer 5, which will be described later.

[0013] The multiple element regions 2, 3 include a first element region 2 and multiple second element regions 3. The first element region 2 may be an element region in which an LDMOS (Lateral Double-Diffused MOS) is formed as a circuit element. The multiple second element regions 3 may be regions in which other functional elements (e.g., protection diodes for the LDMOS, resistors, capacitors, etc.) are formed. Note that while four element regions 2, 3 are shown in FIG. 1, the semiconductor device 1 may have a greater number of element regions.

[0014] Fig. 2 is a schematic plan view of the semiconductor device 1 showing the first element region 2 of Fig. 1. Fig. 3 is a cross-sectional view showing the III-III cross section of Fig. 2. Fig. 4 is a cross-sectional view showing the IV-IV cross section of Fig. 2.

[0015] The semiconductor device 1 may include a semiconductor substrate 4, a semiconductor layer 5, a buried layer 6, an element isolation portion 7, a field insulating film 8, a body region 9, a source region 10, a body contact region 11, a drain region 12, a gate insulating film 13, a gate electrode 14, a first interlayer insulating film 15, a first wiring layer 16, a second interlayer insulating film 17, and a second wiring layer 18.

[0016] In this embodiment, the semiconductor substrate 4 is formed of a single crystal silicon (Si) substrate, but may be formed of other materials (for example, silicon carbide (SiC) or the like). ＋The semiconductor substrate 4 is, for example, 1×10 １９ cm －３ 5x10 or more ２１ cm －３ The semiconductor substrate 4 may have the following impurity concentrations: The thickness of the semiconductor substrate 4 before grinding may be, for example, 500 μm or more and 800 μm or less.

[0017] The semiconductor layer 5 is formed on the semiconductor substrate 4. The semiconductor layer 5 has an element main surface 19 and a bonding surface 20 facing the opposite side of the element main surface 19 in the thickness direction of the semiconductor layer 5. The element main surface 19 is the surface on which the element regions 2 and 3 are formed. On the other hand, the bonding surface 20 is the surface in contact with the semiconductor substrate 4.

[0018] The semiconductor layer 5 has a conductivity type opposite to that of the semiconductor substrate 4, and in this embodiment, － The semiconductor layer 5 is, for example, 5×10 １４ cm －３ 1x10 or more １７ cm －３ The semiconductor layer 5 may have an impurity concentration of 0.1 to 1.0 μm or less. The thickness of the semiconductor layer 5 may be, for example, 3 μm or more and 40 μm or less. The semiconductor layer 5 may be, for example, a layer formed by epitaxial growth on the semiconductor substrate 4, and in that case, may be referred to as an epitaxial layer. The semiconductor substrate 4 and the semiconductor layer 5 may be collectively referred to as a semiconductor chip.

[0019] 3 and 4 , the buried layer 6 may be formed in the middle of the semiconductor layer 5 in the thickness direction, or may be sandwiched between the semiconductor substrate 4 and the semiconductor layer 5. In this embodiment, the buried layer 6 spans a plurality of element regions 2 and 3 and is distributed at the same depth in the thickness direction of the semiconductor layer 5. The semiconductor layer 5 is also divided into upper and lower parts in the thickness direction by the buried layer 6. As a result, the semiconductor layer 5 may include an upper semiconductor layer 5A above the buried layer 6 (on the element main surface 19 side) and a lower semiconductor layer 5B below the buried layer 6 (on the junction surface 20 side). The upper semiconductor layer 5A may be thicker or thinner than the lower semiconductor layer 5B.

[0020] The buried layer 6 has the same conductivity type as the semiconductor layer 5, and in this embodiment, has a higher impurity concentration than the semiconductor layer 5. ＋ The thickness of buried layer 6 may be, for example, not less than 2 μm and not more than 3 μm.

[0021] In this embodiment, the element isolation portion 7 is formed in a closed ring shape and may include a trench 21, an element isolation film 22, and a first embedded body 23. The trench 21 is a trench that separates the element regions 2 and 3, and may therefore be referred to as an element isolation trench.

[0022] The trench 21 may be formed from the device main surface 19 of the semiconductor layer 5 through the buried layer 6 to reach the semiconductor substrate 4. The trench 21 may also have a bottom in the semiconductor substrate 4.

[0023] 2, the trench 21 may include a linear first portion 24 extending in a first direction A and a linear second portion 25 extending in a second direction B perpendicular to the first direction A. The term "linear" is not particularly limited as long as it is an elongated trench that separates the element regions 2 and 3, and may include a straight line as shown in FIG. 2 or a curved line.

[0024] Furthermore, in the semiconductor layer 5, a second element region 3, which is electrically floating like the first element region 2, is defined in a peripheral region of the first element region 2. The second element region 3 may be formed adjacent to the first element region 2 across the element isolation portion 7, or may be formed in a region separated from the first element region 2 by an element isolation structure (not shown) (for example, a trench structure similar to the element isolation portion 7). The first element region 2 may be a low-voltage element region that operates based on a low reference voltage of, for example, about 5 V or more and 100 V or less, or may be a high-voltage element region that operates based on a high reference voltage of, for example, about 400 V or more and 600 V or less.

[0025] The first filling body 23 is buried inside the device isolation film in the trench 21. The first filling body 23 may be buried from the bottom of the trench 21 to the device main surface 19 of the semiconductor layer 5. In this embodiment, the first filling body 23 may be formed of doped polysilicon.

[0026] Although specific edges of the field insulating film 8 are not shown in Fig. 2, the field insulating film 8 is formed in a band shape that describes a closed curve. Like the element isolation portion 7, the field insulating film 8 is formed in a quadrangular ring shape in plan view so as to surround the periphery of the first element region 2. Note that Fig. 2 schematically shows the range of the active region 30 that is surrounded by the field insulating film 8 and in which the MISFET is formed. In the first element region 2, the body region 9 is formed in a region other than the active region 30, but the region may be one in which the source region 10 and the body contact region 11 are not formed.

[0027] The field insulating film 8 may be, for example, a LOCOS film formed by selectively oxidizing the device main surface 19 of the semiconductor layer 5. The field insulating film 8 has a first opening 31 that exposes the body region 9 and the source region 10, and a second opening 32 that exposes the drain region 12.

[0028] The body region 9 is formed on the element main surface 19 of the semiconductor layer 5. The body region 9 is spaced inward from the peripheral edge of the first opening 31 in the field insulating film 8. The annular region sandwiched between the outer periphery of the body region 9 and the peripheral edge of the field insulating film 8 and formed by part of the semiconductor layer 5 is a semiconductor region 33 of the same conductivity type as the semiconductor layer 5.

[0029] The body region 9 is formed to extend in the first direction A. For example, the body region 9 may have an elongated shape along the first direction A. In this embodiment, the body region 9 is p － The body region 9 is a semiconductor region of the type having a capacitance of, for example, 1×10 １７ cm －３ 1x10 or more １８ cm －３3 and 4, the depth of body region 9 may be deeper than the bottom position of field insulating film 8, and may be, for example, 0.5 μm to 4.0 μm.

[0030] The source region 10 and the body contact region 11 are formed in an inner region of the body region 9 on the element main surface 19 of the semiconductor layer 5. The source region 10 and the body contact region 11 are spaced inward from the outer periphery of the body region 9 and have outer peripheries that run along the outer periphery of the body region 9. The region sandwiched between the outer periphery of the body region 9 and the outer periphery of the source region 10 and made up of the body region 9 is a channel region 34 in which a channel is formed when an appropriate voltage is applied to the gate electrode 14.

[0031] A plurality of source regions 10 and a plurality of body contact regions 11 are formed alternately along the first direction A. Adjacent source regions 10 and body contact regions 11 are in contact with each other.

[0032] In this embodiment, the source region 10 is ＋ The source region 10 is a semiconductor region of the type having a thickness of, for example, 1×10 １９ cm －３ 5x10 or more ２１ cm －３ The source region 10 has an impurity concentration of 0.2 μm or more and 1.0 μm or less. The depth of the source region 10 is shallower than that of the body region 9, and may be, for example, 0.2 μm or more and 1.0 μm or less. Therefore, in a cross-sectional view, the side and bottom of the source region 10 are integrally covered with the body region 9.

[0033] In this embodiment, the body contact region 11 is ＋ The body contact region 11 is a semiconductor region of a type having a higher impurity concentration than the body region 9. The body contact region 11 has a dopant concentration of, for example, 1×10 １９ cm －３ 5x10 or more ２１ cm －３The body contact region 11 has an impurity concentration of 0.2 μm or more and 1.0 μm or less. The depth of the body contact region 11 is shallower than that of the body region 9, and may be, for example, 0.2 μm or more and 1.0 μm or less. Therefore, in a cross-sectional view, the side and bottom of the body contact region 11 are integrally covered with the body region 9.

[0034] The drain region 12 is formed in the device main surface 19 of the semiconductor layer 5. The drain region 12 is spaced apart from the body region 9 in the second direction B, and has an outer periphery that follows the periphery of the second opening 32 in the field insulating film 8. The drain regions 12 may also be formed as a pair facing each other in the second direction B with the source region 10 interposed therebetween. Each drain region 12 extends in the first direction A. In this embodiment, the drain region 12 is formed in an elongated shape along the first direction A.

[0035] In this embodiment, the drain region 12 is ＋ The drain region 12 is a semiconductor region of the type having a dopant concentration of, for example, 1×10 １９ cm －３ 5x10 or more ２１ cm －３ The drain region 12 may have the following impurity concentration: The depth of the drain region 12 may be, for example, 0.2 μm or more and 2.0 μm or less. For example, the drain region 12 may have the same depth as the source region 10.

[0036] The gate insulating film 13 is formed on the element main surface 19 of the semiconductor layer 5. More specifically, the gate insulating film 13 is formed in a region extending from the outer periphery of the source region 10 to the periphery of the first opening 31 in the field insulating film 8, is integrated with the field insulating film 8, and covers the channel region 34 and the semiconductor region 33.

[0037] In this embodiment, the gate insulating film 13 is made of silicon oxide (SiO ２ ), but may be formed of other insulating materials (for example, silicon oxide nitride (SiON)). The thickness of the gate insulating film 13 may be thinner than that of the field insulating film 8, for example, between 2 nm and 55 nm.

[0038] The gate electrode 14 is formed on the gate insulating film 13. The gate electrode 14 faces the channel region 34 and the semiconductor region 33 via the gate insulating film 13, and extends continuously from the gate insulating film 13 onto the field insulating film 8. As a result, the gate electrode 14 covers a part of the field insulating film 8. The part of the gate electrode 14 facing the channel region 34 may be referred to as a main body 35 of the gate electrode 14. Furthermore, the part of the gate electrode 14 on the field insulating film 8 may be referred to as a field plate 36, for example.

[0039] In this embodiment, the gate electrode 14 is formed in a ring shape surrounding the source region 10 and has an opening 37 that exposes the source region 10. As shown in FIGS. 3 and 4 , the source region 10 is formed larger than the opening 37 and overlaps the periphery of the opening 37. In other words, the periphery of the opening 37 is adjacent to the source region 10 in the thickness direction of the semiconductor layer 5. In this embodiment, the opening 37 is an opening that is mainly used to expose the source region 10, and may be referred to as a source contact opening, for example.

[0040] The main body 35 of the gate electrode 14 may be formed in an elongated shape (substantially rectangular shape) along the first direction A.

[0041] In this embodiment, the gate electrode 14 is formed of, for example, an n-type impurity-containing ＋ The gate electrode 14 includes a polycrystalline silicon gate electrode of, for example, 1×10 １９ cm －３ 5x10 or more ２１ cm －３ It has the following impurity concentrations:

[0042] The first interlayer insulating film 15 is formed on the element main surface 19 of the semiconductor layer 5. The first interlayer insulating film 15 covers the body region 9, the source region 10, the body contact region 11, the drain region 12, and the gate electrode 14. In this embodiment, the first interlayer insulating film 15 is made of silicon oxide (SiO ２), but may be formed of other insulating materials (for example, silicon nitride (SiN) or the like). Also, first interlayer insulating film 15 may be formed of a plurality of materials, for example, a stacked structure of silicon oxide and silicon nitride. Also, the thickness of first interlayer insulating film 15 may be, for example, 0.3 μm or more and 2.0 μm or less.

[0043] The first wiring layer 16 is formed on the first interlayer insulating film 15. In this embodiment, the first wiring layer 16 includes a main body layer 40 (for example, an aluminum (Al) layer) and barrier layers 41 (for example, a Ti / TiN stacked structure) sandwiching the main body layer 40 from above and below, but may be formed of another conductive material (for example, copper (Cu) or the like).

[0044] The first wiring layer 16 may include a first source wiring layer 42 , a first contact wiring layer 26 , a first drain wiring layer 43 and a first gate wiring layer 44 .

[0045] The first source wiring layer 42 is formed on the source region 10 and the body contact region 11. The first source wiring layer 42 is drawn out from the active region 30 across the element isolation portion 7 to the outside of the first element region 2. The first source wiring layer 42 may also be connected to a ground potential at a position not shown.

[0046] The first source wiring layer 42 is connected to the source region 10 and the body contact region 11 by source contacts 45 and body contacts 46 embedded in the first interlayer insulating film 15. The source contacts 45 and body contacts 46 are arranged in a dot pattern at intervals along the first direction A. In this embodiment, the source contacts 45 and body contacts 46 are made of tungsten (W), but may be made of other conductive materials (e.g., aluminum (Al), copper (Cu), etc.). In this case, it goes without saying that a barrier layer such as TiN may be used.

[0047] The first contact wiring layer 26 is integrally branched off from the first source wiring layer 42. Therefore, the first contact wiring layer 26 may be connected to the ground potential via the first source wiring layer 42. The first contact wiring layer 26 may have a connection portion 27 with the first source wiring layer 42 above the element isolation portion 7, for example, as shown in FIG. 2 . In other words, the first contact wiring layer 26 may be branched off from the first source wiring layer 42 above the element isolation portion 7.

[0048] 2 , the first contact wiring layer 26 may be formed in a line shape along the linear element isolation portion 7 (trench 21) in a plan view. In other words, the first contact wiring layer 26 may extend along the element isolation portion 7 in a region above the linear element isolation portion 7 (trench 21). The first contact wiring layer 26 may be entirely formed in a region above the element isolation portion 7, or a portion of the first contact wiring layer 26 may be formed in a region above the element isolation portion 7, with the other portion being formed in a region other than the region above the element isolation portion 7. In the latter case, a portion of the first contact wiring layer 26 may cross the element isolation portion 7 in a plan view. In this embodiment, the first contact wiring layer 26 is formed in a line shape along the element isolation portion 7 in a plan view and in a closed loop shape. In other words, the first contact wiring layer 26 is formed in a closed loop shape that overlaps the element isolation portion 7 over its entire periphery in a plan view.

[0049] The first contact wiring layer 26 is connected to the first embedded body 23 by a first contact 59 embedded in the first interlayer insulating film 15. Like the first contact wiring layer 26, the first contact 59 may be formed in a line shape along the linear element isolation portion 7 (trench 21) in plan view, as shown in FIG. 2 . In this embodiment, the first contact 59 is formed in a line shape along the element isolation portion 7 in plan view and in a closed loop shape. That is, the first contact 59 is formed in a closed loop shape that overlaps the element isolation portion 7 and the first contact wiring layer 26 over the entire periphery in plan view.

[0050] In this embodiment, the first contact 59 is made of tungsten (W), but it may be made of other conductive materials (for example, aluminum (Al), copper (Cu), etc.) In this case, it goes without saying that a barrier layer such as TiN may also be used.

[0051] The first drain wiring layer 43 is formed on the drain region 12. The first drain wiring layer 43 is formed so as to fit within the active region 30. In other words, both end portions of the first drain wiring layer 43 are formed inside the outer periphery of the active region 30.

[0052] The first drain wiring layer 43 is connected to the drain region 12 by a first drain contact 47 embedded in the first interlayer insulating film 15. The first drain contacts 47 are arranged in a dot pattern at intervals along the first direction A. In this embodiment, the first drain contacts 47 are made of tungsten (W), but may be made of other conductive materials (e.g., aluminum (Al), copper (Cu), etc.). In this case, it goes without saying that a barrier layer such as TiN may be used.

[0053] The first gate wiring layer 44 is formed on the gate electrode 14. The first gate wiring layer 44 is formed outside the active region 30 and inside the first element region 2. In other words, both end portions of the first gate wiring layer 44 are formed inside the element isolation portion 7.

[0054] The second interlayer insulating film 17 is formed on the first interlayer insulating film 15 so as to cover the first wiring layer 16. In this embodiment, the second interlayer insulating film 17 is made of silicon oxide (SiO ２ ), but may be formed of other insulating materials (for example, silicon nitride (SiN) or the like). Also, second interlayer insulating film 17 may be formed of a plurality of materials, for example, a stacked structure of silicon oxide and silicon nitride. Also, the thickness of second interlayer insulating film 17 may be, for example, 0.3 μm or more and 2.0 μm or less.

[0055] The second wiring layer 18 is formed on the second interlayer insulating film 17. In this embodiment, the second wiring layer 18 includes a main body layer 49 (for example, an aluminum (Al) layer) and barrier layers 50 (for example, a Ti / TiN stacked structure) sandwiching the main body layer 49 from above and below, but may be formed of another conductive material (for example, copper (Cu) or the like).

[0056] The second wiring layer 18 may include a second drain wiring layer 51 and a second gate wiring layer 52 .

[0057] The second drain wiring layer 51 is formed to cover the first source wiring layer 42 and the first drain wiring layer 43. The second drain wiring layer 51 may include a contact portion 53 formed on the active region 30 and covering the first source wiring layer 42 and the first drain wiring layer 43, and a lead portion 54 led from the contact portion 53 to the outside of the first element region 2, across the element isolation portion 7 and the first contact wiring layer 26. As shown in FIGS. 3 and 4 , the second drain wiring layer 51 (contact portion 53) is formed to cross an upper region of the source region 10 and straddle a pair of drain regions 12.

[0058] The second drain wiring layer 51 (contact portion 53 in this embodiment) is connected to the first drain wiring layer 43 by a second drain contact 55 embedded in the second interlayer insulating film 17. The second drain contacts 55 are arranged in a dot pattern at intervals along the first direction A. In this embodiment, the second drain contacts 55 are made of tungsten (W), but may be made of other conductive materials (for example, aluminum (Al), copper (Cu), etc.). In this case, it goes without saying that a barrier layer such as TiN may be used.

[0059] The second gate wiring layer 52 is formed so as to cover the first gate wiring layer 44. The second gate wiring layer 52 may include a contact portion 56 formed on the first gate wiring layer 44 and covering the first gate wiring layer 44, and a lead portion 57 led from the contact portion 56 across the element isolation portion 7 and the first contact wiring layer 26 to the outside of the first element region 2.

[0060] The second gate wiring layer 52 (contact portion 56 in this embodiment) is connected to the first gate wiring layer 44 by a gate contact 58 embedded in the second interlayer insulating film 17. The gate contacts 58 are arranged in a dot pattern at intervals along the second direction B. In this embodiment, the gate contacts 58 are made of tungsten (W), but may be made of other conductive materials (for example, aluminum (Al), copper (Cu), etc.). In this case, it goes without saying that a barrier layer such as TiN may be used.

[0061] <Structure of Element Isolation Region 7 According to First Embodiment> Next, a specific structure of the element isolation region 7 according to the first embodiment will be described. (1) First Shape Fig. 5 is an enlarged view of a main portion of the element isolation region 7 in Figs. 3 and 4, showing a first shape of the element isolation film 22. In Fig. 5, elements necessary for explaining the specific structure of the element isolation region 7 are selectively shown, and elements that are not particularly necessary are omitted. For example, the buried layer 6 is omitted in Fig. 5.

[0062] The trench 21 may include a first trench 60 , a second trench 61 , an isolation film 22 , a first filling body 23 , and a second filling body 77 .

[0063] The first trench 60 and the second trench 61 are sequentially continuous toward the side opposite the principal surface. The second trench 61 is formed from the element principal surface 19 toward the bottom wall of the trench 21 to partway through the thickness direction of the semiconductor layer 5, and the first trench 60 is formed from the bottom wall 65 of the second trench 61. The first trench 60 is formed to reach the semiconductor substrate 4. The second trench 61 is formed in the surface portion of the element principal surface 19 and is continuous with the upper end of the first trench 60. In other words, the trench 21 may include the second trench 61 formed from the element principal surface 19 of the semiconductor layer 5 toward the downward side in the thickness direction of the semiconductor layer 5, and the first trench 60 formed from the bottom of the second trench 61 toward the downward side in the thickness direction of the semiconductor layer 5.

[0064] The first trench 60 has a width W of, for example, 0.2 μm or more and 20 μm or less. １When the first trench 60 has a tapered cross-sectional shape in which the width becomes narrower as the depth increases, the width W １ may be the maximum width of the first trench 60. Also, the depth D of the first trench 60 １ may be, for example, 2 μm or more and 100 μm or less.

[0065] The first trench 60 has sidewalls 62 and a bottom wall 63. The sidewalls 62 of the first trench 60 may be inclined relative to the bottom wall 63. The sidewalls 62 of the first trench 60 are formed of the semiconductor layer 5. The bottom wall 63 of the first trench 60 is formed of the semiconductor substrate 4. In other words, the sidewalls 62 and the bottom wall 63 of the first trench 60 may be formed of semiconductors having different impurity concentrations. More specifically, the bottom wall 63 of the first trench 60 is formed of a first semiconductor of a first conductivity type (in this embodiment, p ＋ The sidewalls 62 of the first trenches 60 are made of a second semiconductor (in this embodiment, n － The semiconductor layer 5 may be formed of a metal.

[0066] The second trench 61 has a width W that is wider than the first trench 60. ２ The width W ２ When the second trench 61 has a tapered cross-sectional shape in which the width becomes narrower as the second trench 61 becomes deeper, the width W ２ may be the maximum width of the second trench 61. The second trench 61 has a depth D ２ The depth D ２ may be, for example, not less than 0.05 μm and not more than 2 μm. In this way, the first trench 60 and the second trench 61 have different depths.

[0067] The second trench 61 has a sidewall 64 and a bottom wall 65. The sidewall 64 of the second trench 61 may be inclined with respect to the bottom wall 65.

[0068] For example, the first trench 60 may be referred to as a DTI (Deep Trench Isolation) structure, and the second trench 61 may be referred to as an STI (Shallow Trench Isolation) structure.

[0069] The element isolation film 22 is disposed between the semiconductor layer 5 and the first filling body 23, and provides insulation between the semiconductor layer 5 and the first filling body 23. The first filling body 23 is insulated from the semiconductor layer 5 by the element isolation film 22.

[0070] The element isolation film 22 is formed along the bottom wall 63 and sidewall 62 of the first trench 60. Specifically, the element isolation film 22 has one surface (outer surface) in contact with the bottom wall 63 and sidewall 62 of the first trench 60 and another surface (inner surface) on the opposite side thereof, and is formed on the bottom wall 63 and sidewall 62 so that the one surface and the other surface are parallel to the bottom wall 63 and sidewall 62. As a result, the element isolation film 22 forms a concave space inside the first trench 60.

[0071] The element isolation film 22 may include a first film 71 and a second film 72. The element isolation film 22 has a laminated structure of the first film 71 in contact with the bottom wall 63 and the side wall 62, and the second film 72 formed on the first film 71 and separated from the bottom wall 63 and the side wall 62 by the first film 71.

[0072] The first film 71 is formed along the bottom wall 63 and the sidewall 62 of the first trench 60 and is in contact with the bottom wall 63 and the sidewall 62. The first film 71 integrally covers a partial region of the bottom wall 63 and the entire region of the sidewall 62. As a result, in a cross-sectional view, the first film 71 is formed in an L-shape having bent portions at both ends in the width direction of the bottom wall 63 of the first trench 60. Specifically, the first film 71 may include a first portion 73 covering the sidewall 62 and a second portion 74 covering the bottom wall 63. The first portion 73 and the second portion 74 may be referred to as a sidewall-coating film and a bottom wall-coating film, respectively.

[0073] The first portion 73 of the first film 71 is formed so as to extend from the bottom wall 63 of the first trench 60 along the sidewall 62 to the bottom wall 65 of the second trench 61. As a result, the entire sidewall 62 is covered with the first portion 73 of the first film 71. The first portion 73 of the first film 71 has one surface 81 (outer side surface, see FIG. 6 ) in contact with the sidewall 62 of the first trench 60 and another surface 82 (inner surface, see FIG. 6 ) on the opposite side, and is formed on the sidewall 62 so that the one surface 81 and the other surface 82 are parallel to the sidewall 62.

[0074] The second portion 74 of the first film 71 is drawn out from the lower end of the first portion 73 along the bottom wall 63 of the first trench 60, and has a bottom end 75 in the center of the bottom wall 63. As a result, a portion of the bottom wall 63 is covered by the second portion 74 of the first film 71. The second portion 74 of the first film 71 has one surface (lower surface) in contact with the bottom wall 63 of the first trench 60 and another surface (upper surface) on the opposite side thereof, and is formed on the side wall 62 so that the one surface and the other surface are parallel to the bottom wall 63.

[0075] In the first trench 60 , the space defined by the bottom end 75 of the second portion 74 is a contact opening 76 that partially exposes the bottom wall 63 .

[0076] The first film 71 may be an insulating film. In this embodiment, the first film 71 is made of silicon oxide (SiO ２ ), but may be formed of other insulating materials (for example, silicon oxide nitride (SiON)). The first film 71 has a constant thickness as a whole. For example, the first portion 73 and the second portion 74 of the first film 71 may have the same thickness. The thickness of the first film 71 is, for example, not less than 0.02 μm and not more than 2.0 μm, and preferably not less than 0.6 μm and not more than 1.5 μm.

[0077] The second film 72 is formed from the upper surface region of the second portion 74 of the first film 71 along the first portion 73. As a result, the inner surface of the first portion 73 of the first film 71 and the upper surface of the second portion 74 are covered by the second film 72. The second film 72 has one surface 86 (outer surface, see FIG. 6 ) in contact with the first portion 73 of the first film 71 and another surface 87 (inner surface, see FIG. 6 ) on the opposite side, and is laminated on the first portion 73 so that the one surface 86 and the other surface 87 are parallel to the first portion 73 of the first film 71.

[0078] The other surface 87 (inner surface) of the second film 72 is flush with and continuous with the bottom end 75 of the first film 71. As a result, no step is formed between the other surface 87 (inner surface) of the second film 72 and the bottom end 75 of the first film 71. Therefore, the element isolation film 22 is formed as a film of a constant thickness from the bottom wall 63 of the first trench 60 toward the element main surface 19, by combining the L-shaped first film 71 and the linear second film 72 in a cross-sectional view.

[0079] In this embodiment, the second film 72 is formed of a material having an etching selectivity with respect to the first film 71. Having an etching selectivity with respect to the first film 71 means, for example, that the etching selectivity (a / b), which is the ratio of the etching amount (a) of the first film 71 to the etching amount (b) of the second film 72 when etching the first film 71, is preferably 1.5 or more, and more preferably 5.0 or more. The higher the etching selectivity (a / b), the better, but the upper limit may be, for example, 1000 or less.

[0080] The first film 71 is SiO ２ In the case of a film, the second film 72 having an etching selectivity relative to the first film 71 may be, for example, a film made of one material selected from polysilicon, doped polysilicon, silicon nitride (SiN), silicon carbide (SiC), carbon-added silicon oxide (SiOC), and metal (for example, W, Ti, TiN, Ta, TaN, Al, Cu, etc.). An example of these materials is a mixture of insulating materials and conductive materials. In FIG. 5, the second film 72 is made of an insulating material as an example, and is hatched to indicate the insulating material.

[0081] The thickness of the second film 72 is thinner than the thickness of the first film 71, and is, for example, 0.02 μm or more and 1.0 μm or less, and preferably 0.05 μm or more and 0.3 μm or less. However, the thickness of the second film 72 may be the same as the thickness of the first film 71 or may be thicker than the thickness of the first film 71.

[0082] The first filling body 23 is buried inside the element isolation film 22. The first filling body 23 may be electrically connected to the semiconductor substrate 4 exposed from the contact opening 76. The first filling body 23 may include a first protrusion 66 that selectively protrudes into the second trench 61. The first filling body 23 may be buried inside the element isolation film 22 in the first trench 60, and may further protrude upward from a bottom wall 65 of the second trench 61.

[0083] The first embedded body 23 may have a first upper surface 67, which is the upper surface of the first protrusion 66, and a second upper surface 68 formed at a lower level than the first upper surface 67. The first protrusion 66 may be formed by selectively protruding a portion of the top of the first embedded body 23. In this embodiment, the second upper surfaces 68 are formed on one and the other sides of the first protrusion 66 in a direction intersecting the extension direction of the first contact 59. For example, FIG. 5 is a cross-sectional view taken along the second direction B, showing an aspect in which the first contact 59 extends in the first direction A. Therefore, the second upper surfaces 68 are formed on one and the other sides of the first protrusion 66 in the second direction B.

[0084] The element isolation film 22 may have a second protruding portion 69 that protrudes above the second upper surface 68 of the first filling body 23. The second protruding portion 69 may have a peak at a midpoint in the depth direction of the second trench 61. Therefore, the protruding amount of the second protruding portion 69 is determined based on the depth D of the second trench 61. ２ The first protrusion 66 and the second protrusion 69 may extend upward with a gap between them.

[0085] The second filling body 77 is filled in the second trench 61. In this embodiment, the second filling body 77 is made of silicon oxide (SiO ２ ), but may be formed of other insulating materials (for example, silicon nitride (SiN), etc.). The second trench 61 may have an upper surface 78 that is flush with the first upper surface 67 of the first filling body 23. Therefore, a surface formed by the first upper surface 67 of the first filling body 23 and the upper surface 78 of the second filling body 77 may be exposed at the opening end of the second trench 61. In other words, the first filling body 23 may penetrate the second filling body 77 and be selectively exposed from the upper surface 78 of the second filling body 77.

[0086] Fig. 6 is an enlarged view of the portion surrounded by the dashed line VI in Fig. 5. Fig. 7 is a view showing a modification of the element isolation film 22 in Fig. 6. Next, the structure of the second protrusion 69 of the element isolation film 22 will be described in detail.

[0087] 6 and 7 , the second protruding portion 69 of the element isolation film 22 protrudes from the bottom wall 65 of the second trench 61 into the second trench 61 and is embedded in the second filling body 77. The second protruding portion 69 may be a part of an upper end portion 90 of the element isolation film 22 arranged on the upper side in the depth direction of the trench 21.

[0088] In this first shape, the upper end 90 of the element isolation film 22 is a stacked upper end 90 formed by a stacked structure of a first film 71 and a second film 72. The first film 71 and the second film 72 are stacked in contact with each other in a direction intersecting the depth direction of the trench 21, and protrude into the second trench 61 as a second protruding portion 69. The stacked upper end 90 forms the second protruding portion 69, and is also formed in a vicinity 107 of the boundary between the first trench 60 and the second trench 61. The vicinity 107 of the boundary may be, for example, a region having a depth of 0.15 μm to 0.5 μm from the bottom wall 65 of the second trench 61.

[0089] In the second protruding portion 69, a recess 80 is formed at an upper end 79 of the first film 71 (first portion 73) by recessing the upper end of the first film 71. Specifically, the recess 80 is formed at a thickness T １The central portion of the first film 71 in the direction of １ The upper end 79 of the first film 71 may be recessed toward the bottom wall 63 of the first trench 60 (see FIG. 5) with respect to both ends in the direction of the thickness T １ A pair of upper end protrusions 83 may be formed, with both ends in the direction of the upper end protruding selectively protruding along one surface 81 and the other surface 82 of the first film 71, respectively. This may form a recess 80 consisting of a space sandwiched between the pair of upper end protrusions 83. The one surface 81 and the other surface 82 may be an outer side surface in contact with the sidewall 62 of the first trench 60 and an inner side surface on the opposite side, respectively. In a cross-sectional view, the recess 80 is formed from the tip of the pair of upper end protrusions 83 to the thickness T of the first film 71. １ For example, in cross section, the inner surface of the recess 80 may have a thickness T １ The surface 81 may have an apex at a center 84 in the direction of the arrow A, and may be formed in an arc shape that slopes upward toward each of the one surface 81 and the other surface 82 with the center 84 as a boundary.

[0090] In the second protrusion 69, the thickness T of the upper end 85 of the second film 72 ２ may become thinner going upward in the depth direction of the first trench 60. For example, the second film 72 may include one surface 86 (interface with the first film 71) in contact with the first film 71, another surface 87 formed substantially parallel to the one surface 86 and in contact with the first filling body 23, and an inclined surface 88 that is continuous with the other surface 87 at an upper end 85 of the second film 72 and inclined toward the one surface 86.

[0091] The portion (upper end 85) where the thickness of the second film 72 changes to be thinner may be entirely formed in the second protruding portion 69 as shown in FIG. 6 , or a portion thereof may be formed within the first trench 60 as shown in FIG. 7 . That is, the boundary portion 89 between the other surface 87 and the inclined surface 88 may be located within the second trench 61 as shown in FIG. 6 , or may be located within the first trench 60 as shown in FIG. 7 . In this embodiment, the bottom of the recess 80 of the first film 71 may be located above the boundary portion 89 of the second film 72 as shown in FIGS. 6 and 7 , below the boundary portion 89 (not shown), or at the same depth as the boundary portion 89 (not shown).

[0092] The angle θ between the inclined surface 88 of the second film 72 and the one surface 86 of the second film 72 is an acute angle, and may be, for example, greater than or equal to 15° and less than or equal to 50°.

[0093] (2) Second Shape Figure 8 is an enlarged view of a main part of the element isolation portion 7 in Figures 3 and 4, showing a second shape of the element isolation film 22. Figure 9 is an enlarged view of the part surrounded by dashed line IX in Figure 8. Figure 10 is a view showing a modified example of the second protrusion 69 in Figure 9. In the following, structures corresponding to those described with respect to the first shape of the element isolation film 22 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0094] Referring to FIG. 8, like the first shape, the element isolation film 22 has a second protruding portion 69 that protrudes above a second upper surface 68 of the first filling body 23 .

[0095] 9 , the second protruding portion 69 of the element isolation film 22 protrudes from the bottom wall 65 of the second trench 61 into the second trench 61 and is embedded in the second filling body 77. The second protruding portion 69 may be a part of the upper end portion 108 of the element isolation film 22 arranged on the upper side in the depth direction of the trench 21.

[0096] In this second shape, the upper end 108 of the element isolation film 22 is a stepped upper end 108 formed by the first film 71 selectively protruding more than the upper end 92 of the second film 72. A step 93 is formed in the depth direction of the second trench 61 between the upper end 91 of the first film 71 and the upper end 92 of the second film 72. In FIG. 9 , the step 93 may correspond to the amount of protrusion of the first film 71 from the bottom wall 65 of the second trench 61.

[0097] The upper end 92 of the second film 72 does not have the above-described inclined surface 88, and may be a flat surface that follows the bottom wall 65 of the second trench 61. In FIG. 9 , the upper end 92 of the second film 72 is flush with the bottom wall 65 of the second trench 61 and forms part of the bottom wall 65. In this case, the second protruding portion 69 of the element isolation film 22 may be formed of a single layer of the first film 71.

[0098] 10 , the second film 72 may protrude from the bottom wall 65 by a smaller amount than the protrusion of the first film 71. In this case, the second protrusion 69 of the element isolation film 22 may include a base portion having a laminated structure of the first film 71 and the second film 72, and an extension portion having a single-layer structure of the first film 71 that selectively extends upward from the base portion.

[0099] In both of the cases of FIGS. 9 and 10, the stacked portion of the first film 71 and the second film 72 in the step upper end portion 108 is formed in the vicinity 107 of the boundary between the first trench 60 and the second trench 61.

[0100] In this second shape, the second film 72 having an etching selectivity relative to the first film 71 may be made of one material selected from polysilicon and doped polysilicon. The second film 72 may be made of the same material as the first filling body 23. In this embodiment, when the first filling body 23 is made of polysilicon, the second film 72 may be made of the same material as the first filling body 23, i.e., polysilicon. If the second film 72 is made of the same material as the first filling body 23, the width of the first filling body 23 can be ensured to be wide, thereby reducing the resistance value of the first filling body 23.

[0101] 3 and 4, showing a third shape of the element isolation film 22. In the following, structures corresponding to those described with respect to the first and second shapes of the element isolation film 22 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0102] In the first and second shapes, an interface was formed between the second film 72 of the element isolation film 22 and the first filling body 23, and the second film 72 and the first filling body 23 were distinguishable from each other. Distinguishable may mean, for example, that they are visually distinguishable when the element isolation portion 7 is viewed in an image of an electron microscope (TEM, SEM, etc.). On the other hand, when the second film 72 is formed of the same material as the first filling body 23, as in the second shape, the interface between the second film 72 and the first filling body 23 may not be clearly formed, and the second film 72 and the first filling body 23 may not be distinguishable from each other.

[0103] 11 shows a structure in which no clear boundary surface is formed between the second film 72 and the first filling body 23. In the condition in which no clear boundary surface is formed, the second film 72 may be integrally formed with the first filling body 23 and may be a part of the first filling body 23.

[0104] Structurally, the third shape will be described as follows: the element isolation film 22 is formed of a single layer of the first film 71. Therefore, the element isolation film 22 has the same structure as the first film 71 of the first and second shapes. That is, the element isolation film 22 is formed in an L-shape having bent portions at both widthwise ends of the bottom wall 63 of the first trench 60 in a cross-sectional view.

[0105] The first embedded body 23 may include a main body portion 94 embedded inside the element isolation film 22 and a connection portion 95 electrically connected to the semiconductor substrate 4 from the main body portion 94 via the contact opening 76. A step 96 corresponding to the length of the second portion 74 of the element isolation film 22 is formed between the main body portion 94 and the connection portion 95.

[0106] The step 96 is formed by a sidewall end 97 of the main body 94. The sidewall end 97 protrudes from the upper part of the connection portion 95 to the upper surface region of the second portion 74 of the element isolation film 22. The sidewall end 97 is formed in a portion corresponding to the second film 72 described above. In other words, the sidewall end 97 is formed so as to extend from the upper surface region of the second portion 74 of the element isolation film 22 to the bottom wall 65 of the second trench 61. The sidewall end 97 forms the sidewall of the first embedded body 23 throughout the entire depth direction of the first trench 60.

[0107] 11 , a dashed line indicates a boundary 99 between the sidewall end 97 and another portion (a central portion 98) of the main body 94 of the first embedded body 23 adjacent to the sidewall end 97. The boundary 99 does not have to be visible when the element isolation portion 7 is observed in an image of an electron microscope (TEM, SEM, or the like).

[0108] 12A to 12H are diagrams showing steps related to the formation of the element isolation portion 7 according to the first embodiment. Next, a method for forming the element isolation portion 7 shown in FIG. 5 will be described.

[0109] 12A, a mask 100 is formed on the element main surface 19 of the semiconductor layer 5. The mask 100 includes, for example, a first hard mask 101 made of silicon nitride (SiN) and a second hard mask 102 made of silicon oxide (SiO ２ The mask 100 may be a hard mask having a laminated structure with a second hard mask 102 made of a silicon dioxide film. The mask 100 has an opening 103 that exposes a region where the first trench 60 is to be formed. The semiconductor layer 5 is then etched through the mask 100 to form the first trench 60.

[0110] 12B, after the first trench 60 is formed, the inner surface of the first trench 60 is thermally oxidized while the mask 100 remains. As a result, a first insulating material film 104 for the first film 71 is formed on the upper surface of the mask 100 and on the sidewall 62 and bottom wall 63 of the first trench 60. The first insulating material film 104 is made of, for example, silicon oxide (SiO ２ ) may be referred to as a liner oxide film.

[0111] 12C , a second insulating material film 105 for the second film 72 is formed along the first insulating material film 104. The second insulating material film 105 is formed by depositing an insulating material on the first insulating material film 104 by, for example, a CVD method. As a result, the second insulating material film 105 is formed on the first insulating material film 104 along the sidewalls 62 and the bottom wall 63 of the first trench 60.

[0112] In this embodiment, the second insulating material film 105 is formed of a material having an etching selectivity with respect to the first insulating material film 104. For example, the etching selectivity (a / b), which is the ratio of the etching amount (a) of the first insulating material film 104 to the etching amount (b) of the second insulating material film 105 when etching the first insulating material film 104, is preferably 1.5 or more, and more preferably 5.0 or more. The higher the etching selectivity (a / b), the better, but the upper limit may be, for example, 1000 or less.

[0113] The first insulating material film 104 is made of SiO ２ In the case of a film, the second insulating material film 105 having an etching selectivity relative to the first insulating material film 104 may be, for example, a material film selected from polysilicon, doped polysilicon, silicon nitride (SiN), silicon carbide (SiC), silicon carbide oxide film (SiOC), and metal (for example, W, Ti, TiN, Ta, TaN, Al, Cu, etc.).

[0114] 12D, the second insulating material film 105 is selectively etched. The etching is performed by supplying an etching gas from above the device main surface 19. For example, when the second insulating material film 105 is made of polysilicon or doped polysilicon, the etching gas may be Cl, O, or the like. ２, HBr, or the like is used. As a result, portions of the second insulating material film 105 along the device main surface 19 and the bottom wall 63 of the first trench 60 are selectively removed, forming the second film 72. A portion of the first insulating material film 104 is exposed at the bottom wall 63 of the first trench 60. At this time, portions of the second insulating material film 105 along the sidewall 62 of the first trench 60 are also etched sequentially from the upper end. As a result, a structure of the upper end 85 of the second film 72 including the inclined surface 88 (see FIG. 6 specifically) is formed.

[0115] 12E, the first insulating material film 104 is selectively etched. The etching is performed by supplying an etching gas from above the element main surface 19. The etching gas may be, for example, CF ４ , CHF ３ , C ４ F ８ , C ４ F ６ , O ２ , Ar, or the like is used. By using this etching gas, an etching selectivity of the second insulating material film 105 relative to the first insulating material film 104 is ensured. As a result, portions of the first insulating material film 104 along the device main surface 19 and the bottom wall 63 of the first trench 60 are selectively removed, forming the first film 71. A contact opening 76 is formed in the bottom wall 63 of the first trench 60, exposing a portion of the semiconductor substrate 4. At this time, portions of the first insulating material film 104 along the sidewall 62 of the first trench 60 are also etched sequentially from the upper end. As a result, a structure of the upper end 79 of the first film 71 including the recess 80 (see FIG. 6 specifically) is formed.

[0116] Next, as shown in FIG. 12F, a conductive material 106 for the first filling body 23 is formed by, for example, CVD so as to fill the first trench 60 .

[0117] 12G, unnecessary portions of the conductive material 106 are removed by etch-back to form the first filling body 23. Thereafter, the mask 100 is removed by etching.

[0118] 12H , the semiconductor layer 5 and the first filling body 23 are selectively etched to form a second trench 61. At this time, a portion of the semiconductor layer 5 made of single crystal silicon is removed, and a portion of the first filling body 23 made of polycrystalline silicon is also removed, forming a first protrusion 66 of the first filling body 23. At this time, portions of the first film 71 and the second film 72 are also removed from their upper ends, so that the amount of protrusion of the element isolation film 22 from the bottom wall 65 of the second trench 61 is adjusted to the length of the second protrusion 69.

[0119] Next, an insulating material is filled into the second trench 61 by, for example, CVD, thereby forming the second filling body 77. Through the above steps, the element isolation portion 7 shown in FIGS.

[0120] Effects of Semiconductor Device 1 As described above, in the semiconductor device 1, the second film 72 (second insulating material film 105) is stacked on the first film 71 (first insulating material film 104), thereby forming the isolation film 22. Because the second film 72 has an etching selectivity with respect to the first film 71, the first film 71 can be protected by the second film 72 during etching of the contact opening 76 (see FIG. 12E ). Because the second film 72 serves as a protective film and covers the other surface 82 of the first film 71 (see FIGS. 6 , 7 , 9 , and 10 ), etching of the first film 71 from the inside of the first trench 60 can be suppressed. This prevents the isolation film 22 from being locally thinned at the upper ends 90 and 108 of the isolation film 22. As a result, a decrease in breakdown voltage at the sidewalls 62 of the first trenches 60 for isolation can be suppressed.

[0121] Furthermore, since a stacked structure of the first film 71 and the second film 72 is formed at least near the boundary 107 between the first trench 60 and the second trench 61, a sufficient thickness can be ensured for the element isolation film 22, and a highly reliable semiconductor device 1 with excellent voltage resistance can be provided.

[0122] 13 is an enlarged view of a main portion of the element isolation portion 7 according to the second embodiment of the semiconductor device 1. In the following, structures corresponding to those described for the element isolation portion 7 with reference to FIG. 5 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0123] In the above-described element isolation portion 7, the second embedded body 77 was formed so as to embed the second protruding portion 69 of the element isolation film 22. In other words, the second embedded body 77 had a portion formed inside the element isolation film 22 (second protruding portion 69) and a portion formed outside the element isolation film 22 (second protruding portion 69).

[0124] In contrast to this, in the element isolation portion 7 according to the second embodiment, the second embedded body 77 is selectively formed outside the element isolation film 22 (second protruding portion 69). The second protruding portion 69 has its top at the opening end of the second trench 61 (i.e., at the same height as the element main surface 19). Therefore, the protruding amount of the second protruding portion 69 is determined by the depth D of the second trench 61. ２ may be the same as

[0125] 14A to 14H are diagrams showing steps related to the formation of the element isolation portion 7 according to the second embodiment. Next, a method for forming the element isolation portion 7 shown in FIG. 13 will be described.

[0126] 14A , the semiconductor layer 5 is selectively etched to form a second trench 61. Next, an insulating material is filled into the second trench 61 by, for example, a CVD method. As a result, a second filling body 77 is formed.

[0127] 14B, a mask 100 is formed on the element main surface 19 of the semiconductor layer 5. The mask 100 includes, for example, a first hard mask 101 made of silicon nitride (SiN) and a second hard mask 102 made of silicon oxide (SiO ２The mask 100 may have a laminated structure with a second hard mask 102 made of a first insulating film 104 and a second hard mask 102 made of a second insulating film 104. The mask 100 has an opening 103 that exposes a region where the first trench 60 is to be formed. The second filling body 77 is exposed from the opening 103. The second filling body 77 and the semiconductor layer 5 are then etched through the mask 100 to form the first trench 60.

[0128] 14C , after the first trench 60 is formed, the inner surface of the first trench 60 is thermally oxidized while the mask 100 remains. As a result, a first insulating material film 104 for the first film 71 is formed on the upper surface of the mask 100 and on the sidewalls 62 and bottom wall 63 of the first trench 60. The first insulating material film 104 covers the sidewalls of the second filling body 77 exposed in the trench 21. The first insulating material film 104 is made of, for example, silicon oxide (SiO ２ ) may be referred to as a liner oxide film.

[0129] 14D , a second insulating material film 105 for the second film 72 is formed along the first insulating material film 104. The second insulating material film 105 is formed by depositing an insulating material on the first insulating material film 104 by, for example, a CVD method. As a result, the second insulating material film 105 is formed on the first insulating material film 104 along the sidewalls 62 and the bottom wall 63 of the first trench 60.

[0130] In this embodiment, the second insulating material film 105 is formed of a material having an etching selectivity with respect to the first insulating material film 104. For example, the etching selectivity (a / b), which is the ratio of the etching amount (a) of the first insulating material film 104 to the etching amount (b) of the second insulating material film 105 when etching the first insulating material film 104, is preferably 1.5 or more, and more preferably 5.0 or more. The higher the etching selectivity (a / b), the better, but the upper limit may be, for example, 1000 or less.

[0131] The first insulating material film 104 is made of SiO ２In the case of a film, the second insulating material film 105 having an etching selectivity relative to the first insulating material film 104 may be, for example, a material film selected from polysilicon, doped polysilicon, silicon nitride (SiN), silicon carbide (SiC), silicon carbide oxide film (SiOC), and metal (for example, W, Ti, TiN, Ta, TaN, Al, Cu, etc.).

[0132] 14E, the second insulating material film 105 is selectively etched. The etching is performed by supplying an etching gas from above the device main surface 19. For example, when the second insulating material film 105 is made of polysilicon or doped polysilicon, the etching gas may be Cl, O, or the like. ２ , HBr, or the like is used. As a result, portions of the second insulating material film 105 along the device main surface 19 and the bottom wall 63 of the first trench 60 are selectively removed, forming the second film 72. A portion of the first insulating material film 104 is exposed at the bottom wall 63 of the first trench 60. At this time, portions of the second insulating material film 105 along the sidewall 62 of the first trench 60 are also etched sequentially from the upper end. As a result, a structure of the upper end 85 of the second film 72 including the inclined surface 88 (see FIG. 6 specifically) is formed.

[0133] 14F, the first insulating material film 104 is selectively etched. The etching is performed by supplying an etching gas from above the element main surface 19. The etching gas may be, for example, CF ４ , CHF ３ , C ４ F ８ , C ４ F ６ , O ２, Ar, or the like is used. By using this etching gas, an etching selectivity of the second insulating material film 105 relative to the first insulating material film 104 is ensured. As a result, portions of the first insulating material film 104 along the device main surface 19 and the bottom wall 63 of the first trench 60 are selectively removed, forming the first film 71. A contact opening 76 is formed in the bottom wall 63 of the first trench 60, exposing a portion of the semiconductor substrate 4. At this time, portions of the first insulating material film 104 along the sidewall 62 of the first trench 60 are also etched sequentially from the upper end. As a result, a structure of the upper end 79 of the first film 71 including the recess 80 (see FIG. 6 specifically) is formed.

[0134] Next, as shown in FIG. 14G, a conductive material 106 for the first filling body 23 is formed by, for example, CVD so as to fill the first trench 60 .

[0135] 14H, unnecessary portions of the conductive material 106 are removed by etch-back, thereby forming the first filling body 23. Thereafter, the mask 100 is removed by etching. Through the above steps, the element isolation portion 7 shown in FIG. 13 can be formed.

[0136] The embodiments of the present disclosure are to be considered as illustrative in all respects and not restrictive, and are intended to include modifications in all respects.

[0137] For example, in the above-described embodiment, a configuration in which the conductivity types of the semiconductor portions are reversed may be adopted, i.e., the semiconductor device 1 may be adopted in which the p-type portions are made n-type and the n-type portions are made p-type.

[0138] The following characteristics can be extracted from the description of this specification and the drawings.

[0139] [Supplementary Note 1-1] A chip (4, 5) having a main surface (19); an isolation trench (60) defining an element region (2, 3) on the main surface (19) side of the chip (4, 5) and having a sidewall (62) and a bottom wall (63); and an insulating first film (71) formed along the sidewall (62) of the element isolation trench (60), the first film (71) having a first portion (73) formed from the bottom wall (63) of the element isolation trench (60) along the sidewall (62), and a second portion (74) drawn from the first portion (73) along the bottom wall (63) of the element isolation trench (60) and having an opening (76) exposing the bottom wall (63) of the element isolation trench (60); a second film (72) including a material having an etching selectivity with respect to the first film (71), the second film (72) being formed from an upper surface region of the second portion (74) of the first film (71) along the first portion (73); and a conductive filling body (23) filled in the element isolation trench (60).

[0140] According to this configuration, the isolation film (22) is formed by stacking the second film (72) on the first film (71). Because the second film (72) has an etching selectivity relative to the first film (71), the first film (71) can be protected by the second film (72) during etching to form the opening (76) that exposes the bottom wall (63) of the isolation trench (60). Because the second film (72) covers the first film (71) as a protective film, etching of the first film (71) from the inside of the isolation trench (60) can be suppressed. This prevents the isolation film (22) from becoming thin. As a result, a decrease in breakdown voltage at the sidewall (62) of the isolation trench (60) can be suppressed.

[0141] [Supplementary Note 1-2] The first portion (73) of the first film (71) has a thickness (T １ The semiconductor device (1) according to Appendix 1-1, wherein a central portion (84) in the thickness direction has an upper end portion (79) on which a recess (80) recessed toward the bottom wall (63) of the element isolation trench (60) is formed relative to both end portions (83) in the thickness direction.

[0142] [Appendix 1-3] The semiconductor device (1) according to Appendix 1-2, wherein, in a cross-sectional view, the recess (80) of the first film (71) has an inner surface that slopes in a curved manner from the both end portions (83) toward the central portion (84).

[0143] [Additional Note 1-3-1] In cross-sectional view, the inner surface of the recess (80) has a thickness (T １ ) and is formed in an arc shape inclined upward toward one surface (81) and the other surface (82) of the first film, respectively, with the center (84) as a boundary.

[0144] [Appendix 1-4] The semiconductor device (1) according to any one of Appendices 1-1 to 1-3, wherein the second film (72) has an upper end (85) on which an inclined surface (88) is formed that is inclined with respect to a boundary surface (86) between the first film (71) and the second film (72).

[0145] [Appendix 1-5] The semiconductor device (1) according to Appendix 1-4, wherein an angle (θ) between the inclined surface (88) of the second film (72) and the boundary surface (86) between the first film (71) and the second film (72) is an acute angle.

[0146] [Supplementary Note 1-6] The first portion (73) of the first film (71) has a thickness (T １ a central portion (84) in the thickness direction has an upper end portion (79) on which a recess (80) recessed toward the bottom wall (63) of the element isolation trench (60) is formed relative to both end portions (83) in the thickness direction, and the second film (72) has an upper end portion (85) on which an inclined surface (88) inclined at an acute angle with respect to a boundary surface (86) between the first film (71) and the second film (72) is formed.

[0147] [Appendix 1-7] The semiconductor device (1) according to any one of Appendices 1-1 to 1-6, wherein the first film (71) and the second film (72) extend parallel to each other along the sidewall (62) of the element isolation trench (60) and contact each other on the main surface (19) side of the chip (4, 5), thereby forming a stacked upper end portion (90).

[0148] [Supplementary Note 1-7-1] The semiconductor device (1) according to Supplementary Note 1-7, wherein the second film (72) is formed of a material different from that of the buried body (23).

[0149] [Supplementary Note 1-7-2] The semiconductor device (1) according to Supplementary Note 1-7-1, wherein the buried body (23) is formed of doped polysilicon, and the second film (72) is formed of one material selected from SiN, SiC, SiOC, and a metal.

[0150] [Appendix 1-8] The semiconductor device (1) according to any one of Appendices 1-1 to 1-6, wherein the first film (71) and the second film (72) extend parallel to each other along the sidewalls (62) of the element isolation trench (60), and an upper end (108) of a step (93) is formed on the main surface (19) side of the chip (4, 5) by the first film (71) selectively protruding beyond an upper end of the second film (72).

[0151] [Supplementary Note 1-8-1] The semiconductor device (1) according to Supplementary Note 1-8, wherein the second film (72) is formed from the same material as the buried body (23).

[0152] [Supplementary Note 1-8-2] The semiconductor device (1) according to Supplementary Note 1-8-1, wherein the buried body (23) is formed of doped polysilicon, and the second film (72) is formed of polysilicon or doped polysilicon.

[0153] [Supplementary Note 1-9] A trench is formed on the surface of the chip (4, 5) so as to be continuous with the upper end of the isolation trench (60), and has a width (W) wider than that of the isolation trench (60). ２ ) and has a depth (D) shallower than that of the isolation trench (60). ２) a second element isolation trench (61) having a second insulating filler (77) buried in the second element isolation trench (61).

[0154] [Appendix 1-10] The semiconductor device (1) according to Appendix 1-9, wherein upper ends (79, 85) of the first film (71) and the second film (72) selectively protrude from a bottom wall (65) of the second element isolation trench (61) into the second embedded body (77).

[0155] [Note 1-11] The first film (71) is made of SiO ２ The semiconductor device (1) according to any one of Supplementary Notes 1-1 to 1-10, further comprising a film, wherein the second film (72) comprises a film of one material selected from polysilicon, doped polysilicon, SiN, SiC, SiOC, and a metal.

[0156] [Appendix 1-12] The semiconductor device (1) according to any one of Appendices 1-1 to 1-11, wherein the second film (72) has an etching selectivity of 1.5 or more with respect to the first film (71).

[0157] [Appendix 1-12-1] The semiconductor device (1) according to any one of Appendices 1-1 to 1-12, wherein the second film (72) has an etching selectivity of 5.0 or more with respect to the first film (71).

[0158] [Appendix 1-13] The semiconductor device (1) according to any one of Appendices 1-1 to 1-12, wherein the chips (4, 5) further include a semiconductor substrate (4), a semiconductor layer (5) supported by the semiconductor substrate (4) and forming the main surface (19) of the chips (4, 5), and a buried layer (6) buried between the semiconductor substrate (4) and the semiconductor layer (5), and the element isolation trench (60) passes through the buried layer (6) from the main surface (19) of the semiconductor layer (5) to reach the semiconductor substrate (4).

[0159] [Supplementary Note 1-14] A process of forming a mask (100) having an opening (103) selectively on a main surface (19) of a semiconductor layer (5); A process of forming an isolation trench (60) having a sidewall (62) and a bottom wall (63) so as to partition an element region (2, 3) on the main surface (19) side of the semiconductor layer (5) by etching the semiconductor layer (5) through the mask (100); A process of forming an insulating first film (71) along the sidewall (62) and the bottom wall (63) of the element isolation trench (60); A process of forming an element isolation film (22) by stacking a second film (72) containing a material having an etching selectivity with respect to the first film (71) on the first film (71) along the sidewall (62) and the bottom wall (63) of the element isolation trench (60); a step of selectively removing the second film (72) so as to expose the first film (71) on the bottom wall (63) of the element isolation trench (60); a step of selectively removing the first film (71) exposed from the second film (72) on the bottom wall (63) of the element isolation trench (60) so as to form an opening (76) that exposes the bottom wall (63) of the element isolation trench (60); and a step of filling the element isolation trench (60) with a conductive filling body (23) after forming the opening (76).

[0160] According to this method, a device isolation film (22) is formed by stacking a second film (72) on a first film (71). Because the second film (72) has an etching selectivity relative to the first film (71), the first film (71) can be protected by the second film (72) during etching to form an opening (76) that exposes the bottom wall (63) of the device isolation trench (60). Because the second film (72) covers the first film (71) as a protective film, etching of the first film (71) from the inside of the device isolation trench (60) can be suppressed. This prevents the device isolation film (22) from becoming thin. As a result, a semiconductor device (1) can be provided that can suppress a decrease in breakdown voltage at the sidewall (62) of the device isolation trench (60).

[0161] [Note 1-15] The first film (71) is made of SiO ２ The method for manufacturing a semiconductor device (1) according to appendix 1-14, wherein the second film (72) includes a film of one material selected from polysilicon, doped polysilicon, SiN, SiC, SiOC, and a metal.

[0162] [Supplementary Note 2-1] A semiconductor device comprising: a chip (4, 5) having a main surface (19); an isolation trench (60) that defines an element region (2, 3) on the main surface (19) side of the chip (4, 5) and has a sidewall (62) and a bottom wall (63); an isolation film (22) formed along the sidewall (62) of the isolation trench (60), the isolation film (22) having a first portion (73) formed from the bottom wall (63) of the isolation trench (60) along the sidewall (62) and a second portion (74) drawn from the first portion (73) along the bottom wall (63) of the isolation trench (60) and having an opening (76) that exposes the bottom wall (63) of the isolation trench (60); and a conductive filling body (23) filled in the isolation trench (60), The embedded body (23) includes a main body (94) embedded inside the element isolation film (22) and a connection part (95) electrically connected to the chip (4, 5) from the main body (94) through the opening (76), and a step (93) corresponding to the length of the second part (74) of the element isolation film (22) is formed between the main body (94) and the connection part (95).

[0163] [Appendix 2-2] The semiconductor device (1) according to Appendix 2-1, wherein the main body (94) of the embedded body (23) includes a sidewall end (97) that protrudes from an upper portion of the connection portion (95) to an upper surface region of the second portion (74) of the element isolation film (22) and forms a sidewall (62) of the embedded body (23) in a depth direction of the element isolation trench (60).

[0164] 1: Semiconductor device 2: First element region 3: Second element region 4: Semiconductor substrate 5: Semiconductor layer 5A: Upper semiconductor layer 5B: Lower semiconductor layer 6: Buried layer 7: Element isolation portion 8: Field insulating film 9: Body region 10: Source region 11: Body contact region 12: Drain region 13: Gate insulating film 14: Gate electrode 15: First interlayer insulating film 16: First wiring layer 17: Second interlayer insulating film 18: Second wiring layer 19: Element main surface 20: Junction surface 21: Trench 22: Element isolation film 23: First buried body 24: First portion 25: Second portion 26: First contact wiring layer 27: Connection portion 30: Active region 31: First opening 32: Second opening 33: Semiconductor region 34: Body channel region 35: Main body portion 36: Field plate 37: Opening 40: Main body layer 41: Barrier layer 42: First source wiring layer 43: First drain wiring layer 44: First gate wiring layer 45: Source contact 46: Body contact 47: First drain contact 49: Main body layer 50: Barrier layer 51: Second drain wiring layer 52: Second gate wiring layer 53: Contact portion 54: Lead portion 55: Second drain contact 56: Contact portion 57: Lead portion 58: Gate contact 59: First contact 60: First trench 61: Second trench 62: Side wall 63: Bottom wall 64: Side wall 65: Bottom wall 66: First protrusion 67 : First upper surface 68 : Second upper surface 69 : Second protruding portion 71 : First film 72 : Second film 73 : First portion 74 : Second portion 75 : Bottom end portion 76 : Contact opening 77 : Second buried body 78 : Upper surface79: Upper end 80: Recess 81: One surface 82: Other surface 83: Upper end protrusion 84: Center portion 85: Upper end 86: One surface 87: Other surface 88: Inclined surface 89: Boundary portion 90: Upper end of stack 91: Upper end 92: Upper end 93: Step 94: Main body portion 95: Connection portion 96: Step 97: Sidewall end 98: Center portion 99: Boundary portion 100: Mask 101: First hard mask 102: Second hard mask 103: Opening 104: First insulating material film 105: Second insulating material film 106: Conductive material 107: Vicinity of boundary portion 108: Upper end of step D １ : Depth D ２ : Depth T １ : Thickness T ２ : Thickness W １ :Width W ２ : Width θ : Angle

Claims

1. a chip having a major surface; an isolation trench defining an element region on the main surface side of the chip and having a sidewall and a bottom wall; a first film having insulating properties formed along the sidewall of the element isolation trench, the first film having a first portion formed along the sidewall from the bottom wall of the element isolation trench, and a second portion drawn from the first portion along the bottom wall of the element isolation trench and having an opening exposing the bottom wall of the element isolation trench; a second film including a material having an etching selectivity with respect to the first film and formed from an upper surface region of the second portion of the first film along the first portion; a conductive filling body filled in the element isolation trench.

2. 2. The semiconductor device according to claim 1, wherein the first portion of the first film has an upper end portion in which a recess is formed in a central portion in a thickness direction of the first film that is recessed toward the bottom wall of the element isolation trench relative to both ends in the thickness direction.

3. The semiconductor device according to claim 2 , wherein in a cross-sectional view, the recess of the first film has an inner surface that is inclined in a curved shape from the both end portions toward the center portion.

4. 2 . The semiconductor device according to claim 1 , wherein said second film has an upper end formed with an inclined surface inclined with respect to an interface between said first film and said second film.

5. 5. The semiconductor device according to claim 4, wherein an angle between said inclined surface of said second film and said interface between said first film and said second film is an acute angle.

6. the first portion of the first film has an upper end portion in which a central portion in a thickness direction of the first film is formed with a recess that is recessed toward the bottom wall of the element isolation trench with respect to both end portions in the thickness direction; 2. The semiconductor device according to claim 1, wherein said second film has an upper end formed with an inclined surface that is inclined at an acute angle with respect to a boundary surface between said first film and said second film.

7. 3. The semiconductor device according to claim 1, wherein the first film and the second film extend parallel to each other along the sidewall of the element isolation trench and contact each other on the main surface side of the chip to form an upper end portion of the stack.

8. 3. The semiconductor device according to claim 1, wherein the first film and the second film extend parallel to each other along the sidewalls of the element isolation trench, and a stepped upper end is formed on the main surface side of the chip by the first film selectively protruding beyond an upper end of the second film.

9. a second isolation trench formed on a surface portion of the chip so as to be continuous with an upper end of the isolation trench, the second isolation trench having a width greater than that of the isolation trench and a depth shallower than that of the isolation trench; 7. The semiconductor device according to claim 2, further comprising: a second insulating filling body filled in said second element isolation trench.

10. 10. The semiconductor device according to claim 9, wherein upper ends of the first film and the second film selectively protrude from a bottom wall of the second element isolation trench into the second buried body.

11. The first film is made of SiO ２ A membrane is included.

2. The semiconductor device according to claim 1, wherein the second film includes a film of one material selected from the group consisting of polysilicon, doped polysilicon, SiN, SiC, SiOC, and a metal.

12. 2. The semiconductor device according to claim 1, wherein said second film has an etching selectivity of 1.5 or more with respect to said first film.

13. the chip further includes a semiconductor substrate, a semiconductor layer supported by the semiconductor substrate and forming the main surface of the chip, and a buried layer buried between the semiconductor substrate and the semiconductor layer; The semiconductor device according to claim 1 , wherein the element isolation trench extends from the main surface of the semiconductor layer through the buried layer and reaches the semiconductor substrate.

14. forming a mask having an opening selectively on a main surface of the semiconductor layer; forming an isolation trench having a sidewall and a bottom wall by etching the semiconductor layer through the mask so as to partition an element region on the main surface side of the semiconductor layer; forming an insulating first film along the sidewalls and the bottom wall of the element isolation trench; forming an isolation film by stacking a second film including a material having an etching selectivity with respect to the first film on the first film so as to be aligned along the sidewalls and the bottom wall of the isolation trench; selectively removing the second film to expose the first film on the bottom wall of the isolation trench; selectively removing the first film exposed from the second film on the bottom wall of the isolation trench to form an opening exposing the bottom wall of the isolation trench; after forming the opening, filling the element isolation trench with a conductive filling material.

15. The first film is made of SiO ２ A membrane is included.

15. The method of claim 14, wherein the second film includes a film of one material selected from polysilicon, doped polysilicon, SiN, SiC, SiOC, and a metal.