Electric power conversion unit

Abstract

This electric power conversion unit is provided with a plurality of semiconductor devices, a mounting object, and one mounting member. The plurality of semiconductor devices each comprise a semiconductor element and a sealing part which covers the semiconductor element. The mounting object comprises a main body part which is in contact with each one of the plurality of semiconductor devices. The one mounting member holds the plurality of semiconductor devices on the mounting object. The one mounting member comprises a fixed part which is fixed to the mounting object, and a pressing part which presses the plurality of semiconductor devices against the main body part.

Description

Power Conversion Unit

[0001] The present disclosure relates to a power conversion unit.

[0002] Conventionally, semiconductor devices including semiconductor elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) have been known. For example, Patent Document 1 (JP-A-2005-102626) discloses a power module, which is an example of a conventional semiconductor device. The power module described in Patent Document 1 includes a power element, a ceramic substrate, and a sealing resin. The power element is, for example, an IGBT. A conductor pattern is formed on one surface of the ceramic substrate. The power element is bonded to the conductor pattern. A conductor film is formed on the other surface of the ceramic substrate. The conductor film is exposed from the sealing resin. Such a semiconductor device is attached to an external cooler, for example, to efficiently dissipate heat from the power element to the outside. At this time, the conductor film exposed from the sealing resin comes into contact with the external cooler.

[0003] JP 2011-172483 A

[0004] Power conversion units such as three-phase inverters use multiple semiconductor devices. In such power conversion units, the multiple semiconductor devices are sometimes attached to a common external cooler. In this case, for example, if there is a gap between the external cooler and each semiconductor device, the heat dissipation performance of each power element is reduced. In other words, if the multiple semiconductor devices are not properly attached to the external cooler, the heat dissipation performance of the power conversion unit is reduced.

[0005] An object of the present disclosure is to provide an improved power conversion unit compared to conventional power conversion units. In particular, in view of the above circumstances, an object of the present disclosure is to provide a power conversion unit that can suppress a decrease in heat dissipation performance.

[0006] A power conversion unit according to one aspect of the present disclosure includes a plurality of semiconductor devices, each including a semiconductor element and a sealing portion covering the semiconductor element, an attachment object including a main body portion in contact with the plurality of semiconductor devices, and a mounting member that holds the plurality of semiconductor devices on the attachment object. The mounting member includes a fixing portion fixed to the attachment object and a pressing portion that presses the plurality of semiconductor devices against the main body portion.

[0007] According to the above configuration, it is possible to suppress a decrease in heat dissipation performance.

[0008] FIG. 1 is a perspective view showing a power conversion unit according to a first embodiment. FIG. 2 is a view in which the wiring board is omitted from the perspective view of FIG. 1. FIG. 3 is a plan view showing the power conversion unit according to the first embodiment. FIG. 4 is a view in which the wiring board is omitted from the plan view of FIG. 3. FIG. 5 is a front view showing the power conversion unit according to the first embodiment. FIG. 6 is a bottom view showing the power conversion unit according to the first embodiment. FIG. 7 is a left side view showing the power conversion unit according to the first embodiment. FIG. 8 is a right side view showing the power conversion unit according to the first embodiment. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 4. FIG. 10 is a cross-sectional view taken along line X-X in FIG. 4. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 4. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 4. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 4. FIG. 14 is a partially enlarged cross-sectional view of the power conversion unit according to the first embodiment. FIG. 15 is a perspective view showing a semiconductor device of a power conversion unit according to the first embodiment. FIG. 16 is a plan view showing the semiconductor device of a power conversion unit according to the first embodiment. FIG. 17 is a view showing the sealing portion in imaginary lines in the plan view of FIG. 16. FIG. 18 is a view showing the sealing portion and the second conductive member in the plan view of FIG. 17, but omitting them. FIG. 19 is a front view showing the semiconductor device of a power conversion unit according to the first embodiment. FIG. 20 is a bottom view showing the semiconductor device of a power conversion unit according to the first embodiment. FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 17. FIG. 22 is a partially enlarged cross-sectional view of FIG. 21. FIG. 23 is a partially enlarged cross-sectional view of FIG. 21. FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 17. FIG. 25 is a cross-sectional view taken along line XXV-XXV in FIG. 17. FIG. 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. 17. Fig. 27 is a plan view showing a power conversion unit according to the second embodiment, with the wiring board omitted. Fig. 28 is a cross-sectional view taken along line XXVIII-XXVIII in Fig. 27. Fig. 29 is a cross-sectional view taken along line XXIX-XXIX in Fig. 27. Fig. 30 is a cross-sectional view taken along line XXX-XXX in Fig. 27. Fig. 31 is a plan view showing a power conversion unit according to a first modified example of the second embodiment, with the wiring board omitted.FIG. 32 is a cross-sectional view taken along line XXXII-XXXII in FIG. 31 . FIG. 33 is a right side view showing a power conversion unit according to a first modified example of the second embodiment in an unassembled state. FIG. 34 is a plan view showing a power conversion unit according to a second modified example of the second embodiment, with the wiring board omitted. FIG. 35 is a cross-sectional view taken along line XXXV-XXXV in FIG. 34 . FIG. 36 is a cross-sectional view taken along line XXXVI-XXXVI in FIG. 34 . FIG. 37 is a plan view showing a power conversion unit according to the third embodiment, with the wiring board omitted. FIG. 38 is a cross-sectional view taken along line XXXVIII-XXXVIII in FIG. 37 . FIG. 39 is a cross-sectional view taken along line XXXIX-XXXIX in FIG. 37 . FIG. 40 is a plan view showing a power conversion unit according to a modified example, with the wiring board omitted.

[0009] A preferred embodiment of the power conversion unit of the present disclosure will be described below with reference to the drawings. Hereinafter, identical or similar components will be designated by the same reference numerals, and redundant description will be omitted. Terms such as "first," "second," and "third" in the present disclosure are merely used as labels and are not intended to necessarily assign any order to their objects.

[0010] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an) object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an) object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on (an) object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an) object B" includes "a certain object A is in contact with a certain object B and is located on (an) object B" and "a certain object A is located on (an) object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, "when viewed from a certain direction, an object A overlaps an object B" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, "an object A (is made of) a certain material C" includes "an object A (is made of) a certain material C" and "an object A (is made of) a certain material C as its main component."

[0011] 1 to 14 show a power conversion unit A10 according to the first embodiment. The power conversion unit A10 includes a plurality of semiconductor devices B1, an attachment object C1, an attachment member D1, and a wiring board E1.

[0012] In the following description, the thickness direction z, the first direction x, and the second direction y, which are perpendicular to each other, will be referred to. The thickness direction z corresponds to the thickness direction of the power conversion unit A10. Furthermore, "plan view" refers to the view in the thickness direction z. The first direction x is perpendicular to the thickness direction z. The second direction y is perpendicular to the thickness direction z and the first direction x. One side of the first direction x will be referred to as the x1 side of the first direction x, and the other side of the first direction x will be referred to as the x2 side of the first direction x. Furthermore, one side of the second direction y will be referred to as the y1 side of the second direction y, and the other side of the second direction y will be referred to as the y2 side of the second direction y. Furthermore, one side of the thickness direction z will be referred to as the z1 side of the thickness direction z, and the other side of the thickness direction z will be referred to as the z2 side of the thickness direction z. Furthermore, the z1 side of the thickness direction z will sometimes be referred to as the upper side, and the z2 side of the thickness direction z will sometimes be referred to as the lower side. Note that terms such as "top," "bottom," "upper," "lower," "top surface," and "bottom surface" indicate the relative positional relationship of each part in the thickness direction z, and are not necessarily terms that define the relationship with the direction of gravity.

[0013] As shown in FIGS. 2 , 4 , 7 , and 8 , the multiple semiconductor devices B1 are arranged along the second direction y. Each of the multiple semiconductor devices B1 includes multiple semiconductor elements 21. As will be understood from the configuration described in detail below, the multiple semiconductor elements 21 are switching elements such as MOSFETs and IGBTs, and each of the multiple semiconductor devices B1 constitutes, for example, a half-bridge switching circuit. Furthermore, as shown in FIGS. 1 to 9 , each of the multiple semiconductor devices B1 includes multiple power terminals 13, multiple signal terminals 17, and a sealing portion 50. In each of the multiple semiconductor devices B1, the multiple semiconductor elements 21 are covered by the sealing portion 50. The multiple power terminals 13 protrude in the first direction x from a side surface (a second side surface 532 described below) of the sealing portion 50. The multiple signal terminals 17 protrude in the thickness direction z from an upper surface (a top surface 51 described below) of the sealing portion 50.

[0014] In the illustrated example, the power conversion unit A10 includes three semiconductor devices B1, but may include two or four or more semiconductor devices B1. In the following description, when distinguishing between the three semiconductor devices B1, they are referred to as a first device B11, a second device B12, and a third device B13. The first device B11 is located closest to the y1 side of the multiple semiconductor devices B1 in the second direction y. The third device B13 is located closest to the y2 side of the multiple semiconductor devices B1 in the second direction y. The second device B12 is located between the first device B11 and the third device B13 in the second direction y.

[0015] The mounting object C1 supports the multiple semiconductor devices B1. The mounting object C1 is, for example, a heat sink. Instead of a heat sink, the mounting object C1 may be a housing (frame, etc.) of an electronic device, an electric vehicle, or the like. The majority of the mounting object C1 is located below the multiple semiconductor devices B1 in the thickness direction z (on the z2 side). The mounting object C1 faces the lower surfaces (bottom surfaces 52, described below) of the sealing portions 50 of the multiple semiconductor devices B1. The material of the mounting object C1 includes, for example, aluminum. The material is not limited to aluminum, and may be other metal materials or resin materials (preferably those with good thermal conductivity). The mounting object C1 includes a main body 71, multiple pedestal portions 72, and multiple positioning portions 73.

[0016] The main body 71 is a plate material. The plurality of semiconductor devices B1 are mounted on the main body 71. Therefore, as shown in FIGS. 2, 4, 7, and 8, the plurality of semiconductor devices B1 are arranged on the main body 71 along the second direction y. The main body 71 faces the lower surface (bottom surface 52 described below) of each sealing portion 50 of the plurality of semiconductor devices B1. The main body 71 contacts each semiconductor device B1. The main body 71 is, for example, rectangular in plan view.

[0017] 2, 5, and 7 to 13, the plurality of pedestals 72 each protrude upward in the thickness direction z from the main body 71. In the illustrated example, the plurality of pedestals 72 are formed integrally with the main body 71, but may also be attached to the main body 71 as separate bodies.

[0018] As shown in FIGS. 9 to 13 , each of the multiple pedestal portions 72 includes a first portion 721 and a second portion 722. The first portion 721 is interposed between the wiring substrate E1 and the main body portion 71 in the thickness direction z. The dimension of the first portion 721 in the thickness direction z is greater than the dimension of the sealing portion 50 of each semiconductor device B1 in the thickness direction z. The second portion 722 is disposed on the first portion 721. The wiring substrate E1 is sandwiched between the first portion 721 and the second portion 722. With this configuration, the wiring substrate E1 is disposed at a fixed distance from the upper surface of the main body portion 71.

[0019] In the illustrated example, the first part 721 has a recessed part with an internal thread, and the second part 722 has a protruding part with an external thread. The second part 722 is fastened to the first part 721 by inserting the externally threaded part (protruding part) of the second part 722 into the internally threaded part (recessed part) of the first part 721. Note that each pedestal part 72 may have a structure in which the first part 721 and the second part 722 are fitted together. For example, the pedestal part 72 may have a structure in which the second part 722 is press-fitted into the first part 721. Alternatively, the first part 721 may have a protruding part and the second part 722 may have a recessed part.

[0020] As shown in FIGS. 2 and 13 , each of the positioning portions 73 protrudes upward from the main body portion 71 in the thickness direction z. In the illustrated example (e.g., FIG. 13 ), each of the positioning portions 73 is attached to the main body portion 71 as a separate body. Alternatively, each positioning portion 73 may be formed integrally with the main body portion 71. In the example shown in FIG. 13 , each positioning portion 73 is press-fitted into a through-hole formed in the main body portion 71. Each positioning portion 73 is cylindrical and tapered toward the z1 side in the thickness direction z. In the illustrated example, the diameter of each positioning portion 73 in a plan view is smaller than the diameter of each base portion 72 in a plan view. As shown in FIGS. 3 and 4 , some of the positioning portions 73 are positioned closer to the y1 side of the first device B11 in the second direction y, and others are positioned closer to the y2 side of the third device B13 in the second direction y.

[0021] The mounting member D1 holds multiple semiconductor devices B1 on the mounting object C1. The mounting member D1 is, for example, a leaf spring. The elastic force of the mounting member D1 presses the multiple semiconductor devices B1 against the mounting object C1. The material of the mounting member D1 is not limited in any way, but may be, for example, copper, iron, titanium, or an alloy containing any of these (including, for example, stainless steel). As shown in FIGS. 4 and 7 to 13, the mounting member D1 includes multiple pressing portions 81 and multiple fixing portions 82.

[0022] The pressing portions 81 are provided individually for the semiconductor devices B1, respectively. Each pressing portion 81 contacts the sealing portion 50 (top surface 51) of the corresponding semiconductor device B1. Each pressing portion 81 presses the semiconductor device B1 it contacts against the main body 71 of the attachment object C1.

[0023] Each of the multiple fixing portions 82 is fixed to the attachment object C1, and in this embodiment, is fixed to the main body portion 71. Each of the multiple fixing portions 82 is, for example, a flat plate parallel (or approximately parallel) to the xy plane. A through hole is formed in each of the multiple fixing portions 82. A fastener 89 (a hexagonal bolt in the illustrated example) is inserted into the through hole. The fastener 89 fixes the fixing portion 82 to the main body portion 71.

[0024] The multiple fixed portions 82 include multiple double-ended portions 821 and multiple intermediate portions 822. In the power conversion unit A10, the multiple fixed portions 82 include a pair of double-ended portions 821 and two intermediate portions 822. As shown in FIGS. 4 and 10 , one of the pair of double-ended portions 821 is located on the y1 side of the first device B11 in the second direction y, and the other of the pair of double-ended portions 821 is located on the y2 side of the third device B13 in the second direction y. One of the two intermediate portions 822 is located between the first device B11 and the second device B12, and the other of the two intermediate portions 822 is located between the second device B12 and the third device B13.

[0025] In the example shown in FIG. 4 , the width (dimension in the first direction x) of each of the two-end arrangement portions 821 is smaller than the width (dimension in the first direction x) of each of the pressing portions 81 and the width (dimension in the first direction x) of each of the intermediate arrangement portions 822. This prevents interference between the mounting member D1 (each of the two-end arrangement portions 821) and each of the positioning portions 73. Unlike this example, the width of the pressing portion 81 and the width of each of the intermediate arrangement portions 822 may be the same (or approximately the same) as the width of each of the two-end arrangement portions 821. In this case, the mounting member D1 can be formed into a rectangular (strip-like) shape in a plan view. Alternatively, the width of each of the intermediate arrangement portions 822 may be the same (or approximately the same) as the width of each of the two-end arrangement portions 821.

[0026] As shown in FIGS. 1, 3, 7, and 8, the wiring board E1 is provided in common for multiple semiconductor devices B1. Alternatively, multiple wiring boards E1 may be provided individually for multiple semiconductor devices B1. As can be seen from FIGS. 9 and 11, the signal terminals 17 of the multiple semiconductor devices B1 are inserted into the wiring board E1. The wiring board E1 is electrically connected to each signal terminal 17. The wiring board E1 is, for example, a drive circuit that controls the operation of each semiconductor element 21 of the multiple semiconductor devices B1. In an example where each semiconductor element 21 is a MOSFET or IGBT, the wiring board E1 is a gate driver. The wiring board E1 faces the upper surface (top surface 51) of each sealing portion 50 of the multiple semiconductor devices B1. The wiring board E1 is located on the opposite side of the multiple semiconductor devices B1 from the main body portion 71 of the mounting object C1. In a plan view, the wiring board E1 overlaps each sealing portion 50 of the multiple semiconductor devices B1. The wiring board E1 is held by a plurality of pedestals 72 at a fixed distance in the thickness direction z.

[0027] As shown in FIG. 14 , the wiring board E1 has a substrate 91, main wiring 92, back wiring 93, and internal wiring 94. The substrate 91 is provided with a plurality of through holes 911 that penetrate in the thickness direction z. The main wiring 92 is formed on the upper surface of the substrate 91 (the surface facing the z1 side in the thickness direction z). The back wiring 93 is formed on the lower surface of the substrate 91 (the surface facing the z2 side in the thickness direction z). The internal wiring 94 is disposed on the inner surfaces of the plurality of through holes 911. The internal wiring 94 is connected to the main wiring 92 and the back wiring 93. The main wiring 92 forms a path for mutual conduction between the back wiring 93 and the internal wiring 94 and circuits provided in the wiring board E1.

[0028] Each signal terminal 17 of the plurality of semiconductor devices B1 is inserted into a corresponding one of the plurality of through holes 911 of the wiring substrate E1. Fig. 14 shows a state in which any signal terminal 17 of the plurality of semiconductor devices B1 is inserted into the through hole 911 of the substrate 91. Note that all of the signal terminals 17 of the plurality of semiconductor devices B1 are inserted into the through hole 911 of the substrate 91, as shown in Fig. 14.

[0029] 14 , each signal terminal 17 has a base 170A and a bulge 170B. One side of the base 170A in the thickness direction z is press-fitted into one of the multiple sleeves 64 (described later) of the multiple semiconductor devices B1. The bulge 170B is provided on one side (z1 side) of the base 170A in the thickness direction z. The bulge 170B bulges in a direction perpendicular to the thickness direction z.

[0030] As shown in FIG. 14 , each signal terminal 17 is press-fitted into one of the plurality of through holes 911 in the wiring board E1. As a result, the internal wiring 94 arranged in one of the plurality of through holes 911 is pressed against the bulging portion 170B of the signal terminal 17 inserted into the corresponding through hole 911. Therefore, each signal terminal 17 is press-fitted into the through hole 911 in the thickness direction z, thereby establishing electrical continuity with the wiring board E1. By press-fitting each signal terminal 17 into a corresponding one of the plurality of through holes 911, the wiring board E1 is supported by each signal terminal 17. Alternatively, each signal terminal 17 may not include the bulging portion 170B and may be formed only by the base portion 170A. In other words, each signal terminal 17 may be a straight pin with no change in thickness. In this case, each signal terminal 17 is inserted into the through hole 911 and then soldered to the wiring board E1.

[0031] As shown in FIGS. 3, 9, and 11 to 13, a plurality of mounting holes 951 and a plurality of positioning holes 952 are formed in the wiring board E1.

[0032] As shown in FIGS. 3, 9, and 11 to 13, a plurality of pedestal portions 72 (e.g., second portions 722) are individually inserted into the plurality of mounting holes 951. Each mounting hole 951 is formed, for example, as a perfect circle in plan view. The diameter of each mounting hole 951 in plan view is smaller than the diameter of each pedestal portion 72 (particularly the first portions 721) in plan view. Therefore, the wiring substrate E1 is held above the first portions 721 in the thickness direction z (on the z1 side).

[0033] As shown in FIGS. 3 and 13 , a plurality of positioning portions 73 are individually inserted into the plurality of positioning holes 952. In the illustrated example, two positioning holes 952 are formed in the wiring board E1. One of the two positioning holes 952 (the positioning hole 952 located on the y1 side in the second direction y) is formed as a perfect circle, and the other of the two positioning holes 952 (the positioning hole 952 located on the y2 side in the second direction y) is formed as an elongated hole. This facilitates positioning of the wiring board E1 relative to the attachment object C1. Forming one of the two positioning holes 952 as an elongated hole can suppress slight misalignment between the attachment object C1 and the wiring board E1 due to manufacturing errors.

[0034] Next, configuration examples of the multiple semiconductor devices B1 will be described with reference to FIGS. 15 to 26. FIGS. 15 to 26 are enlarged views of one of the multiple semiconductor devices B1. The multiple semiconductor devices B1 all have the same structure. Unless otherwise specified, the semiconductor device B1 described below is common to the first device B11, the second device B12, and the third device B13.

[0035] 15 to 26 , each semiconductor device B1 (each of the first device B11, second device B12, and third device B13) includes the above-described plurality of power terminals 13, plurality of signal terminals 17, plurality of semiconductor elements 21, and sealing portion 50, as well as a support substrate 11, a pair of thermistors 22, a first conductive member 31, a second conductive member 32, a plurality of wires, and a pair of control wirings 60. The plurality of power terminals 13 include a first power terminal 14, two second power terminals 15, and two third power terminals 16, and the plurality of signal terminals 17 include a first signal terminal 171, a second signal terminal 172, a third signal terminal 173, a fourth signal terminal 174, a pair of fifth signal terminals 181, and a pair of sixth signal terminals 182. The plurality of wires include a plurality of first wires 41, a plurality of second wires 42, a plurality of third wires 43, and a fourth wire 44.

[0036] Each semiconductor device B1 converts a DC power supply voltage applied to a first power terminal 14 and two second power terminals 15 into AC power using a plurality of semiconductor elements 21. The converted AC power is input from two third power terminals 16 to a power supply target such as a motor.

[0037] As shown in Figures 18 and 21, the support substrate 11 supports a plurality of semiconductor elements 21 in the thickness direction z. The support substrate 11 is made of, for example, a DBC (Direct Bonded Copper) substrate. As shown in Figures 21 to 26, the support substrate 11 includes an insulating layer 111, a first wiring layer 112, and a second wiring layer 113. The support substrate 11 is covered with a sealing portion 50 except for a portion of the second wiring layer 113.

[0038] 21 to 26, the insulating layer 111 includes a portion interposed between the first wiring layer 112 and the second wiring layer 113 in the thickness direction z. The insulating layer 111 is made of a material with relatively high thermal conductivity. The insulating layer 111 is made of ceramics containing aluminum nitride (AlN), for example. The insulating layer 111 may be made of an insulating resin sheet instead of ceramics.

[0039] As shown in FIGS. 18 and 21 to 26, the first wiring layer 112 is located above (on the z1 side of) the insulating layer 111 in the thickness direction z. The composition of the first wiring layer 112 includes copper (Cu). As shown in FIG. 18, the first wiring layer 112 is surrounded by the periphery of the insulating layer 111 in a planar view. As shown in FIGS. 18 and 21 to 26, the first wiring layer 112 includes a first mounting portion 1121 and a second mounting portion 1122. The first mounting portion 1121 and the second mounting portion 1122 are each rectangular in a planar view. The first mounting portion 1121 and the second mounting portion 1122 are spaced apart from each other in the first direction x. Each of the multiple semiconductor elements 21 is bonded to either the first mounting portion 1121 or the second mounting portion 1122.

[0040] As shown in Figures 21 to 26, the second wiring layer 113 is located below (on the z2 side of) the insulating layer 111 in the thickness direction z. As shown in Figure 20, the second wiring layer 113 is exposed from the sealing portion 50. The second wiring layer 113 contacts the upper surface (the surface facing the z1 side in the thickness direction z) of the main body portion 71 of the attachment target C1. The composition of the second wiring layer 113 includes copper. The second wiring layer 113 is rectangular in plan view. The second wiring layer 113 is surrounded by the periphery of the insulating layer 111 in plan view.

[0041] As shown in FIGS. 18 and 21 , each of the multiple semiconductor elements 21 is mounted on either the first mounting portion 1121 or the second mounting portion 1122. Each semiconductor element 21 is, for example, a MOSFET. Alternatively, each semiconductor element 21 may be a switching element such as an IGBT or a diode. In the description of the semiconductor device B1, the semiconductor element 21 is an n-channel MOSFET with a vertical structure. The semiconductor element 21 includes a compound semiconductor substrate. The compound semiconductor substrate has a composition including silicon carbide (SiC) or silicon (Si).

[0042] As shown in FIGS. 18 and 21 , in each semiconductor device B1, the multiple semiconductor elements 21 include multiple first elements 21A and multiple second elements 21B. The structure of each of the multiple second elements 21B is the same as the structure of each of the multiple first elements 21A. As shown in FIGS. 18 , 21 , and 22 , the multiple first elements 21A are mounted on a first mounting portion 1121. The multiple first elements 21A are arranged along the second direction y. As shown in FIGS. 18 , 21 , and 23 , the multiple second elements 21B are mounted on a second mounting portion 1122. The multiple second elements 21B are arranged along the second direction y.

[0043] As shown in FIGS. 18, 22 and 23, the plurality of semiconductor elements 21 have a first electrode 211, a second electrode 212, a third electrode 213 and two fourth electrodes 214.

[0044] 22 and 23 , the first electrode 211 faces either the first mounting portion 1121 or the second mounting portion 1122. A current corresponding to the power before being converted by the semiconductor element 21 flows through the first electrode 211. In other words, the first electrode 211 corresponds to the drain electrode of the semiconductor element 21.

[0045] 22 and 23 , the second electrode 212 is located on the opposite side of the first electrode 211 in the thickness direction z. A current corresponding to the power converted by the semiconductor element 21 flows through the second electrode 212. In other words, the second electrode 212 corresponds to the source electrode of the semiconductor element 21.

[0046] 18 , the third electrode 213 is located on the same side as the second electrode 212 in the thickness direction z. A drive signal (gate voltage) for driving the semiconductor element 21 is input to the third electrode 213. That is, the third electrode 213 corresponds to the gate electrode of the semiconductor element 21. As shown in FIG. 18 , the area of ​​the third electrode 213 is smaller than the area of ​​the second electrode 212 in a plan view.

[0047] 18 , 22 , and 23 , the two fourth electrodes 214 are located on the same side as the second electrode 212 in the thickness direction z and adjacent to the third electrode 213 in the first direction x. In the illustrated example, the two fourth electrodes 214 are arranged on both sides of the third electrode 213 in the first direction x, with the third electrode 213 sandwiched therebetween. The potential of each fourth electrode 214 is equal to the potential of the second electrode 212. Unlike the illustrated example, each semiconductor element 21 may include only one of the two fourth electrodes 214, or may include neither of the two fourth electrodes 214.

[0048] As shown in FIGS. 22 and 23 , the conductive bonding layer 23 is interposed between either the first mounting portion 1121 or the second mounting portion 1122 and the first electrode 211 of one of the multiple semiconductor elements 21. The conductive bonding layer 23 is, for example, solder. Alternatively, the conductive bonding layer 23 may include a sintered body of metal particles. The first electrodes 211 of the multiple first elements 21A are conductively bonded to the first mounting portion 1121 via the conductive bonding layer 23. As a result, each of the first electrodes 211 of the multiple first elements 21A is electrically connected to the first mounting portion 1121. The first electrodes 211 of the multiple second elements 21B are conductively bonded to the second mounting portion 1122 via the conductive bonding layer 23. As a result, each of the first electrodes 211 of the multiple second elements 21B is electrically connected to the second mounting portion 1122.

[0049] The plurality of power terminals 13 are electrically connected to the plurality of semiconductor elements 21, respectively. A current corresponding to the power before being converted by the plurality of semiconductor elements 21 or a current corresponding to the power after being converted by the plurality of semiconductor elements 21 flows through the plurality of power terminals 13. The plurality of power terminals 13 include a first power terminal 14, two second power terminals 15, and two third power terminals 16.

[0050] As shown in FIGS. 18 and 24 , the first power terminal 14 is joined to the first mounting portion 1121. This joining method is not limited to any particular method and may be performed using a conductive joining material (e.g., solder), laser welding, or crimping. The first power terminal 14 is electrically connected to the first electrodes 211 of the multiple first elements 21A via the first mounting portion 1121. The first power terminal 14 is a P terminal (positive electrode) to which a DC power supply voltage to be converted into power is applied. As shown in FIG. 18 , the first power terminal 14 is located on the opposite side of the second mounting portion 1122 in the first direction x, with the first mounting portion 1121 sandwiched therebetween. The first power terminal 14 extends from the first mounting portion 1121 to one side (x1 side) in the first direction x and protrudes from the sealing portion 50 to one side (x1 side) in the first direction x. 17 and 24 , the first power terminal 14 includes a portion covered by the sealing portion 50 and a portion exposed from the sealing portion 50. In the first power terminal 14, the portion covered by the sealing portion 50 is joined to the first mounting portion 1121. In addition, in the first power terminal 14, the portion exposed from the sealing portion 50 is used as the aforementioned P terminal of each semiconductor device B1.

[0051] A second conductive member 32 is joined to the two second power terminals 15. The two second power terminals 15 are electrically connected to the second electrodes 212 of the multiple second elements 21B via the second conductive member 32. The two second power terminals 15 are N terminals (negative electrodes) to which the DC power supply voltage to be converted is applied. The two second power terminals 15 are spaced apart from each other in the second direction y. The first power terminal 14 is located between the two second power terminals 15. As shown in FIG. 18 , the two second power terminals 15 are located on the same side as the first power terminal 14 with respect to the first mounting portion 1121 and the second mounting portion 1122 in the first direction x. The two second power terminals 15 are spaced apart from the first mounting portion 1121 and the second mounting portion 1122. Each of the two second power terminals 15 extends in the first direction x and protrudes from the sealing portion 50 to one side in the first direction x (x1 side). As shown in Figures 17 and 21 , each of the two second power terminals 15 includes a portion covered by the sealing portion 50 and a portion exposed from the sealing portion 50. In each second power terminal 15, a second conductive member 32 is joined to the portion covered by the sealing portion 50. In addition, in each second power terminal 15, the portion exposed from the sealing portion 50 is used as the aforementioned N terminal of each semiconductor device B1.

[0052] As shown in FIGS. 18 and 21 , the two third power terminals 16 are each joined to the second mounting portion 1122. This joining method is not limited to any particular method and may be performed using a conductive joining material (e.g., solder), laser welding, or crimping. Each of the two third power terminals 16 is electrically connected to the first electrodes 211 of the plurality of second elements 21B via the second mounting portion 1122. Each of the two third power terminals 16 is also electrically connected to the second electrodes 212 of the plurality of first elements 21A via the second mounting portion 1122 and the first conductive member 31. AC power converted by the plurality of semiconductor elements 21 (the plurality of first elements 21A and the plurality of second elements 21B) is output from the two third power terminals 16. In other words, each of the two third power terminals 16 is an output terminal for the AC power. The two third power terminals 16 are spaced apart from each other in the second direction y. As shown in FIG. 18 , the two third power terminals 16 are located on the opposite side of the first mounting portion 1121 in the first direction x, with the second mounting portion 1122 sandwiched between them. Each of the two third power terminals 16 extends from the second mounting portion 1122 toward the other side (x2 side) in the first direction x and protrudes from the sealing portion 50 toward the other side (x2 side) in the first direction x. As shown in FIGS. 17 and 21 , each of the two third power terminals 16 includes a portion covered by the sealing portion 50 and a portion exposed from the sealing portion 50. In each third power terminal 16, the portion covered by the sealing portion 50 is joined to the second mounting portion 1122. In addition, in each third power terminal 16, the portion exposed from the sealing portion 50 is used as the aforementioned output terminal of each semiconductor device B1.

[0053] The pair of control wirings 60 constitute part of the conductive paths between the plurality of signal terminals 17 and the plurality of semiconductor elements 21. As shown in FIGS. 17 , 18 , and 24 , the pair of control wirings 60 includes a first wiring 601 and a second wiring 602. The first wiring 601 is located between the plurality of first elements 21A and the first power terminal 14 and two second power terminals 15 in the first direction x. The first wiring 601 is bonded to the first mounting portion 1121 as shown in FIGS. 18 and 24 . The second wiring 602 is located between the plurality of second elements 21B and two third power terminals 16 in the first direction x. The second wiring 602 is bonded to the second mounting portion 1122 as shown in FIGS. 18 and 24 . The pair of control wirings 60 includes an insulating layer 61, a plurality of wiring layers 62, a metal layer 63, and a plurality of sleeves 64. The pair of control wirings 60 are covered by the sealing portion 50 except for a portion of each of the plurality of sleeves 64. Unless otherwise specified, the insulating layer 61, the plurality of wiring layers 62, the metal layer 63, and the plurality of sleeves 64 described below are common to the pair of control wirings 60 (first wiring 601 and second wiring 602).

[0054] 24 , the insulating layer 61 includes a portion interposed between the plurality of wiring layers 62 and the metal layer 63 in the thickness direction z. The insulating layer 61 is made of, for example, ceramics. The insulating layer 61 may be made of an insulating resin sheet instead of ceramics.

[0055] 24 , the multiple wiring layers 62 are located above (on the z1 side of) the insulating layer 61 in the thickness direction z. The multiple wiring layers 62 contain copper. As shown in FIG. 18 , the multiple wiring layers 62 include a first wiring layer 621, a second wiring layer 622, a third wiring layer 623, a fourth wiring layer 624, and a fifth wiring layer 625.

[0056] 24 , the metal layer 63 is located on the opposite side of the multiple wiring layers 62 in the thickness direction z, with the insulating layer 61 sandwiched therebetween. The metal layer 63 contains copper. The metal layer 63 of the first wiring 601 is bonded to the first mounting portion 1121 by an adhesive layer (not shown). The metal layer 63 of the second wiring 602 is bonded to the second mounting portion 1122 by an adhesive layer (not shown). These adhesive layers are made of materials that may or may not be conductive. For example, these adhesive layers are solder.

[0057] As shown in FIG. 24 , each of the multiple sleeves 64 is bonded to one of the multiple wiring layers 62 by a conductive bonding layer (e.g., solder) not shown. The multiple sleeves 64 are made of a conductive material such as metal. Each of the multiple sleeves 64 has a cylindrical shape extending along the thickness direction z. One end of each of the multiple sleeves 64 (the edge on the z2 side in the thickness direction z) is conductively bonded to one of the multiple wiring layers 62. As shown in FIG. 24 , the other end of each of the multiple sleeves 64 (the edge on the z1 side in the thickness direction z) is exposed from the sealing portion 50.

[0058] As shown in FIG. 18 , one of the pair of thermistors 22 straddles and is conductively joined to a pair of third wiring layers 623 of the first wiring 601. As shown in FIG. 18 , the other of the pair of thermistors 22 straddles and is conductively joined to a pair of third wiring layers 623 of the second wiring 602. Each of the pair of thermistors 22 is, for example, an NTC (Negative Temperature Coefficient) thermistor. NTC thermistors have the characteristic of gradually decreasing resistance as temperature increases. Each of the pair of thermistors 22 is used as a temperature detection sensor for the semiconductor device B1.

[0059] As shown in FIGS. 15 and 24 , each of the signal terminals 17 is a metal pin extending in the thickness direction z. The signal terminals 17 protrude from a top surface 51 (described later) of the sealing portion 50. The signal terminals 17 are individually press-fitted into the sleeves 64 of the pair of control wires 60. As a result, each of the signal terminals 17 is supported by one of the sleeves 64 and is electrically connected to one of the wiring layers 62. The signal terminals 17 include a first signal terminal 171, a second signal terminal 172, a third signal terminal 173, a fourth signal terminal 174, a pair of fifth signal terminals 181, a pair of sixth signal terminals 182, and a seventh signal terminal 19. These first signal terminal 171, second signal terminal 172, third signal terminal 173, fourth signal terminal 174, a pair of fifth signal terminals 181, a pair of sixth signal terminals 182 and seventh signal terminal 19 are inserted into wiring board E1 and input or output each signal to wiring board E1.

[0060] The first signal terminal 171 is press-fitted into one of the multiple sleeves 64 that is joined to the first wiring layer 621 of the first wiring 601. As a result, the first signal terminal 171 is supported by the sleeve 64 and is electrically connected to the first wiring layer 621 of the first wiring 601. Furthermore, the first signal terminal 171 is electrically connected to the third electrodes 213 of the multiple first elements 21A. A gate voltage for driving the multiple first elements 21A is applied to the first signal terminal 171.

[0061] The second signal terminal 172 is press-fitted into one of the multiple sleeves 64 that is joined to the first wiring layer 621 of the second wiring 602. As a result, the second signal terminal 172 is supported by the sleeve 64 and is electrically connected to the first wiring layer 621 of the second wiring 602. Furthermore, the second signal terminal 172 is electrically connected to the third electrodes 213 of the multiple second elements 21B. A gate voltage for driving the multiple second elements 21B is applied to the second signal terminal 172.

[0062] 18 , the third signal terminal 173 is located adjacent to the first signal terminal 171 in the second direction y. The third signal terminal 173 is press-fitted into one of the multiple sleeves 64 that is joined to the second wiring layer 622 of the first wiring 601. As a result, the third signal terminal 173 is supported by the sleeve 64 and is electrically connected to the second wiring layer 622 of the first wiring 601. Furthermore, the third signal terminal 173 is electrically connected to the fourth electrodes 214 of the multiple first elements 21A. A voltage corresponding to the maximum current among the currents flowing through the fourth electrodes 214 of the multiple first elements 21A is applied to the third signal terminal 173.

[0063] 8 , the fourth signal terminal 174 is located adjacent to the second signal terminal 172 in the second direction y. The fourth signal terminal 174 is press-fitted into one of the multiple sleeves 64 that is joined to the second wiring layer 622 of the second wiring 602. As a result, the fourth signal terminal 174 is supported by the sleeve 64 and is electrically connected to the second wiring layer 622 of the second wiring 602. Furthermore, the fourth signal terminal 174 is electrically connected to the fourth electrodes 214 of the multiple second elements 21B. A voltage corresponding to the maximum current among the currents flowing through the fourth electrodes 214 of the multiple second elements 21B is applied to the fourth signal terminal 174.

[0064] 18 , the pair of fifth signal terminals 181 are located on the opposite side of the first signal terminal 171 from the third signal terminal 173 in the second direction y. The pair of fifth signal terminals 181 are adjacent to each other in the second direction y. The pair of fifth signal terminals 181 are individually press-fitted into a pair of sleeves 64 that are respectively joined to a pair of third wiring layers 623 of the first wiring 601. As a result, the pair of fifth signal terminals 181 are individually supported by the pair of sleeves 64 and are individually electrically connected to the pair of third wiring layers 623 of the first wiring 601. Furthermore, the pair of fifth signal terminals 181 are electrically connected to the thermistor 22 on the first wiring 601.

[0065] 18 , the pair of sixth signal terminals 182 are located on the opposite side of the second signal terminal 172 from the fourth signal terminal 174 in the second direction y. The pair of sixth signal terminals 182 are adjacent to each other in the second direction y. The pair of sixth signal terminals 182 are individually press-fitted into a pair of sleeves 64 that are respectively joined to a pair of third wiring layers 623 of the second wiring 602. As a result, the pair of sixth signal terminals 182 are individually supported by the pair of sleeves 64 and are individually electrically connected to the pair of third wiring layers 623 of the second wiring 602. Furthermore, the pair of sixth signal terminals 182 are electrically connected to the thermistor 22 on the second wiring 602.

[0066] 18 , the seventh signal terminal 19 is located on the opposite side of the first signal terminal 171 in the second direction y, with the third signal terminal 173 sandwiched therebetween. The seventh signal terminal 19 is press-fitted into a sleeve 64 joined to the fifth wiring layer 625 of the first wiring 601. As a result, the seventh signal terminal 19 is supported by the sleeve 64 and is electrically connected to the fifth wiring layer 625 of the first wiring 601. Furthermore, the seventh signal terminal 19 is electrically connected to the first mounting portion 1121. A voltage equivalent to the DC power input to the first power terminal 14 is applied to the seventh signal terminal 19.

[0067] The plurality of first wires 41, the plurality of second wires 42, the plurality of third wires 43, and the fourth wire 44 electrically connect portions spaced apart from one another. The plurality of first wires 41, the plurality of second wires 42, the plurality of third wires 43, and the fourth wire 44 are each bonding wires. Note that the plurality of first wires 41, the plurality of second wires 42, the plurality of third wires 43, and the fourth wire 44 are omitted in Figure 17 and Figures 21 to 24.

[0068] As shown in FIG. 18 , some of the multiple first wires 41 are conductively joined to the third electrodes 213 of the multiple first elements 21A and the fourth wiring layer 624 of the first wiring 601. As shown in FIG. 18 , some of the multiple third wires 43 are conductively joined to the fourth wiring layer 624 of the first wiring 601 and the first wiring layer 621 of the first wiring 601. This allows the first signal terminal 171 to be conductively connected to the third electrodes 213 of the multiple first elements 21A. The composition of the multiple first wires 41 and the multiple third wires 43 includes gold (Au). Alternatively, the composition of the multiple first wires 41 and the multiple third wires 43 may include copper or aluminum.

[0069] 18, some of the plurality of first wires 41 are conductively joined to the third electrodes 213 of the plurality of second elements 21B and the fourth wiring layer 624 of the second wiring 602. Furthermore, some of the plurality of third wires 43 are conductively joined to the fourth wiring layer 624 of the second wiring 602 and the first wiring layer 621 of the second wiring 602. As a result, the second signal terminal 172 is electrically connected to the third electrodes 213 of the plurality of second elements 21B.

[0070] As shown in FIG. 18 , some of the multiple second wires 42 are conductively bonded to either of the two fourth electrodes 214 of the multiple first elements 21A and the second wiring layer 622 of the first wiring 601. As a result, the third signal terminal 173 is electrically connected to either of the two fourth electrodes 214 of the multiple first elements 21A. Furthermore, as shown in FIG. 18 , some of the multiple second wires 42 are conductively bonded to either of the two fourth electrodes 214 of the multiple second elements 21B and the second wiring layer 622 of the second wiring 602. As a result, the fourth signal terminal 174 is electrically connected to either of the two fourth electrodes 214 of the multiple second elements 21B. The composition of the multiple second wires 42 includes gold. Alternatively, the composition of the multiple second wires 42 may include copper or aluminum. In addition, if each semiconductor element 21 (each of the multiple first elements 21A and the multiple second elements 21B) does not include either of the two fourth electrodes 214, the multiple second wires 42 are joined one by one to the second electrodes 212 of the multiple semiconductor elements 21.

[0071] 18 , the fourth wire 44 is conductively bonded to the fifth wiring layer 625 of the first wiring 601 and the first mounting portion 1121. As a result, the seventh signal terminal 19 is electrically connected to the first electrodes 211 of the multiple first elements 21A via the first mounting portion 1121. The composition of the fourth wire 44 includes gold. Alternatively, the composition of the fourth wire 44 may include copper or aluminum.

[0072] As shown in Figures 18 and 21 , the first conductive member 31 is conductively bonded to the second electrodes 212 of the multiple first elements 21A and the second mounting portion 1122. This allows the second electrodes 212 of the multiple first elements 21A to be electrically connected to the second mounting portion 1122. The first conductive member 31 contains copper. The first conductive member 31 is a metal clip. As shown in Figures 18 and 21 , the first conductive member 31 has a main body 311, multiple first joint portions 312, and multiple second joint portions 313.

[0073] The main body portion 311 forms a major portion of the first conductive member 31. As shown in FIG. 18 , the main body portion 311 extends in the first direction x. As shown in FIGS. 18 and 21 , the main body portion 311 straddles the first mounting portion 1121 and the second mounting portion 1122. In the example shown in FIG. 18 , a plurality of through holes are formed in the main body portion 311. Each of the plurality of through holes penetrates the main body portion 311 in the thickness direction z. In a plan view, the plurality of through holes overlap between the first mounting portion 1121 and the second mounting portion 1122. This allows the sealing portion 50 to flow smoothly downward in the thickness direction z of the main body portion 311 (toward the z2 side in the thickness direction z) during the formation of the sealing portion 50.

[0074] As shown in FIGS. 18 , 21 , and 22 , the multiple first joints 312 are individually joined to the second electrodes 212 of the multiple first elements 21A. Each of the multiple first joints 312 faces one of the second electrodes 212 of the multiple first elements 21A. In a plan view, each first joint 312 extends from the main body 311 toward the x1 side in the first direction x. In the illustrated example, the multiple first joints 312 are bifurcated from the main body 311, but they do not necessarily need to be bifurcated. The base end of each first joint 312 (the end connected to the main body 311) is bent downward in the thickness direction z (toward the z2 side in the thickness direction z). Therefore, the tip of each first joint 312 (the end opposite to the end connected to the main body 311) is located downward in the thickness direction z (toward the z2 side in the thickness direction z) relative to the main body 311 in the thickness direction z.

[0075] 18 and 21 , the multiple second joint portions 313 are joined to the second mounting portion 1122. Each of the multiple second joint portions 313 faces the second mounting portion 1122. In a plan view, each second joint portion 313 extends from the main body portion 311 toward the x2 side in the first direction x. The base end of each second joint portion 313 (the end connected to the main body portion 311) is bent downward in the thickness direction z (toward the z2 side in the thickness direction z). Therefore, the tip end of each second joint portion 313 (the end opposite to the end connected to the main body portion 311) is located downward in the thickness direction z (toward the z2 side in the thickness direction z) relative to the main body portion 311 in the thickness direction z.

[0076] 22 , the semiconductor device B1 further includes a first conductive bonding layer 33. The first conductive bonding layer 33 is interposed between the second electrodes 212 of the plurality of first elements 21A and the plurality of first bonding portions 312. The first conductive bonding layer 33 conductively bonds the second electrodes 212 of the plurality of first elements 21A to the plurality of first bonding portions 312. The first conductive bonding layer 33 is, for example, solder. Alternatively, the first conductive bonding layer 33 may include a sintered body of metal particles.

[0077] 21 , the semiconductor device B1 further includes a second conductive bonding layer 34. The second conductive bonding layer 34 is interposed between the second mounting portion 1122 and the second bonding portion 313. The second conductive bonding layer 34 conductively bonds the second mounting portion 1122 and the second bonding portion 313. The second conductive bonding layer 34 is, for example, solder. Alternatively, the second conductive bonding layer 34 may include a sintered body of metal particles.

[0078] As shown in Fig. 17 , the second conductive member 32 is conductively joined to the second electrodes 212 of the plurality of second elements 21B and the two second power terminals 15. As a result, the second electrodes 212 of the plurality of second elements 21B are electrically connected to the two second power terminals 15. The second conductive member 32 contains copper. The second conductive member 32 is a metal clip. As shown in Figs. 17 and 21 to 26 , the second conductive member 32 includes a main body portion 321, a plurality of third joint portions 322, and a pair of fourth joint portions 323.

[0079] The main body 321 forms a main part of the second conductive member 32. As shown in Figures 21 and 25, the main body 321 is disposed parallel (or approximately parallel) to the upper surface of the first mounting portion 1121 and the upper surface of the second mounting portion 1122. The main body 321 is spaced apart from the main body 311 of the first conductive member 31, and is also spaced apart from the first mounting portion 1121 and the second mounting portion 1122.

[0080] As shown in FIGS. 17 , 21 , and 23 , the third joints 322 are individually joined to the second electrodes 212 of the second elements 21B. Each of the third joints 322 faces one of the second electrodes 212 of the second elements 21B. In a plan view, the third joints 322 extend in the first direction x from the main body 321. The base end of each third joint 322 (the end connected to the main body 321) is bent downward in the thickness direction z (toward the z2 side in the thickness direction z). Therefore, the tip of each third joint 322 (the end opposite to the end connected to the main body 321) is located downward in the thickness direction z (toward the z2 side in the thickness direction z) from the main body 321 in the thickness direction z.

[0081] 17 and 21 , the pair of fourth joint portions 323 are individually joined to the two second power terminals 15. Each of the pair of fourth joint portions 323 faces a corresponding one of the two second power terminals 15.

[0082] 23 , the semiconductor device B1 further includes a third conductive bonding layer 35. The third conductive bonding layer 35 is interposed between the second electrodes 212 of the plurality of second elements 21B and the plurality of third bonding portions 322. The third conductive bonding layer 35 conductively bonds the second electrodes 212 of the plurality of second elements 21B to the plurality of third bonding portions 322. The third conductive bonding layer 35 is, for example, solder. Alternatively, the third conductive bonding layer 35 may include a sintered body of metal particles.

[0083] 21 , the semiconductor device B1 further includes a fourth conductive bonding layer 36. The fourth conductive bonding layer 36 is interposed between the two second power terminals 15 and the pair of fourth joints 323. The fourth conductive bonding layer 36 conductively bonds the two second power terminals 15 and the pair of fourth joints 323. The fourth conductive bonding layer 36 is, for example, solder. Alternatively, the fourth conductive bonding layer 36 may include a sintered body of metal particles.

[0084] As shown in FIGS. 15 to 26 , the sealing portion 50 covers the semiconductor elements 21, the first conductive members 31, the second conductive members 32, the first wires 41, the second wires 42, the third wires 43, and the fourth wires 44. Furthermore, the sealing portion 50 covers a portion of each of the support substrate 11, the power terminals 13, and the signal terminals 17. The sealing portion 50 has electrical insulation properties. The sealing portion 50 contains, for example, a black epoxy resin. The sealing portion 50 is formed, for example, by molding. As shown in FIGS. 15 to 17 and 19 to 26 , the sealing portion 50 has a top surface 51, a bottom surface 52, a plurality of resin side surfaces 53, and a pair of recesses 55.

[0085] As shown in Figures 21 and 24 to 26, the top surface 51 faces the same direction as the upper surfaces of the first mounting portion 1121 and the second mounting portion 1122 in the thickness direction z. The top surface 51 of each semiconductor device B1 contacts the mounting member D1. As shown in Figures 19, 21, and 24 to 26, the bottom surface 52 faces the opposite side from the top surface 51 in the thickness direction z. As shown in Figures 20, 21, and 24 to 26, the second wiring layer 113 of the support substrate 11 is exposed from the bottom surface 52. The bottom surface 52 of each semiconductor device B1 contacts the main body portion 71 of the mounting object C1.

[0086] The plurality of resin side surfaces 53 are connected to the top surface 51. The plurality of resin side surfaces 53 include a pair of first side surfaces 531 and a pair of second side surfaces 532.

[0087] As shown in Figures 16, 17, 19 to 21, and 24, the pair of first side surfaces 531 are spaced apart from each other in the first direction x. The pair of first side surfaces 531 face opposite each other in the first direction x and extend in the second direction y. The pair of first side surfaces 531 are connected to the top surface 51. A first power terminal 14 and two second power terminals 15 each protrude from the first side surface 531 on the x1 side in the first direction x. Two third power terminals 16 each protrude from the first side surface 531 on the x2 side in the first direction x.

[0088] 16 , 17 , 20 , 25 , and 26 , the pair of second side surfaces 532 are spaced apart from each other in the second direction y. The pair of second side surfaces 532 face opposite each other in the second direction y and extend in the first direction x. The pair of second side surfaces 532 are connected to the top surface 51 and the bottom surface 52.

[0089] 16 , 17 , and 20 , the pair of recesses 55 are recessed in the first direction x from the first side surface 531 on the x1 side in the first direction x of the pair of first side surfaces 531. The pair of recesses 55 extend from the top surface 51 to the bottom surface 52 in the thickness direction z. The pair of recesses 55 are located on both sides of the first power terminal 14 in the second direction y.

[0090] The specific configuration of the semiconductor device B1 described above is merely an example and is not limited to the above example. For example, the number of signal terminals 17, the signals input / output to / from each signal terminal 17, the number of semiconductor elements 21, the configuration of the first wiring 601 and the second wiring 602, and the like may be changed as appropriate. Furthermore, the support substrate 11 may have a conductive plate-like member bonded to the first wiring layer 112 (each of the first mounting portion 1121 and the second mounting portion 1122). In this case, the plurality of semiconductor elements 21 (each of the plurality of first elements 21A and the plurality of second elements 21B) and a pair of control wirings 60 are mounted on the conductive plate-like member.

[0091] The power conversion unit A10 has the following functions and effects.

[0092] In the power conversion unit A10, the mounting member D1 includes a fixing portion 82 fixed to the mounting object C1 and a pressing portion 81 that presses the multiple semiconductor devices B1 against the main body portion 71 (mounting object C1). With this configuration, the mounting member D1 presses the multiple semiconductor devices B1 against the main body portion 71, thereby preventing gaps from forming between the mounting object C1 and each semiconductor device B1. Therefore, the power conversion unit A10 can suppress a decrease in heat dissipation. In particular, in the power conversion unit A10, a single mounting member D1 applies a pressing force to the multiple semiconductor devices B1. This configuration allows the distance between two adjacent semiconductor devices B1 in the second direction y to be smaller than when a mounting member is attached individually to each semiconductor device B1. In other words, the power conversion unit A10 can reduce the planar area while suppressing a decrease in heat dissipation.

[0093] In the power conversion unit A10, the fixing portion 82 of the mounting member D1 is attached to the main body 71 of the mounting target C1, and the pressing portion 81 of the mounting member D1 contacts the upper surface of the sealing portion 50 of the semiconductor device B1. In this configuration, the mounting member D1 bends upward in the thickness direction z from the fixing portion 82 on the y1 side of the second direction y of each semiconductor device B1 along the sealing portion 50 to connect to the pressing portion 81. The pressing portion 81 also bends downward in the thickness direction z along the sealing portion 50 to connect to the fixing portion 82 on the y2 side of the second direction y. Therefore, the sealing portion 50 of each semiconductor device B1 has its side in the second direction y surrounded by the mounting member D1. In other words, the power conversion unit A10 can limit misalignment of each semiconductor device B1 in the second direction y.

[0094] In the power conversion unit A10, the mounting object C1 includes a plurality of pedestals 72 protruding upward in the thickness direction z from the main body 71. Each of the plurality of pedestals 72 holds a wiring substrate E1. With this configuration, the wiring substrate E1 can be positioned at a fixed distance in the thickness direction z from each sealing portion 50 of the plurality of semiconductor devices B1. Therefore, misalignment in the thickness direction z between the bulging portion 170B of each signal terminal 17 and each through-hole 911 can be suppressed, and therefore the power conversion unit A10 can suppress poor conductivity between each signal terminal 17 and the wiring substrate E1.

[0095] In the power conversion unit A10, the attachment object C1 includes a positioning portion 73 that protrudes upward in the thickness direction z from a main body portion 71. The positioning portion 73 is inserted into a positioning hole 952 of the wiring substrate E1. This configuration makes it easy to position the wiring substrate E1.

[0096] In the power conversion unit A10, the sealing portion 50 of each semiconductor device B1 does not have a through-hole or the like formed therein for attaching the semiconductor device B1 to the attachment object C1. To provide such a through-hole in the sealing portion 50 would require expanding the planar area of ​​the sealing portion 50. In this case, the planar area of ​​the semiconductor device B1 would be increased, making it difficult to miniaturize the power conversion unit A10. On the other hand, in the power conversion unit A10, each semiconductor device B1 can be attached to the attachment object C1 using the attachment member D1. As described above, therefore, there is no need to form a through-hole or the like in each semiconductor device B1 for attaching it to the attachment object C1. Therefore, the planar area of ​​the sealing portion 50 in each semiconductor device B1 can be minimized, thereby enabling the power conversion unit A10 to have a reduced planar area.

[0097] Other embodiments and modifications of the power conversion unit of the present disclosure will be described below. The configurations of the components in the embodiments and modifications can be combined with each other to the extent that no technical contradiction occurs.

[0098] 27 to 30 show a power conversion unit A20 according to the second embodiment. The power conversion unit A20 differs from the power conversion unit A10 in the configuration of the mounting member D1. Specifically, the mounting member D1 of the power conversion unit A20 is entirely located on the z1 side in the thickness direction z relative to the sealing portion 50 of each semiconductor device B1.

[0099] In the mounting member D1, each fixing portion 82 (each of the end-arrangement portions 821 and each of the intermediate arrangement portions 822) is fixed to a corresponding one of the plurality of pedestal portions 72. At this time, each fixing portion 82 is sandwiched between the first portion 721 and the second portion 722 of the corresponding pedestal portion 72.

[0100] In the illustrated example, each fixing portion 82 is strip-shaped in plan view with its longitudinal direction aligned in the first direction x. The dimension of each fixing portion 82 in the first direction x is greater than the dimension of the pressing portion 81 in the first direction x. Two through holes 851 are formed in each fixing portion 82. Each of the two through holes 851 overlaps a corresponding one of the base portions 72 in plan view. The second portion 722 of the base portion 72 is inserted into each through hole 851 together with the mounting hole 951.

[0101] In the power conversion unit A20, a through hole 852 is formed in each of the two-end arrangement portions 821 of the multiple fixing portions 82. In each of the two-end arrangement portions 821, the positioning portion 73 is inserted into the through hole 852 together with the positioning hole 952.

[0102] The mounting member D1 of the power conversion unit A20 bends downward in the thickness direction z from a fixing portion 82 on the y1 side in the second direction y of each semiconductor device B1 to connect to a pressing portion 81. The mounting member D1 also bends upward in the thickness direction z from the pressing portion 81 to connect to a fixing portion 82 on the y2 side in the second direction y. The portion connecting the pressing portion 81 and fixing portion 82 adjacent to each other in the second direction y is inclined with respect to the xy plane.

[0103] In the power conversion unit A20, as in the power conversion unit A10, the mounting member D1 includes a fixing portion 82 fixed to the mounting object C1 and a pressing portion 81 that presses the multiple semiconductor devices B1 against the main body portion 71 (mounting object C1). Therefore, as in the power conversion unit A10, the power conversion unit A20 can prevent gaps from forming between the mounting object C1 and each semiconductor device B1, thereby suppressing a decrease in heat dissipation. In particular, as in the power conversion unit A10, the power conversion unit A20 applies a pressing force to the multiple semiconductor devices B1 with a single mounting member D1, thereby suppressing a decrease in heat dissipation and reducing the planar area of ​​the power conversion unit A10.

[0104] In the power conversion unit A20, the fixing portion 82 of the mounting member D1 is fixed to the base portion 72. With this configuration, the mounting member D1 can be attached to the base portion 72 for attaching the wiring board E1, so there is no need to form a hole for attaching the mounting member D1 in the main body portion 71. In other words, the power conversion unit A20 does not require any processing to attach the mounting member D1 to the attachment object C1.

[0105] 31 to 33 show a power conversion unit A21 according to a first modified example of the second embodiment. The power conversion unit A21 differs from the power conversion unit A20 in the following respect: the fixing portion 82 of the mounting member D1 does not include an intermediate portion 822.

[0106] As shown in FIG. 32 , the mounting member D1 of this modified example curves slightly upward in the thickness direction z between the pressing portion 81 for the first device B11 and the pressing portion 81 for the third device B13. As shown in FIG. 33 , the mounting member D1 of this modified example has the following configuration before being attached to the mounting object C1. The pressing portions 81 corresponding to the first device B11 and the third device B13 are located lower in the thickness direction z (on the z2 side) than the respective end-arrangement portions 821. The pressing portion 81 corresponding to the second device B12 is located lower in the thickness direction z (on the z2 side) than the respective pressing portions 81 corresponding to the first device B11 and the third device B13. When attaching such a mounting member D1 to the mounting object C1, the pressing portion 81 corresponding to the second device B12 first contacts the sealing portion 50 of the second device B12. When the mounting member D1 is further pressed downward in the thickness direction z, the pressing portion 81 for the second device B12 remains engaged with the second device B12, and then the pressing portions 81 for the first device B11 and the third device B13 come into contact with the sealing portions 50 of the corresponding first device B11 and third device B13. At this time, the portion between two pressing portions 81 adjacent in the second direction y curves upward in the thickness direction z relative to the two pressing portions 81. In this way, by elastically deforming the mounting member D1 as shown in FIG. 32 , a downward pressing force in the thickness direction z is generated on the multiple semiconductor devices B1 even without the intermediate arrangement portion 822.

[0107] 34 to 36 show a power conversion unit A22 according to a second modified example of the second embodiment. The power conversion unit A22 differs from the power conversion unit A20 in the following respect: the mounting member D1 includes a plurality of abutting portions 83. The abutting portions 83 are formed in place of the plurality of intermediate portions 822. In other words, in the mounting member D1 of this modified example, the plurality of fixing portions 82 do not include any of the plurality of intermediate portions 822.

[0108] In the mounting member D1 of the power conversion unit A22, the multiple abutting portions 83 contact the underside of the wiring board E1 (the surface facing the z2 side in the thickness direction z). This causes each abutting portion 83 to engage with the wiring board E1. In the mounting member D1 of this modified example, the multiple abutting portions 83 are pressed against the wiring board E1 toward the z2 side in the thickness direction z, generating an elastic force in the mounting member D1, and the pressing portions 81 press the semiconductor device B1 against the mounting object C1.

[0109] The power conversion units A21 and A22 according to the first and second modifications of the second embodiment have the same effects as the power conversion unit A20.

[0110] 37 to 39 show a power conversion unit A30 according to the third embodiment. The power conversion unit A30 differs from the power conversion unit A10 in the following respects: The power conversion unit A30 includes a plurality of attachment members D1.

[0111] 37 and 38, each of the plurality of mounting members D1 holds a corresponding one of the plurality of semiconductor devices B1 on a mounting object C1. As shown in Fig. 37, each mounting member D1 includes a pressing portion 81 and a pair of fixing portions 82A, 82B.

[0112] The pair of fixing portions 82A, 82B are arranged at both ends of the corresponding semiconductor device B1 in the second direction y. The fixing portion 82A is located on the y1 side in the second direction y relative to the fixing portion 82B. The pair of fixing portions 82A, 82B do not overlap with each other when viewed in the second direction y. The fixing portion 82A is arranged offset in the first direction x relative to the fixing portion 82B. In the illustrated example, the fixing portion 82A is located on the x2 side in the first direction x relative to the fixing portion 82B.

[0113] The fixing portion 82B of the mounting member D1 holding the first device B11 and the fixing portion 82A of the mounting member D1 holding the second device B12 overlap when viewed in the first direction x. Furthermore, the fixing portion 82B of the mounting member D1 holding the second device B12 and the fixing portion 82A of the mounting member D1 holding the third device B13 overlap when viewed in the first direction x. With this configuration, the pairs of fixing portions 82A, 82B are alternately arranged on two mounting members D1 adjacent to each other in the second direction y.

[0114] In the power conversion unit A30, the multiple mounting members D1 press the multiple semiconductor devices B1 individually against the main body 71, thereby preventing gaps from forming between the mounting object C1 and each semiconductor device B1, for example. Therefore, the power conversion unit A30 can prevent a decrease in heat dissipation performance.

[0115] Furthermore, in the power conversion unit A30, for two mounting members D1 adjacent to each other in the second direction y, the fixing portion 82B of the mounting member D1 on the y1 side in the second direction y and the fixing portion 82A of the mounting member D1 on the y2 side in the second direction y overlap when viewed in the first direction x. With this configuration, these fixing portions 82A, 82B are arranged side by side in the first direction x. Therefore, the dimension of the power conversion unit A30 in the second direction y is reduced compared to when these fixing portions 82A, 82B are arranged side by side in the second direction y. In other words, even when a mounting member D1 is provided for each semiconductor device B1, the power conversion unit A30 can achieve a reduced planar area.

[0116] In an example different from the first to third embodiments (including their variations), the attachment object C1 may not include the positioning portions 73. For example, FIG. 40 shows a power conversion unit according to this variation, which is a configuration example in which the attachment object C1 does not include the positioning portions 73 in the power conversion unit A10. The power conversion unit shown in FIG. 40 can increase the dimension of each end-arrangement portion 821 in the first direction x compared to the power conversion unit A10. Therefore, in the power conversion unit shown in FIG. 40, the rigidity of the attachment member D1 can be increased compared to the power conversion unit A10, making it possible to generate a greater elastic force (pressing force on each semiconductor device B1).

[0117] The power conversion unit according to the present disclosure is not limited to the above-described embodiments. The specific configuration of each part of the power conversion unit according to the present disclosure can be freely designed in various ways. For example, the power conversion unit according to the present disclosure includes the following embodiments. Supplementary Note 1. A power conversion unit comprising: a plurality of semiconductor devices, each including a semiconductor element and a sealing portion covering the semiconductor element; an attachment object including a main body portion in contact with the plurality of semiconductor devices; and a mounting member for holding the plurality of semiconductor devices on the attachment object, wherein the one mounting member includes a fixing portion fixed to the attachment object and a pressing portion for pressing the plurality of semiconductor devices against the main body portion. Supplementary Note 2. The power conversion unit according to Supplementary Note 1, wherein each of the plurality of semiconductor devices comprises a signal terminal protruding from the sealing portion in one direction in a thickness direction of the sealing portion. Supplementary Note 3. The power conversion unit according to Supplementary Note 2, wherein each of the plurality of semiconductor devices comprises a power terminal protruding from the sealing portion in a first direction perpendicular to the thickness direction, and the plurality of semiconductor devices are arranged in a second direction perpendicular to the thickness direction and the first direction. Supplementary Note 4. The power conversion unit according to Supplementary Note 3, wherein the fixing portion is located on one side in the thickness direction relative to the sealing portion of each of the plurality of semiconductor devices. Supplementary Note 5. The power conversion unit according to Supplementary Note 4, wherein the attachment object includes a base portion protruding from the main body portion in the one side in the thickness direction, and the fixing portion is attached to the base portion. Supplementary Note 6. The power conversion unit according to Supplementary Note 5, wherein the entire one attachment member is located on the one side in the first direction relative to the sealing portion of each of the plurality of semiconductor devices, and the pressing portion is located on the other side in the thickness direction relative to the fixing portion. Supplementary Note 7. The power conversion unit according to Supplementary Note 3, wherein the fixing portion is located on the other side in the thickness direction relative to the sealing portion of each of the plurality of semiconductor devices. Supplementary Note 8. The power conversion unit according to Supplementary Note 7, wherein the fixing portion is attached to the main body portion. Supplementary Note 9. The power conversion unit according to any of Supplements 3 to 8, wherein the fixing portion includes double-ended portions that are arranged on both ends of the plurality of semiconductor devices in the second direction.Supplementary Note 10. The power conversion unit according to Supplementary Note 9, wherein the fixing portion includes an intermediate portion disposed between the plurality of semiconductor devices in the second direction. Supplementary Note 11. The power conversion unit according to any of Supplements 3 to 10, further comprising a control board that controls the semiconductor elements of each of the plurality of semiconductor devices. Supplementary Note 12. The power conversion unit according to Supplementary Note 11, wherein a plurality of through holes are formed in the control board, and the signal terminal of each of the plurality of semiconductor devices is inserted into one of the plurality of through holes. Supplementary Note 13. The power conversion unit according to Supplementary Note 12, wherein the signal terminal of each of the plurality of semiconductor devices is a press-fit terminal. Supplementary Note 14. The power conversion unit according to any of Supplements 11 to 13, wherein the one mounting member is located between the control board and the mounting object in the thickness direction. Supplementary Note 15. The power conversion unit according to any one of Supplementary Note 3 to Supplementary Note 14, wherein each of the plurality of semiconductor devices includes a support substrate on which the semiconductor element is mounted, the support substrate of each of the plurality of semiconductor devices has a bottom surface facing the other side in the thickness direction, and in each of the plurality of semiconductor devices, the bottom surface is exposed from the sealing portion and in contact with the main body portion.Supplementary Note 16. The power conversion unit according to any one of Supplementary Note 1 to Supplementary Note 15, wherein the attachment object is a heat sink.

[0118] A10, A20, A21, A22, A30: Power conversion unit B1: Semiconductor device B11: First device B12: Second device B13: Third device C1: Mounting object D1: Mounting member E1: Wiring board 11: Support substrate 111: Insulating layer 112: First wiring layer 1121: First mounting portion 1122: Second mounting portion 113: Second wiring layer 13: Power terminal 14: First power terminal 15: Second power terminal 16: Third power terminal 17: Signal terminal 170A: Base 170B: Bulging portion 171: First signal terminal 172: Second signal terminal 173: Third signal terminal 174: Fourth signal terminal 181: Fifth signal terminal 182: Sixth signal terminal 19: Seventh signal terminal 21: Semiconductor element 21A: First element 21B: Second element 211: First electrode 212: Second electrode 213: Third electrode 214: Fourth electrode 22: Thermistor 23: Conductive bonding layer 31: First conductive member 311: Main body 312: First bonding portion 313: Second bonding portion 32: Second conductive member 321: Main body 322: Third bonding portion 323: Fourth bonding portion 33: First conductive bonding layer 34: Second conductive bonding layer 35: Third conductive bonding layer 36: Fourth conductive bonding layer 41: First wire 42: Second wire 43: Third wire 44: Fourth wire 50: Sealing portion 51: Top surface 52: Bottom surface 53: Resin side surface 531: First side surface 532: Second side surface 55: Recess 60: Control wiring 601: First wiring 602: Second wiring 61: Insulating layer 62: Wiring layer 621: First wiring layer 622: Second wiring layer 623: Third wiring layer 624: Fourth wiring layer 625: Fifth wiring layer 63: Metal layer 64: Sleeve 71: Main body 72: Base 721: First part 722: Second part 73: Positioning part 81: Pressing part 82, 82A, 82B: Fixing part 821: Both end arrangement parts 822: Middle arrangement part 83: Contact part 851: Through hole 852: Through hole 89: Fastener 91: Substrate 911: Through hole 92: Main part wiring 93: Back part wiring 94: Internal wiring 951: Mounting hole 952: Positioning hole

Claims

1. A plurality of semiconductor devices each including a semiconductor element and a sealing portion covering the semiconductor element; an attachment object including a main body portion in contact with the plurality of semiconductor devices; a mounting member for holding the plurality of semiconductor devices on the mounting object; Equipped with The one mounting member includes a fixing portion fixed to the mounting object, and a pressing portion pressing the plurality of semiconductor devices against the main body portion.

2. The power conversion unit according to claim 1 , wherein each of the plurality of semiconductor devices includes a signal terminal protruding from the sealing portion to one side in a thickness direction of the sealing portion.

3. Each of the plurality of semiconductor devices includes a power terminal protruding from the sealing portion in a first direction perpendicular to the thickness direction, The power conversion unit according to claim 2 , wherein the plurality of semiconductor devices are arranged in a second direction perpendicular to the thickness direction and the first direction.

4. The power conversion unit according to claim 3 , wherein the fixing portion is located on the one side in the thickness direction relative to the sealing portion of each of the plurality of semiconductor devices.

5. the attachment object includes a base portion protruding from the main body portion to the one side in the thickness direction, The power conversion unit according to claim 4 , wherein the fixing portion is attached to the base portion.

6. the one mounting member is located entirely on the one side in the first direction relative to the sealing portions of the plurality of semiconductor devices, The power conversion unit according to claim 5 , wherein the pressing portion is located on the other side of the fixing portion in the thickness direction.

7. The power conversion unit according to claim 3 , wherein the fixing portion is located on the other side in the thickness direction than the sealing portion of each of the plurality of semiconductor devices.

8. The power conversion unit according to claim 7 , wherein the fixing portion is attached to the main body portion.

9. The power conversion unit according to claim 3 , wherein the fixing portion includes two-end arrangement portions that are arranged on both ends of the plurality of semiconductor devices in the second direction.

10. The power conversion unit according to claim 9 , wherein the fixed portion includes an intermediate portion disposed between the plurality of semiconductor devices in the second direction.

11. The power conversion unit according to claim 3 , further comprising a control board that controls the semiconductor element of each of the plurality of semiconductor devices.

12. The control board has a plurality of through holes formed therein, The power conversion unit according to claim 11 , wherein the signal terminal of each of the plurality of semiconductor devices is inserted into one of the plurality of through holes.

13. The power conversion unit according to claim 12 , wherein the signal terminal of each of the plurality of semiconductor devices is a press-fit terminal.

14. The power conversion unit according to claim 11 , wherein the one mounting member is located between the control board and the mounting object in the thickness direction.

15. Each of the plurality of semiconductor devices includes a support substrate on which the semiconductor element is mounted, the supporting substrate of each of the plurality of semiconductor devices has a bottom surface facing the other side in the thickness direction, The power conversion unit according to claim 3 , wherein the bottom surface of each of the plurality of semiconductor devices is exposed from the sealing portion and is in contact with the main body portion.

16. 16. The power conversion unit according to claim 1, wherein the object to be attached is a heat sink.