Signal transmission device

Abstract

This signal transmission device comprises: a first chip including a first transformer, a second chip, a plurality of first terminals, a plurality of second terminals, a plurality of third terminals, inter-chip wires, and a plurality of first terminal wires. The inter-chip wire individually connects the first chip and the second chip. The inter-chip wire individually connects the first chip and the third chip. The first terminal wires individually electrically connect the first chip and a plurality of first ends. The inter-chip wire is made of a material containing gold. The first terminal wire is made of a material containing copper or aluminum.

Description

signal transmission device

[0001] The present disclosure relates to a signal transmission device.

[0002] A signal transmission device has been known that includes a first die pad, a second die pad disposed at a distance from the first die pad, a first chip and a transformer chip mounted on the first die pad, a second chip mounted on the second die pad, and a sealing resin that seals the die pads and chips (see, for example, Patent Document 1). In such a signal transmission device, the first chip and the transformer chip are electrically connected by a wire, and the transformer chip and the second chip are electrically connected by another wire.

[0003] Japanese Patent Application Laid-Open No. 2016-207714

[0004] From the viewpoint of the insulation reliability of the signal transmission device, it is desired to inspect the shape and height of the inter-chip wires that electrically connect adjacent chips with each other with higher accuracy.

[0005] a third chip receiving signals from the first chip and transmitting signals to the first chip; a first die pad on which the first chip is mounted, the second die pad being spaced apart from the first die pad in a first direction, a second die pad on which the second chip is mounted, the second die pad being spaced apart from the first die pad in the first direction and spaced apart from the second die pad in a second direction perpendicular to the first direction in a plan view; a third die pad on which the third chip is mounted, the third die pad being spaced apart from the first chip and the second die pad in a second direction perpendicular to the first direction in a plan view; a third die pad on which the third chip is mounted, the third die pad being spaced apart from the second chip and the third chip in a second direction perpendicular to the first direction in a plan view; a plurality of second terminals arranged in a straight line in the first direction, a plurality of third terminals disposed on an opposite side of the third chip from the first chip in the first direction and arranged in the second direction; inter-chip wires individually connecting the first chip to the second chip and the third chip; first terminal wires individually and electrically connecting the first chip to the plurality of first terminals; and a sealing resin having a sealing front surface and a sealing back surface facing opposite to each other in a third direction orthogonal to both the first direction and the second direction, and sealing the first chip, the second chip, the third chip, the first die pad, the second die pad, the third die pad, the inter-chip wires, the first terminal wires, the plurality of first terminals, the plurality of second terminals, and the plurality of third terminals, wherein each of the first terminals, each of the second terminals, and each of the third terminals is exposed from the sealing back surface, and the inter-chip wires are formed of a material containing gold, and the first terminal wires are formed of a material containing copper or aluminum.

[0006] According to the signal transmission device, the wire height of the inter-chip wires can be inspected with higher accuracy.

[0007] FIG. 1 is a perspective view of a signal transmission device according to a first embodiment. FIG. 2 is a rear view of the signal transmission device of FIG. 1. FIG. 3 is a schematic plan view showing the internal configuration of the signal transmission device of FIG. 1. FIG. 4 is a schematic cross-sectional view of the signal transmission device taken along line F4-F4 of FIG. 3. FIG. 5 is an enlarged view of the first die pad and its periphery of FIG. 3. FIG. 6 is a schematic cross-sectional view of a first internal terminal portion of a first terminal. FIG. 7 is an enlarged view of the second die pad and third die pad and their periphery of FIG. 3. FIG. 8 is a schematic cross-sectional view of a second internal terminal portion of a second terminal. FIG. 9 is a circuit diagram of a signal transmission device according to a first embodiment. FIG. 10 is a schematic plan view showing an example of the internal structure of a first chip in the signal transmission device according to the first embodiment. FIG. 11 is an enlarged plan view of the transformer region of FIG. 10. FIG. 12 is a schematic plan view showing an example of the internal structure of the first chip at a position different from that of FIG. 10 in the thickness direction of the first chip. FIG. 13 is an enlarged plan view of the transformer region of FIG. 11. FIG. 14 is a cross-sectional view showing the cross-sectional structure of the first chip taken along line F14-F14 in FIG. 10. FIG. 15 is an enlarged view of a portion of the first chip in FIG. 14. FIG. 16 is an enlarged view of the conductor wires of the first front-side coil in the first chip in FIG. 15. FIG. 17 is an enlarged view of the conductor wires of the first back-side coil in the first chip in FIG. 15. FIG. 18 is a cross-sectional view showing the cross-sectional structure of a portion of the circuit region of the first chip. FIG. 19 is an enlarged view of the first via and its periphery in FIG. 18. FIG. 20 is an enlarged plan view of the first die pad and its periphery in the signal transmission device of the second embodiment. FIG. 21 is an enlarged plan view of the first die pad and its periphery in the signal transmission device of the third embodiment. FIG. 22 is an enlarged perspective view of the second bond portion of the first terminal wire in FIG. 21 and its periphery. FIG. 23 is a schematic plan view showing the internal configuration of a signal transmission device of the fourth embodiment. Fig. 24 is a schematic cross-sectional view of a first chip and a first die pad in a signal transmission device according to a fifth embodiment. Fig. 25 is a schematic cross-sectional view of the first chip and the first die pad cut in a direction different from that of Fig. 24. Fig. 26 is a schematic cross-sectional view of a second chip and a second die pad. Fig. 27 is a schematic cross-sectional view of the second chip and the second die pad cut in a direction different from that of Fig. 26.FIG. 28 is a schematic cross-sectional view of the third chip and the third die pad. FIG. 29 is a schematic cross-sectional view of the third chip and the third die pad cut in a direction different from that of FIG. 28 . FIG. 30 is a cross-sectional view schematically showing an example of a manufacturing process for the signal transmission device of the fifth embodiment. FIG. 31 is a cross-sectional view schematically showing an example of a manufacturing process for the signal transmission device subsequent to FIG. 30 . FIG. 32 is a cross-sectional view schematically showing an example of a manufacturing process for the signal transmission device subsequent to FIG. 31 . FIG. 33 is a cross-sectional view schematically showing an example of a manufacturing process for the signal transmission device subsequent to FIG. 32 . FIG. 34 is a cross-sectional view schematically showing an example of a cross-sectional structure of the first transformer of the first chip and its periphery in the signal transmission device of the sixth embodiment. FIG. 35 is an enlarged cross-sectional view of a portion of the first transformer of FIG. 34 and its periphery. FIG. 36 is a cross-sectional view schematically showing an example of a manufacturing process for the signal transmission device of the sixth embodiment. FIG. 37 is a cross-sectional view schematically showing an example of a manufacturing process for the signal transmission device subsequent to FIG. 36 . FIG. 38 is a cross-sectional view schematically showing an example of a manufacturing process for the signal transmission device subsequent to FIG. 37 . FIG. 39 is a cross-sectional view showing a cross-sectional structure of a first transformer of a first chip and a portion of its periphery in a signal transmission device of a seventh embodiment. FIG. 40 is a cross-sectional view enlarging a portion of a first surface side coil of a first transformer of a first chip and its periphery in a signal transmission device of an eighth embodiment. FIG. 41 is a cross-sectional view schematically showing an example of a manufacturing process for the signal transmission device of the eighth embodiment. FIG. 42 is a cross-sectional view schematically showing an example of a manufacturing process for the signal transmission device subsequent to FIG. 41 . FIG. 43 is a cross-sectional view schematically showing an example of a manufacturing process for the signal transmission device subsequent to FIG. 42 . FIG. 44 is a cross-sectional view schematically showing an example of a manufacturing process for the signal transmission device subsequent to FIG. 43 . FIG. 45 is a cross-sectional view schematically showing an example of a manufacturing process for the signal transmission device subsequent to FIG. 44 . FIG. 46 is a cross-sectional view schematically showing an example of a manufacturing process for the signal transmission device subsequent to FIG. 45 . Fig. 47 is an enlarged cross-sectional view of a portion of the first surface side coil of the first transformer of the first chip and its periphery in the signal transmission device of the ninth embodiment. Fig. 48 is a cross-sectional view schematically showing an example of a manufacturing process for the signal transmission device of the ninth embodiment. Fig. 49 is a cross-sectional view schematically showing an example of a manufacturing process for the signal transmission device subsequent to Fig. 48.50 is a cross-sectional view schematically showing an example of a manufacturing process for a signal transmission device subsequent to FIG. 49 . FIG. 51 is a cross-sectional view schematically showing an example of a manufacturing process for a signal transmission device subsequent to FIG. 50 . FIG. 52 is a cross-sectional view schematically showing an example of a manufacturing process for a signal transmission device subsequent to FIG. 51 . FIG. 53 is a schematic plan view showing an example of the internal structure of a first chip in a signal transmission device of a modified example. FIG. 54 is a schematic plan view showing an example of the internal structure of the first chip at a position different from that in FIG. 53 in the thickness direction of the first chip. FIG. 55 is an enlarged plan view of the first die pad and its periphery in a signal transmission device of a modified example. FIG. 56 is an enlarged plan view of the second die pad, the third die pad, and their periphery in a signal transmission device of a modified example.

[0008] Hereinafter, several embodiments of a signal transmission device according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, the components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] <First Embodiment> A signal transmission device 10 according to a first embodiment will be described with reference to Figures 1 to 19. Figures 1 and 2 show the external structure of the signal transmission device 10. Figures 3 to 8 show the internal structure of the signal transmission device 10. Figure 9 shows the circuit configuration of the signal transmission device 10. Figures 10 to 19 show the internal structure of a first chip 60 (described later) of the signal transmission device 10.

[0011] [External Configuration of Signal Transmission Device] Fig. 1 shows a perspective view of the front side of a signal transmission device 10. Fig. 2 shows a plan view of the rear side of the signal transmission device 10.

[0012] 1 and 2, the package structure of the signal transmission device 10 is a small outline non-leaded package (SON). Note that the package structure of the signal transmission device 10 can be changed as desired, and may be, for example, a quad for non-leaded package (QFN).

[0013] The signal transmission device 10 includes a sealing resin 90, and a plurality of (seven in the first embodiment) first terminals 11 to 17, a plurality of (three in the first embodiment) second terminals 41 to 43, and a plurality of (three in the first embodiment) third terminals 44 to 46 sealed in the sealing resin 90. As shown in Fig. 2, the plurality of first terminals 11 to 17, the plurality of second terminals 41 to 43, and the plurality of third terminals 44 to 46 are exposed from a sealing back surface 92 of the sealing resin 90, which will be described later.

[0014] As shown in FIG. 1 , the sealing resin 90 is formed in a rectangular flat plate shape. Here, in this specification, the thickness direction of the sealing resin 90 is referred to as the "Z direction," and two mutually orthogonal directions perpendicular to the Z direction are referred to as the "X direction" and the "Y direction." Furthermore, the upper side of the Z direction is referred to as the "+Z direction," and the lower side is referred to as the "-Z direction." In FIG. 1 , the front side of the X direction is referred to as the "+X direction," and the rear side is referred to as the "-X direction." In FIG. 1 , the right side of the Y direction is referred to as the "+Y direction," and the left side is referred to as the "-Y direction." Furthermore, in this specification, the term "plan view" refers to viewing the signal transmission device 10 from the thickness direction of the sealing resin 90. Unless otherwise specified, the term "plan view" refers to viewing the signal transmission device 10 from the +Z direction.

[0015] The shape of the sealing resin 90 in plan view is, for example, approximately square. In one example, the size (thickness) of the sealing resin 90 in the Z direction is ⅓ or less of the sizes of the sealing resin 90 in the X direction and the Y direction. In one example, the size (thickness) of the sealing resin 90 in the Z direction is ¼ or less of the sizes of the sealing resin 90 in the X direction and the Y direction. In one example, the size (thickness) of the sealing resin 90 in the Z direction is ⅕ or more of the sizes of the sealing resin 90 in the X direction and the Y direction. In one example, in plan view, the size of the sealing resin 90 in the X direction is about 5 mm, and the size of the sealing resin 90 in the Y direction is about 5 mm. The size (thickness) of the sealing resin 90 in the Z direction is a maximum of 1.06 mm.

[0016] 1 and 2, the sealing resin 90 has a sealing front surface 91 and a sealing back surface 92 that face opposite each other in the Z direction. The sealing front surface 91 faces the +Z direction, and the sealing back surface 92 faces the −Z direction. Here, the Z direction corresponds to a “third direction that is orthogonal to both the first direction and the second direction.”

[0017] The sealing resin 90 has first to fourth sealing side surfaces 93 to 96 that connect a sealing front surface 91 and a sealing back surface 92. The first sealing side surface 93 and the second sealing side surface 94 constitute both end surfaces of the sealing resin 90 in the X direction, and the third sealing side surface 95 and the fourth sealing side surface 96 constitute both end surfaces of the sealing resin 90 in the Y direction. The first sealing side surface 93 is a surface that faces the +X direction, and the second sealing side surface 94 is a surface that faces the -X direction. The third sealing side surface 95 is a surface that faces the +Y direction, and the fourth sealing side surface 96 is a surface that faces the -Y direction.

[0018] As shown in Fig. 1, a recess 91A is formed in the sealing surface 91. The recess 91A is circular in plan view. The recess 91A is recessed in a curved concave shape from the sealing surface 91. The recess 91A is formed in a portion of the sealing surface 91 that is closer to the first sealing side surface 93 and the fourth sealing side surface 96. The recess 91A serves as a marker for distinguishing the first terminals 11 to 17 from the second terminals 41 to 43 and the third terminals 44 to 46.

[0019] The sealing resin 90 is formed, for example, by transfer molding. In one example, the third sealing side surface 95 has a trace (not shown) of the gate of a molding die. This trace is formed when a resin portion located at the gate of the molding die is separated from the sealing resin 90. The trace is formed, for example, in the center of the third sealing side surface 95 in the Z direction. In one example, as shown in FIG. 1 , the third sealing side surface 95 is partitioned in the X direction into three regions R1 to R3. The regions R1 to R3 are regions of equal size. The region R1 is a region of the third sealing side surface 95 closer to the first sealing side surface 93, the region R3 is a region of the third sealing side surface 95 closer to the second sealing side surface 94, and the region R2 is a region between the regions R1 and R3 in the X direction. The trace may be provided in the region R1. The trace may also be provided in the region R2. The trace may also be provided in the region R3.

[0020] The surface roughness Rz of each of the sealing surface 91, sealing back surface 92, and first to fourth sealing side surfaces 93 to 96 of the sealing resin 90 is, for example, 5 μm or more and 20 μm or less. In the first embodiment, the surface roughness Rz of the entire sealing surface 91 and sealing back surface 92 is, for example, 5 μm or more and 20 μm or less. The surface roughness Rz of the entire first to fourth sealing side surfaces 93 to 96 is, for example, 5 μm or more and 20 μm or less. Here, the surface roughness Rz can be expressed as the sum of the height of the highest peak and the depth of the deepest valley of the profile curve in the reference length. In one example, the sealing surface 91, sealing back surface 92, and first to fourth sealing side surfaces 93 to 96 are subjected to a surface roughening treatment, thereby making each surface roughness Rz, for example, 5 μm or more and 20 μm or less. Examples of the surface roughening treatment include shot blasting.

[0021] In one example, the surface roughness Rz of each of the sealing surface 91, the sealing back surface 92, and the first to fourth sealing side surfaces 93 to 96 is, for example, 8 μm or more. In one example, the surface roughness Rz of each of the sealing surface 91, the sealing back surface 92, and the first to fourth sealing side surfaces 93 to 96 is, for example, 8 μm or more and 20 μm or less. In one example, the surface roughness Rz of the sealing surface 91, the sealing back surface 92, and the first to fourth sealing side surfaces 93 to 96 may be greater than the surface roughness Rz of the surfaces that form the recess 91A.

[0022] In the first embodiment, the surface roughness Rz of the sealing surface 91, the sealing back surface 92, and the first to fourth sealing side surfaces 93 to 96 was 5 μm or more and 20 μm or less, but this is not limited thereto. In one example, the surface roughness Rz of each of the third sealing side surface 95 and the fourth sealing side surface 96 may be less than 5 μm or greater than 20 μm. In another example, the surface roughness Rz of each of the first sealing side surface 93 and the second sealing side surface 94 may be less than 5 μm or greater than 20 μm. In another example, the surface roughness Rz of each of the first to fourth sealing side surfaces 93 to 96 may be less than 5 μm or greater than 20 μm. In another example, the surface roughness Rz of the sealing surface 91 may be less than 5 μm or greater than 20 μm. In short, it is sufficient that the surface roughness Rz of at least the sealing back surface 92 is 5 μm or more and 20 μm or less.

[0023] The sealing resin 90 is made of an insulating material. One example of the insulating material is black epoxy resin. The sealing resin 90 contains sulfur (S) as an additive. By including sulfur, the sealing resin 90 can enhance the adhesive strength between the sealing resin 90 and the first die pad 30, the second die pad 50A, and the third die pad 50B described below. On the other hand, if the sealing resin 90 contains sulfur, there is a risk of sulfide corrosion of copper-based components in the signal transmission device 10. The sulfur concentration in the sealing resin 90 is set in consideration of the balance between improving the adhesive strength between the sealing resin 90 and the first die pad 30, the second die pad 50A, and the third die pad 50B and suppressing sulfide corrosion. In one example, the sulfur concentration in the sealing resin 90 is set to 300 μg / g or less.

[0024] 2, each of the first terminals 11 to 17, second terminals 41 to 43, and third terminals 44 to 46 includes a first external electrode 11A to 17A, a second external electrode 41A to 43A, and a third external electrode 44A to 46A exposed from the sealed back surface 92. The first external electrodes 11A to 17A are exposed from a portion of the sealed back surface 92 closer to the first sealed side surface 93. The second external electrodes 41A to 43A and the third external electrodes 44A to 46A are exposed from a portion of the sealed back surface 92 closer to the second sealed side surface 94.

[0025] The first external electrodes 11A to 17A are arranged at the same positions in the X direction and spaced apart from one another in the Y direction. The first external electrodes 11A to 17A are arranged in the order of first external electrodes 11A, 12A, 13A, 14A, 15A, 16A, and 17A from the fourth sealed side surface 96 toward the third sealed side surface 95.

[0026] The second external electrodes 41A to 43A are arranged at the same positions in the X direction and spaced apart from one another in the Y direction. The second external electrodes 41A to 43A are arranged in the order of second external electrodes 41A, 42A, 43A from the third sealed side surface 95 toward the fourth sealed side surface 96.

[0027] The third external electrodes 44A to 46A are arranged at the same positions in the X direction and spaced apart from one another in the Y direction. The third external electrodes 44A to 46A are arranged in the order of 44A, 45A, 46A from the third sealed side surface 95 toward the fourth sealed side surface 96.

[0028] In a plan view, the first external electrodes 11A to 17A, the second external electrodes 41A to 43A, and the third external electrodes 44A to 46A each have a rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction. In one example, the first external electrodes 11A to 17A, the second external electrodes 41A to 43A, and the third external electrodes 44A to 46A are all the same size. The length of the first external electrodes 11A to 17A, the second external electrodes 41A to 43A, and the third external electrodes 44A to 46A in the X direction is, for example, approximately 0.75 mm, and the length of the Y direction is, for example, approximately 0.3 mm.

[0029] In one example, the pitch of the first external electrodes 11A to 17A is equal to the pitch of the second external electrodes 41A to 43A. The pitch of the first external electrodes 11A to 17A is equal to the pitch of the third external electrodes 44A to 46A. The pitch of the second external electrodes 41A to 43A is equal to the pitch of the third external electrodes 44A to 46A. The pitch of the first external electrodes 11A to 17A, the pitch of the second external electrodes 41A to 43A, and the pitch of the third external electrodes 44A to 46A are each, for example, approximately 0.65 mm. Here, the pitch of the first external electrodes 11A to 17A can be defined by the center-to-center distance between two adjacent first external electrodes among the first external electrodes 11A to 17A. The pitch of the second external electrodes 41A to 43A can be defined by the center-to-center distance between two adjacent second external electrodes among the second external electrodes 41A to 43A in the Y direction. The pitch of the third external electrodes 44A to 46A can be defined by the center-to-center distance between two third external electrodes 44A to 46A that are adjacent to each other in the Y direction.

[0030] The distance between the second external electrode 43A and the third external electrode 44A in the Y direction is greater than the pitch of the first external electrodes 11A to 17A, the pitch of the second external electrodes 41A to 43A, and the pitch of the third external electrodes 44A to 46A.

[0031] [Internal Structure of Signal Transmission Device] Fig. 3 shows the overall internal structure of the signal transmission device 10. Fig. 4 schematically shows the cross-sectional structure of the signal transmission device 10. In Fig. 3, Fig. 5, and Fig. 7, the sealing resin 90 is indicated by a two-dot chain line to facilitate understanding of the drawings.

[0032] 3 , the signal transmission device 10 includes a first die pad 30, a second die pad 50A, a third die pad 50B, a first chip 60 mounted on the first die pad 30, a second chip 70 mounted on the second die pad 50A, and a third chip 80 mounted on the third die pad 50B. The sealing resin 90 seals the first die pad 30, the second die pad 50A, the third die pad 50B, the first chip 60, the second chip 70, and the third chip 80.

[0033] The first die pad 30 is disposed closer to the first sealing side surface 93 than the center of the sealing resin 90 in the X direction. The first chip 60 mounted on the first die pad 30 is formed in a flat plate shape with the thickness direction in the Z direction. The shape of the first chip 60 in plan view is rectangular with the short side direction in the X direction and the long side direction in the Y direction. The first chip 60 is mounted on the first die pad 30 by a first conductive bonding material SD1. More specifically, the first chip 60 is die-bonded to the first die pad 30.

[0034] Both the second die pad 50A and the third die pad 50B are disposed in the X direction closer to the second sealing side surface 94 relative to the first die pad 30 and spaced apart from the first die pad 30. In other words, the X direction can be said to be the arrangement direction of the first die pad 30 and the second die pad 50A and the third die pad 50B. Both the second die pad 50A and the third die pad 50B are disposed in the X direction closer to the second sealing side surface 94 than the center of the sealing resin 90. Both the second die pad 50A and the third die pad 50B are disposed opposite the first die pad 30 in the X direction. In other words, the first die pad 30 has a size in the Y direction that allows it to face the second die pad 50A and the third die pad 50B. Here, the X direction corresponds to the "first direction."

[0035] The second die pad 50A and the third die pad 50B are arranged spaced apart from each other in the Y direction. That is, in the first embodiment, the Y direction can be said to be the arrangement direction of the second die pad 50A and the third die pad 50B. The second die pad 50A is arranged closer to the third sealing side surface 95 than the third die pad 50B. The second die pad 50A is arranged closer to the third sealing side surface 95 than the center of the sealing resin 90 in the Y direction. The third die pad 50B is arranged closer to the fourth sealing side surface 96 than the center of the sealing resin 90 in the Y direction. Here, the Y direction corresponds to the "second direction."

[0036] The second chip 70 mounted on the second die pad 50A is formed in a flat plate shape. In plan view, the second chip 70 has a rectangular shape with the X direction as the short side and the Y direction as the long side. The size of the second chip 70 in the X direction is smaller than the size of the first chip 60 in the X direction. The size of the second chip 70 in the Y direction is smaller than the size of the first chip 60 in the Y direction. The second chip 70 is mounted on the second die pad 50A with a second conductive bonding material SD2. More specifically, the second chip 70 is die-bonded to the second die pad 50A.

[0037] The second chip 70 is disposed closer to the third die pad 50B of the second die pad 50A. When viewed from the X direction, the second chip 70 is disposed closer to the third sealing side surface 95 than the first chip 60. In the example of FIG. 3 , when viewed from the X direction, the second chip 70 is disposed so as to partially overlap the first chip 60.

[0038] The third chip 80 mounted on the third die pad 50B is formed in a flat plate shape. In plan view, the third chip 80 has a rectangular shape with its short side in the X direction and its long side in the Y direction. The size of the third chip 80 in the X direction is smaller than the size of the first chip 60 in the X direction. The size of the third chip 80 in the Y direction is smaller than the size of the first chip 60 in the Y direction. In one example, the sizes of the third chip 80 in the X and Y directions are the same as the sizes of the second chip 70 in the X and Y directions. The third chip 80 is mounted on the third die pad 50B with a third conductive bonding material SD3. More specifically, the third chip 80 is die-bonded to the third die pad 50B. The first to third conductive bonding materials SD1 to SD3 may be, for example, solder paste or silver paste.

[0039] The third chip 80 is disposed on the third die pad 50B closer to the fourth sealing side surface 96. When viewed from the X direction, the third chip 80 is disposed closer to the fourth sealing side surface 96 than the first chip 60. In the example of FIG. 3 , when viewed from the X direction, the third chip 80 is disposed so as to partially overlap the first chip 60.

[0040] As shown in FIGS. 5 and 7 , the signal transmission device 10 includes first internal terminal portions 12B-17B, second internal terminal portions 42B, 43B, and third internal terminal portions 45B, 46B. A sealing resin 90 seals the first internal terminal portions 12B-17B, the second internal terminal portions 42B, 43B, and the third internal terminal portions 45B, 46B. The first internal terminal portions 12B-17B constitute part of the first terminals 12-17. In other words, the first terminals 12-17 can be said to include the first internal terminal portions 12B-17B. The second internal terminal portions 42B, 43B constitute part of the second terminals 42, 43. In other words, the second terminals 42, 43 can be said to include the second internal terminal portions 42B, 43B. The third internal terminal portions 45B, 46B constitute part of the third terminals 45, 46. In other words, the third terminals 45 and 46 can be said to include third internal terminal portions 45B and 46B.

[0041] 3, in a plan view, the first terminals 11 to 17 are arranged on the opposite side of the first chip 60 in the X direction from the second chip 70 and the third chip 80. In the first embodiment, in a plan view, the first terminals 11 to 17 are arranged closer to the first sealing side surface 93 than the first chip 60 in the X direction.

[0042] In a plan view, the second terminals 41 to 43 are arranged on the opposite side of the second chip 70 from the first chip 60 in the X direction. In other words, in a plan view, the second terminals 41 to 43 are arranged on the opposite side of the second chip 70 from the first die pad 30 in the X direction. In the first embodiment, in a plan view, the second terminals 41 to 43 are arranged closer to the second sealing side surface 94 than the second chip 70.

[0043] In a plan view, the third terminals 44 to 46 are arranged on the opposite side of the third chip 80 from the first chip 60 in the X direction. In other words, in a plan view, the third terminals 44 to 46 are arranged on the opposite side of the third chip 80 from the first die pad 30 in the X direction. In the first embodiment, in a plan view, the third terminals 44 to 46 are arranged closer to the second sealing side surface 94 than the third chip 80.

[0044] As shown in FIG. 4 , the first terminal 17 has a configuration in which a first external electrode 17A and a first internal terminal portion 17B are connected by a first via 17C. The first internal terminal portion 17B is disposed closer to the sealing surface 91 than the first external electrode 17A and is spaced apart. The first internal terminal portion 17B is disposed at the same position as the first die pad 30 in the Z direction. The first via 17C is provided between the first external electrode 17A and the first internal terminal portion 17B in the Z direction. Note that, as shown in FIG. 5 , the first terminals 12 to 16 have the same configuration as the first terminal 17. That is, the first terminals 12 to 16 have a configuration in which the first external electrodes 12A to 16A and the first internal terminal portions 12B to 16B are connected by the first vias 12C to 16C.

[0045] On the other hand, the first terminal 11 includes a first via 11C that connects the first external electrode 11A and the first die pad 30. In other words, the first terminal 11 includes the first external electrode 11A and the first via 11C. It can be said that the first terminal 11 is electrically connected to the first die pad 30.

[0046] When viewed from the X direction, the first external electrodes 11A, 12A are arranged closer to the fourth sealing side surface 96 than the first chip 60. When viewed from the X direction, it can also be said that the first external electrodes 11A, 12A are arranged between the first chip 60 and the fourth sealing side surface 96. When viewed from the X direction, the first external electrodes 13A to 15A are arranged in positions that overlap with the first chip 60. When viewed from the X direction, the first external electrodes 16A, 17A are arranged closer to the third sealing side surface 95 than the first chip 60. When viewed from the X direction, it can also be said that the first external electrodes 16A, 17A are arranged between the first chip 60 and the third sealing side surface 95.

[0047] 4, the second terminal 41 includes a second via 41C that connects the second external electrode 41A and the second die pad 50A. That is, the second terminal 41 includes the second external electrode 41A and the second via 41C. It can be said that the second terminal 41 is electrically connected to the second die pad 50A.

[0048] 7, the second terminals 42, 43 are configured such that the second external electrodes 42A, 43A are connected to the second internal terminal portions 42B, 43B by the second vias 42C, 43C. The second internal terminal portions 42B, 43B are disposed closer to the sealing surface 91 (see FIG. 4) than the second external electrodes 42A, 43A. In one example, the second internal terminal portions 42B, 43B are disposed at the same position in the Z direction as the second die pad 50A. In another example, the second internal terminal portions 42B, 43B are disposed at the same position in the Z direction as the first internal terminal portions 12B to 17B.

[0049] When viewed from the X direction, the second external electrode 41A is disposed closer to the third sealing side surface 95 than the second chip 70. When viewed from the X direction, the second external electrode 41A can also be said to be disposed between the second chip 70 and the third sealing side surface 95 in the Y direction. When viewed from the X direction, the second external electrodes 42A and 43A are disposed in positions that overlap the second chip 70.

[0050] The third terminal 44 includes a third via 44C that connects the third external electrode 44A and the third die pad 50B. In other words, the third terminal 44 includes the third external electrode 44A and the third via 44C. It can be said that the third terminal 44 is electrically connected to the third die pad 50B.

[0051] On the other hand, the third terminals 45, 46 are configured such that the third external electrodes 45A, 46A are connected to the third internal terminal portions 45B, 46B by third vias 45C, 46C. The third internal terminal portions 45B, 46B are arranged closer to the sealing surface 91 and spaced apart from the third external electrodes 45A, 46A. In one example, the third internal terminal portions 45B, 46B are arranged at the same position in the Z direction as the third die pad 50B. In another example, the third internal terminal portions 45B, 46B are arranged at the same position in the Z direction as the first internal terminal portions 12B to 17B.

[0052] When viewed from the X direction, the third external electrode 44A is disposed closer to the third sealing side surface 95 than the third chip 80. When viewed from the X direction, the third external electrodes 45A and 46A are disposed in positions that overlap the third chip 80.

[0053] The detailed planar structures of the first die pad 30 and the first terminals 11 to 17 will be described. As shown in FIG. 5 , the first die pad 30 is formed over a large portion of the area between the third sealing side surface 95 and the fourth sealing side surface 96 in the Y direction. The first die pad 30 has a first leading end surface 31, a first base end surface 32, a first side surface 33, and a second side surface 34. The first leading end surface 31 is the end surface closest to the second sealing side surface 94 (see FIG. 3 ) among both end surfaces of the first die pad 30 in the X direction, and the first base end surface 32 is the end surface closest to the first sealing side surface 93 among both end surfaces of the first die pad 30 in the X direction. The first side surface 33 is the end surface closest to the third sealing side surface 95 (see FIG. 3 ) among both end surfaces of the first die pad 30 in the Y direction, and the second side surface 34 is the end surface closest to the fourth sealing side surface 96 (see FIG. 3 ) among both end surfaces of the first die pad 30 in the Y direction. The first tip surface 31 is a surface that faces both the second die pad 50A and the third die pad 50B (see FIG. 3 ) in the X direction and extends along the Y direction in plan view. The length of the first tip surface 31 in the Y direction is longer than the length of the first base end surface 32 in the Y direction. Both the first side surface 33 and the second side surface 34 are surfaces that extend along the X direction in plan view.

[0054] The first die pad 30 further has a first tip curved surface 35A, a second tip curved surface 35B, and a base curved surface 36. The first tip curved surface 35A is formed between the first tip surface 31 and the first side surface 33. The first tip curved surface 35A has a shape in which the portion between the first tip surface 31 and the first side surface 33 is R-chamfered. The second tip curved surface 35B is formed between the first tip surface 31 and the second side surface 34. The second tip curved surface 35B has a shape in which the portion between the first tip surface 31 and the second side surface 34 is R-chamfered. In one example, in a plan view, the arc length of the first tip curved surface 35A and the arc length of the second tip curved surface 35B are equal to each other. In one example, it can also be said that the curvature radius of the first tip curved surface 35A and the curvature radius of the second tip curved surface 35B are equal to each other in a plan view.

[0055] The base-side curved surface 36 is formed between the first base-side surface 32 and the first side surface 33. The base-side curved surface 36 has a shape in which the portion between the first base-side surface 32 and the first side surface 33 is rounded and chamfered. In the first embodiment, in a plan view, the arc lengths of both the first tip-side curved surface 35A and the second tip-side curved surface 35B are equal to the arc length of the base-side curved surface 36. In other words, in a plan view, the radii of curvature of both the first tip-side curved surface 35A and the second tip-side curved surface 35B are equal to the radius of curvature of the base-side curved surface 36.

[0056] The first die pad 30 further has a first recess 37A into which the first internal terminal 12B fits, a second recess 37B into which the first internal terminal 13B fits, and a third recess 37C into which the first internal terminals 14B to 17B fit. The first to third recesses 37A to 37C are open toward the first sealing side surface 93.

[0057] In a plan view, the first recessed portion 37A is provided between the first external electrode 11A and the first external electrode 13A in the Y direction. In a plan view, the first recessed portion 37A is provided at a position overlapping with the first external electrode 12A. A corner portion of the first external electrode 12A, which is on the fourth sealing side surface 96 and closer to the first chip 60, is provided at a position overlapping with the first die pad 30.

[0058] The first recessed portion 37A includes a first surface 37A1 extending in the X direction from the first base end surface 32, a second surface 37A2 which is an inclined surface extending from the first surface 37A1 toward the first chip 60, and a curved concave surface 37A3 connected to the second surface 37A2.

[0059] In a plan view, the first surface 37A1 is formed closer to the first external electrode 11A than the first external electrode 12A. In a plan view, the distance between the first external electrode 12A and the first surface 37A1 in the Y direction is smaller than the distance between the first external electrode 11A and the first surface 37A1 in the Y direction.

[0060] The second surface 37A2 is located closer to the first internal terminal portion 12B than the corner portion of the first external electrode 12A in a plan view. The second surface 37A2 is inclined so as to approach the first side surface 33 from the first base end surface 32 toward the first tip surface 31.

[0061] The curved concave surface 37A3 is provided closer to the first external electrode 13A than the first external electrode 12A in plan view. The curved concave surface 37A3 does not have a portion that overlaps with the first external electrode 12A in plan view.

[0062] The first internal terminal 12B has a shape that generally follows the shape of the first recess 37A in a plan view. The tip surface of the first internal terminal 12B that faces the curved concave surface 37A3 includes a curved convex surface that follows the shape of the curved concave surface 37A3.

[0063] In a planar view, the first internal terminal portion 12B includes a via connection portion 12BA that overlaps the first external electrode 12A and to which the first via 11C is connected, and a wire connection portion 12BB that extends from the via connection portion 12BA toward the first chip 60.

[0064] The via connection portion 12BA constitutes an end portion of the first internal terminal portion 12B that is closer to the first sealing side surface 93. The via connection portion 12BA is connected to a portion of the first external electrode 12A that is closer to the first sealing side surface 93 than the center in the X direction.

[0065] The wire connection portion 12BB extends obliquely from the first base end surface 32 toward the first tip surface 31 toward the third sealing side surface 95. It can also be said that the wire connection portion 12BB extends from the via connection portion 12BA toward the first chip 60. The wire connection portion 12BB includes a protruding portion that protrudes from the first external electrode 12A toward the first external electrode 13A in a plan view. It can also be said that this protruding portion protrudes from the first external electrode 12A toward the first chip 60 in a plan view. The wire connection portion 12BB includes a tip surface of the first internal terminal portion 12B that faces the curved concave surface 37A3.

[0066] The first via 12C connects the via connection portion 12BA and the first external electrode 12A. Therefore, the first via 12C is connected to a portion of the first external electrode 12A that is closer to the first sealing side surface 93 than the center in the X direction.

[0067] The second recessed portion 37B is provided between the first external electrode 12A and the first external electrode 14A in the Y direction in a plan view. The second recessed portion 37B is provided at a position overlapping with the first external electrode 13A in a plan view. The second recessed portion 37B is provided at a position overlapping with a portion of the first external electrode 13A closer to the first chip 60 than the center in the X direction of the first external electrode 13A. The end of the first external electrode 13A closer to the first chip 60 in the X direction is provided at a position overlapping with the first die pad 30 in a plan view. A curved concave surface is formed in the portion of the second recessed portion 37B closer to the first recessed portion 37A.

[0068] The tip surface of the first internal terminal 13B facing the second recess 37B includes a curved convex surface that follows the shape of the curved concave surface of the second recess 37B. In a plan view, the first internal terminal 13B extends obliquely toward the third sealing side surface 95 as it moves from the first base end surface 32 toward the first tip end surface 31. The first internal terminal 13B is formed so that its width increases as it moves from the end on the first tip end surface 31 side toward the end on the first base end surface 32 side. Here, the width of the first internal terminal 13B can be defined by the size in a direction perpendicular to the direction in which the first internal terminal 13B extends in a plan view.

[0069] The first internal terminal 13B includes a protruding portion that protrudes from the first external electrode 13A toward the first external electrode 12A in a plan view. This protruding portion protrudes closer to the first internal terminal 12B than the second recessed portion 37B when viewed from the X direction. Therefore, when viewed from the X direction, a portion of the protruding portion of the first internal terminal 13B is located in a position that overlaps with the first recessed portion 37A. The protruding portion of the first internal terminal 13B is located closer to the first sealing side surface 93 than the protruding portion of the first internal terminal 12B.

[0070] The first via 13C connects the end of the first internal terminal 13B that enters the second recess 37B to the first external electrode 13A. The first via 13C is connected to a portion of the first external electrode 13A that is closer to the first chip 60 than the center in the X direction.

[0071] In a plan view, the third recessed portion 37C is provided closer to the third sealing side surface 95 than the first external electrode 13A. The third recessed portion 37C includes a curved concave surface 37C1 extending from the second recessed portion 37B toward the first chip 60, a bottom surface 37C2 extending from the curved concave surface 37C1 along the Y direction, and an inclined surface 37C3 connected to the bottom surface 37C2.

[0072] Curved concave surface 37C1 is a surface that connects to second recessed portion 37B and has a larger radius of curvature than curved concave surface 37A3 of first recessed portion 37A. Curved concave surface 37C1 curves toward third sealing side surface 95 as it moves from second recessed portion 37B toward first chip 60.

[0073] The bottom surface 37C2 extends across the first external electrodes 14A to 16A in the Y direction. The bottom surface 37C2 is located closer to the first chip 60 than the first external electrodes 14A to 16A in a plan view.

[0074] The inclined surface 37C3 is provided closer to the third sealing side surface 95 than the first external electrode 16A in the Y direction. The inclined surface 37C3 slopes from the bottom surface 37C2 toward the first base end surface 32 and toward the third sealing side surface 95. The inclined surface 37C3 extends across the first external electrode 17A in plan view. A portion of the first external electrode 17A that is closer to the first tip surface 31 and the first side surface 33 is provided in a position that overlaps with the first die pad 30 in plan view.

[0075] The first internal terminal 17B is formed across substantially the entire third recess 37C in the Y direction in plan view. The first internal terminal 17B includes a side surface that conforms to the shape of the third recess 37C in plan view. That is, the first internal terminal 17B includes a first side surface that is a curved convex surface along the curved concave surface 37C1, a second side surface that extends in the Y direction along the bottom surface 37C2, and a third side surface that extends along the inclined surface 37C3. The first internal terminal 17B extends from the first external electrode 17A to a position closer to the first external electrode 13A than the first external electrode 14A in plan view. The first internal terminal 17B is located closer to the third sealed side surface 95 than the first external electrode 13A in plan view.

[0076] The first internal terminal 17B includes an inclined portion 17BA, an extension portion 17BB, and a wire connection portion 17BC. The inclined portion 17BA is formed by a portion of the first internal terminal 17B that is closer to the third sealed side surface 95 than the first external electrode 16A in the X direction. The inclined portion 17BA extends obliquely toward the third sealed side surface 95 from the first distal end surface 31 toward the first proximal end surface 32. The inclined portion 17BA includes an overlapping portion that overlaps with the first external electrode 17A in a plan view. The inclined portion 17BA includes the third side surface.

[0077] The extension portion 17BB extends in the Y direction from the inclined portion 17BA toward the fourth sealed side surface 96. A portion of the extension portion 17BB closer to the inclined portion 17BA is provided so as to overlap a portion of the first external electrode 16A closer to the first tip surface 31 than the center in the X direction in a plan view. The extension portion 17BB is disposed closer to the first tip surface 31 than the first external electrode 15A in a plan view. The extension portion 17BB includes the second side surface.

[0078] A recessed portion 17BD is provided in a portion of extension portion 17BB closer to first sealing side surface 93. Recessed portion 17BD is provided closer to fourth sealing side surface 96 than first external electrode 16A in the Y direction. Recessed portion 17BD is recessed toward first chip 60 in the portion of extension portion 17BB closer to first sealing side surface 93.

[0079] The wire connection portion 17BC is formed by a portion of the first internal terminal portion 17B that is closer to the fourth sealing side surface 96 than the recessed portion 17BD. In a plan view, the wire connection portion 17BC includes a portion that overlaps with the first external electrode 14A. The wire connection portion 17BC extends from the extension portion 17BB toward the first sealing side surface 93. The wire connection portion 17BC extends obliquely toward the fourth sealing side surface 96 as it approaches the first sealing side surface 93. In one example, the acute angle formed between the extension direction of the wire connection portion 17BC and the X direction is, for example, greater than 0° and equal to or less than 30°.

[0080] First via 17C connects the overlapping portion of inclined portion 17BA to first external electrode 17A. First via 17C is connected to the end of the overlapping portion of inclined portion 17BA that is closer to third sealing side surface 95. First via 17C is connected to the center of first external electrode 17A in the X direction.

[0081] The first internal terminals 14B to 16B are disposed at a distance from the first internal terminal 17B toward the first sealing side surface 93. The first internal terminal 14B is disposed at a position overlapping the wire connection portion 17BC and the recessed portion 17BD when viewed from the X direction. A portion of the first internal terminal 14B extends into the recessed portion 17BD.

[0082] In a plan view, the first internal terminal portion 14B includes a first terminal portion 14BA extending along the Y direction and a second terminal portion 14BB extending from the first terminal portion 14BA toward the first chip 60.

[0083] The first terminal portion 14BA is located closer to the first sealed side surface 93 than the center of the first external electrode 14A in the X direction in a plan view. The tip surface of the first terminal portion 14BA is located closer to the first external electrode 14A than the first external electrode 13A in a plan view. Here, the tip surface of the first terminal portion 14BA forms the end face of the first terminal portion 14BA in the Y direction. The first terminal portion 14BA includes an overlapping portion that overlaps with the first external electrode 14A and a protruding portion that protrudes from the first external electrode 14A toward the first external electrode 13A.

[0084] The second terminal portion 14BB extends obliquely from the first base end surface 32 toward the first tip end surface 31 toward the third sealed side surface 95. In plan view, the second terminal portion 14BB is located closer to the first external electrode 14A than the first external electrode 15A. The second terminal portion 14BB includes an overlapping portion that overlaps with the first external electrode 14A and a protruding portion that protrudes from the first external electrode 14A toward the first external electrode 15A. In plan view, the area of ​​the protruding portion of the second terminal portion 14BB is larger than the area of ​​the overlapping portion.

[0085] The first via 14C connects the end of the first terminal 14BA closer to the second terminal 14BB to the first external electrode 14A. The first via 14C is connected to a portion of the first external electrode 14A closer to the first sealing side surface 93 than the center in the X direction.

[0086] The first internal terminal 15B is disposed at a position overlapping the recess 17BD when viewed from the X direction. A portion of the first internal terminal 15B is recessed into the recess 17BD. The tip surface of the first internal terminal 15B facing the recess 17BD includes a curved convex surface that is convex toward the recess 17BD. This curved convex surface forms a side surface facing the first die pad 30.

[0087] In plan view, the first internal terminal portion 15B extends obliquely from the first base end face 32 toward the first distal end face 31 toward the fourth sealed side surface 96. The first internal terminal portion 15B is formed so that its width increases from the end on the first distal end face 31 side toward the end on the first base end face 32 side. Here, the width of the first internal terminal portion 15B can be defined by the size in a direction perpendicular to the direction in which the first internal terminal portion 15B extends in plan view. The first internal terminal portion 15B includes a protruding portion that protrudes from the first external electrode 15A toward the first external electrode 16A in plan view.

[0088] The first via 15C connects the end of the first internal terminal 15B that fits into the recess 17BD to the first external electrode 15A. The first via 15C is connected to a portion of the first external electrode 15A that is closer to the first chip 60 than the center in the X direction.

[0089] In a plan view, the first internal terminal 16B is located closer to the first sealing side surface 93 than the center of the first external electrode 16A in the X direction. The first internal terminal 16B is located closer to the first sealing side surface 93 than the recessed portion 17BD. The first internal terminal 16B is located at a position overlapping with an end of the extension portion 17BB that is closer to the inclined portion 17BA when viewed from the X direction. The tip end of the first internal terminal 16B is located at a position overlapping with the recessed portion 17BD when viewed from the X direction. The tip end surface of the first internal terminal 16B faces the first chip 60. Therefore, the tip end surface of the first internal terminal 16B forms a side surface facing the first die pad 30. The tip end surface of the first internal terminal 16B includes a curved convex surface that is convex toward the recessed portion 17BD.

[0090] In a plan view, the first internal terminal portion 16B extends obliquely toward the fourth sealing side surface 96 from the first base end surface 32 toward the first distal end surface 31. In the first embodiment, in a plan view, the acute angle formed between the extension direction of the first internal terminal portion 16B and the X direction is larger than the acute angle formed between the extension direction of the first internal terminal portion 15B and the X direction. In one example, the acute angle formed between the extension direction of the first internal terminal portion 16B and the X direction is greater than or equal to 30° and less than or equal to 50°. In the example shown in FIG. 5 , the acute angle formed between the extension direction of the first internal terminal portion 16B and the X direction is 40°.

[0091] In a plan view, the first internal terminal portion 16B includes an overlapping portion that overlaps with the first external electrode 16A and a protruding portion that protrudes from the first external electrode 16A toward the first external electrode 15A. The protruding portion includes a tip surface of the first internal terminal portion 16B.

[0092] The first via 16C connects the first external electrode 16A to an end of the first internal terminal 16B that is closer to the first sealing side surface 93. The first via 16C is connected to a portion of the first external electrode 16A that is closer to the first sealing side surface 93 than the center in the X direction.

[0093] The first die pad 30 further has a cover portion 39 that surrounds a portion of the third recessed portion 37C that is closer to the third sealing side surface 95 from the first sealing side surface 93. The cover portion 39 extends from a corner portion of the first die pad 30 that is closer to the first sealing side surface 93 and the third sealing side surface 95 toward the fourth sealing side surface 96. In a plan view, the cover portion 39 and the inclined surface 37C3 of the third recessed portion 37C surround the inclined portion 17BA of the first internal terminal 17B. Therefore, a portion of the cover portion 39 is disposed between the inclined portion 17BA and the first internal terminal 16B.

[0094] The first die pad 30 further has an inclined surface 38A formed between the first base end surface 32 and the second side surface 34, and a protrusion 38B protruding from the inclined surface 38A in a plan view. The inclined surface 38A is inclined so as to approach the second side surface 34 as it extends from the first base end surface 32 toward the first tip surface 31. The inclined surface 38A extends across the first external electrode 11A in a plan view. Therefore, the first external electrode 11A includes a portion that overlaps with the first die pad 30 in a plan view.

[0095] The first via 11C connects the first external electrode 11A to a portion of the first die pad 30 that overlaps with the first external electrode 11A. The first via 11C is connected to a portion of the first external electrode 11A that is closer to the first tip surface 31 than the center in the X direction.

[0096] Protrusion 38B extends in a direction perpendicular to inclined surface 38A in plan view. Protrusion 38B is triangular in plan view and includes a separation portion 38B1 disposed at a distance from inclined surface 38A, and a connection portion 38B2 connecting separation portion 38B1 and inclined surface 38A. Separation portion 38B1 includes a protruding portion that protrudes from first external electrode 11A toward fourth sealed side surface 96 in plan view.

[0097] Next, the detailed cross-sectional structure of the first internal terminal portions 12B to 17B will be described. Fig. 6 shows the cross-sectional structure of the wire connection portion 12BB of the first internal terminal portion 12B. Note that the cross-sectional structure of the first internal terminal portions 13B to 17B is similar to the cross-sectional structure of the wire connection portion 12BB, and therefore drawings and detailed description thereof will be omitted.

[0098] 6, the internal terminal body 20 of the wire connection portion 12BB has an internal terminal surface 21, an internal terminal back surface 22 opposite to the internal terminal surface 21, and an internal terminal side surface 23 connecting the internal terminal surface 21 and the internal terminal back surface 22. The internal terminal side surface 23 includes a tip surface 24 facing the first recessed portion 37A (see FIG. 5) of the first die pad 30. The internal terminal surface 21 is the surface to which a first terminal wire WB (described later) is bonded, and faces the same side as the sealing surface 91 (see FIG. 4).

[0099] In the cross-sectional view of Fig. 6, the tip surface 24 is formed in a concave shape that is recessed away from the first die pad 30. The tip surface 24 is recessed from both the end on the internal terminal front surface 21 side and the end on the internal terminal back surface 22 side toward the center of the tip surface 24 in the Z direction. In one example, the deepest position of the concave tip surface 24 is located at a position approximately 1 / 3 of the thickness of the wire connection portion 12BB from the internal terminal back surface 22. Note that the shape of the tip surface 24 in the cross-sectional view of Fig. 6 can be changed as desired.

[0100] A plating layer 25 is formed on the inner terminal surface 21. The plating layer 25 is formed of a material containing silver, for example. The plating layer 25 is formed over substantially the entire inner terminal surface 21 of the wire connection portion 12BB. The thickness of the plating layer 25 is thinner than the thickness of the inner terminal body 20 of the wire connection portion 12BB.

[0101] An end surface 25A of the plating layer 25 closer to the tip surface 24 is formed at a position closer to the via connection portion 12BA (see FIG. 5 ) than the edge of the internal terminal surface 21 closer to the tip surface 24. In other words, the plating layer 25 does not cover the end surface of the internal terminal surface 21 closer to the tip surface 24. As a result, the end of the internal terminal surface 21, including the edge closer to the tip surface 24, is in contact with the sealing resin 90 (see FIG. 1 ).

[0102] The end surface 25A of the plating layer 25 is inclined from the front surface of the plating layer 25 toward the back surface thereof so as to move away from the edge of the internal terminal surface 21 closer to the tip surface 24. In one example, the distance in the X direction between the back surface of the plating layer 25 and the edge of the internal terminal surface 21 closer to the tip surface 24 is, for example, equal to or greater than the thickness of the plating layer 25. Note that the distance in the X direction between the back surface of the plating layer 25 and the edge of the internal terminal surface 21 closer to the tip surface 24 can be changed as desired.

[0103] Furthermore, the plating layer 25 does not cover the tip surface 24 of the wire connection portion 12BB. Therefore, the tip surface 24 is in contact with the sealing resin 90 (see FIG. 4 ). Furthermore, although not shown, the plating layer 25 does not cover the internal terminal side surface 23 other than the tip surface 24. Therefore, the internal terminal side surface 23 is in contact with the sealing resin 90.

[0104] The detailed planar structures of the second die pad 50A and the second terminals 41 to 43 will be described. As shown in FIG. 7 , the second die pad 50A has a second leading end surface 51A, a second base end surface 52A, a third side surface 53A, and a fourth side surface 54A. The second leading end surface 51A is the end surface closest to the first sealing side surface 93 (see FIG. 3 ) among both end surfaces of the second die pad 50A in the X direction, and the second base end surface 52A is the end surface closest to the second sealing side surface 94 among both end surfaces of the second die pad 50A in the X direction. The third side surface 53A is the end surface closest to the third sealing side surface 95 among both end surfaces of the second die pad 50A in the Y direction, and the fourth side surface 54A is the end surface closest to the fourth sealing side surface 96 among both end surfaces of the second die pad 50A in the Y direction. The second tip surface 51A is a surface facing the first die pad 30 (see FIG. 3) in the X direction and extends along the Y direction in plan view. Both the third side surface 53A and the fourth side surface 54A are surfaces extending along the X direction in plan view.

[0105] The second die pad 50A further has a third tip curved surface 55AA, a fourth tip curved surface 55AB, and a base curved surface 56A. The third tip curved surface 55AA is formed between the second tip surface 51A and the third side surface 53A. The third tip curved surface 55AA has a shape in which the portion between the second tip surface 51A and the third side surface 53A is R-chamfered. The fourth tip curved surface 55AB is formed between the second tip surface 51A and the fourth side surface 54A. The fourth tip curved surface 55AB has a shape in which the portion between the second tip surface 51A and the fourth side surface 54A is R-chamfered. In one example, in a plan view, the arc length of the third tip curved surface 55AA and the arc length of the fourth tip curved surface 55AB are equal to each other. In one example, it can be said that the radius of curvature of the third distal curved surface 55AA and the radius of curvature of the fourth distal curved surface 55AB are equal to each other in a plan view.

[0106] In one example, in a plan view, the arc lengths of the third and fourth distal curved surfaces 55AA and 55AB are equal to the arc lengths of the first and second distal curved surfaces 35A and 35B. In a plan view, the radii of curvature of the third and fourth distal curved surfaces 55AA and 55AB are equal to the radii of curvature of the first and second distal curved surfaces 35A and 35B.

[0107] The base-side curved surface 56A is formed between the second base-side surface 52A and the fourth side surface 54A. The base-side curved surface 56A has a shape in which the portion between the second base-side surface 52A and the fourth side surface 54A is rounded and chamfered. In the first embodiment, in a plan view, the arc lengths of both the third distal-side curved surface 55AA and the sixth distal-side curved surface 55BB are equal to the arc length of the base-side curved surface 56A. In other words, in a plan view, the radii of curvature of both the third distal-side curved surface 55AA and the fourth distal-side curved surface 55AB are equal to the radius of curvature of the base-side curved surface 56A.

[0108] The second die pad 50A further has a first recessed portion 57AA and a second recessed portion 57AB. The first recessed portion 57AA and the second recessed portion 57AB are located at the same position in the X direction and spaced apart from each other in the Y direction. Both the first recessed portion 57AA and the second recessed portion 57AB are located so as to overlap with the second chip 70 when viewed from the X direction. The first recessed portion 57AA and the second recessed portion 57AB are located closer to the fourth side surface 54A than the second external electrode 41A in a plan view. The second recessed portion 57AB is located closer to the fourth side surface 54A than the first recessed portion 57AA. Both the first recessed portion 57AA and the second recessed portion 57AB are located closer to the second sealing side surface 94 than the second chip 70 in a plan view.

[0109] Both the first recessed portion 57AA and the second recessed portion 57AB are open toward the second sealing side surface 94. Both the first recessed portion 57AA and the second recessed portion 57AB include a pair of side surfaces extending in the X direction from the second base end surface 52A toward the second tip surface 51A, and a curved concave surface provided between the pair of side surfaces and recessed toward the second tip surface 51A.

[0110] In plan view, the second terminal 42 fits into the first recessed portion 57AA. The second external electrode 42A of the second terminal 42 includes a protruding portion that protrudes from the first recessed portion 57AA toward the second sealing side surface 94 in plan view.

[0111] The second internal terminal portion 42B of the second terminal 42 is accommodated in the first recessed portion 57AA in plan view. As a result, the second internal terminal portion 42B is arranged to overlap the second external electrode 42A in plan view. The second internal terminal portion 42B is formed in a rectangular shape with its longitudinal direction in the X direction and its lateral direction in the Y direction in plan view. The four corners of the second internal terminal portion 42B are configured with curved surfaces.

[0112] The second via 42C connects the end of the second internal terminal 42B closer to the second chip 70 in the X direction to the second external electrode 42A. The second via 42C is connected to the end of the second external electrode 42A closer to the second chip 70.

[0113] In plan view, the second terminal 43 fits into the second recessed portion 57AB. The second external electrode 43A of the second terminal 43 includes a protruding portion that protrudes from the second recessed portion 57AB toward the second sealing side surface 94 in plan view.

[0114] The second internal terminal portion 43B of the second terminal 43 is accommodated in the second recess portion 57AB in a plan view. As a result, the second internal terminal portion 43B is positioned to overlap the second external electrode 43A in a plan view. The second internal terminal portion 43B is formed in a rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction in a plan view. Four corners of the second internal terminal portion 43B are formed by curved surfaces. In the example shown in FIG. 7 , the shape of the second internal terminal portion 43B in a plan view is the same as the shape of the second internal terminal portion 42B in a plan view.

[0115] The second via 43C connects the end of the second internal terminal 43B closer to the second chip 70 in the X direction to the second external electrode 43A. The second via 43C is connected to the end of the second external electrode 43A closer to the second chip 70.

[0116] The second die pad 50A further has an inclined surface 58 and a protruding portion 59. The inclined surface 58 and the protruding portion 59 are provided closer to the third side surface 53A than the first recessed portion 57AA. The inclined surface 58 is provided to cut out a corner portion of the second die pad 50A closer to the second sealing side surface 94 and the third sealing side surface 95. The inclined surface 58 is provided between the second base end surface 52A and the third side surface 53A. The inclined surface 58 is inclined so as to approach the third sealing side surface 95 as it moves from the second base end surface 52A toward the second tip surface 51A.

[0117] The inclined surface 58 includes a portion that overlaps with the second external electrode 41A in a plan view. Therefore, the second external electrode 41A includes a portion that overlaps with the second die pad 50A in a plan view. The second via 41C is arranged closer to the second front end surface 51A than the inclined surface 58 in a plan view. The second via 41C connects the portion of the second die pad 50A that overlaps with the second external electrode 41A to the second external electrode 41A. The second via 41C is connected to the end of the second external electrode 41A that is closer to the second front end surface 51A.

[0118] In plan view, protrusion 59 extends from inclined surface 58 toward third sealed side surface 95. In plan view, protrusion 59 has a generally L-shaped shape. An end of protrusion 59 closer to third sealed side surface 95 extends in the X direction toward second tip surface 51A. In plan view, protrusion 59 includes an overlapping portion that overlaps with second external electrode 41A and a protruding portion that protrudes from second external electrode 41A toward third sealed side surface 95.

[0119] Next, the detailed cross-sectional structure of the second internal terminal portions 42B, 43B will be described. Fig. 8 shows the cross-sectional structure of the second internal terminal portion 42B. Note that the cross-sectional structure of the second internal terminal portion 43B is similar to that of the second internal terminal portion 42B, and therefore the drawings and detailed description thereof will be omitted. For convenience, the reference numerals relating to the second internal terminal portion 42B will be the same as those relating to the wire connection portion 12BB of the first internal terminal portion 12B shown in Fig. 6.

[0120] 8, the internal terminal body 20 of the second internal terminal portion 42B has an internal terminal surface 21, an internal terminal back surface 22 opposite to the internal terminal surface 21, and an internal terminal side surface 23 connecting the internal terminal surface 21 and the internal terminal back surface 22. The internal terminal surface 21 of the second internal terminal portion 42B faces the same side as the internal terminal surface 21 of the first internal terminal portion 12B (see FIG. 6), and the internal terminal back surface 22 of the second internal terminal portion 42B faces the same side as the internal terminal back surface 22 of the first internal terminal portion 12B (see FIG. 6).

[0121] In the cross-sectional view of FIG. 8 , the leading end surface 24 faces the bottom surface of the first recessed portion 57AA of the second die pad 50A in the X direction (see FIG. 7 ). The leading end surface 24 is formed in a concave shape recessed away from the bottom surface of the first recessed portion 57AA. The leading end surface 24 is recessed from both the end on the internal terminal front surface 21 side and the end on the internal terminal back surface 22 side toward the center of the leading end surface 24 in the Z direction. In one example, the deepest position of the concave leading end surface 24 is approximately ⅓ of the thickness of the second internal terminal portion 42B from the internal terminal back surface 22. Note that the shape of the leading end surface 24 in the cross-sectional view of FIG. 8 can be changed as desired.

[0122] A plating layer 25 is formed on the internal terminal surface 21. The plating layer 25 is formed of a material containing, for example, silver. In one example, the plating layer 25 is formed of the same material as the plating layer 25 of the wire connection portion 12BB (see FIG. 6 ). The plating layer 25 is formed over substantially the entire internal terminal surface 21. The thickness of the plating layer 25 is thinner than the thickness of the internal terminal body 20 of the second internal terminal portion 42B. In one example, the thickness of the plating layer 25 of the second internal terminal portion 42B is equal to the thickness of the plating layer 25 of the wire connection portion 12BB. Here, if the difference between the thickness of the plating layer 25 of the second internal terminal portion 42B and the thickness of the plating layer 25 of the wire connection portion 12BB is, for example, within 20% of the thickness of the plating layer 25 of the second internal terminal portion 42B, then the thickness of the plating layer 25 of the second internal terminal portion 42B can be said to be equal to the thickness of the plating layer 25 of the wire connection portion 12BB.

[0123] In plan view, an end surface 25A of the plating layer 25 that is closer to the tip surface 24 of the second internal terminal portion 42B is formed closer to the second via 42C (see FIG. 7) than the edge of the internal terminal surface 21 that is closer to the tip surface 24. In other words, the plating layer 25 does not cover the edge of the internal terminal surface 21 that is closer to the tip surface 24. As a result, the end of the internal terminal surface 21, including the edge that is closer to the tip surface 24, is in contact with the sealing resin 90 (see FIG. 1).

[0124] 8 , the end surface 25A of the plating layer 25 is inclined from the front surface of the plating layer 25 toward the back surface thereof so as to move away from the end surface of the internal terminal surface 21 closer to the tip surface 24. The distance in the X direction between the back surface of the plating layer 25 and the edge of the internal terminal surface 21 closer to the tip surface 24 is, for example, equal to or greater than the thickness of the plating layer 25. Note that the distance in the X direction between the back surface of the plating layer 25 and the edge of the internal terminal surface 21 closer to the tip surface 24 can be changed as desired.

[0125] Furthermore, the plating layer 25 does not cover the tip surface 24 of the second internal terminal portion 42B. Therefore, the tip surface 24 is in contact with the sealing resin 90. Furthermore, although not shown, the plating layer 25 does not cover the internal terminal side surface 23 other than the tip surface 24. Therefore, the internal terminal side surface 23 is in contact with the sealing resin 90.

[0126] The detailed planar structures of the third die pad 50B and the third terminals 44 to 46 will be described. As shown in FIG. 7 , the third die pad 50B has a third leading end surface 51B, a third base end surface 52B, a fifth side surface 53B, and a sixth side surface 54B. The third leading end surface 51B is the end surface closest to the first sealing side surface 93 (see FIG. 3 ) among both end surfaces of the third die pad 50B in the X direction, and the third base end surface 52B is the end surface closest to the second sealing side surface 94 among both end surfaces of the third die pad 50B in the X direction. The fifth side surface 53B is the end surface closest to the third sealing side surface 95 among both end surfaces of the third die pad 50B in the Y direction, and the sixth side surface 54B is the end surface closest to the fourth sealing side surface 96 among both end surfaces of the third die pad 50B in the Y direction. The third tip surface 51B is a surface facing the first die pad 30 (see FIG. 3) in the X direction and extending along the Y direction in plan view. Both the fifth side surface 53B and the sixth side surface 54B are surfaces extending along the X direction in plan view.

[0127] The third die pad 50B further has a fifth tip curved surface 55BA, a sixth tip curved surface 55BB, and base curved surfaces 56BA and 56BB. The fifth tip curved surface 55BA is formed between the third tip surface 51B and the fifth side surface 53B. The fifth tip curved surface 55BA has a rounded chamfered shape at the portion between the third tip surface 51B and the fifth side surface 53B. The sixth tip curved surface 55BB is formed between the third tip surface 51B and the sixth side surface 54B. The sixth tip curved surface 55BB has a rounded chamfered shape at the portion between the third tip surface 51B and the sixth side surface 54B. In one example, in a plan view, the arc length of the fifth tip curved surface 55BA and the arc length of the sixth tip curved surface 55BB are equal to each other. In one example, it can be said that the radius of curvature of the fifth distal curved surface 55BA and the radius of curvature of the sixth distal curved surface 55BB are equal to each other in a plan view.

[0128] In one example, in a plan view, the arc lengths of the fifth and sixth distal curved surfaces 55BA and 55BB are equal to the arc lengths of the first and second distal curved surfaces 35A and 35B. In a plan view, the radii of curvature of the fifth and sixth distal curved surfaces 55BA and 55BB are equal to the radii of curvature of the first and second distal curved surfaces 35A and 35B.

[0129] In one example, in a plan view, the arc lengths of the fifth and sixth distal curved surfaces 55BA and 55BB are equal to the arc lengths of the third and fourth distal curved surfaces 55AA and 55AB. In a plan view, the radii of curvature of the fifth and sixth distal curved surfaces 55BA and 55BB are equal to the radii of curvature of the third and fourth distal curved surfaces 55AA and 55AB.

[0130] The proximal curved surface 56BA is formed between the third base end surface 52B and the fifth side surface 53B, and the proximal curved surface 56BB is formed between the third base end surface 52B and the sixth side surface 54B. The proximal curved surface 56BA has a R-chamfered shape at the portion between the second base end surface 52A and the fifth side surface 53B, and the proximal curved surface 56BB has a R-chamfered shape at the portion between the second base end surface 52A and the sixth side surface 54B. In the first embodiment, in a plan view, the arc lengths of both the fifth distal curved surface 55BA and the sixth distal curved surface 55BB are equal to the arc lengths of the proximal curved surfaces 56BA, 56BB. In other words, in a plan view, the radii of curvature of both the fifth distal curved surface 55BA and the sixth distal curved surface 55BB are equal to the radii of curvature of the proximal curved surfaces 56BA, 56BB.

[0131] The third die pad 50B further includes a third recessed portion 57BA and a fourth recessed portion 57BB. The third recessed portion 57BA and the fourth recessed portion 57BB are located at the same position in the X direction and spaced apart from each other in the Y direction. Both the third recessed portion 57BA and the fourth recessed portion 57BB are located so as to overlap the second chip 70 when viewed from the X direction. The third recessed portion 57BA and the fourth recessed portion 57BB are located closer to the sixth side surface 54B than the third external electrode 44A in a plan view. The fourth recessed portion 57BB is located closer to the sixth side surface 54B than the third recessed portion 57BA. Both the third recessed portion 57BA and the fourth recessed portion 57BB are located closer to the second sealing side surface 94 than the third chip 80 in a plan view.

[0132] Both the third recessed portion 57BA and the fourth recessed portion 57BB are open toward the second sealing side surface 94. Both the third recessed portion 57BA and the fourth recessed portion 57BB include a pair of side surfaces extending in the X direction from the third base end surface 52B toward the third tip surface 51B, and a curved concave surface provided between the pair of side surfaces and recessed toward the third tip surface 51B.

[0133] In plan view, the third terminal 45 fits into the third recessed portion 57BA. The third external electrode 45A of the third terminal 45 includes a protruding portion that protrudes from the third recessed portion 57BA toward the second sealing side surface 94 in plan view.

[0134] The third internal terminal portion 45B of the third terminal 45 is accommodated in the third recessed portion 57BA in plan view. As a result, the third internal terminal portion 45B is arranged to overlap the third external electrode 45A in plan view. The third internal terminal portion 45B is formed in a rectangular shape with its longitudinal direction in the X direction and its lateral direction in the Y direction in plan view. Four corners of the third internal terminal portion 45B are configured with curved surfaces.

[0135] The third via 45C connects the end of the third internal terminal 45B closer to the third chip 80 in the X direction to the third external electrode 45A. The third via 45C is connected to the end of the third external electrode 45A closer to the second chip 70.

[0136] In plan view, the third terminal 46 fits into the fourth recessed portion 57BB. The third external electrode 46A of the third terminal 46 includes a protruding portion that protrudes from the fourth recessed portion 57BB toward the second sealing side surface 94 in plan view.

[0137] The third internal terminal portion 46B of the third terminal 46 is accommodated in the fourth recessed portion 57BB in a plan view. As a result, the third internal terminal portion 46B is positioned to overlap the third external electrode 46A in a plan view. The third internal terminal portion 46B is formed in a rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction in a plan view. Four corners of the third internal terminal portion 46B are configured with curved surfaces. In the example shown in FIG. 7 , the shape of the third internal terminal portion 46B in a plan view is the same as the shape of the third internal terminal portion 46B in a plan view.

[0138] The third via 46C connects the end of the third internal terminal 46B closer to the third chip 80 in the X direction to the third external electrode 46A. The third via 46C is connected to the end of the third external electrode 46A closer to the second chip 70.

[0139] The third die pad 50B includes a portion that overlaps with the third external electrode 44A in plan view. The third external electrode 44A includes a portion that protrudes from the third die pad 50B toward the second sealing side surface 94 in plan view.

[0140] The third via 44C connects the third external electrode 44A to a portion of the third die pad 50B that overlaps with the third external electrode 44A. The third via 44C is connected to an end of the third external electrode 44A that is closer to the third tip surface 51B.

[0141] The cross-sectional structure of the third internal terminal portions 45B, 46B is the same as the cross-sectional structure of the second internal terminal portions 42B, 43B shown in Fig. 8. Therefore, description of the cross-sectional structure of the third internal terminal portions 45B, 46B will be omitted.

[0142] Next, we will explain the schematic configuration of the first chip 60, the second chip 70, and the third chip 80. As shown in Figure 5, the first chip 60 mounted on the first die pad 30 has a chip front surface 61, a chip back surface 62 (see Figure 14) facing the opposite side to the chip front surface 61 in the Z direction, and first to fourth chip side surfaces 63 to 66 connecting the chip front surface 61 and the chip back surface 62.

[0143] The chip front surface 61 faces the side opposite to the first die pad 30 with respect to the first chip 60, and the chip back surface 62 faces the side facing the first die pad 30. The first chip side surface 63 and the second chip side surface 64 constitute both end faces of the first chip 60 in the X direction in a plan view. The first chip side surface 63 is the chip side surface on the side of the first chip 60 on which the first terminals 11 to 17 are arranged, and the second chip side surface 64 is the chip side surface on the side of the first chip 60 on which the second chip 70 and the third chip 80 (both see FIG. 7 ) are arranged. The third chip side surface 65 and the fourth chip side surface 66 constitute both end faces of the first chip 60 in the Y direction in a plan view. The third chip side surface 65 is the chip side surface closer to the third sealing side surface 95 of the sealing resin 90, and the fourth chip side surface 66 is the chip side surface closer to the fourth sealing side surface 96.

[0144] The first chip 60 has a plurality of first electrode pads 67 (six in the first embodiment), a plurality of second electrode pads 68 (seven in the first embodiment), and a plurality of third electrode pads 69 (two in the first embodiment). Each of the first electrode pads 67, each of the second electrode pads 68, and each of the third electrode pads 69 are provided so as to be exposed from the chip surface 61. The number of each of the second electrode pads 68 and the third electrode pads 69 can be changed as desired.

[0145] Each of the first electrode pads 67, second electrode pads 68, and third electrode pads 69 may include at least one of titanium (Ti), titanium nitride (TiN), copper (Cu), aluminum (Al), and tungsten (W). In one example, each of the first electrode pads 67, second electrode pads 68, and third electrode pads 69 has a laminated structure of titanium and copper. Note that the material constituting one or two of the first electrode pads 67, second electrode pads 68, and third electrode pads 69 may be different from the material constituting the remaining electrode pads.

[0146] In another example, each of the first electrode pads 67, second electrode pads 68, and third electrode pads 69 contains aluminum. In this case, each of the first electrode pads 67, second electrode pads 68, and third electrode pads 69 exposed from the chip surface 61 has a thickness of 2 μm or more. Note that the thickness of each of the first electrode pads 67, second electrode pads 68, and third electrode pads 69 can be changed as desired.

[0147] The multiple first electrode pads 67 are electrode pads electrically connected to the second chip 70 and the third chip 80. The multiple first electrode pads 67 are provided at positions closer to the second chip side surface 64 than the center of the chip surface 61 in the X direction in a plan view. The multiple first electrode pads 67 are arranged at the same positions as each other in the X direction and spaced apart from each other in the Y direction. The multiple first electrode pads 67 can be divided into three first electrode pads 67 electrically connected to the second chip 70 and three first electrode pads 67 electrically connected to the third chip 80. The three first electrode pads 67 electrically connected to the second chip 70 are arranged closer to the third chip side surface 65 on the chip surface 61. The three first electrode pads 67 electrically connected to the third chip 80 are arranged closer to the fourth chip side surface 66 on the chip surface 61.

[0148] The second electrode pads 68 are electrode pads that are individually and electrically connected to the first terminals 12 to 17. The second electrode pads 68 are provided at positions closer to the first chip side surface 63 than the center of the chip surface 61 in the X direction in a plan view.

[0149] The multiple third electrode pads 69 are electrode pads electrically connected to the first die pad 30. Each third electrode pad 69 has the same potential as the first die pad 30, i.e., the first ground potential. The multiple third electrode pads 69 are provided at an end of the chip surface 61 closer to the fourth sealing side surface 96 in a plan view. The multiple third electrode pads 69 are provided at a portion of the chip surface 61 closer to the first chip side surface 63 in a plan view.

[0150] As shown in FIG. 7, the second chip 70 mounted on the second die pad 50A has a chip surface 71, a chip back surface (not shown) facing the opposite side of the chip surface 71 in the Z direction, and first to fourth chip side surfaces 73 to 76 connecting the chip surface 71 and the chip back surface.

[0151] The chip front surface 71 faces the side opposite to the second die pad 50A with respect to the second chip 70, and the chip back surface faces the side facing the second die pad 50A. The first chip side surface 73 and the second chip side surface 74 constitute both end faces of the second chip 70 in the X direction in a plan view. The first chip side surface 73 is the chip side surface of the second chip 70 on which the first chip 60 (see FIG. 5) is arranged, and the second chip side surface 74 is the chip side surface of the second chip 70 on which the second terminals 41 to 43 are arranged. The third chip side surface 75 and the fourth chip side surface 76 constitute both end faces of the second chip 70 in the Y direction in a plan view. The third chip side surface 75 is the chip side surface closer to the third sealing side surface 95 of the sealing resin 90, and the fourth chip side surface 76 is the chip side surface closer to the fourth sealing side surface 96.

[0152] The second chip 70 has a plurality of (three in the first embodiment) first electrode pads 77, a plurality of (four in the first embodiment) second electrode pads 78, and a plurality of (three in the first embodiment) third electrode pads 79. Each of the first electrode pads 77, each of the second electrode pads 78, and each of the third electrode pads 79 is provided so as to be exposed from the chip surface 71.

[0153] Each of the first electrode pads 77, second electrode pads 78, and third electrode pads 79 may contain at least one of titanium, titanium nitride, copper, aluminum, and tungsten. In one example, each of the first electrode pads 77, second electrode pads 78, and third electrode pads 79 has a laminated structure of titanium and copper. Note that the material constituting one or two of the first electrode pads 77, second electrode pads 78, and third electrode pads 79 may be different from the material constituting the remaining electrode pads.

[0154] In another example, each of the first electrode pads 77, second electrode pads 78, and third electrode pads 79 contains aluminum. In this case, each of the first electrode pads 77, second electrode pads 78, and third electrode pads 79 exposed from the chip surface 71 has a thickness of 2 μm or more. Note that the thickness of each of the first electrode pads 77, second electrode pads 78, and third electrode pads 79 can be changed as desired.

[0155] The first electrode pads 77 are electrode pads that are individually and electrically connected to three first electrode pads 67 (see FIG. 5 ) that are closer to the third chip side surface 65 among the first electrode pads 67 of the first chip 60. The first electrode pads 77 are provided at positions closer to the first chip side surface 73 than the center in the X direction of the chip surface 71 in a plan view. The first electrode pads 77 are arranged at the same positions as each other in the X direction and spaced apart from each other in the Y direction.

[0156] The second electrode pads 78 are electrode pads that are individually and electrically connected to the second terminals 42 and 43. The second electrode pads 78 are provided at positions closer to the fourth chip side surface 76 than the center of the chip surface 71 in the Y direction in a plan view.

[0157] The multiple third electrode pads 79 are electrode pads electrically connected to the second die pad 50A. Each third electrode pad 79 has the same potential as the second die pad 50A, i.e., the second ground potential. The multiple third electrode pads 79 are provided at the ends of the chip surface 71 in the Y direction that are closer to the third sealing side surface 95 in a plan view. The multiple third electrode pads 79 are arranged at the same positions as each other in the Y direction and spaced apart from each other in the X direction.

[0158] As shown in FIG. 7, the third chip 80 mounted on the third die pad 50B has a chip surface 81, a chip back surface (not shown) facing the opposite side of the chip surface 81 in the Z direction, and first to fourth chip side surfaces 83 to 86 connecting the chip surface 81 and the chip back surface.

[0159] The chip front surface 81 faces the side opposite to the third die pad 50B with respect to the third chip 80, and the chip back surface faces the side facing the third die pad 50B. The first chip side surface 83 and the second chip side surface 84 constitute both end faces of the third chip 80 in the X direction in a plan view. The first chip side surface 83 is the chip side surface of the third chip 80 on which the first chip 60 (see FIG. 5) is arranged, and the second chip side surface 84 is the chip side surface of the third chip 80 on which the third terminals 44 to 46 are arranged. The third chip side surface 85 and the fourth chip side surface 86 constitute both end faces of the third chip 80 in the Y direction in a plan view. The third chip side surface 85 is the chip side surface closer to the third sealing side surface 95 of the sealing resin 90, and the fourth chip side surface 86 is the chip side surface closer to the fourth sealing side surface 96.

[0160] The third chip 80 has a plurality of (three in the first embodiment) first electrode pads 87, a plurality of (four in the first embodiment) second electrode pads 88, and a plurality of (two in the first embodiment) third electrode pads 89. Each of the first electrode pads 87, each of the second electrode pads 88, and each of the third electrode pads 89 is provided so as to be exposed from the chip surface 81.

[0161] Each of the first electrode pads 87, second electrode pads 88, and third electrode pads 89 may contain at least one of titanium, titanium nitride, copper, aluminum, and tungsten. In one example, each of the first electrode pads 87, second electrode pads 88, and third electrode pads 89 has a laminated structure of titanium and copper. Note that the material constituting one or two of the first electrode pads 87, second electrode pads 88, and third electrode pads 89 may be different from the material constituting the remaining electrode pads.

[0162] In another example, each of the first electrode pads 87, second electrode pads 88, and third electrode pads 89 contains aluminum. In this case, each of the first electrode pads 87, second electrode pads 88, and third electrode pads 89 exposed from the chip surface 81 has a thickness of 2 μm or more. Note that the thickness of each of the first electrode pads 87, second electrode pads 88, and third electrode pads 89 can be changed as desired.

[0163] The multiple first electrode pads 87 are electrode pads that are individually and electrically connected to three first electrode pads 67 that are closer to the fourth chip side surface 66 among the multiple first electrode pads 67 of the first chip 60. The multiple first electrode pads 87 are provided at positions closer to the first chip side surface 83 than the center in the X direction of the chip surface 81 in a plan view. The multiple first electrode pads 87 are arranged at the same positions as each other in the X direction and spaced apart from each other in the Y direction.

[0164] The second electrode pads 88 are electrode pads that are individually and electrically connected to the third terminals 45, 46. The second electrode pads 88 are provided at positions closer to the fourth chip side surface 86 than the center of the chip surface 81 in the Y direction in a plan view.

[0165] The multiple third electrode pads 89 are electrode pads electrically connected to the third die pad 50B. Each third electrode pad 89 has the same potential as the third die pad 50B, i.e., the third ground potential. The multiple third electrode pads 89 are provided at the ends of the chip surface 81 in the Y direction that are closer to the third sealing side surface 95 in a plan view. The multiple third electrode pads 89 are arranged at the same positions as each other in the Y direction and spaced apart from each other in the X direction.

[0166] Next, the electrical connection configuration of the first chip 60, the second chip 70, and the third chip 80 will be described. As shown in Figure 3, the signal transmission device 10 includes inter-chip wires WA that individually connect the first chip 60 to the second chip 70 and the third chip 80, first terminal wires WB that individually connect the first chip 60 to the first terminals 12 to 17, and first die pad wires WC that connect the first chip 60 to the first die pad 30. The inter-chip wires WA, the first terminal wires WB, and the first die pad wires WC are sealed with sealing resin 90.

[0167] 5 and 7 , three of the first electrode pads 67 on the first chip 60 that are closer to the third chip side surface 65 are individually connected to the first electrode pads 77 on the second chip 70 by a plurality of inter-chip wires WA (three in the first embodiment). This electrically connects the first electrode pads 67 to the first electrode pads 77 individually. Because the first electrode pads 77 are positioned closer to the third sealing side surface 95 than the first electrode pads 67, each inter-chip wire WA extends obliquely toward the third sealing side surface 95 from the first electrode pad 67 toward the first electrode pad 77 in a planar view. The three inter-chip wires WA are parallel to each other in a planar view.

[0168] Of the multiple first electrode pads 67 of the first chip 60, three first electrode pads 67 closest to the fourth chip side surface 66 are individually connected to the multiple first electrode pads 87 of the third chip 80 by multiple inter-chip wires WA (three in the first embodiment). This electrically connects the multiple first electrode pads 67 to the multiple first electrode pads 87 individually. Because the multiple first electrode pads 87 are positioned closer to the fourth sealing side surface 96 than the multiple first electrode pads 67, each inter-chip wire WA extends obliquely toward the fourth sealing side surface 96 as it moves from the first electrode pad 67 to the first electrode pad 87 in a planar view. The three inter-chip wires WA are parallel to each other in a planar view.

[0169] 5, the second electrode pads 68 of the first chip 60 and the first terminals 12 to 17 are individually connected by a plurality of first terminal wires WB (seven in the first embodiment). This electrically connects the first chip 60 to the first terminals 12 to 17. Each of the first terminals 12 to 16 is individually connected to the second electrode pads 68 by one first terminal wire WB. The first terminal 17 is individually connected to the second electrode pads 68 by two first terminal wires WB.

[0170] The first terminal wire WB is a bonding wire formed by a wire bonding device. In one example, the first terminal wire WB has a first bond portion bonded to the second electrode pad 68 and a second bond portion bonded to the first terminals 12 to 17. The first terminal wire WB is connected to the first internal terminal portions 12B to 17B of the first terminals 12 to 17.

[0171] The wire connection portion 12BB of the first internal terminal 12B includes a side surface that intersects with the first terminal wire WB connected to the wire connection portion 12BB in a planar view. This side surface faces the first die pad 30 in a planar view. In the first embodiment, the side surface of the wire connection portion 12BB forms the tip surface of the wire connection portion 12BB and faces the curved concave surface 37A3 of the first recessed portion 37A of the first die pad 30 in the Y direction. The first terminal wire WB is connected to an end of the wire connection portion 12BB of the first terminal 12 that is closer to the first chip 60. The first terminal wire WB is connected to a protruding portion of the wire connection portion 12BB that protrudes from the first external electrode 12A in a planar view. In other words, the first terminal wire WB is connected to a portion of the wire connection portion 12BB that is closer to the first chip 60 than the first external electrode 12A in a planar view.

[0172] The first internal terminal portion 13B includes a side surface that intersects with the first terminal wire WB connected to the first internal terminal portion 13B in a plan view. This side surface faces the first die pad 30 in a plan view. In the first embodiment, the side surface of the first internal terminal portion 13B forms the tip surface of the first internal terminal portion 13B and faces the second recessed portion 37B of the first die pad 30 in the X direction. The first terminal wire WB is connected to a portion of the first internal terminal portion 13B of the first terminal 13 that is closer to the first sealing side surface 93 than the first via 13C.

[0173] The first internal terminal portion 14B includes a side surface that intersects with the first terminal wire WB connected to the first internal terminal portion 14B in a plan view. This side surface faces the first die pad 30 in a plan view. In the first embodiment, the side surface of the first internal terminal portion 14B forms an opposing surface of the first terminal portion 14BA of the first internal terminal portion 14B that faces the first die pad 30 in the X direction. The first terminal wire WB is connected to a protruding portion of the first terminal portion 14BA of the first internal terminal portion 14B that protrudes from the first external electrode 14A in a plan view.

[0174] The first internal terminal portion 15B includes a side surface that intersects with the first terminal wire WB connected to the first internal terminal portion 15B in a plan view. This side surface faces the first die pad 30 in a plan view. In the first embodiment, the side surface of the first internal terminal portion 15B forms the tip surface of the first internal terminal portion 15B and faces the bottom surface 37C2 of the third recessed portion 37C of the first die pad 30 in the X direction. The first terminal wire WB is connected to a portion of the first internal terminal portion 15B of the first terminal 15 that is closer to the first sealing side surface 93 than the first via 15C.

[0175] The first terminal wire WB connected to the first internal terminal portion 16B is connected to a portion of the first internal terminal portion 16B that protrudes from the first external electrode 16A in a plan view. The first terminal wire WB is connected to the first internal terminal portion 16B that is closer to the first chip 60 than the first external electrode 16A in the direction in which the first terminal wire WB extends in a plan view.

[0176] The wire connection portion 17BC of the first internal terminal portion 17B includes a side surface that intersects with the first terminal wire WB connected to the wire connection portion 17BC in a plan view. This side surface faces the first die pad 30 in a plan view. In the first embodiment, the side surface of the wire connection portion 17BC faces the curved concave surface 37C1 of the third recessed portion 37C of the first die pad 30 in the X direction. The first terminal wire WB is connected to a portion of the first terminal 17 that is closer to the first chip 60 than the first external electrode 17A in a plan view.

[0177] The multiple third electrode pads 69 of the first chip 60 and the first die pad 30 are individually connected by multiple (two in the first embodiment) first die pad wires WC. This electrically connects the first chip 60 and the first die pad 30. In other words, the multiple third electrode pads 69 are at the first ground potential. It can also be said that the multiple third electrode pads 69 are electrically connected to the first terminals 11.

[0178] The first die pad wire WC is a bonding wire formed by a wire bonding apparatus. In one example, the first die pad wire WC has a first bond portion at the bonded portion with the third electrode pad 69 and a second bond portion at the bonded portion with the first die pad 30. In the first embodiment, the second bond portion is formed in a portion of the first die pad 30 closer to the second side surface 34 than the first chip 60.

[0179] 7 , signal transmission device 10 includes second terminal wires WD that individually connect second chip 70 to multiple second terminals 42, 43, and second die pad wires WE that connect second chip 70 to second die pad 50A. Second terminal wires WD and second die pad wires WE are sealed with sealing resin 90.

[0180] 7 , the second electrode pads 78 of the second chip 70 and the second terminals 42, 43 are individually connected by a plurality of second terminal wires WD (four in the first embodiment). This electrically connects the second chip 70 to the second terminals 42, 43. Each of the second terminals 42, 43 is individually connected to the second electrode pads 78 by two second terminal wires WD.

[0181] The second terminal wire WD is a bonding wire formed by a wire bonding apparatus. In one example, the second terminal wire WD has a first bond portion bonded to the second electrode pad 78 and a second bond portion bonded to the second terminals 42, 43. The second terminal wire WD is connected to the second internal terminal portions 42B, 43B of the second terminals 42, 43.

[0182] More specifically, the second internal terminal portion 42B includes a side surface that intersects with the second terminal wire WD connected to the second internal terminal portion 42B in a plan view. This side surface faces the second die pad 50A in a plan view. In the first embodiment, the side surface of the second internal terminal portion 42B constitutes the tip surface of the second internal terminal portion 42B and faces the curved concave surface of the first recessed portion 57AA of the second die pad 50A in the X direction.

[0183] The second internal terminal portion 43B includes a side surface that intersects with the second terminal wire WD connected to the second internal terminal portion 43B in a plan view. This side surface faces the second die pad 50A in a plan view. In the first embodiment, the side surface of the second internal terminal portion 43B constitutes the tip surface of the second internal terminal portion 43B and faces the curved concave surface of the second recess portion 57AB of the second die pad 50A in the X direction.

[0184] The multiple third electrode pads 79 of the second chip 70 and the second die pad 50A are individually connected by multiple (three in the first embodiment) second die pad wires WE. This electrically connects the second chip 70 and the second die pad 50A. Therefore, the third electrode pads 79 of the second chip 70 are at the second ground potential. It can also be said that the third electrode pads 79 are electrically connected to the second terminals 41. The second die pad wires WE are connected to a portion of the second die pad 50A that is closer to the third side surface 53A than the second chip 70.

[0185] 7 , signal transmission device 10 includes third terminal wires WF that individually connect third chip 80 to multiple third terminals 45, 46, and third die pad wires WG that connect third chip 80 to third die pad 50B. Third terminal wires WF and third die pad wires WG are sealed with sealing resin 90.

[0186] The second electrode pads 88 of the third chip 80 and the third terminals 45, 46 are individually connected by a plurality of third terminal wires WF (four in the first embodiment), thereby electrically connecting the third chip 80 and the third terminals 45, 46 individually. Each of the third terminals 45, 46 is individually connected to the second electrode pads 88 by two third terminal wires WF.

[0187] The third terminal wire WF is a bonding wire formed by a wire bonding apparatus. In one example, the third terminal wire WF has a first bond portion bonded to the second electrode pad 88 and a second bond portion bonded to the third terminals 45, 46. The third terminal wire WF is connected to the third internal terminal portions 45B, 46B of the third terminals 45, 46.

[0188] More specifically, the third internal terminal portion 45B includes a side surface that intersects with the third terminal wire WF connected to the third internal terminal portion 45B in a plan view. This side surface faces the third die pad 50B in a plan view. In the first embodiment, the side surface of the third internal terminal portion 45B constitutes the tip surface of the third internal terminal portion 45B and faces the curved concave surface of the third recessed portion 57BA of the third die pad 50B in the X direction.

[0189] The third internal terminal portion 46B includes a side surface that intersects with the third terminal wire WF connected to the third internal terminal portion 46B in a plan view. This side surface faces the third die pad 50B in a plan view. In the first embodiment, the side surface of the third internal terminal portion 46B constitutes the tip surface of the third internal terminal portion 46B and faces the curved concave surface of the fourth recessed portion 57BB of the third die pad 50B in the X direction.

[0190] The third electrode pads 89 of the third chip 80 and the third die pad 50B are individually connected by a plurality of third die pad wires WG (two in the first embodiment). This electrically connects the third chip 80 and the third die pad 50B. Therefore, the third electrode pads 89 of the third chip 80 are at a third ground potential. It can also be said that the third electrode pads 89 are electrically connected to the third terminals 44. The third die pad wires WG are connected to a portion of the third die pad 50B that is closer to the fifth side surface 53B than the third chip 80.

[0191] The second die pad wire WE and the third die pad wire WG are each a bonding wire formed by a wire bonding apparatus. In one example, the second die pad wire WE has a first bond portion bonded to the third electrode pad 79 and a second bond portion bonded to the second die pad 50A. In one example, the third die pad wire WG has a first bond portion bonded to the third electrode pad 89 and a second bond portion bonded to the third die pad 50B.

[0192] 3 , the inter-chip wire WA is made of a material different from the materials constituting the first terminal wire WB, the first die pad wire WC, the second terminal wire WD, the second die pad wire WE, the third terminal wire WF, and the third die pad wire WG. In one example, the first terminal wire WB, the first die pad wire WC, the second terminal wire WD, the second die pad wire WE, the third terminal wire WF, and the third die pad wire WG are made of the same material.

[0193] The inter-chip wires WA are formed of a material containing gold. The first terminal wires WB, the first die pad wires WC, the second terminal wires WD, the second die pad wires WE, the third terminal wires WF, and the third die pad wires WG are each formed of a material containing copper. In one example, the first terminal wires WB, the first die pad wires WC, the second terminal wires WD, the second die pad wires WE, the third terminal wires WF, and the third die pad wires WG are each configured as copper wires whose surfaces are coated with palladium (Pd). This allows for improved oxidation resistance and corrosion resistance compared to copper wires whose surfaces are not coated with palladium.

[0194] In addition, each of the first terminal wire WB, the first die pad wire WC, the second terminal wire WD, the second die pad wire WE, the third terminal wire WF, and the third die pad wire WG may be formed from a material containing aluminum.

[0195] [Circuit Configuration of Signal Transmission Device] The circuit configuration of the signal transmission device 10 of the first embodiment will be described with reference to Figure 9. The signal transmission device 10 includes a first circuit 500, a second circuit 520, and a third circuit 530, as well as a first transformer 111 and a second transformer 112. In the first embodiment, the first chip 60 includes the first circuit 500, the first transformer 111, and the second transformer 112, the second chip 70 includes the second circuit 520, and the third chip 80 includes the third circuit 530. The first transformer 111 is configured to insulate the first circuit 500 from the second circuit 520 and to enable signal exchange between the first circuit 500 and the second circuit 520. The second transformer 112 is configured to insulate the first circuit 500 from the third circuit 530 and to enable signal exchange between the first circuit 500 and the third circuit 530.

[0196] The signal transmission device 10 also has first terminals P1 to P6 which are external terminals electrically connected to the first circuit 500, and second terminals Q1 to Q6 which are external terminals electrically connected to the second circuit 520 and the third circuit 530.

[0197] The first terminal P1 is a power supply terminal (VDDI), the first terminal P2 is a regulator terminal (SLDO), the first terminal P3 is a signal input terminal (PWM), the first terminal P4 is an unused terminal (DISABLE), the first terminal P5 is a timing adjustment terminal (TNEG), and the first terminal P6 is a ground terminal (GNDI). In the first embodiment, the first terminal P1 corresponds to the first terminal 17, the first terminal P2 corresponds to the first terminal 14, the first terminal P3 corresponds to the first terminal 12, the first terminal P4 corresponds to the first terminal 15, the first terminal P5 corresponds to the first terminal 16, and the first terminal P6 corresponds to the first terminal 11. In the first embodiment, the first terminal 13 is, for example, a test terminal.

[0198] The second terminal Q1 is a ground terminal (GNDG), the second terminal Q2 is an output terminal (OUTG), the second terminal Q3 is a power supply terminal (VDDG), the second terminal Q4 is a ground terminal (GNDS), the second terminal Q5 is an output terminal (OUTS), and the second terminal Q6 is a power supply terminal (VDDS). In the first embodiment, the second terminal Q1 corresponds to the second terminal 41, the second terminal Q2 corresponds to the second terminal 42, the second terminal Q3 corresponds to the second terminal 43, the second terminal Q4 corresponds to the third terminal 44, the second terminal Q5 corresponds to the third terminal 45, and the second terminal Q6 corresponds to the third terminal 46.

[0199] The first circuit 500 includes a first transmitting unit 501, a second transmitting unit 502, a logic unit 503, an LDO (Low Dropout) unit 504, an UVLO (Under Voltage Lock Out) unit 505, a delay unit 506, Schmitt triggers 507 and 508, and resistors 509 and 510.

[0200] The first terminal P1 is electrically connected to the UVLO unit 505 and the LDO unit 504, the first terminal P2 is electrically connected to the LDO unit 504, the first terminals P3 and P4 are electrically connected to the logic unit 503, and the first terminal P5 is electrically connected to the delay unit 506. The LDO unit 504 is electrically connected to the UVLO unit 505. The UVLO unit 505, the delay unit 506, the first transmission unit 501, and the second transmission unit 502 are each electrically connected to the logic unit 503.

[0201] The first transmitting unit 501 is electrically connected to the first coil of the first transformer 111. The first transmitting unit 501 is configured to transmit the PWM signal input from the logic unit 503 to the second circuit 520 using the first transformer 111.

[0202] The second transmitting unit 502 is electrically connected to the first coil of the second transformer 112. The second transmitting unit 502 is configured to transmit the PWM signal input from the logic unit 503 to the third circuit 530 using the second transformer 112.

[0203] The logic unit 503 is configured to exchange various signals with an external control device (not shown) of the signal transmission device 10 via the first terminals P3 to P5, and to exchange various signals with the second circuit 520 and the third circuit 530 using the first transmission unit 501 and the second transmission unit 502.

[0204] A Schmitt trigger 507 and a resistor 509 are provided in the conductive path between the first terminal P3 and the logic unit 503. An input terminal of the Schmitt trigger 507 is electrically connected to the first terminal P3, and an output terminal of the Schmitt trigger 507 is electrically connected to the logic unit 503. The resistor 509 is, for example, a pull-down resistor. A first terminal of the resistor 509 is electrically connected between the first terminal P3 and the input terminal of the Schmitt trigger 507 in the conductive path, and a second terminal of the resistor 509 is electrically connected to the first terminal P6.

[0205] A Schmitt trigger 508 and a resistor 510 are provided in the conductive path between the first terminal P4 and the logic unit 503. An input terminal of the Schmitt trigger 508 is electrically connected to the first terminal P4, and an output terminal of the Schmitt trigger 508 is electrically connected to the logic unit 503. The resistor 510 is, for example, a pull-down resistor. A first terminal of the resistor 510 is electrically connected between the first terminal P4 and the input terminal of the Schmitt trigger 508 in the conductive path, and a second terminal of the resistor 510 is electrically connected to the first terminal P6.

[0206] The LDO unit 504 is, for example, a shunt regulator, and is configured to set the voltage between the first terminal P1 and the first terminal P6 to a preset reference voltage. The UVLO unit 505 stops the operation of the logic unit 503 when the voltage of the control power supply electrically connected to the first terminal P1 falls below a threshold voltage, thereby suppressing malfunction.

[0207] The second circuit 520 includes a first receiving unit 521, a logic unit 522, a UVLO unit 523, buffer circuits 524 and 525, switching elements 526 and 527, and a resistor 528. The second terminals Q1 and Q2 are electrically connected to the logic unit 522, and the second terminal Q1 is electrically connected to the UVLO unit 523. The UVLO unit 523 and the first receiving unit 521 are electrically connected to the logic unit 522.

[0208] The first receiving unit 521 is electrically connected to the second coil of the first transformer 111. The first receiving unit 521 is configured to receive the PWM signal from the first transmitting unit 501 via the first transformer 111 and output the received PWM signal to the logic unit 522.

[0209] The UVLO unit 523 stops operation of the logic unit 522 when the voltage of the control power supply electrically connected to the second terminal Q3 falls below a threshold voltage, thereby preventing malfunction. The logic unit 522 is configured to individually control the switching elements 526 and 527. More specifically, the logic unit 522 is individually and electrically connected to the gates of the switching elements 526 and 527. A buffer circuit 524 is provided between the logic unit 522 and the gate of the switching element 526. An input terminal of the buffer circuit 524 is electrically connected to the logic unit 522, and an output terminal of the buffer circuit 524 is electrically connected to the gate of the switching element 526. A buffer circuit 525 is provided between the logic unit 522 and the gate of the switching element 527. An input terminal of the buffer circuit 525 is electrically connected to the logic unit 522, and an output terminal of the buffer circuit 525 is electrically connected to the gate of the switching element 527.

[0210] A p-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is used as the switching element 526, and an n-channel MOSFET is used as the switching element 527. The source of the switching element 526 is electrically connected to the second terminal Q3, and the drain of the switching element 526 is electrically connected to the drain of the switching element 527. The source of the switching element 527 is electrically connected to the second terminal Q1. The node between the drain of the switching element 526 and the drain of the switching element 527 is electrically connected to the second terminal Q2. A resistor 528 is provided between the gate and drain of the switching element 526.

[0211] The third circuit 530 includes a second receiving unit 531, a logic unit 532, a UVLO unit 533, buffer circuits 534 and 535, switching elements 536 and 537, and a resistor 538. The second terminals Q4 and Q5 are electrically connected to the logic unit 532, and the second terminal Q6 is electrically connected to the UVLO unit 533. The UVLO unit 533 and the second receiving unit 531 are electrically connected to the logic unit 532.

[0212] The second receiving unit 531 is electrically connected to the second coil of the second transformer 112. The second receiving unit 531 is configured to receive the PWM signal from the second transmitting unit 502 via the second transformer 112 and output the received PWM signal to the logic unit 532.

[0213] The UVLO unit 533 stops operation of the logic unit 532 when the voltage of the control power supply electrically connected to the second terminal Q6 falls below a threshold voltage, thereby preventing malfunction. The logic unit 532 is configured to individually control the switching elements 536 and 537. More specifically, the logic unit 532 is electrically connected to the gates of the switching elements 536 and 537 individually. A buffer circuit 534 is provided between the logic unit 532 and the gate of the switching element 536. An input terminal of the buffer circuit 534 is electrically connected to the logic unit 532, and an output terminal of the buffer circuit 534 is electrically connected to the gate of the switching element 536. A buffer circuit 535 is provided between the logic unit 532 and the gate of the switching element 537. An input terminal of the buffer circuit 535 is electrically connected to the logic unit 532, and an output terminal of the buffer circuit 535 is electrically connected to the gate of the switching element 537.

[0214] A p-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is used as the switching element 536, and an n-channel MOSFET is used as the switching element 537. The source of the switching element 536 is electrically connected to the second terminal Q6, and the drain of the switching element 536 is electrically connected to the drain of the switching element 537. The source of the switching element 537 is electrically connected to the second terminal Q4. The node between the drain of the switching element 536 and the drain of the switching element 537 is electrically connected to the second terminal Q5. A resistor 538 is provided between the gate and drain of the switching element 536.

[0215] [Detailed Configuration of First Chip] The detailed configuration of the first chip 60 including part of the circuit configuration of the signal transmission device 10 described above will be described with reference to FIGS.

[0216] 10 to 13 show a schematic planar structure of an example of the internal configuration of the first chip 60. Figures 14 to 19 show a schematic cross-sectional structure of an example of the internal configuration of the first chip 60. To make the drawings easier to understand, hatching lines have been omitted from the schematic cross-sectional structure of the first chip 60 in Figure 14.

[0217] (Planar Structure of First Chip) Fig. 10 shows a schematic planar structure of an example of the internal configuration of the first chip 60 near the chip surface 61. Fig. 11 is an enlarged view of an insulating transformer region 110, which will be described later, in Fig. 10. Fig. 12 shows a schematic planar structure of an example of the internal structure of the first chip 60 near the chip back surface 62. Fig. 13 is an enlarged view of the insulating transformer region 110 in Fig. 12.

[0218] The first chip 60 has an isolation transformer region 110, a circuit region 120, and a peripheral guard ring 100 connected to the isolation transformer region 110 and surrounding the circuit region 120. The isolation transformer region 110 electrically insulates the circuit region 120 from the second chip 70 while allowing signal transmission between the circuit region 120 and the second chip 70 and the third chip 80. The isolation transformer region 110 is formed closer to the second chip side surface 64 with respect to the center of the first chip 60 in the X direction in a plan view. That is, the isolation transformer region 110 is formed in a region of the first chip 60 close to the second chip 70 and the third chip 80 (see FIG. 3 for both). The isolation transformer region 110 extends across substantially the entire first chip 60 in the Y direction.

[0219] 9 are formed in the circuit region 120. These components include a first transmission unit 501, a second transmission unit 502, a logic unit 503, an LDO unit 504, and a UVLO unit 505. In the following description, the components of the first circuit 500 other than the first transformer 111 and the second transformer 112 may be referred to as "plurality of first function units" and "plurality of circuit elements."

[0220] A plurality of second electrode pads 68 and a plurality of third electrode pads 69 are formed in the circuit region 120. The plurality of second electrode pads 68 are electrically connected to at least one of the plurality of first function units and the plurality of circuit elements. The plurality of third electrode pads 69 are electrically connected to the plurality of circuit elements.

[0221] A first transformer 111 and a second transformer 112 are formed in the isolation transformer region 110. The first transformer 111 and the second transformer 112 are arranged at the same position in the X direction and spaced apart from each other in the Y direction. In the example shown in Fig. 10 , the first transformer 111 is arranged closer to the third chip side surface 65 in the isolation transformer region 110, and the second transformer 112 is arranged closer to the fourth chip side surface 66 in the isolation transformer region 110.

[0222] 10 and 12, the first transformer 111 includes a first front-side coil 111A and a first back-side coil 111B, a second front-side coil 112A and a second back-side coil 112B, and the second transformer 112 includes a third front-side coil 113A and a third back-side coil 113B, and a fourth front-side coil 114A and a fourth back-side coil 114B.

[0223] 10, the first to fourth surface side coils 111A to 114A are arranged at the same positions in the X direction and spaced apart from one another in the Y direction. The first to fourth surface side coils 111A to 114A are arranged in the order of the first surface side coil 111A, the second surface side coil 112A, the third surface side coil 113A, and the fourth surface side coil 114A, moving from the third chip side surface 65 to the fourth chip side surface 66.

[0224] 12, the first to fourth back-side coils 111B to 114B are arranged at the same positions in the X direction and spaced apart from one another in the Y direction. The first to fourth back-side coils 111B to 114B are arranged in the following order from the third chip side surface 65 to the fourth chip side surface 66: the first back-side coil 111B, the second back-side coil 112B, the third back-side coil 113B, and the fourth back-side coil 114B.

[0225] Although not shown, the first front surface side coil 111A, the second front surface side coil 112A, the third front surface side coil 113A, and the fourth front surface side coil 114A are arranged at the same positions in the Z direction. The first back surface side coil 111B, the second back surface side coil 112B, the third back surface side coil 113B, and the fourth back surface side coil 114B are arranged at the same positions in the Z direction.

[0226] The first to fourth front-surface side coils 111A to 114A and the first to fourth back-surface side coils 111B to 114B may each contain at least one of titanium, titanium nitride, copper, aluminum, and tungsten. For example, the first to fourth front-surface side coils 111A to 114A contain copper, and the first to fourth back-surface side coils 111B to 114B contain aluminum. For example, the first to fourth front-surface side coils 111A to 114A have a laminated structure of titanium and copper, and the first to fourth back-surface side coils 111B to 114B have a laminated structure of titanium nitride and aluminum.

[0227] 10 , a plurality of first electrode pads 67 are formed in the insulating transformer region 110. The plurality of first electrode pads 67 are arranged at the same positions in the X direction and spaced apart from one another in the Y direction. The plurality of first electrode pads 67 include six first electrode pads 67A to 67F. The first electrode pads 67A to 67F are arranged in the order of first electrode pads 67A, 67B, 67C, 67D, 67E, and 67F as they move from the third chip side surface 65 to the fourth chip side surface 66.

[0228] 11 , the first surface-side coil 111A includes a first coil portion 111A1 that is spiral in plan view, a first outer coil end portion 111A2, and a first inner coil end portion 111A3. The first outer coil end portion 111A2 constitutes the end portion of the outermost periphery of the first coil portion 111A1 in the winding direction, and the first inner coil end portion 111A3 constitutes the end portion of the innermost periphery of the first coil portion 111A1 in the winding direction.

[0229] The second surface-side coil 112A includes a second coil portion 112A1 that is spiral in plan view, a second outer coil end portion 112A2, and a second inner coil end portion 112A3. The second outer coil end portion 112A2 constitutes the end portion of the second coil portion 112A1 in the winding direction at the outermost periphery, and the second inner coil end portion 112A3 constitutes the end portion of the second coil portion 112A1 in the winding direction at the innermost periphery.

[0230] The first electrode pad 67A is disposed in an inner space including the winding center of the first coil portion 111A1 in a plan view. The first electrode pad 67A can be said to be located more inward than the first coil portion 111A1. The first electrode pad 67A is connected to the first inner coil end portion 111A3. Therefore, the first electrode pad 67A can be said to be electrically connected to the first end portion of the first surface side coil 111A.

[0231] The first electrode pad 67B is disposed between the first surface side coil 111A and the second surface side coil 112A in the Y direction in a plan view. The first electrode pad 67B is connected to the first outer coil end 111A2 of the first surface side coil 111A. The first electrode pad 67B is also connected to the second outer coil end 112A2 of the second surface side coil 112A. Therefore, it can be said that the first electrode pad 67B is electrically connected to the second end of the first surface side coil 111A and the second end of the second surface side coil 112A.

[0232] The first electrode pad 67C is disposed in an inner space including the winding center of the second coil portion 112A1 in a plan view. The first electrode pad 67C can be said to be located more inward than the second coil portion 112A1. The first electrode pad 67C is connected to the second inner coil end portion 112A3. Therefore, the first electrode pad 67C can be said to be electrically connected to the first end portion of the second surface side coil 112A.

[0233] The third surface-side coil 113A includes a third coil portion 113A1 that is spiral in plan view, a third outer coil end portion 113A2, and a third inner coil end portion 113A3. The third outer coil end portion 113A2 constitutes the end portion of the third coil portion 113A1 in the winding direction at the outermost periphery, and the third inner coil end portion 113A3 constitutes the end portion of the third coil portion 113A1 in the winding direction at the innermost periphery.

[0234] The fourth surface-side coil 114A includes a fourth coil portion 114A1 that is spiral in plan view, a fourth outer coil end portion 114A2, and a fourth inner coil end portion 114A3. The fourth outer coil end portion 114A2 constitutes the end portion of the fourth coil portion 114A1 in the winding direction at the outermost periphery, and the fourth inner coil end portion 114A3 constitutes the end portion of the fourth coil portion 114A1 in the winding direction at the innermost periphery.

[0235] The first electrode pad 67D is disposed in an inner space including the winding center of the third coil portion 113A1 in a plan view. The first electrode pad 67D can be said to be located more inward than the third coil portion 113A1. The first electrode pad 67D is connected to the third inner coil end portion 113A3. Therefore, the first electrode pad 67D can be said to be electrically connected to the first end portion of the third surface side coil 113A.

[0236] The first electrode pad 67E is disposed between the third surface side coil 113A and the fourth surface side coil 114A in the Y direction in a plan view. The first electrode pad 67E is connected to the third outer coil end 113A2 of the third surface side coil 113A. The first electrode pad 67E is also connected to the fourth outer coil end 114A2 of the fourth surface side coil 114A. Therefore, it can be said that the first electrode pad 67E is electrically connected to the second end of the third surface side coil 113A and the second end of the fourth surface side coil 114A.

[0237] The first electrode pad 67F is disposed in an inner space including the winding center of the fourth coil portion 114A1 in a plan view. The first electrode pad 67F can be said to be located inward of the fourth coil portion 114A1. The first electrode pad 67F is connected to the fourth inner coil end portion 114A3. Therefore, the first electrode pad 67F can be said to be electrically connected to the first end portion of the fourth surface side coil 114A.

[0238] 10 and 11 , the first to fourth surface side coils 111A to 114A have the same number of windings. In a plan view, the winding direction of the first surface side coil 111A and the winding direction of the second surface side coil 112A are opposite to each other, and the winding direction of the third surface side coil 113A and the winding direction of the fourth surface side coil 114A are opposite to each other. The winding direction of the first surface side coil 111A and the winding direction of the third surface side coil 113A are the same, and the winding direction of the second surface side coil 112A and the winding direction of the fourth surface side coil 114A are the same.

[0239] As shown in FIG. 13 , the first back-side coil 111B is disposed opposite the first front-side coil 111A (see FIG. 11 ) in the Z direction. The first back-side coil 111B includes a first coil portion 111B1 having a spiral shape in a plan view, a first outer coil end portion 111B2, and a first inner coil end portion 111B3. The first outer coil end portion 111B2 constitutes the end portion of the outermost periphery of the first coil portion 111B1 in the winding direction, and the first inner coil end portion 111B3 constitutes the end portion of the innermost periphery of the first coil portion 111B1 in the winding direction. The first outer coil end portion 111B2 is connected to a first connection wiring 118A extending in the X direction. The first connection wiring 118A is electrically connected to the first transmitter 501 (see FIG. 9 ) in the circuit area 120 (see FIG. 10 ). The first inner coil end portion 111B3 is connected to a first wiring (not shown). The first wiring is electrically connected to the first transmitting unit 501 in the circuit area 120 .

[0240] The second back-side coil 112B is positioned opposite the second front-side coil 112A (see FIG. 11 ) in the Z direction. The second back-side coil 112B includes a second coil portion 112B1 that is spiral-shaped in a plan view, a second outer coil end portion 112B2, and a second inner coil end portion 112B3. The second outer coil end portion 112B2 constitutes the end portion of the outermost periphery of the second coil portion 112B1 in the winding direction, and the second inner coil end portion 112B3 constitutes the end portion of the innermost periphery of the second coil portion 112B1 in the winding direction. The second outer coil end portion 112B2 is connected to a second connection wiring 118B that extends in the X direction. The second connection wiring 118B is positioned adjacent to the first connection wiring 118A in the Y direction. The second connection wiring 118B is positioned closer to the second back-side coil 112B than the first connection wiring 118A. The second connection wiring 118B is electrically connected to the first transmitter 501 of the circuit area 120. The second inner coil end 112B3 is connected to a second wiring (not shown). The second wiring is electrically connected to the first transmitter 501 of the circuit area 120.

[0241] The third back-surface-side coil 113B is disposed opposite the third front-surface-side coil 113A (see FIG. 11 ) in the Z direction. The third back-surface-side coil 113B includes a third coil portion 113B1 having a spiral shape in a plan view, a third outer coil end portion 113B2, and a third inner coil end portion 113B3. The third outer coil end portion 113B2 constitutes the end portion of the third coil portion 113B1 in the winding direction at the outermost periphery, and the third inner coil end portion 113B3 constitutes the end portion of the third coil portion 113B1 in the winding direction at the innermost periphery. The third outer coil end portion 113B2 is connected to a third connection wiring 118C extending in the X direction. The third connection wiring 118C is electrically connected to the second transmitter 502 (see FIG. 9 ) of the circuit area 120. The third inner coil end portion 113B3 is connected to a third wiring (not shown). The third wiring is electrically connected to the second transmitting unit 502 in the circuit area 120 .

[0242] The fourth back-side coil 114B is positioned opposite the fourth front-side coil 114A (see FIG. 11 ) in the Z direction. The fourth back-side coil 114B includes a fourth coil portion 114B1 that is spiral-shaped in a plan view, a fourth outer coil end portion 114B2, and a fourth inner coil end portion 114B3. The fourth outer coil end portion 114B2 constitutes the end portion of the fourth coil portion 114B1 in the winding direction at the outermost periphery, and the fourth inner coil end portion 114B3 constitutes the end portion of the fourth coil portion 114B1 in the winding direction at the innermost periphery. The fourth outer coil end portion 114B2 is connected to a fourth connection wiring 118D extending in the X direction. The fourth connection wiring 118D is positioned adjacent to the third connection wiring 118C in the Y direction. The fourth connection wiring 118D is positioned closer to the fourth back-side coil 114B than the third connection wiring 118C. The fourth connection wiring 118D is electrically connected to the second transmitter 502 of the circuit area 120. The fourth inner coil end 114B3 is connected to a fourth wiring (not shown). The fourth wiring is electrically connected to the second transmitter 502 of the circuit area 120.

[0243] Here, the first to fourth back-side coils 111B to 114B have the same number of windings. In a plan view, the winding direction of the first back-side coil 111B and the winding direction of the second back-side coil 112B are opposite to each other, and the winding direction of the third back-side coil 113B and the winding direction of the fourth back-side coil 114B are opposite to each other. The winding direction of the first back-side coil 111B and the winding direction of the third back-side coil 113B are the same, and the winding direction of the second back-side coil 112B and the winding direction of the fourth back-side coil 114B are the same. In one example, the number of windings of the first to fourth back-side coils 111B to 114B is equal to the number of windings of the first to fourth front-side coils 111A to 114A.

[0244] 11, a front-side guard ring 115 is formed in the insulating transformer region 110. The front-side guard ring 115 surrounds the first to fourth front-side coils 111A to 114A and the first electrode pads 67A to 67F in a plan view. The front-side guard ring 115 has a track shape in a plan view.

[0245] 13, a back-side guard ring 116 is formed in the insulating transformer region 110 to surround the first to fourth back-side coils 111B to 114B in a plan view. The back-side guard ring 116 has a track shape in a plan view. The back-side guard ring 116 has the same shape and size as the front-side guard ring 115. In a plan view, the back-side guard ring 116 is formed at a position overlapping the front-side guard ring 115.

[0246] A plurality of vias 117 are formed in the insulating transformer region 110 to connect the front-side guard ring 115 and the back-side guard ring 116. The vias 117 are arranged at positions that overlap both the front-side guard ring 115 and the back-side guard ring 116 in a plan view.

[0247] As shown in FIG. 10 , the circuit region 120 is provided with a plurality of wiring layers 121. The plurality of wiring layers 121 includes a wiring layer that electrically connects the plurality of first functional units and a wiring layer that electrically connects the plurality of functional units to the first transformer 111 and the second transformer 112 of the insulating transformer region 110. The plurality of first functional units are formed in positions in the circuit region 120 closer to the chip back surface 62 (see FIG. 14 ) in the Z direction than the plurality of wiring layers 121. In one example, although not shown in FIG. 12 , the plurality of first functional units are formed in the same positions in the Z direction as the first to fourth back surface side coils 111B to 114B. Note that the positions in the Z direction at which the plurality of first functional units are formed can be changed as desired.

[0248] 10 and 12 , the peripheral guard ring 100 includes a front-side peripheral guard ring 101 and a back-side peripheral guard ring 102. As shown in Fig. 10 , the front-side peripheral guard ring 101 is connected to a front-side guard ring 115. More specifically, the front-side peripheral guard ring 101 is connected to both ends of the front-side guard ring 115 in the Y direction. The front-side peripheral guard ring 101 includes a first portion extending in the X direction at a position adjacent to the third chip side surface 65 in the Y direction in a plan view, a second portion continuing from the first portion and extending in the Y direction at a position adjacent to the first chip side surface 63 in the X direction, and a third portion continuing from the second portion and extending in the X direction at a position adjacent to the fourth chip side surface 66 in the Y direction. The front-side outer periphery guard ring 101 further includes a first connection portion that extends from the first portion toward the front-side guard ring 115 in the Y direction and is connected to the front-side guard ring 115, and a second connection portion that extends from the third portion toward the front-side guard ring 115 in the Y direction and is connected to the front-side guard ring 115. In this way, the front-side outer periphery guard ring 101 is electrically connected to the front-side guard ring 115.

[0249] 12 , the back-side outer periphery guard ring 102 is connected to the back-side guard ring 116. More specifically, the back-side outer periphery guard ring 102 is connected to both ends of the back-side guard ring 116 in the Y direction. The back-side outer periphery guard ring 102 includes a first portion extending in the X direction at a position adjacent to the third chip side surface 65 in the Y direction in a plan view, a second portion continuing from the first portion and extending in the Y direction at a position adjacent to the first chip side surface 63 in the X direction, and a third portion continuing from the second portion and extending in the X direction at a position adjacent to the fourth chip side surface 66 in the Y direction. The back-side outer periphery guard ring 102 further includes a first connection portion extending in the Y direction from the first portion toward the back-side guard ring 116 and connected to the back-side guard ring 116, and a second connection portion extending in the Y direction from the third portion toward the back-side guard ring 116 and connected to the back-side guard ring 116. In this way, the rear surface-side outer peripheral guard ring 102 is electrically connected to the rear surface-side guard ring 116. The shape and size of the rear surface-side outer peripheral guard ring 102 in a plan view are the same as those of the front surface-side outer peripheral guard ring 101. The rear surface-side outer peripheral guard ring 102 is disposed at a position overlapping the front surface-side outer peripheral guard ring 101 in a plan view.

[0250] Although not shown, the first chip 60 has a plurality of peripheral vias that connect the front-side peripheral guard ring 101 and the back-side peripheral guard ring 102. The front-side peripheral guard ring 101 and the back-side peripheral guard ring 102 are electrically connected by the plurality of peripheral vias. Each peripheral via extends in the Z direction.

[0251] (Cross-sectional structure of first chip) A cross-sectional structure of the insulating transformer region 110 will be described as an example of the internal configuration of the first chip 60. Note that in the insulating transformer region 110, the first transformer 111 and the second transformer 112 have the same configuration, and therefore, the following describes in detail the configuration of the first transformer 111, and omits a detailed description of the second transformer 112.

[0252] Fig. 14 shows a cross-sectional structure of the first transformer 111 cut along line F14-F14 in Fig. 10. Fig. 15 is an enlarged view of a portion of the first transformer 111 in Fig. 14. Fig. 16 is an enlarged view of a portion F16 of the first front-surface side coil 111A of the first transformer 111 in Fig. 15, and Fig. 17 is an enlarged view of a portion F17 of the first back-surface side coil 111B of the first transformer 111 in Fig. 15. Note that hatching lines have been omitted in Fig. 14 to facilitate understanding of the drawing.

[0253] As shown in FIG. 14 , the first chip 60 includes the substrate 130 described above and an element insulating layer 150 formed on the substrate 130. The substrate 130 is formed, for example, of a semiconductor substrate. In the first embodiment, the substrate 130 is a semiconductor substrate formed of a material containing silicon (Si). Note that a wide bandgap semiconductor or a compound semiconductor may be used as the semiconductor substrate for the substrate 130. Furthermore, instead of a semiconductor substrate, the substrate 130 may be an insulating substrate formed of a material containing glass or a material containing ceramics such as alumina.

[0254] Wide bandgap semiconductors are semiconductor substrates with a bandgap of 2.0 eV or more. Wide bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (GaO). ２ O ３ The compound semiconductor may be any one of III-V compound semiconductors. The compound semiconductor may include at least one of aluminum nitride (AlN), indium nitride (InN), gallium nitride, and gallium arsenide (GaAs).

[0255] The substrate 130 is formed in a flat plate shape and has a substrate front surface 131 and a substrate back surface 132 opposite to the substrate front surface 131. The substrate back surface 132 constitutes the chip back surface 62 of the first chip 60.

[0256] The element insulating layer 150 is in contact with the substrate surface 131. In one example, the element insulating layer 150 is formed over the entire surface of the substrate surface 131. In one example, the element insulating layer 150 is made of silicon oxide (SiO ２ ) The element insulating layer 150 may be formed by stacking a plurality of such oxide films. The material forming the element insulating layer 150 can be changed as desired.

[0257] The element insulating layer 150 has a layer front surface 151 and a layer back surface 152 opposite to the layer front surface 151. The layer front surface 151 faces the same side as the substrate front surface 131, and the layer back surface 152 faces the same side as the substrate back surface 132. The layer back surface 152 is in contact with the substrate front surface 131.

[0258] A plurality of first electrode pads 67A to 67F (not shown in FIG. 14, see FIG. 11), a passivation film 161, and a protective film 162 are formed on the element insulating layer 150. The plurality of first electrode pads 67A to 67F are in contact with a layer surface 151 of the element insulating layer 150. In one example, the plurality of first electrode pads 67A to 67F are formed at the same positions as each other in the Z direction.

[0259] As shown in FIG. 15 , the passivation film 161 is a film that protects the element insulating layer 150 and is formed to cover the layer surface 151. The passivation film 161 is formed to cover the multiple first electrode pads 67A to 67F. Meanwhile, the passivation film 161 has openings (not shown) that expose portions of the multiple first electrode pads 67A to 67F in the Z direction. The protective film 162 is formed on the passivation film 161. In one example, the passivation film 161 is formed of a single layer of a silicon nitride (SiN) film or a silicon oxynitride (SiON) film. In another example, the passivation film 161 is formed of a stacked structure of a silicon oxide film and a silicon nitride film. In this case, the silicon nitride film may be formed on a silicon oxide film. In another example, the passivation film 161 is formed of a stacked structure of a silicon oxide film and a silicon oxynitride film. In this case, the silicon oxynitride film may be formed on a silicon oxide film.

[0260] The thickness of the passivation film 161 (the size of the passivation film 161 in the Z direction) is thinner than the thickness of the protective film 162 (the size of the protective film 162 in the Z direction). In one example, the thickness of the passivation film 161 is ⅓ or less of the thickness of the protective film 162. In another example, the thickness of the passivation film 161 is ¼ or less of the thickness of the protective film 162. In another example, the thickness of the passivation film 161 is ⅕ or more of the thickness of the protective film 162. In the example shown in FIG. 15 , the thickness of the passivation film 161 is about 1.3 μm.

[0261] The protective film 162 is formed on the passivation film 161. The protective film 162 is a film that protects the first chip 60, and is formed of a material containing, for example, polyimide (PI). The protective film 162 can also be said to be a layer that relieves stress between the sealing resin 90 and the element insulating layer 150 and between the sealing resin 90 and the substrate 130. The protective film 162 forms the chip surface 61 of the first chip 60.

[0262] The first surface side coil 111A and the first back side coil 111B of the first transformer 111 are arranged opposite to each other with a gap in the Z direction. An element insulating layer 150 is interposed between the first surface side coil 111A and the first back side coil 111B in the Z direction. The first surface side coil 111A and the first back side coil 111B are provided in the element insulating layer 150. The first back side coil 111B can also be said to be embedded in the element insulating layer 150. The first surface side coil 111A is arranged closer to the layer surface 151 of the element insulating layer 150 than the first back side coil 111B. In other words, the first back side coil 111B is arranged closer to the layer back surface 152 of the element insulating layer 150 (closer to the substrate 130) than the first surface side coil 111A. The first surface side coil 111A is exposed from the layer surface 151 of the element insulating layer 150 in the Z direction. The first front surface side coil 111A is covered with a passivation film 161. The first back surface side coil 111B is disposed at a distance in the Z direction from the layer back surface 152 of the element insulating layer 150. In other words, the first back surface side coil 111B is disposed at a distance in the Z direction from the substrate 130. The element insulating layer 150 is interposed between the first back surface side coil 111B and the substrate 130.

[0263] 16, the first surface side coil 111A is embedded in a recess 153 recessed from the layer front surface 151 toward the layer back surface 152 (see FIG. 15) of the element insulating layer 150. The recess 153 is formed in a spiral shape in a plan view. The first surface side coil 111A is formed by a single conductor 170 embedded in the recess 153. In other words, the first surface side coil 111A is configured by a single conductor 170 formed in a spiral shape in a plan view.

[0264] The conducting wire 170 has a coil front surface 171, a coil back surface 172 opposite the coil front surface 171, and a pair of coil side surfaces 173 connecting the coil front surface 171 and the coil back surface 172. The coil front surface 171 faces the same side as the layer front surface 151 of the element insulating layer 150, and the coil back surface 172 faces the same side as the layer back surface 152. The pair of coil side surfaces 173 are formed in a tapered shape whose size in the X direction decreases from the coil front surface 171 toward the coil back surface 172. The coil back surface 172 and the pair of coil side surfaces 173 are in contact with the recess 153. In other words, the coil back surface 172 and the pair of coil side surfaces 173 are in contact with the element insulating layer 150. The coil front surface 171 is covered with a passivation film 161.

[0265] The conductive wire 170 includes a barrier layer 174 and a metal layer 175 formed on the barrier layer 174. The barrier layer 174 is formed so as to contact the recess 153. The barrier layer 174 can be said to be a thin film interposed between the metal layer 175 and the element insulating layer 150. The metal layer 175 is formed so as to fill the recess 153.

[0266] The metal layer 175 is formed of a material containing, for example, copper. The barrier layer 174 has a function of suppressing the diffusion of copper, for example. The barrier layer 174 may contain at least one of titanium, titanium nitride, tantalum (Ta), and tantalum nitride (TaN). The metal layer 175 may also contain at least one of aluminum, gold (Au), silver, and tungsten (W).

[0267] The thickness of the conductor 170 of the first front-side coil 111A is thicker than the thickness of the passivation film 161 and thinner than the thickness of the protective film 162. The thickness of the conductor 170 is thicker than the thickness of the first back-side coil 111B (see FIG. 15 ). In one example, the thickness of the conductor 170 is between two and three times the thickness of the passivation film 161. In one example, the thickness of the conductor 170 is half or less the thickness of the protective film 162. In one example, the thickness of the conductor 170 is one-third or more the thickness of the protective film 162. Here, the thickness of the conductor 170 can be defined by the distance between the coil front surface 171 and the coil back surface 172 in the Z direction.

[0268] The width of coil surface 171 of conductor 170 (the length in the X direction in FIG. 16 ) is longer than the thickness of conductor 170. In one example, the width of coil surface 171 is more than twice the thickness of conductor 170. In another example, the width of coil surface 171 is less than three times the thickness of conductor 170. In the example of FIG. 16 , the width of coil surface 171 is approximately 6.8 μm.

[0269] In the first surface side coil 111A, an element insulating layer 150 is interposed between adjacent conductors 170 in the X direction. That is, in the first surface side coil 111A, the conductors 170 are spaced apart from each other in the X direction. The distance between adjacent conductors 170 in the X direction gradually increases from the coil front surface 171 toward the coil back surface 172.

[0270] In FIG. 16 , the distance between adjacent conductors 170 in the X direction, and the distance between the coil surfaces 171 of adjacent conductors 170 in the X direction, is defined as the inter-conductor distance. This inter-conductor distance refers to the minimum distance between adjacent conductors 170 in the X direction. The inter-conductor distance is smaller than the length of the coil surface 171 in the X direction. In one example, the inter-conductor distance is ½ or less of the width of the coil surface 171. In one example, the inter-conductor distance is ⅓ or less of the width of the coil surface 171. In one example, the inter-conductor distance is ¼ or less of the width of the coil surface 171. In one example, the inter-conductor distance is ⅕ or less of the width of the coil surface 171. In one example, the inter-conductor distance is ⅙ or less of the width of the coil surface 171. In one example, the inter-conductor distance is ⅙ or less of the width of the coil surface 171. In one example, the inter-conductor distance is ⅙ or more of the width of the coil surface 171. The inter-conductor distance is smaller than the thickness of the conductors 170. In one example, the distance between the conductors is equal to or less than half the thickness of the conductors 170. In another example, the distance between the conductors is equal to or more than one-third the thickness of the conductors 170. In the example of Fig. 16, the distance between the conductors is about 1 µm.

[0271] 15 and 17 , the first back-side coil 111B is composed of two coil layers 111BA and 111BB. The coil layer 111BA constitutes a conductor closer to the layer front surface 151 of the element insulating layer 150, and the coil layer 111BB constitutes a conductor closer to the layer back surface 152. The coil layers 111BA and 111BB are spaced apart in the Z direction. The element insulating layer 150 is interposed between the coil layers 111BA and 111BB in the Z direction. Each of the coil layers 111BA and 111BB includes a conductor 180. That is, the coil layer 111BA is constituted by a conductor 180 formed in a spiral shape in a plan view, and the coil layer 111BB is constituted by another conductor 180 formed in a spiral shape in a plan view. Here, the number of turns of the first back-side coil 111B can be defined as the sum of the number of turns of the coil layer 111BA and the number of turns of the coil layer 111BB.

[0272] As shown in Fig. 15, the coil layer 111BA and the coil layer 111BB are arranged to be offset from each other in the X direction. In plan view, the coil layer 111BA and the coil layer 111BB are arranged to partially overlap each other. In other words, in plan view, the coil layer 111BA and the coil layer 111BB are arranged to have portions that do not overlap each other. In the example shown in Fig. 17, the coil layer 111BA is arranged to be offset from the coil layer 111BB in the X direction by half the width dimension of the conductor 180 (the length in the X direction in Fig. 17).

[0273] Each of the coil layers 111BA and 111BB is disposed offset in the X direction with respect to the first surface side coil 111A. In a plan view, the coil layers 111BA and 111BB are disposed so as to partially overlap the first surface side coil 111A. In the example shown in FIG. 17 , the coil layer 111BA is offset toward the first chip side surface 63 (see FIG. 10 ) with respect to the first surface side coil 111A (see FIG. 15 ). The coil layer 111BB is offset toward the second chip side surface 64 (see FIG. 10 ) with respect to the first surface side coil 111A.

[0274] The number of turns of the coil layer 111BA and the number of turns of the coil layer 111BB are the same. The number of turns of the coil layers 111BA and 111BB is less than the number of turns of the first front-side coil 111A. In one example, the number of turns of the coil layer 111BA is half the number of turns of the first front-side coil 111A, and the number of turns of the coil layer 111BB is half the number of turns of the first front-side coil 111A. In other words, the sum of the number of turns of the coil layer 111BA and the number of turns of the coil layer 111BB is the same as the number of turns of the first front-side coil 111A. Therefore, the number of turns of the first back-side coil 111B is the same as the number of turns of the first front-side coil 111A.

[0275] The coil layers 111BA and 111BB are formed by identically shaped conductors 180 that are spirally wound in a plan view. The conductor 180 has a coil front surface 181, a coil back surface 182 opposite the coil front surface 181, and a pair of coil side surfaces 183 connecting the coil front surface 181 and the coil back surface 182. The coil front surface 181 faces the same side as the layer front surface 151 of the element insulating layer 150, and the coil back surface 172 faces the same side as the layer back surface 152. The pair of coil side surfaces 183 extend along the Z direction. The coil front surface 181, the coil back surface 182, and the pair of coil side surfaces 183 each contact the element insulating layer 150.

[0276] As shown in FIG. 17, the conductive wire 180 includes a back-side barrier layer 184, a metal layer 185 formed on the back-side barrier layer 184, and a front-side barrier layer 186 formed on the metal layer 185.

[0277] The back-surface-side barrier layer 184 constitutes the coil back surface 182 of the conductor 180. The back-surface-side barrier layer 184 can be said to be a thin film interposed between the back surface of the metal layer 185 and the element insulating layer 150 in the Z direction.

[0278] The front-side barrier layer 186 constitutes the coil surface 181 of the conductor 180. The front-side barrier layer 186 can be said to be a thin film interposed between the surface of the metal layer 185 and the element insulating layer 150 in the Z direction.

[0279] The metal layer 185 has a thickness greater than that of the back-side barrier layer 184 and the front-side barrier layer 186. A pair of side surfaces of the metal layer 185 are not covered by either the back-side barrier layer 184 or the front-side barrier layer 186 and are in contact with the element insulating layer 150. The pair of side surfaces of the metal layer 185 constitute part of the pair of coil side surfaces 183 in the Z direction.

[0280] The metal layer 185 is formed of a material containing, for example, aluminum. Both the back-side barrier layer 184 and the front-side barrier layer 186 may contain titanium or titanium nitride. In this way, the material constituting the first back-side coil 111B is different from the material constituting the first front-side coil 111A.

[0281] The materials constituting the first front-side coil 111A and the first back-side coil 111B can be changed as desired. For example, the materials constituting the first front-side coil 111A and the first back-side coil 111B may be the same.

[0282] As shown in FIG. 15 , the thickness of the conductor 180 of the first back-side coil 111B is thinner than the thickness of the protective film 162. The thickness of the conductor 180 is thinner than the thickness of the conductor 170. In one example, the thickness of the conductor 180 is half or less of the thickness of the conductor 170. In one example, the thickness of the conductor 180 is about one-third of the thickness of the conductor 170. The thickness of the conductor 180 is thinner than the thickness of the passivation film 161. The thickness of the conductor 180 is half or more of the thickness of the passivation film 161. Here, the thickness of the conductor 180 can be defined by the distance in the Z direction between the coil front surface 181 and the coil back surface 182 (both see FIG. 17 ).

[0283] The width of the conductor 180 (the length in the X direction in FIG. 15 ) is longer than the thickness of the conductor 180. In one example, the width of the conductor 180 is at least twice the thickness of the conductor 180. In one example, the width of the conductor 180 is at least five times the thickness of the conductor 180. In one example, the width of the conductor 180 is at least ten times the thickness of the conductor 180. In one example, the width of the conductor 180 is at least twelve times the thickness of the conductor 180. In one example, the width of the conductor 180 is at least fifteen times the thickness of the conductor 180. In one example, the width of the conductor 180 is at least sixteen times the thickness of the conductor 180. In one example, the width of the conductor 180 is approximately seventeen times the thickness of the conductor 180.

[0284] In one example, the width dimension of the conductor 180 is longer than the width dimension of the conductor 170. The width dimension of the conductor 180 is at least twice the width dimension of the conductor 170. The width dimension of the conductor 180 is no more than three times the width dimension of the conductor 170. In the example of FIG. 15 , the width dimension of the conductor 180 is approximately 15.8 μm. The width dimension of the conductor 170 can be defined as the size in a direction perpendicular to the direction in which the conductor 170 extends in a planar view. The width dimension of the conductor 180 can be defined as the size in a direction perpendicular to the direction in which the conductor 180 extends in a planar view.

[0285] In the coil layers 111BA and 111BB, an element insulating layer 150 is interposed between adjacent conductors 180 in the X direction. That is, in the coil layers 111BA and 111BB, the conductors 180 are spaced apart in the X direction. The distance between adjacent conductors 180 in the X direction (hereinafter referred to as the "inter-conductor distance") is the same from the coil front surface 181 to the coil back surface 182. The inter-conductor distance is smaller than the width of the conductors 180. For example, the inter-conductor distance is ½ or less of the width of the conductors 180. For example, the inter-conductor distance is ⅕ or less of the width of the conductors 180. For example, the inter-conductor distance is 1 / 10 or less of the width of the conductors 180. For example, the inter-conductor distance is 1 / 15 or less of the width of the conductors 180. For example, the inter-conductor distance is 1 / 16 or less of the width of the conductors 180. In one example, the inter-wire distance is 1 / 17 or less of the width dimension of the conductor 180. In one example, the inter-wire distance is 1 / 18 or less of the width dimension of the conductor 180. In one example, the inter-wire distance is 1 / 19 or less of the width dimension of the conductor 180. In one example, the inter-wire distance is 1 / 20 or more of the width dimension of the conductor 180. The inter-wire distance is smaller than the thickness of the conductor 180. On the other hand, the inter-wire distance is 1 / 2 or more of the thickness of the conductor 180. The inter-wire distance of the coil layers 111BA, 111BB is smaller than the inter-wire distance of the first surface-side coil 111A. In the example of FIG. 15 , the inter-wire distance is approximately 0.8 μm.

[0286] The distance in the Z direction between the first front surface side coil 111A and the first back surface side coil 111B is greater than the distance in the Z direction between the layer back surface 152 of the element insulating layer 150 and the first back surface side coil 111B. In one example, the distance in the Z direction between the first front surface side coil 111A and the first back surface side coil 111B is smaller than the width dimension of the conductive wire 180. The distance in the Z direction between the first front surface side coil 111A and the first back surface side coil 111B is, for example, approximately 12.8 μm. Here, the distance in the Z direction between the first front surface side coil 111A and the first back surface side coil 111B can be defined by the distance in the Z direction between the coil back surface 172 of the conductive wire 170 and the coil front surface 181 of the conductive wire 180 of the coil layer 111BA. The distance in the Z direction between the first front side coil 111A and the first back side coil 111B is set according to the desired dielectric strength and the electric field strength of each of the first front side coil 111A and the first back side coil 111B.

[0287] In the first embodiment, the conductor 170 of the first surface side coil 111A is formed so that the coil front surface 171 thereof is exposed from the element insulating layer 150 in the Z direction, but this is not limited to this. The conductor 170 of the first surface side coil 111A may be embedded in the element insulating layer 150. In other words, the coil front surface 171 of the conductor 170 may be in contact with the element insulating layer 150. In other words, the conductor 170 may be disposed closer to the layer rear surface 152 than the layer front surface 151 of the element insulating layer 150.

[0288] 18 and 19, an example of the wiring structure of the circuit region 120 will be described. The circuit region 120 includes a wiring layer 121 and a substrate-side wiring layer 122 arranged closer to the substrate 130 than the wiring layer 121.

[0289] In one example, the wiring layer 121 is formed at the same position in the Z direction as the first surface side coil 111A of the first transformer 111. That is, the surface of the wiring layer 121 is exposed from the layer surface 151 of the element insulating layer 150 and is covered with the passivation film 161. In the example shown in Fig. 18, the thickness of the wiring layer 121 is 2.8 µm.

[0290] The substrate-side wiring layer 122 is embedded in the element insulating layer 150. In one example, the substrate-side wiring layer 122 includes a first wiring layer 122A, a second wiring layer 122B, and a third wiring layer 122C. The first wiring layer 122A is arranged closer to the substrate 130 in the Z direction than the second wiring layer 122B and the third wiring layer 122C. The first wiring layer 122A is arranged spaced apart in the Z direction from the layer rear surface 152 of the element insulating layer 150. In other words, the first wiring layer 122A is arranged spaced apart from the substrate 130 in the Z direction. The element insulating layer 150 is interposed between the first wiring layer 122A and the substrate 130 in the Z direction.

[0291] The circuit region 120 includes a first via 123 that connects the wiring layer 121 and the substrate-side wiring layer 122. In the example shown in Fig. 18, the first via 123 connects the wiring layer 121 and the first wiring layer 122A. The first via 123 is formed of, for example, the same material as the wiring layer 121.

[0292] 19, the first via 123 includes a barrier layer 123A and a metal layer 123B, similar to, for example, the conductive wire 170. The materials constituting the barrier layer 123A and the metal layer 123B are the same as, for example, the materials constituting the barrier layer 174 and the metal layer 175 of the conductive wire 170 (both of which are shown in FIG. 16).

[0293] 18, the circuit region 120 includes a second via 124 connecting the first wiring layer 122A and the substrate 130, a third via 125 connecting the first wiring layer 122A and the second wiring layer 122B, and a fourth via 126 connecting the second wiring layer 122B and the third wiring layer 122C. As a result, in the example shown in Fig. 18, the substrate-side wiring layer 122 is electrically connected to the substrate 130. The first to fourth vias 123 to 126 are formed of a material containing, for example, tungsten.

[0294] As shown in FIG. 19 , the first wiring layer 122A, the second wiring layer 122B, and the third wiring layer 122C have different thicknesses. The thickness of the first wiring layer 122A is thinner than both the thickness of the second wiring layer 122B and the thickness of the third wiring layer 122C. The thickness of the second wiring layer 122B is the same as the thickness of the third wiring layer 122C. In other words, the thicknesses of the first to third wiring layers 122A to 122C are thinner in the Z direction near the substrate 130. In other words, the thicknesses of the first to third wiring layers 122A to 122C are thicker as they move away from the substrate 130 in the Z direction. In one example, the thicknesses of the second wiring layer 122B and the third wiring layer 122C are less than twice the thickness of the first wiring layer 122A. 19, the thickness of the first wiring layer 122A is, for example, 0.52 μm, and the thickness of the second wiring layer 122B and the third wiring layer 122C is, for example, 0.93 μm. In addition, in one example, the second wiring layer 122B is formed at the same position in the Z direction as the coil layer 111BB of the first back-side coil 111B, and the third wiring layer 122C is formed at the same position in the Z direction as the coil layer 111BA.

[0295] [Effects] The signal transmission device 10 of the first embodiment provides the following effects. (1-1) The signal transmission device 10 includes inter-chip wires WA that electrically connect the first chip 60 and the second chip 70, and first terminal wires WB that individually connect the first chip 60 and the first terminals 12 to 17. The inter-chip wires WA are made of a material containing gold. The first terminal wires WB are made of a material containing copper or aluminum.

[0296] The inter-chip wires WA are relatively important from the viewpoint of the insulation reliability of the signal transmission device 10, and the height and shape of the wires must be inspected with high precision. In this regard, in the first embodiment, the inter-chip wires WA are formed from a material containing gold, and therefore, when the height of the inter-chip wires WA is inspected using, for example, X-ray inspection, the inter-chip wires WA are displayed more clearly than when the inter-chip wires WA are formed from a material containing copper or aluminum. Therefore, the height of the inter-chip wires WA can be inspected accurately. Furthermore, the shape of the inter-chip wires WA can also be inspected accurately.

[0297] On the other hand, the first terminal wires WB are less important than the inter-chip wires WA in terms of the insulation reliability of the signal transmission device 10. In this regard, in the first embodiment, the first terminal wires WB are formed from a material containing copper or aluminum, which allows for cost reduction compared to when the first terminal wires WB are formed from a material containing gold. In this way, it is possible to achieve both improved quality and cost reduction for the signal transmission device 10.

[0298] (1-2) The first terminal wire WB is configured such that the surface of the copper wire is coated with palladium. With this configuration, the palladium coated on the surface of the copper wire can increase the bonding area of ​​the bonding portion between the first terminal wire WB, which serves as the second bond portion of the first terminal wire WB, and the first terminals 12 to 17. This increases the bonding strength between the first terminal wire WB and the first terminals 12 to 17, thereby suppressing the occurrence of cracks at the bonding portions between the first terminal wire WB and the first terminals 12 to 17.

[0299] (1-3) The signal transmission device 10 further includes a plurality of second terminal wires WD that individually connect the second chip 70 to the second terminals 42, 43. The signal transmission device 10 further includes a plurality of third terminal wires WF that individually connect the third chip 80 to the third terminals 45, 46. Each of the second terminal wires WD and the third terminal wires WF is formed from a material containing copper or aluminum.

[0300] According to this configuration, the second terminal wire WD and the third terminal wire WF, which are less important than the inter-chip wire WA from the standpoint of insulation reliability of the signal transmission device 10, are each formed from a material containing copper or aluminum, thereby enabling cost reduction compared to when the second terminal wire WD and the third terminal wire WF are each formed from a material containing gold.

[0301] (1-4) The second terminal wire WD is a copper wire coated with palladium. The third terminal wire WF is a copper wire coated with palladium. This configuration provides the same effect as that of (1-2) above.

[0302] (1-5) The signal transmission device 10 further includes a first die pad wire WC that connects the first chip 60 and the first die pad 30. The first die pad wire WC is made of a material containing copper or aluminum. This configuration provides the same effect as the effect described in (1-3) above.

[0303] (1-6) The first die pad wire WC is a copper wire whose surface is coated with palladium. This configuration provides the same effect as that of (1-2) above.

[0304] (1-7) The signal transmission device 10 further includes a second die pad wire WE that connects the second chip 70 and the second die pad 50A. The second die pad wire WE is made of a material containing copper or aluminum. This configuration provides the same effect as the effect described in (1-3) above.

[0305] (1-8) The second die pad wire WE is a copper wire whose surface is coated with palladium. This configuration provides the same effect as that of (1-2) above.

[0306] (1-9) The signal transmission device 10 further includes a third die pad wire WG that connects the third chip 80 and the third die pad 50B. The third die pad wire WG is made of a material containing copper or aluminum. This configuration provides the same effect as the effect described in (1-3) above.

[0307] (1-10) The third die pad wire WG is a copper wire whose surface is coated with palladium. This configuration provides the same effect as that of (1-2) above.

[0308] (1-11) Each of the first electrode pads 67, second electrode pads 68, and third electrode pads 69 of the first chip 60 has a thickness of 2 μm or more. With this configuration, even if an inter-chip wire WA is bonded to each of the first electrode pads 67, it is possible to prevent cracks from occurring in the element insulating layer 150 directly below each of the first electrode pads 67. Even if a first terminal wire WB is bonded to each of the second electrode pads 68, it is possible to similarly prevent cracks from occurring in the element insulating layer 150. Even if a first die pad wire WC is bonded to each of the third electrode pads 69, it is possible to similarly prevent cracks from occurring in the element insulating layer 150.

[0309] (1-12) The sealing resin 90 contains sulfur as an additive. The concentration of sulfur added is 300 μg / g or less. This configuration can reduce sulfide corrosion of copper wires whose surfaces are coated with palladium, such as the first terminal wire WB, the second terminal wire WD, the third terminal wire WF, the first die pad wire WC, the second die pad wire WE, and the third die pad wire WG.

[0310] (1-13) A plating layer 25 is formed on the internal terminal surface 21 of the first internal terminal portion 12B of the first terminal 12. The plating layer 25 is not formed on the end portion of the internal terminal surface 21 of the first internal terminal portion 12B on the tip surface 24 side, and the end portion is in contact with the sealing resin 90.

[0311] This configuration can prevent peeling of the plating layer 25 at the end portion of the inner terminal surface 21 of the first inner terminal portion 12B near the tip surface 24 from occurring between the sealing resin 90. Note that the first inner terminal portions 12B to 17B of the first terminals 12 to 17 have a similar configuration, and therefore the same effect can be obtained.

[0312] (1-14) A plating layer 25 is formed on the internal terminal surface 21 of the second internal terminal portions 42B, 43B of the second terminals 42, 43. The plating layer 25 is not formed on the end portion of the internal terminal surface 21 of the second internal terminal portions 42B, 43B on the tip surface 24 side, and the end portion is in contact with the sealing resin 90. This configuration can suppress peeling between the plating layer 25 and the sealing resin 90 on the end portion of the internal terminal surface 21 of the second internal terminal portions 42B, 43B that is closer to the tip surface 24.

[0313] (1-15) A plating layer 25 is formed on the internal terminal surface 21 of the third internal terminal portions 45B, 46B of the third terminals 45, 46. The plating layer 25 is not formed on the end portion of the internal terminal surface 21 of the third internal terminal portions 45B, 46B on the tip surface 24 side, and the end portion is in contact with the sealing resin 90. This configuration can suppress peeling between the plating layer 25 and the sealing resin 90 at the end portion of the internal terminal surface 21 of the third internal terminal portions 45B, 46B that is closer to the tip surface 24.

[0314] (1-16) The outer surface of the sealing resin 90 is formed so that the surface roughness Rz is 8 μm or more. This configuration increases the creepage distance through the sealing resin 90 between the first terminals 11 to 17 and the second terminals 41 to 43 and the third terminals 44 to 46. This improves the dielectric strength between the first terminals 11 to 17 and the second terminals 41 to 43 and the third terminals 44 to 46.

[0315] (1-17) The distance in the Y direction between the second terminal 43 and the third terminal 44, which is the shortest distance between the multiple second terminals 41 to 43 and the multiple third terminals 44 to 46, is greater than the distance in the Y direction between the second terminal 41 and the second terminal 42, which is the distance between adjacent second terminals in the second direction among the multiple second terminals 41 to 43.

[0316] This configuration allows for a large creepage distance between the second terminals 41 to 43 and the third terminals 44 to 46. Therefore, the dielectric strength between the second chip 70 and the third chip 80 can be improved.

[0317] Second Embodiment A signal transmission device 10 according to a second embodiment will be described with reference to Fig. 20. The signal transmission device 10 according to the second embodiment differs from the signal transmission device 10 according to the first embodiment in the configuration of some of the first terminals 11 to 17. In the following description, configurations that differ from the first embodiment will be described in detail, and components that are common to the first embodiment will be denoted by the same reference numerals and will not be described again.

[0318] As shown in FIG. 20 , the shape of the first terminal 16 among the first terminals 12 to 17 is different from that of the first embodiment. More specifically, the first internal terminal portion 16B of the first terminal 16 extends toward the second electrode pad 68, which serves as the first bond portion of the first terminal wire WB connected to the first internal terminal portion 16B. This causes the direction of extension of the first terminal wire WB connected to the first internal terminal portion 16B to be parallel to the direction of extension of the first internal terminal portion 16B in a planar view. Here, if the absolute value of the difference between the direction of extension of the first terminal wire WB connected to the first internal terminal portion 16B and the direction of extension of the first internal terminal portion 16B in a planar view is within 5°, it can be said that the direction of extension of the first terminal wire WB connected to the first internal terminal portion 16B is parallel to the direction of extension of the first internal terminal portion 16B in a planar view.

[0319] In a plan view, the first terminal wires WB connected to the first internal terminal portions 16B extend so as to pass through the tip surfaces of the first internal terminal portions 16B. The first terminal wires WB that have passed through the tip surfaces of the first internal terminal portions 16B in a plan view are then joined to the first internal terminal portions 16B. Here, the tip surfaces of the first internal terminal portions 16B are the side surfaces that face the first die pad 30, and are the side surfaces of the first internal terminal portions 16B that face the first chip 60. In the second embodiment, the tip surfaces of the first internal terminal portions 16B correspond to "side surfaces that intersect with the first terminal wires WB connected to the first internal terminal portions 16B in a plan view."

[0320] [Effects] The signal transmission device 10 of the second embodiment has the following effects: (2-1) In a plan view, the direction in which the first internal terminal portion 16B of the first terminal 16 extends is parallel to the direction in which the first terminal wire WB connected to the first internal terminal portion 16B extends. With this configuration, the first terminal wire WB can be stably joined to the first internal terminal portion 16B of the first terminal 16.

[0321] 21 and 22 , a signal transmission device 10 according to a third embodiment will be described. The signal transmission device 10 according to the third embodiment is different from the signal transmission device 10 according to the first embodiment in the configuration of the second bond portions of some of the first terminal wires WB among the plurality of first terminal wires WB. In the following description, configurations that differ from the first embodiment will be described in detail, and components that are common to the first embodiment will be denoted by the same reference numerals and will not be described again.

[0322] 21, in the third embodiment, a security bond WB1 is formed on the second bond portion of the first terminal wire WB connected to the first internal terminal portions 13B to 16B, while no security bond WB1 is formed on the second bond portion of the first terminal wire WB connected to the first internal terminal portions 12B, 17B.

[0323] In other words, the multiple first terminal wires WB include first specified wires in which a security bond WB1 is formed at the joint with the first internal terminal portion (first internal terminal portions 13B to 16B in the third embodiment), and second specified wires in which a security bond WB1 is not formed at the joint with the first internal terminal portion (first internal terminal portions 12B, 17B in the third embodiment).

[0324] 22 shows a perspective view of the second bond portion of the first terminal wire WB joined to the first internal terminal 15B and its surrounding area. Note that the second bond portions of the first terminal wire WB joined to the first internal terminals 13B, 14B, and 16B have the same structure as the second bond portion of the first terminal wire WB joined to the first internal terminal 15B. Therefore, the configuration of the second bond portion of the first terminal wire WB joined to the first internal terminal 15B will be described in detail, and a detailed description of the configuration of the second bond portion of the first terminal wire WB joined to the first internal terminals 13B, 14B, and 16B will be omitted.

[0325] 22, the second bond portion of the first terminal wire WB includes a bonding portion WBP bonded to the first internal terminal portion 15B. The bonding portion WBP is a portion that is crushed by being pressed against the first internal terminal portion 15B by a wire bonding device. The thickness of the bonding portion WBP is smaller than the diameter of the first terminal wire WB.

[0326] The security bond WB1 is formed, for example, by providing a stud bump SB on the bonding portion WBP. In one example, the stud bump SB is formed by ball bonding using a wire bonding device. The bonding portion WBP is sandwiched between the first internal terminal portion 15B and the stud bump SB.

[0327] [Effects] According to the signal transmission device 10 of the third embodiment, the following effects can be obtained: (3-1) A security bond WB1 is formed on the second bond portion of the first terminal wire WB connected to the first internal terminal portions 13B to 16B.

[0328] With this configuration, even if force is applied to the first terminal wire WB during the manufacturing process, the security bond WB1 can prevent the first terminal wire WB from peeling off from the first internal terminal portions 13B to 16B. Furthermore, since the security bond WB1 is not formed on the second bond portion of the first terminal wire WB connected to the first internal terminal portions 12B and 17B, the manufacturing process can be simplified. Therefore, the manufacturing cost of the signal transmission device 10 can be reduced.

[0329] <Fourth Embodiment> A signal transmission device 10 of a fourth embodiment will be described with reference to Fig. 23. The signal transmission device 10 of the fourth embodiment is different from the signal transmission device 10 of the first embodiment in the configurations of the first die pad 30, the second die pad 50A, and the third die pad 50B. In the following description, configurations that differ from the first embodiment will be described in detail, and components that are common to the first embodiment will be assigned the same reference numerals and their description will be omitted.

[0330] 23 , the first die pad 30 of the fourth embodiment differs from the first embodiment in the first tip curved surface 35A and the second tip curved surface 35B. Specifically, in a plan view, the arc lengths of the first tip curved surface 35A and the second tip curved surface 35B are longer than the arc length of the base curved surface 36. In other words, in a plan view, the radii of curvature of the first tip curved surface 35A and the second tip curved surface 35B are larger than the radius of curvature of the base curved surface 36. In one example, in a plan view, the arc lengths of the first tip curved surface 35A and the second tip curved surface 35B are at least twice the arc length of the base curved surface 36.

[0331] In the fourth embodiment, in a plan view, the arc length of the first distal curved surface 35A is equal to the arc length of the second distal curved surface 35B. Here, if the difference between the arc lengths of the first distal curved surface 35A and the second distal curved surface 35B is, for example, 10% or less of the arc length of the first distal curved surface 35A, it can be said that the arc length of the first distal curved surface 35A is equal to the arc length of the second distal curved surface 35B. It can also be said that the radius of curvature of the first distal curved surface 35A is equal to the radius of curvature of the second distal curved surface 35B in a plan view.

[0332] In the second die pad 50A of the fourth embodiment, the third tip curved surface 55AA is different from that of the first embodiment. Specifically, in a plan view, the arc length of the third tip curved surface 55AA is longer than the arc length of the base curved surface 56A. In other words, in a plan view, the radius of curvature of the third tip curved surface 55AA is larger than the radius of curvature of the base curved surface 56A. In addition, in a plan view, the arc length of the third tip curved surface 55AA is longer than the arc length of the fourth tip curved surface 55AB. In a plan view, it can also be said that the radius of curvature of the third tip curved surface 55AA is larger than the radius of curvature of the fourth tip curved surface 55AB.

[0333] In one example, the arc length of third distal curved surface 55AA is at least twice the arc length of base curved surface 56A in a plan view. In one example, the arc length of third distal curved surface 55AA is at least twice the arc length of fourth distal curved surface 55AB in a plan view.

[0334] In the third die pad 50B of the fourth embodiment, the sixth tip curved surface 55BB is different from that of the first embodiment. Specifically, in a plan view, the arc length of the sixth tip curved surface 55BB is longer than the arc length of the base curved surface 56BA. In other words, in a plan view, the radius of curvature of the sixth tip curved surface 55BB is larger than the radius of curvature of the base curved surface 56BA. In addition, in a plan view, the arc length of the sixth tip curved surface 55BB is longer than the arc length of the base curved surface 56BB. In addition, in a plan view, the radius of curvature of the sixth tip curved surface 55BB is larger than the radius of curvature of the base curved surface 56BB. In addition, in a plan view, the arc length of the sixth tip curved surface 55BB is longer than the arc length of the fifth tip curved surface 55BA. In other words, the radius of curvature of the sixth distal curved surface 55BB is larger than the radius of curvature of the fifth distal curved surface 55BA in plan view.

[0335] In one example, the arc length of the sixth distal curved surface 55BB is at least twice the arc length of the base curved surface 56BA in a plan view. In one example, the arc length of the sixth distal curved surface 55BB is at least twice the arc length of the base curved surface 56BA in a plan view. In one example, the arc length of the sixth distal curved surface 55BB is at least twice the arc length of the fifth distal curved surface 55BA.

[0336] In the fourth embodiment, in a plan view, the arc length of the sixth tip curved surface 55BB of the third die pad 50B is equal to the arc length of the third tip curved surface 55AA of the second die pad 50A. Here, if the difference between the arc length of the sixth tip curved surface 55BB and the arc length of the third tip curved surface 55AA is, for example, 10% or less of the arc length of the sixth tip curved surface 55BB, it can be said that the arc length of the sixth tip curved surface 55BB is equal to the arc length of the third tip curved surface 55AA. Furthermore, in a plan view, it can also be said that the radius of curvature of the sixth tip curved surface 55BB is equal to the radius of curvature of the third tip curved surface 55AA.

[0337] 23 , the first tip curved surface 35A of the first die pad 30 faces the third tip curved surface 55AA of the second die pad 50A in the X direction, and the second tip curved surface 35B of the first die pad 30 faces the sixth tip curved surface 55BB of the third die pad 50B in the X direction.

[0338] [Effects] The signal transmission device 10 of the fourth embodiment has the following effects: (4-1) The first die pad 30 has a first tip-side curved surface 35A formed between the first tip-side surface 31 and the first side surface 33, a second tip-side curved surface 35B formed between the first tip-side surface 31 and the second side surface 34, and a base-side curved surface 36 formed between the first base-side surface 32 and the first side surface 33. In a plan view, the arc lengths of both the first tip-side curved surface 35A and the second tip-side curved surface 35B are longer than the arc length of the base-side curved surface 36.

[0339] With this configuration, the first tip curved surface 35A can alleviate electric field concentration at the corner portion of the tip of the first die pad 30 that is closer to the second die pad 50A. Furthermore, the second tip curved surface 35B can alleviate electric field concentration at the corner portion of the tip of the first die pad 30 that is closer to the third die pad 50B. This makes it possible to avoid dielectric breakdown between the first die pad 30 and the second die pad 50A and the third die pad 50B, thereby improving the dielectric strength voltage of the signal transmission device 10.

[0340] (4-2) The second die pad 50A has a third tip curved surface 55AA formed between the second tip surface 51A and the third side surface 53A, and a base curved surface 56A formed between the second base surface 52A and the fourth side surface 54A. In a plan view, the arc length of the third tip curved surface 55AA is longer than the arc length of the base curved surface 56A.

[0341] According to this configuration, the third tip-side curved surface 55AA can alleviate electric field concentration at the corner portion at the tip of the second die pad 50A that is close to the first die pad 30. This makes it possible to avoid dielectric breakdown between the first die pad 30 and the second die pad 50A, thereby improving the dielectric strength voltage of the signal transmission device 10.

[0342] (4-3) The third die pad 50B has a sixth tip-side curved surface 55BB formed between the third tip-side surface 51B and the sixth side surface 54B, and a base-side curved surface 56BB formed between the third base-side surface 52B and the sixth side surface 54B. In a plan view, the arc length of the sixth tip-side curved surface 55BB is longer than the arc length of the base-side curved surface 56BB.

[0343] According to this configuration, the sixth tip-side curved surface 55BB can alleviate electric field concentration at the corner portion at the tip of the third die pad 50B that is close to the first die pad 30. This makes it possible to avoid dielectric breakdown between the first die pad 30 and the third die pad 50B, thereby improving the dielectric strength voltage of the signal transmission device 10.

[0344] 24 to 33, a signal transmission device 10 according to a fifth embodiment will be described. The signal transmission device 10 according to the fifth embodiment differs from the signal transmission device 10 according to the first embodiment mainly in the configuration of each of the first chip 60, the second chip 70, and the third chip 80. In the following description, configurations that differ from the first embodiment will be described in detail, and components that are common to the first embodiment will be assigned the same reference numerals and will not be described again.

[0345] Fig. 24 shows a schematic cross-sectional structure of the first die pad 30 and the first chip 60 taken along the XZ plane, and Fig. 25 shows a schematic cross-sectional structure of the first die pad 30 and the first chip 60 taken along the YZ plane. In the cross-sectional structures of Fig. 24 and Fig. 25, the wires WA to WC and the sealing resin 90 are omitted.

[0346] 24 and 25 , substrate 130 of first chip 60 has first to fourth substrate side surfaces 133 to 136 that connect substrate front surface 131 and substrate back surface 132. First substrate side surface 133 constitutes a part of first chip side surface 63 of first chip 60, second substrate side surface 134 constitutes a part of second chip side surface 64, third substrate side surface 135 constitutes a part of third chip side surface 65, and fourth substrate side surface 136 constitutes a part of fourth chip side surface 66.

[0347] The substrate 130 can be divided into a first portion 137 and a second portion 138 by a step portion 139. The first portion 137 is a portion of the substrate 130 that is closer to the first die pad 30. The second portion 138 is a portion that is provided on the first portion 137. As shown in FIGS. 24 and 25 , the step portion 139 is formed around the entire periphery of the substrate 130.

[0348] In one example, the thickness dimension (size in the Z direction) of first portion 137 is larger than the thickness dimension (size in the Z direction) of second portion 138. In one example, the thickness dimension of first portion 137 is more than twice the thickness dimension of second portion 138. In one example, the thickness dimension of first portion 137 is more than three times the thickness dimension of second portion 138. In one example, the thickness dimension of first portion 137 is less than four times the thickness dimension of second portion 138.

[0349] 24 and 25 , the first conductive bonding material SD1 is interposed between the first portion 137 and the first die pad 30 in the Z direction, and has a portion that protrudes from the first chip 60 in a direction perpendicular to the Z direction. This protruding portion forms a first fillet SDA between the first portion 137 and the first conductive bonding material SD1. The first fillet SDA is not formed in the second portion 138 due to a step portion 139. In the example shown in FIGS. 24 and 25 , the first fillet SDA is formed over the entire first portion 137 in the Z direction.

[0350] The height dimension (size in the Z direction) of the first fillet SDA can be changed as desired as long as it is lower than the step portion 139. In one example, the height dimension of the first fillet SDA may be approximately half the thickness dimension of the first portion 137.

[0351] Furthermore, the position of the step portion 139 in the first chip 60 in the Z direction can be changed as desired. That is, the relationship between the thickness of the first portion 137 and the thickness of the second portion 138 can be changed as desired. In one example, the thickness of the first portion 137 may be equal to the thickness of the second portion 138. In one example, the thickness of the first portion 137 is ½ or less of the thickness of the second portion 138. In one example, the thickness of the first portion 137 is ⅓ or less of the thickness of the second portion 138. In one example, the thickness of the first portion 137 is ¼ or more of the thickness of the second portion 138. In one example, the thickness of the first portion 137 is ¼ or more and ¾ or less of the thickness (size in the Z direction) of the first chip 60.

[0352] The width H1 of the step portion 139 is equal to each other on the first to fourth substrate side surfaces 133 to 136. The width H1 of the step portion 139 is, for example, about 3 μm. Here, the width H1 of the step portion 139 can be defined, for example, by the distance between a portion of the first substrate side surface 133 corresponding to the first portion 137 and a portion corresponding to the second portion 138.

[0353] Fig. 26 shows a schematic cross-sectional structure of the second die pad 50A and the second chip 70 taken along the XZ plane, and Fig. 27 shows a schematic cross-sectional structure of the second die pad 50A and the second chip 70 taken along the YZ plane. In the cross-sectional structures of Fig. 26 and Fig. 27, the wires WD, WE and the sealing resin 90 are omitted.

[0354] 26 and 27 , the second chip 70 mounted on the second die pad 50A includes a substrate 230. The substrate 230 is formed, for example, of a semiconductor substrate. The substrate 230 is a semiconductor substrate formed of a material containing silicon. Note that a wide bandgap semiconductor or a compound semiconductor may be used as the semiconductor substrate for the substrate 230. Furthermore, instead of a semiconductor substrate, an insulating substrate formed of a material containing glass or a material containing ceramics such as alumina may be used as the substrate 230.

[0355] The wide bandgap semiconductor is a semiconductor substrate having a bandgap of 2.0 eV or greater. The wide bandgap semiconductor may be any one of silicon carbide, gallium nitride, and gallium oxide. The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of aluminum nitride, indium nitride, gallium nitride, and gallium arsenide.

[0356] The substrate 230 of the second chip 70 has first to fourth substrate side surfaces 233 to 236 that connect the substrate front surface 231 and the substrate back surface 232. The first substrate side surface 233 constitutes a part of the first chip side surface 73 of the second chip 70, the second substrate side surface 234 constitutes a part of the second chip side surface 74, the third substrate side surface 235 constitutes a part of the third chip side surface 75, and the fourth substrate side surface 236 constitutes a part of the fourth chip side surface 76. The substrate back surface 232 constitutes the chip back surface 72 of the second chip 70.

[0357] The substrate 230 can be divided into a first portion 237 and a second portion 238 by a step portion 239. The first portion 237 is a portion of the substrate 230 that is closer to the second die pad 50A. The second portion 238 is a portion that is provided on the first portion 237. As shown in FIGS. 26 and 27 , the step portion 239 is formed around the entire periphery of the substrate 230.

[0358] In one example, the thickness dimension (size in the Z direction) of the first portion 237 is larger than the thickness dimension (size in the Z direction) of the second portion 238. In one example, the thickness dimension of the first portion 237 is more than twice the thickness dimension of the second portion 238. In one example, the thickness dimension of the first portion 237 is more than three times the thickness dimension of the second portion 238. In one example, the thickness dimension of the first portion 237 is less than four times the thickness dimension of the second portion 238.

[0359] 26 and 27 , the second conductive bonding material SD2 is interposed between the first portion 237 and the second die pad 50A in the Z direction, and has a portion that protrudes from the second chip 70 in a direction perpendicular to the Z direction. This protruding portion forms a second fillet SDB between the first portion 237 and the second conductive bonding material SD2. The second fillet SDB is not formed in the second portion 238 due to a step portion 239. In the example shown in FIGS. 26 and 27 , the second fillet SDB is formed over the entire first portion 237 in the Z direction.

[0360] The height dimension (size in the Z direction) of the second fillet SDB can be changed as desired as long as it is lower than the step portion 239. In one example, the height dimension of the second fillet SDB may be approximately half the thickness dimension of the first portion 237.

[0361] Furthermore, the position of the step portion 239 in the second chip 70 in the Z direction can be changed as desired. That is, the relationship between the thickness of the first portion 237 and the thickness of the second portion 238 can be changed as desired. In one example, the thickness of the first portion 237 may be equal to the thickness of the second portion 238. In one example, the thickness of the first portion 237 is ½ or less of the thickness of the second portion 238. In one example, the thickness of the first portion 237 is ⅓ or less of the thickness of the second portion 238. In one example, the thickness of the first portion 237 is ¼ or more of the thickness of the second portion 238. In one example, the thickness of the first portion 237 is ¼ or more and ¾ or less of the thickness (size in the Z direction) of the second chip 70.

[0362] The width H2 of the step portion 239 is equal to each other on the first to fourth substrate side surfaces 233 to 236. The width H2 of the step portion 239 is, for example, about 3 μm. Here, the width H2 of the step portion 239 can be defined, for example, by the distance between a portion of the first substrate side surface 233 corresponding to the first portion 237 and a portion of the first substrate side surface 233 corresponding to the second portion 238.

[0363] Fig. 28 shows a schematic cross-sectional structure of the third die pad 50B and the third chip 80 taken along the XZ plane, and Fig. 29 shows a schematic cross-sectional structure of the third die pad 50B and the third chip 80 taken along the YZ plane. For this reason, the wires WF, WG and the sealing resin 90 are omitted from the cross-sectional structures of Fig. 28 and Fig. 29.

[0364] 28 and 29 , the third chip 80 mounted on the third die pad 50B includes a substrate 330. The substrate 330 is formed, for example, of a semiconductor substrate. The substrate 330 is a semiconductor substrate formed of a material containing silicon. Note that a wide bandgap semiconductor or a compound semiconductor may be used as the semiconductor substrate for the substrate 330. Alternatively, instead of a semiconductor substrate, an insulating substrate formed of a material containing glass or a material containing ceramics such as alumina may be used as the substrate 330.

[0365] The wide bandgap semiconductor is a semiconductor substrate having a bandgap of 2.0 eV or greater. The wide bandgap semiconductor may be any one of silicon carbide, gallium nitride, and gallium oxide. The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of aluminum nitride, indium nitride, gallium nitride, and gallium arsenide.

[0366] The substrate 330 of the third chip 80 has first to fourth substrate side surfaces 333 to 336 that connect the substrate front surface 331 and the substrate back surface 332. The first substrate side surface 333 constitutes a part of the first chip side surface 83 of the third chip 80, the second substrate side surface 334 constitutes a part of the second chip side surface 84, the third substrate side surface 335 constitutes a part of the third chip side surface 85, and the fourth substrate side surface 336 constitutes a part of the fourth chip side surface 86. The substrate back surface 332 constitutes the chip back surface 82 of the third chip 80.

[0367] The substrate 330 can be divided into a first portion 337 and a second portion 338 by a step portion 339. The first portion 337 is a portion of the substrate 330 that is closer to the third die pad 50B. The second portion 338 is a portion that is provided on the first portion 337. As shown in FIGS. 28 and 29 , the step portion 339 is formed around the entire periphery of the substrate 330.

[0368] In one example, the thickness dimension (size in the Z direction) of the first portion 337 is larger than the thickness dimension (size in the Z direction) of the second portion 338. In one example, the thickness dimension of the first portion 337 is more than twice the thickness dimension of the second portion 338. In one example, the thickness dimension of the first portion 337 is more than three times the thickness dimension of the second portion 338. In one example, the thickness dimension of the first portion 337 is less than four times the thickness dimension of the second portion 338.

[0369] 28 and 29 , the third conductive bonding material SD3 is interposed between the first portion 337 and the third die pad 50B in the Z direction, and has a portion that protrudes from the third chip 80 in a direction perpendicular to the Z direction. This protruding portion forms a third fillet SDC between the first portion 337 and the third conductive bonding material SD3. The third fillet SDC is not formed in the second portion 338 due to a step portion 339. In the example shown in FIGS. 28 and 29 , the third fillet SDC is formed over the entire first portion 337 in the Z direction.

[0370] The height dimension (size in the Z direction) of the third fillet SDC can be changed as desired as long as it is lower than the step portion 339. In one example, the height dimension of the third fillet SDC may be approximately half the thickness dimension of the first portion 337.

[0371] Furthermore, the position of the step portion 339 in the third chip 80 in the Z direction can be changed as desired. That is, the relationship between the thickness of the first portion 337 and the thickness of the second portion 338 can be changed as desired. In one example, the thickness of the first portion 337 may be equal to the thickness of the second portion 338. In one example, the thickness of the first portion 337 is ½ or less of the thickness of the second portion 338. In one example, the thickness of the first portion 337 is ⅓ or less of the thickness of the second portion 338. In one example, the thickness of the first portion 337 is ¼ or more of the thickness of the second portion 338. In one example, the thickness of the first portion 337 is ¼ or more and ¾ or less of the thickness (size in the Z direction) of the third chip 80.

[0372] The width H3 of the step portion 339 is equal to each other on the first to fourth substrate side surfaces 333 to 336. The width H3 of the step portion 339 is, for example, about 3 μm. Here, the width H3 of the step portion 339 can be defined, for example, by the distance between a portion of the first substrate side surface 333 corresponding to the first portion 337 and a portion of the first substrate side surface 333 corresponding to the second portion 338.

[0373] As described above, the Z-direction positions of step portions 139, 239, and 339 are determined individually for the first chip 60, the second chip 70, and the third chip 80, so the distance in the Z-direction between the first die pad 30 and step portion 139, the distance in the Z-direction between the second die pad 50A and step portion 239, and the distance in the Z-direction between the third die pad 50B and step portion 339 may differ from one another.

[0374] Additionally, the ratio of the thickness dimension of the second portion 138 to the thickness dimension of the first portion 137 of the first chip 60, the ratio of the thickness dimension of the second portion 238 to the thickness dimension of the first portion 237 of the second chip 70, and the ratio of the thickness dimension of the second portion 338 to the thickness dimension of the first portion 337 of the third chip 80 may be different. In one example, the ratio of the thickness dimension of the second portion 138 to the thickness dimension of the first portion 137 of the first chip 60 may be 1 / 3, and the ratio of the thickness dimension of the second portion 238 to the thickness dimension of the first portion 237 of the second chip 70 and the ratio of the thickness dimension of the second portion 338 to the thickness dimension of the first portion 337 of the third chip 80 may both be 1.

[0375] [Method for Manufacturing First Chip] An example of a manufacturing process for the first chip 60 will be described with reference to FIGS. 30 to 33 . The method for manufacturing the first chip 60 includes the steps of preparing a substrate 830, forming an element insulating layer 850 on the substrate 830, forming a passivation film 861, forming a protective film 862, and singulating. An overview of each step will be described below. Note that FIGS. 30 to 33 show a schematic cross-sectional structure of the first chip 60. In FIGS. 31 to 33 , the hatched lines of the passivation film 861 and the protective film 862 have been omitted to facilitate understanding of the drawings. Furthermore, since the second chip 70 and the third chip 80 are manufactured in the same manner as the first chip 60, an example of a manufacturing process for the second chip 70 and the third chip 80 will not be described here.

[0376] 30 , in the step of preparing a substrate 830, a substrate 830 including a plurality of substrates 130 (see FIG. 24 ) is prepared. Here, the first transmission unit 501, the second transmission unit 502, the logic unit 503, the LDO unit 504, the UVLO unit 505, the delay unit 506, the Schmitt triggers 507 and 508, and the resistors 509 and 510 shown in FIG. 9 are formed in regions of the substrate 830 corresponding to each of the plurality of substrates 130.

[0377] As shown in FIG. 31, in the process of forming an element insulating layer 850 on a substrate 830, SiO 2 is deposited on a substrate surface 831 of the substrate 830 by, for example, a CVD method. ２ The film is laminated. ２The film is a film that constitutes the element insulating layer 850. The element insulating layer 850 is made of, for example, a plurality of SiO ２ It is composed of a laminated film structure.

[0378] Although not shown, a step of forming the first to fourth back surface side coils 111B to 114B by, for example, sputtering and etching is carried out during the step of forming the element insulating layer 850 on the substrate 830. Then, after the step of forming the first to fourth back surface side coils 111B to 114B is carried out, the step of forming the element insulating layer 850 on the substrate 830 is carried out again.

[0379] Although not shown, after the element insulating layer 850 is formed, a process is carried out in which the first to fourth surface side coils 111A to 114A and the first to third electrode pads 67 to 69 are formed by sputtering and etching.

[0380] Subsequently, in the step of forming the passivation film 861, the passivation film 861 is formed by, for example, a CVD method on the element insulating layer 850. Although not shown, the passivation film 861 also covers the second to fourth surface-side coils 112A to 114A and the first to third electrode pads 67 to 69.

[0381] Subsequently, in the step of forming the protective film 862, the protective film 862 is formed on the passivation film 861 by, for example, a CVD method. The protective film 862 is formed over the entire surface of the passivation film 861, for example.

[0382] Subsequently, although not shown, openings are formed by, for example, etching in positions that overlap with portions of the first to third electrode pads 67 to 69 in both the protective film 862 and the passivation film 861. As a result, portions of the first to third electrode pads 67 to 69 are exposed in the Z direction from both the protective film 862 and the passivation film 861.

[0383] 32 and 33 , the singulation process includes a first dicing process and a second dicing process. As shown in FIG. 32 , in the first dicing process, the substrate 830 is first placed on the dicing tape DT. The back surface 832 of the substrate 830 is in contact with the dicing tape DT. Next, the first dicing blade DB1 cuts the protective film 862, the passivation film 861, and the element insulating layer 850, and also cuts a portion of the substrate 830 in the Z direction. As a result, a recess 833 is formed in the substrate 830.

[0384] 33, in the second dicing step, the substrate 830 is cut by a second dicing blade DB2. The second dicing blade DB2 is a blade that is narrower than the first dicing blade DB1. The second dicing blade DB2 cuts the substrate 830 from the recess 833 of the substrate 830. As a result, a step portion 839 is formed in the substrate 830. Thereafter, the dicing tape DT is removed. Through the above steps, the first chip 60 is manufactured.

[0385] [Effects] The signal transmission device 10 of the fifth embodiment has the following effects: (5-1) The substrate 130 of the first chip 60 has a first portion 137 including the substrate back surface 132, a second portion 138 provided on the first portion 137, and a step portion 139 formed so that the second portion 138 is positioned inside the substrate 130 with respect to the first portion 137.

[0386] According to this configuration, when the first chip 60 is mounted on the first die pad 30 using the first conductive bonding material SD1, the step portion 139 can prevent the first conductive bonding material SD1 from creeping up to the chip surface 61 of the first chip 60.

[0387] (5-2) The substrate 230 of the second chip 70 has a first portion 237 including the back surface 232 of the substrate, a second portion 238 provided on the first portion 237, and a step portion 239 formed so that the second portion 238 is positioned inside the substrate 230 relative to the first portion 237.

[0388] According to this configuration, when the second chip 70 is mounted on the second die pad 50A using the second conductive bonding material SD2, the step portion 239 can prevent the second conductive bonding material SD2 from creeping up to the chip surface 71 of the second chip 70.

[0389] (5-3) The substrate 330 of the third chip 80 has a first portion 337 including the back surface 332 of the substrate, a second portion 338 provided on the first portion 337, and a step portion 339 formed so that the second portion 338 is positioned inside the substrate 330 relative to the first portion 337.

[0390] According to this configuration, when the third chip 80 is mounted on the third die pad 50B using the third conductive bonding material SD3, the step portion 339 can prevent the third conductive bonding material SD3 from creeping up to the chip surface 81 of the third chip 80.

[0391] Sixth Embodiment A signal transmission device 10 of a sixth embodiment will be described with reference to Figures 34 to 38. The signal transmission device 10 of the sixth embodiment differs from the signal transmission device 10 of the first embodiment in the configuration of the first chip 60. Below, differences in the configuration of the first chip 60 from the first embodiment will be described in detail. Furthermore, components common to the first embodiment will be assigned the same reference numerals, and descriptions thereof will be omitted.

[0392] 34 , a passivation film 161 is formed on the layer surface 151 of the element insulating layer 150, while the multiple first electrode pads 67 are not formed on the layer surface 151. In other words, the passivation film 161 is in contact with the layer surface 151, and the multiple first electrode pads 67 are arranged at a distance from the layer surface 151 in the Z direction. The passivation film 161 is formed over the entire layer surface 151 of the element insulating layer 150.

[0393] The first chip 60 further includes a first organic insulating layer 191 formed on the passivation film 161, and a second organic insulating layer 192 formed on the first organic insulating layer 191. Here, the first organic insulating layer 191 corresponds to the "first resin layer," and the second organic insulating layer 192 corresponds to the "second resin layer."

[0394] Both the first organic insulating layer 191 and the second organic insulating layer 192 are formed of an insulating material having a relative dielectric constant different from that of the element insulating layer 150. Both the first organic insulating layer 191 and the second organic insulating layer 192 may contain at least one of polyimide, phenolic resin, and epoxy resin. The first organic insulating layer 191 and the second organic insulating layer 192 may be formed of the same resin material or different resin materials.

[0395] The first surface side coil 111A and the multiple first electrode pads 67 are formed on the first organic insulating layer 191. In other words, both the first surface side coil 111A and the multiple first electrode pads 67 are provided outside the element insulating layer 150. It can also be said that both the first surface side coil 111A and the multiple first electrode pads 67 are disposed at a distance from the element insulating layer 150 in the Z direction. The first surface side coil 111A and the multiple first electrode pads 67 are provided at the same positions as each other in the Z direction. Although not shown, the second to fourth surface side coils 112A to 114A are also formed on the first organic insulating layer 191. In this way, the first to fourth surface side coils 111A to 114A correspond to "surface side coils."

[0396] The first surface-side coil 111A and the plurality of first electrode pads 67 are covered with a second organic insulating layer 192. The second organic insulating layer 192 has openings 192A that expose a portion of the surface of each first electrode pad 67 in the Z direction. The second organic insulating layer 192 is a protective film that protects the first chip 60 and constitutes the chip surface 61.

[0397] 35 , the coil back surface 172 of the conductor 170 of the first surface side coil 111A is in contact with the first organic insulating layer 191. The first surface side coil 111A is covered with the first organic insulating layer 191 and the second organic insulating layer 192. The second organic insulating layer 192 is in contact with the coil front surface 171 and a pair of coil side surfaces 173 of the conductor 170. The second organic insulating layer 192 is interposed between adjacent conductors 170 in the Y direction of the first surface side coil 111A.

[0398] The thickness of the second organic insulating layer 192 is thinner than the thickness of the element insulating layer 150. The thickness of the second organic insulating layer 192 is thinner than the distance in the Z direction between the coil surface 181 of the conductive wire 180 in the coil layer 111BA of the first back-side coil 111B and the layer surface 151 of the element insulating layer 150. The thickness of the second organic insulating layer 192 is thicker than the thickness of the conductive wire 180. The thickness of the second organic insulating layer 192 is thicker than the thickness of the conductive wire 170. The thickness of the second organic insulating layer 192 is thicker than the thickness of the first electrode pad 67A (the size of the first electrode pad 67A in the Z direction).

[0399] As in the first embodiment, the first back side coil 111B is embedded in the element insulating layer 150. The first back side coil 111B is disposed closer to the layer back surface 152 of the element insulating layer 150. Although not shown, the second to fourth back side coils 112B to 114B are also embedded in the element insulating layer 150. Here, the first to fourth back side coils 111B to 114B correspond to "back side coils."

[0400] As described above, both the element insulating layer 150 and the first organic insulating layer 191 are interposed between the first front-side coil 111A and the first back-side coil 111B in the Z direction. In other words, both an inorganic insulating layer and an organic insulating layer are interposed between the first front-side coil 111A and the first back-side coil 111B in the Z direction. In the example of Fig. 35, three different layers, the element insulating layer 150, the passivation film 161, and the first organic insulating layer 191, are interposed between the first front-side coil 111A and the first back-side coil 111B in the Z direction.

[0401] Although not shown, the front-side guard ring 115 (see FIG. 11 ) is formed on the first organic insulating layer 191. That is, the front-side guard ring 115 is provided at the same position in the Z direction as the first front-side coil 111A and the first electrode pad 67A. In one example, the via 117 has a laminated structure including a first portion, a second portion, and a third portion. The first portion penetrates in the Z direction from the rear-side guard ring 116 (see FIG. 13 ) to the surface 151 of the element insulating layer 150. The first portion is in contact with the rear-side guard ring 116. The second portion penetrates the passivation film 161 in the Z direction to connect to the first portion and is formed on the passivation film 161. The second portion is covered by the first organic insulating layer 191. The third portion penetrates in the Z direction through a portion of the first organic insulating layer 191 that covers the second portion and connects to both the second portion and the front-side guard ring 115.

[0402] 34 and 35, the first chip 60 has a two-layer laminate structure of the first organic insulating layer 191 and the second organic insulating layer 192, but is not limited to this. The first chip 60 may have a structure in which three or more organic insulating layers are laminated.

[0403] 36 to 38, a method for manufacturing the first chip 60, in particular a method for manufacturing the first surface side coil 111A, will be described. Figures 36 to 38 mainly show a process for forming a part of the first surface side coil 111A in the element insulating layer 850.

[0404] Although not shown, the manufacturing method of the first chip 60 includes the steps of preparing a substrate 830, forming an element insulating layer 850 on the substrate 830, forming a first back side coil 111B on the element insulating layer 850, and forming a passivation film 861 on the element insulating layer 850. The second to fourth back side coils 112B to 114B are formed simultaneously with the step of forming the first back side coil 111B.

[0405] Here, the substrate 830 is a substrate that constitutes the plurality of substrates 130. The element insulating layer 850 is formed over an area corresponding to the plurality of substrates 130. The element insulating layer 850 corresponds to the element insulating layer 150 of the first chip 60. The passivation film 861 is formed over the entire surface of the element insulating layer 850. The passivation film 861 corresponds to the passivation film 161 of the first chip 60.

[0406] 36 , the manufacturing method of the first chip 60 includes a step of forming a first organic insulating layer 891. More specifically, the first organic insulating layer 891 is formed on the passivation film 861 by, for example, spin coating. The first organic insulating layer 891 may contain at least one of polyimide, phenolic resin, and epoxy resin. The first organic insulating layer 891 corresponds to the first organic insulating layer 191 of the first chip 60.

[0407] As shown in FIG. 37 , the manufacturing method for the first chip 60 includes a step of forming the first surface side coil 111A and the first electrode pads 67A. More specifically, a barrier layer (not shown) constituting the first surface side coil 111A and the first electrode pads 67A is formed on the first organic insulating layer 191, for example, by sputtering. Here, the barrier layer is a base conductive layer for plating the conductor wires 170 and the first electrode pads 67. The barrier layer may contain at least one of titanium, titanium nitride, tantalum, and tantalum nitride. Next, the barrier layer is removed from the first surface side coil 111A except for the positions where the conductor wires 170 and the first electrode pads 67 are to be formed, for example, by lithography and etching. Next, a conductive material constituting the conductor wires 170 and the first electrode pads 67 is plated on the barrier layer. For example, copper is used as the conductive material. Through the above steps, the first surface side coil 111A and the first electrode pads 67 are manufactured. Although not shown, the second to fourth surface side coils 112A to 114A and the other first electrode pads 67 are manufactured simultaneously in this process.

[0408] As shown in FIG. 38 , the manufacturing method of the first chip 60 includes a step of forming a second organic insulating layer 892. More specifically, the second organic insulating layer 892 is formed on the first organic insulating layer 891 by, for example, spin coating. The second organic insulating layer 892 is formed so as to cover the first surface-side coil 111A and the first electrode pad 67. Although not shown, the second organic insulating layer 892 is formed so as to cover the second to fourth surface-side coils 112A to 114A and the other first electrode pads 67. Subsequently, an opening 892A that exposes a portion of the first electrode pad 67A in the Z direction is formed in the second organic insulating layer 892 by lithography and etching. Note that openings that expose a portion of each of the other first electrode pads 67 in the Z direction are also formed at the same time.

[0409] Next, the manufacturing method of the first chip 60 includes a singulation process. In the singulation process, the substrate 830, the passivation film 861, the first organic insulating layer 891, and the second organic insulating layer 892 are cut by dicing. Through the above processes, the first chip 60 is manufactured.

[0410] [Effects] The signal transmission device 10 of the sixth embodiment has the following effects: (6-1) The first chip 60 includes a first organic insulating layer 191 provided on the element insulating layer 150 and a second organic insulating layer 192 provided on the first organic insulating layer 191. The first transformer 111 includes first to fourth front surface side coils 111A to 114A that are disposed on the first organic insulating layer 191 and covered with the second organic insulating layer 192, and first to fourth back surface side coils 111B to 114B that are disposed opposite the first to fourth front surface side coils 111A to 114A in the Z direction and are embedded in the element insulating layer 150.

[0411] With this configuration, the distance in the Z direction between the first to fourth front-side coils 111A to 114A and the first to fourth back-side coils 111B to 114B can be increased by thickening the first organic insulating layer 191. In other words, the dielectric strength between the first to fourth front-side coils 111A to 114A and the first to fourth back-side coils 111B to 114B can be improved by thickening the first organic insulating layer 191. Therefore, to thicken the element insulating layer 150, it is not necessary to form the element insulating layer 150 into a multi-layer structure in which, for example, etching stopper films formed of silicon nitride films and interlayer insulating films formed of silicon oxide films are alternately stacked one on top of another. This simplifies the configuration of the element insulating layer 150. Additionally, the first organic insulating layer 191 can be easily thickened by spin coating. As a result, compared to when the element insulating layer 150 is thickened, the lead time can be shortened, thereby reducing manufacturing costs.

[0412] Seventh Embodiment A signal transmission device 10 of the seventh embodiment will be described with reference to Fig. 39. The signal transmission device 10 of the seventh embodiment differs from the signal transmission device 10 of the first embodiment in the configuration of the first chip 60. Below, differences in the configuration of the first chip 60 from the first embodiment will be described in detail. Furthermore, components common to the first embodiment will be assigned the same reference numerals, and descriptions thereof will be omitted.

[0413] 39 , in the seventh embodiment, the first chip 60 includes a low-dielectric layer 193 having a dielectric constant lower than that of the passivation film 161. The low-dielectric layer 193 is formed on the passivation film 161. In the seventh embodiment, the low-dielectric layer 193 is formed over the entire surface of the passivation film 161. The low-dielectric layer 193 is in contact with the surface of the passivation film 161. It can be said that the low-dielectric layer 193 is interposed between the passivation film 161 and the sealing resin 90 in the Z direction so that the passivation film 161 and the sealing resin 90 do not come into contact with each other.

[0414] The thickness of the low dielectric layer 193 (the size of the low dielectric layer 193 in the Z direction) is equal to or less than the thickness of the passivation film 161. In one example, the thickness of the low dielectric layer 193 is thinner than the thickness of the passivation film 161. Note that the thickness of the low dielectric layer 193 can be changed as desired. In one example, the thickness of the low dielectric layer 193 may be thicker than the thickness of the passivation film 161.

[0415] The protective film 162 is formed on the low dielectric layer 193. The protective film 162 is in contact with the surface of the low dielectric layer 193. In other words, the low dielectric layer 193 is sandwiched in the Z direction between the passivation film 161 and the protective film 162. The protective film 162 is in contact with the sealing resin 90. The thickness of the protective film 162 is thicker than the thickness of the low dielectric layer 193. In other words, the thickness of the low dielectric layer 193 is thinner than the thickness of the protective film 162.

[0416] Next, a description will be given of the relationship between the dielectric constants of the element insulating layer 150, the passivation film 161, the low dielectric layer 193, the protective film 162, and the sealing resin 90. In the seventh embodiment, the element insulating layer 150 is made of silicon oxide (SiO ２ Since the element insulating layer 150 is made of a material containing silicon nitride (SiN), the relative dielectric constant of the element insulating layer 150 is about 4.1. Since the passivation film 161 is made of a material containing silicon nitride (SiN), the relative dielectric constant of the passivation film 161 is about 7.0. In other words, the relative dielectric constant of the passivation film 161 is higher than the relative dielectric constant of the element insulating layer 150.

[0417] In the seventh embodiment, the protective film 162 is made of a material containing polyimide, and therefore the relative dielectric constant of the protective film 162 is approximately 2.9. In addition, in the seventh embodiment, the sealing resin 90 is made of a material containing epoxy resin, and therefore the relative dielectric constant of the sealing resin 90 is approximately 3.9. In other words, the relative dielectric constant of the sealing resin 90 is lower than the dielectric constant of the passivation film 161. The relative dielectric constant of the sealing resin 90 is higher than the relative dielectric constant of the protective film 162.

[0418] The low-dielectric layer 193 has a lower dielectric constant than the passivation film 161. For example, the low-dielectric layer 193 has a dielectric constant equal to or lower than that of the element insulating layer 150. More specifically, the low-dielectric layer 193 has a dielectric constant lower than that of the element insulating layer 150. The low-dielectric layer 193 may have a dielectric constant equal to or lower than that of the sealing resin 90.

[0419] The low dielectric layer 193 is made of, for example, silicon oxide (SiO ２ ). In this way, the low-dielectric layer 193 may be formed from the same material as the element insulating layer 150. Furthermore, the low-dielectric layer 193 may have a lower dielectric constant than the element insulating layer 150. The low-dielectric layer 193 may be formed from a low-k film. The low-k film may be appropriately selected from, for example, a carbon-doped silicon oxide film (SiOC), a fluorine-doped silicon oxide film (SiOF), a porous film, etc. When the low-dielectric layer 193 is formed from a carbon-doped silicon oxide film, the dielectric constant of the low-dielectric layer 193 is 2.5 or more and 3.0 or less. When the low-dielectric layer 193 is formed from a fluorine-doped silicon oxide film, the dielectric constant of the low-dielectric layer 193 is 3.4 or more and 3.8 or less. When the low-dielectric layer 193 is formed from a porous film, the dielectric constant of the low-dielectric layer 193 is less than 2.5. In this way, by using a Low-K film for the low dielectric layer 193 , the relative dielectric constant of the low dielectric layer 193 can be made lower than that of the element insulating layer 150 and the sealing resin 90 .

[0420] [Effects] The signal transmission device 10 of the seventh embodiment has the following effects: (7-1) The first chip 60 includes an element insulating layer 150, a passivation film 161 formed on the element insulating layer 150 so as to cover the element insulating layer 150, and a low-dielectric layer 193 formed on the surface of the passivation film 161 and having a lower dielectric constant than the passivation film 161. The sealing resin 90 covers the low-dielectric layer 193.

[0421] According to this configuration, the low-dielectric layer 193 is interposed between the passivation film 161 and the sealing resin 90, thereby preventing contact between the passivation film 161 and the sealing resin 90. This prevents partial discharge and, ultimately, creeping discharge from occurring due to gaps present at the boundary between the sealing resin 90 and the passivation film 161. This improves the reliability of the first chip 60.

[0422] (7-2) The relative dielectric constant of the low dielectric layer 193 is equal to or lower than the dielectric constant of the sealing resin 90. With this configuration, the inception voltage of partial discharge at the boundary between the low dielectric layer 193 and the sealing resin 90 can be increased, and therefore, the occurrence of partial discharge, and therefore creeping discharge, due to gaps existing at the boundary between the low dielectric layer 193 and the sealing resin 90 can be suppressed.

[0423] (7-3) The thickness of the low-dielectric layer 193 is equal to or less than the thickness of the passivation film 161. This configuration can prevent the dimension of the first chip 60 in the Z direction from increasing. In other words, the height of the first chip 60 can be reduced.

[0424] Eighth Embodiment A signal transmission device 10 of an eighth embodiment will be described with reference to Figures 40 to 46. The signal transmission device 10 of the eighth embodiment differs from the signal transmission device 10 of the first embodiment in the configuration of the first chip 60. Below, differences in the configuration of the first chip 60 from the first embodiment will be described in detail. Furthermore, components common to the first embodiment will be assigned the same reference numerals, and descriptions thereof will be omitted.

[0425] [Configuration of First Chip] Fig. 40 shows an enlarged cross-sectional structure of a part of the first surface side coil 111A and its surrounding area in the first chip 60. Note that, to make the drawing easier to understand, hatching lines for some of the components of the first chip 60 have been omitted in Fig. 40.

[0426] 40 , the surface-side corner portion 176 formed by the coil surface 171 and the pair of coil side surfaces 173 of the conductor 170 of the first surface-side coil 111A is formed in a rounded curved shape, unlike in the first embodiment. It can also be said that the surface-side corner portion 176 has an R-surface (curved surface). That is, in the eighth embodiment, an R-surface (curved surface) is formed in the portion of the conductor 170 between the coil surface 171 and the pair of coil side surfaces 173. More specifically, the R-surface (curved surface) is formed by both the barrier layer 174 and the metal layer 175 that form the surface-side corner portion 176.

[0427] The coil surface 171 of the conductor 170 is located above the layer surface 151 of the element insulating layer 150. In other words, the conductor 170 protrudes from the layer surface 151 of the element insulating layer 150. The passivation film 161 covers the surface-side corner portions 176 of the conductor 170 and the coil surface 171. Therefore, the surface-side corner portions 176 are not in contact with the element insulating layer 150, but are in contact with the passivation film 161. The portion of the pair of coil side surfaces 173 of the conductor 170 that is closer to the coil back surface 172 than the surface-side corner portions 176 is in contact with the element insulating layer 150.

[0428] The relationship between the conductor 170 and the element insulating layer 150 can be changed as desired. In one example, the conductor 170 may be embedded in the element insulating layer 150. That is, the element insulating layer 150 may be provided so that the front-side corner portion 176 of the conductor 170 and the coil surface 171 are in contact with the element insulating layer 150. In this case, a passivation film 161 is formed over the entire surface 151 of the element insulating layer 150.

[0429] Although not shown, the conductor wires 170 of the second to fourth surface side coils 112A to 114A also have surface side corners 176 formed by the coil surface 171 and the pair of coil side surfaces 173, which are rounded and curved. The configuration of the first to fourth surface side coils 111A to 114A can be changed as desired. In other words, in the eighth embodiment, it is sufficient that the surface side corner 176 of at least one of the first to fourth surface side coils 111A to 114A is rounded and curved.

[0430] 41 to 46, a method for manufacturing the first chip 60, in particular a method for manufacturing the first surface side coil 111A, will be described. Figures 41 to 46 mainly show a process for forming a part of the first surface side coil 111A in the element insulating layer 850.

[0431] Although not shown, the method for manufacturing the first chip 60 includes the steps of preparing a substrate 830, forming an element insulating layer 850 on the substrate 830 (see FIG. 30, for example), and forming the first back side coil 111B (see FIG. 35) on the element insulating layer 850. The second to fourth back side coils 112B to 114B are formed simultaneously with the step of forming the first back side coil 111B.

[0432] 41 , the manufacturing method of the first chip 60 includes a step of forming a recess 853 in the element insulating layer 850. More specifically, in this step, the layer surface 851 of the element insulating layer 850 is selectively etched to form the recess 853. The recess 853 includes a bottom surface 853A and a pair of side surfaces 853B connecting the bottom surface 853A and the layer surface 851. The pair of side surfaces 853B are formed in a tapered shape that approaches each other in the Y direction from the layer surface 851 toward the bottom surface 853A.

[0433] 42 , the manufacturing method of the first chip 60 includes a step of forming a barrier layer 901. More specifically, the barrier layer 901 is formed on both a pair of side surfaces 853B and a bottom surface 853A of the recess 853 and on the layer surface 851 of the element insulating layer 850 by, for example, a sputtering method. The barrier layer 901 may contain tantalum or tantalum nitride. In one example, the barrier layer 901 is formed of a stacked structure (Ta / TaN / Ta) including a first layer containing tantalum, a second layer containing tantalum nitride stacked on the first layer, and a third layer containing tantalum stacked on the second layer.

[0434] Next, the manufacturing method of the first chip 60 includes a step of forming a metal layer 902. More specifically, a conductive material for the conductor 170 is plated from the barrier layer 901. In one example, copper is plated from the barrier layer 901. This forms the metal layer 902 in the recess 853 and on the element insulating layer 850. The metal layer 902 is formed from a material containing copper, for example.

[0435] 43 , the manufacturing method of the first chip 60 includes a step of removing the barrier layer 901 and the metal layer 902 on the element insulating layer 850. More specifically, both the barrier layer 901 and the metal layer 902 on the element insulating layer 850 are removed by chemical mechanical polishing (CMP). As a result, the layer surface 851 of the element insulating layer 850 is exposed.

[0436] 44 , the manufacturing method of the first chip 60 includes a step of removing the upper end portion of the element insulating layer 850. More specifically, the entire upper end portion of the element insulating layer 850 is removed by dry etching or wet etching. As a result, the layer surface 851 after the upper end portion of the element insulating layer 850 is removed is located lower than the respective upper end surfaces of the barrier layer 901 and the metal layer 902 (closer to the bottom surface 853A of the recess 853). In other words, the upper ends of the barrier layer 901 and the metal layer 902 protrude from the layer surface 851.

[0437] As shown in FIG. 45 , the manufacturing method for the first chip 60 includes a process of forming curved surfaces at both Y-direction ends (surface-side corner portions 903 in FIG. 44 ) of the upper ends of the barrier layer 901 and the metal layer 902. More specifically, a resist (not shown) is formed on the upper end surface of the metal layer 902. The resist is formed so that the surface-side corner portions 903 are exposed in a plan view. Next, the barrier layer 901 and the metal layer 902 that constitute the surface-side corner portions 903 are removed by dry etching or wet etching. As a result, the surface-side corner portions 903 are formed in a curved shape. Through the above processes, the conductive wire 170 is formed. As a result, the first to fourth surface-side coils 111A to 114A are formed. Although not shown, a plurality of first electrode pads 67 are formed in parallel with the process of forming the conductive wire 170 shown in FIGS. 41 to 45 .

[0438] 46 , the manufacturing method of first chip 60 includes a step of forming passivation film 861. More specifically, passivation film 861 is formed by, for example, chemical vapor deposition (CVD) or sputtering so as to cover coil surface 171 and front-side corner portion 176 of conducting wire 170 and layer surface 851 of element insulating layer 850. Passivation film 861 is formed of a material containing, for example, silicon nitride.

[0439] Although not shown, the manufacturing method of the first chip 60 includes a step of forming a protective film 862 (see FIG. 31 ). The protective film 862 is formed on the passivation film 861 by CVD or sputtering. The protective film 862 is formed of a material containing, for example, silicon oxide. Furthermore, openings that expose portions of the first electrode pads 67 are formed in both the protective film 862 and the passivation film 861 by etching. Thereafter, the protective film 862, the passivation film 861, the element insulating layer 850, and the substrate 830 are cut by dicing to separate the chip into individual pieces. Through the above steps, the first chip 60 is manufactured.

[0440] [Effects] The signal transmission device 10 of the eighth embodiment has the following effects: (8-1) The first to fourth surface-side coils 111A to 114A of the first transformer 111 each have a coil front surface 171, a coil back surface 172 opposite the coil front surface 171, and a coil side surface 173 connecting the coil front surface 171 and the coil back surface 172. A curved surface is formed between the coil front surface 171 and the coil side surface 173.

[0441] This configuration can mitigate electric field concentration at the front-side corner portion 176 defined by the coil front surface 171 and the coil side surface 173. This prevents the front-side corner portion 176 from becoming a starting point for dielectric breakdown, thereby improving the dielectric strength of the first chip 60.

[0442] 47 to 52, a signal transmission device 10 according to a ninth embodiment will be described. The signal transmission device 10 according to the ninth embodiment differs from the signal transmission device 10 according to the sixth embodiment in the configuration of the first chip 60. The following describes in detail the differences in the configuration of the first chip 60 from the sixth embodiment. Furthermore, the same reference numerals are used to designate components common to the sixth embodiment, and their description will be omitted.

[0443] [Configuration of First Chip] FIG. 47 shows an enlarged cross-sectional structure of a part of the first surface side coil 111A and its surrounding area in the first chip 60. As shown in FIG.

[0444] Similar to the sixth embodiment, the first chip 60 of the ninth embodiment includes a first organic insulating layer 191 formed on the layer surface 151 of the element insulating layer 150, and a second organic insulating layer 192 formed on the first organic insulating layer 191. Similar to the sixth embodiment, both the first surface-side coil 111A and the first electrode pad 67A are formed on the first organic insulating layer 191.

[0445] The surface-side corner portion 176 formed by the coil surface 171 and the pair of coil side surfaces 173 of the conductor 170 of the first surface-side coil 111A is formed in a rounded curved shape, unlike in the first embodiment. The surface-side corner portion 176 can also be said to have an R-surface (curved surface). That is, in the ninth embodiment, an R-surface (curved surface) is formed in the portion of the conductor 170 between the coil surface 171 and the pair of coil side surfaces 173.

[0446] The coil surface 171 of the conductor 170 is located above the layer surface 151 of the element insulating layer 150. In other words, the conductor 170 protrudes from the layer surface 151 of the element insulating layer 150. The passivation film 161 covers the surface-side corner portions 176 of the conductor 170 and the coil surface 171. Therefore, the surface-side corner portions 176 are not in contact with the element insulating layer 150, but are in contact with the passivation film 161. The portion of the pair of coil side surfaces 173 of the conductor 170 that is closer to the coil back surface 172 than the surface-side corner portions 176 is in contact with the element insulating layer 150.

[0447] Unlike the first embodiment, a back-side corner portion 177 of the conductor 170 formed by the coil back surface 172 and the pair of coil side surfaces 173 is formed in a rounded curve. The back-side corner portion 177 can also be said to have an R-surface (curved surface). In other words, in the ninth embodiment, an R-surface (curved surface) is formed in the portion of the conductor 170 between the coil back surface 172 and the pair of coil side surfaces 173.

[0448] The conductor 170 is covered with a second organic insulating layer 192. More specifically, the coil surface 171, the pair of coil side surfaces 173, the front-side corner portion 176, and the back-side corner portion 177 of the conductor 170 are in contact with the second organic insulating layer 192.

[0449] The conductive wire 170 is formed by a laminated structure of a seed layer 178 and a metal layer 179 formed on the seed layer 178. The seed layer 178 constitutes the coil back surface 172. In other words, the seed layer 178 is in contact with the first organic insulating layer 191. The seed layer 178 may contain, for example, at least one of titanium, titanium nitride, and copper. In one example, the seed layer 178 is formed by a laminated structure of a first layer containing titanium and a second layer containing copper laminated on the first layer.

[0450] Because the seed layer 178 is interposed between the metal layer 179 and the first organic insulating layer 191 in the Z direction, the metal layer 179 is disposed at a distance from the first organic insulating layer 191 in the Z direction. The metal layer 179 includes a coil front surface 171, a pair of coil side surfaces 173, a front-side corner portion 176, and a back-side corner portion 177. The metal layer 179 is covered with the second organic insulating layer 192.

[0451] [Method of Manufacturing First Chip] A method of manufacturing the first chip 60, particularly a method of manufacturing the first surface side coil 111A, will be described with reference to FIGS.

[0452] Although not shown, the manufacturing method of the first chip 60 includes the steps of preparing a substrate 830 (see, for example, FIG. 30 ), forming an element insulating layer 850 on the substrate 130, forming a first back side coil 111B (see FIG. 31 ) on the element insulating layer 850, forming a passivation film 861, and forming a first organic insulating layer 891. Note that the second to fourth back side coils 112B to 114B are formed simultaneously with the step of forming the first back side coil 111B. The passivation film 861 is formed on the layer surface 851 of the element insulating layer 850 by, for example, CVD or sputtering. The first organic insulating layer 891 is formed on the passivation film 161 by, for example, spin coating.

[0453] 48 , the manufacturing method of the first chip 60 includes a step of forming a seed layer 911. More specifically, the seed layer 911 is formed on the first organic insulating layer 891 by, for example, a sputtering method. The seed layer 911 may contain titanium and copper. In one example, the seed layer 911 is formed of a stacked structure (Ti / Cu) of a first seed layer 911A containing titanium and a second seed layer 911B containing copper stacked on the first seed layer 911A.

[0454] Next, the manufacturing method of the first chip 60 includes a step of forming a resist 920. More specifically, first, the resist 920 is formed on the seed layer 911. Next, the resist 920 is selectively exposed to light and developed to form openings 921 that expose the portions where the conductive wires 170 (see FIG. 47) and the portions where the first electrode pads 67 (see FIG. 34) are to be formed.

[0455] 48 shows an opening 921 where the conductive wire 170 is to be formed. The surfaces of the resist 920 that form the opening 921 are tapered so that they approach each other as they approach the seed layer 911. The portion of the opening 921 of the resist 920 that contacts the seed layer 911 has an inward protruding portion 922 that is curved and concave.

[0456] As shown in FIG. 49 , the manufacturing method of the first chip 60 includes a step of forming a metal layer 912. More specifically, a conductive material for the conductor 170 is plated from the seed layer 911. In one example, copper is plated from the seed layer 911. This forms the metal layer 912 in the opening 921. The metal layer 912 is formed, for example, from a material containing copper. The metal layer 912 is integrated with the second seed layer 911B. Here, in FIG. 49 , to facilitate understanding of the drawing, the interface between the second seed layer 911B and the metal layer 912 is indicated by a two-dot chain line. However, in reality, this interface may not be formed. Also, although not shown, the metal layer 912 is formed in the opening 921 where the first electrode pad 67 is to be formed. This results in the first electrode pad 67 being manufactured.

[0457] Here, the end of the metal layer 912 on the seed layer 911 side has a rounded corner (curved surface) formed by the inward protrusion 922 of the resist 920. That is, in this process, the metal layer 912 has a rounded corner (curved surface) corresponding to the rear surface corner 177 of the conductive wire 170.

[0458] As shown in FIG. 50 , the manufacturing method for the first chip 60 includes a step of removing the resist 920 (see FIG. 49 ). This exposes the seed layer 911 and the metal layer 912. As shown in FIG. 51 , the manufacturing method for the first chip 60 includes a step of etching the seed layer 911 and the metal layer 912. In one example, this step includes a step of forming curved surfaces at both ends of the upper end of the metal layer 912 in the Y direction (front surface corner portions 913 in FIG. 50 ) and a step of removing the second seed layer 911B of the seed layer 911. More specifically, a resist (not shown) is formed on the upper end surface of the metal layer 912. The resist is formed so that the front surface corner portions 913 are exposed in a planar view. Subsequently, the metal layer 912 constituting the front surface corner portions 913 is removed by dry etching or wet etching. This results in the front surface corner portions 913 having rounded R surfaces (curved surfaces). That is, in this step, an R-surface (curved surface) corresponding to the front-side corner portion 176 of the conductive wire 170 is formed in the metal layer 912. Also, the second seed layer 911B is removed by dry etching or wet etching.

[0459] 52, the method for manufacturing the first chip 60 involves removing the seed layer 911 in a portion other than the portion on which the metal layer 912 is laminated. More specifically, the seed layer 911 in a portion other than the portion on which the metal layer 912 is laminated is removed by, for example, etching. Through the above steps, the conductor 170 is formed. In this way, the first surface side coil 111A is formed. The second to fourth surface side coils 112A to 114A are also formed in a similar manner.

[0460] Although not shown, the method for manufacturing the first chip 60 includes a step of forming a second organic insulating layer 192. The second organic insulating layer 192 is formed on the first organic insulating layer 191 by spin coating. The second organic insulating layer 192 is formed so as to cover the conductive wires 170 and the first electrode pads 67A to 67F. Furthermore, openings are formed in the second organic insulating layer 192 by etching, through which portions of the first electrode pads 67A to 67F are exposed. Through the above steps, the first chip 60 is manufactured.

[0461] [Effects] The signal transmission device 10 of the ninth embodiment has the following effects. (9-1) The first to fourth surface side coils 111A to 114A of the first transformer 111 each have a coil front surface 171, a coil back surface 172 opposite the coil front surface 171, and a coil side surface 173 connecting the coil front surface 171 and the coil back surface 172. A curved surface is formed between the coil front surface 171 and the coil side surface 173. A curved surface is formed between the coil back surface 172 and the coil side surface 173.

[0462] This configuration can alleviate electric field concentration at front-side corner portion 176 defined by coil front surface 171 and coil side surface 173, and can also alleviate electric field concentration at back-side corner portion 177 defined by coil back surface 172 and coil side surface 173. This prevents front-side corner portion 176 and back-side corner portion 177 from becoming starting points for dielectric breakdown, thereby improving the dielectric strength of first chip 60.

[0463] <Modifications> The above-described embodiments can be modified as follows: Furthermore, the above-described embodiments and the following modifications can be combined with each other to the extent that no technical contradiction occurs.

[0464] [Combinations of Embodiments] Examples of combinations of the first to ninth embodiments will be described below: At least one of the configurations of the second to fifth embodiments may be added to the signal transmission device 10 of the first embodiment.

[0465] At least one of the configurations of the sixth and ninth embodiments may be added to the signal transmission device 10 of the first embodiment. At least one of the configurations of the seventh and eighth embodiments may be added to the signal transmission device 10 of the first embodiment.

[0466] At least one of the configurations of the sixth and ninth embodiments may be added to the signal transmission device 10 obtained by adding at least one of the configurations of the second to fifth embodiments to the first embodiment. At least one of the configurations of the seventh and eighth embodiments may be added to the signal transmission device 10 obtained by adding at least one of the configurations of the second to fifth embodiments to the first embodiment.

[0467] [Modifications of First Die Pad and Second Die Pad] In each embodiment, the first die pad 30 may be provided with one or more through holes that penetrate the first die pad 30 in its thickness direction (Z direction). Each through hole is filled with sealing resin 90.

[0468] In each embodiment, the second die pad 50A may be provided with one or more through holes that penetrate the second die pad 50A in its thickness direction (Z direction). Each through hole is filled with sealing resin 90.

[0469] In each embodiment, the third die pad 50B may be provided with one or more through holes that penetrate the third die pad 50B in its thickness direction (Z direction). Each through hole is filled with sealing resin 90.

[0470] [Modifications of the First Terminal, Second Terminal, and Third Terminal] In each embodiment, the coverage area of ​​the plating layer 25 covering the first internal terminal portions 12B to 17B of the first terminals 12 to 17 can be changed as desired. In one example, the plating layer 25 may cover the entire internal terminal surface 21 of each of the first internal terminal portions 12B to 17B. In this case, a portion of the plating layer 25 may cover the tip end surface 24 of the first internal terminal portions 12B to 17B.

[0471] In each embodiment, the coverage area of ​​the plating layer 25 covering the second internal terminal portions 42B, 43B of the second terminals 42, 43 can be changed as desired. In one example, the plating layer 25 may cover the entire internal terminal surface 21 of each of the second internal terminal portions 42B, 43B. In this case, a portion of the plating layer 25 may cover the tip end surface 24 of the second internal terminal portions 42B, 43B.

[0472] In each embodiment, the coverage area of ​​the plating layer 25 covering the third internal terminal portions 45B, 46B of the third terminals 45, 46 can be changed as desired. In one example, the plating layer 25 may cover the entire internal terminal surface 21 of each of the third internal terminal portions 45B, 46B. In this case, a portion of the plating layer 25 may cover the tip end surface 24 of the third internal terminal portion 45B, 46B.

[0473] In each embodiment, the distance between the second terminal 43 and the third terminal 44 in the Y direction may be, for example, equal to or less than the distance between the second terminal 42 and the second terminal 43 in the Y direction. The distance between the second terminal 43 and the third terminal 44 in the Y direction may be, for example, equal to or less than the distance between the third terminal 44 and the third terminal 45 in the Y direction. In other words, the shortest distance between the multiple second terminals 41 to 43 and the multiple third terminals 44 to 46 may be equal to or less than the distance between adjacent second terminals among the multiple second terminals 41 to 43 in the Y direction (second direction). Furthermore, the shortest distance between the multiple second terminals 41 to 43 and the multiple third terminals 44 to 46 may be equal to or less than the distance between adjacent third terminals among the multiple third terminals 44 to 46 in the Y direction (second direction).

[0474] [Modifications of First Chip and Second Chip] In each embodiment, the configuration of the first chip 60 may be changed to the first chip 60 shown in Fig. 53 and Fig. 54. The first chip 60 shown in Fig. 53 and Fig. 54 has a larger ratio of the length in the longitudinal direction to the size in the lateral direction of the first chip 60 than the first chip 60 of the first embodiment.

[0475] 53 , the front-side outer periphery guard ring 101 is formed in an annular shape so as to go around the outer periphery of the first chip 60. In plan view, the portion of the front-side outer periphery guard ring 101 that is adjacent to the second chip side surface 64 in the X direction and extends in the Y direction is connected to the front-side guard ring 115.

[0476] As shown in Figures 53 and 54, the configurations of the first transformer 111 and the second transformer 112 in the insulating transformer region 110 are the same as the configurations of the first transformer 111 and the second transformer 112 in the first embodiment.

[0477] The circuit region 120 includes a plurality of functional units and a plurality of circuit elements of the first chip 60. The functional units and the circuit elements are similar to those of the circuit region 120 of the first embodiment. As shown in FIG. 54 , the circuit region 120 includes a first circuit unit CR1, a second circuit unit CR2, and a third circuit unit CR3. MOSFETs, for example, are formed in the first circuit unit CR1 and the second circuit unit CR2. In one example, the first circuit unit CR1 includes the first transmission unit 501 and the second transmission unit 502 of FIG. 9 , and the second circuit unit CR2 includes the logic unit 503, the UVLO unit 505, the LDO unit 504, and the delay unit 506 of FIG. 9 . A protection element, for example, is formed in the third circuit unit CR3.

[0478] In the fifth embodiment, the step portion 139 of the first chip 60 is not limited to being provided around the entire periphery of the substrate 130 in a plan view. The step portion 139 may be provided partially on the first to fourth substrate side surfaces 133 to 136 of the substrate 130.

[0479] In the fifth embodiment, the step portion 239 of the second chip 70 is not limited to being provided around the entire periphery of the substrate 230 in a plan view. The step portion 239 may be provided partially on the first to fourth substrate side surfaces 233 to 236 of the substrate 230.

[0480] In the fifth embodiment, the step portion 339 of the third chip 80 is not limited to being provided around the entire periphery of the substrate 330 in a plan view. The step portion 339 may be provided partially on the first to fourth substrate side surfaces 333 to 336 of the substrate 330.

[0481] In the fifth embodiment, one or two of the step portion 139 of the first chip 60, the step portion 239 of the second chip 70, and the step portion 339 of the third chip 80 may be omitted. That is, in the sixth embodiment, it is sufficient that a step portion is provided in at least one of the substrate 130 of the first chip 60, the substrate 230 of the second chip 70, and the substrate 330 of the third chip 80.

[0482] In each embodiment, a signal is transmitted from the first chip 60 to the second chip 70 and the third chip 80. However, this is not limiting. For example, a signal may be transmitted from the second chip 70 to the first chip 60. Alternatively, a signal may be transmitted from the first chip 60 to the second chip 70, and from the second chip 70 to the first chip 60. Alternatively, a signal may be transmitted from the third chip 80 to the first chip 60. Alternatively, a signal may be transmitted from the first chip 60 to the third chip 80, and from the third chip 80 to the first chip 60. In short, it is sufficient that the second chip 70 is configured to receive a signal from the first chip 60 and / or transmit a signal to the first chip 60. Also, it is sufficient that the third chip 80 is configured to receive a signal from the first chip 60 and / or transmit a signal to the first chip 60.

[0483] [Modifications to Wires] In each embodiment, the arrangement of the inter-chip wires WA in a plan view can be changed as desired. In one example, the three inter-chip wires WA may be formed such that the spacing between adjacent inter-chip wires WA increases, for example, from the first chip 60 toward the second chip 70 in a plan view. In another example, the three inter-chip wires WA may be formed such that the spacing between adjacent inter-chip wires WA increases, for example, from the first chip 60 toward the third chip 80 in a plan view.

[0484] In the first embodiment, when the surface roughness Rz of each of the sealing surface 91, sealing back surface 92, and first to fourth sealing side surfaces 93 to 96 of the sealing resin 90 is 8 μm or more, the material constituting the inter-chip wire WA is not limited to gold and can be changed as desired.

[0485] In the first embodiment, when the plating layer 25 is not formed on the end portion of the internal terminal surface 21 of the first internal terminal portion 12B to 17B of the first terminal 12 to 17 near the tip surface 24 and the sealing resin 90 is in contact with the internal terminal surface 21, the material constituting the inter-chip wire WA is not limited to gold and can be changed as desired.

[0486] In the first embodiment, when the plating layer 25 is not formed on the end portion of the internal terminal surface 21 of the second internal terminal portion 42B, 43B of the second terminal 42, 43 near the tip surface 24 and the sealing resin 90 is in contact with the end portion, the material constituting the inter-chip wire WA is not limited to gold and can be changed as desired.

[0487] In the first embodiment, when the plating layer 25 is not formed on the end portion of the internal terminal surface 21 of the third internal terminal portion 45B, 46B of the third terminal 45, 46 near the tip surface 24 and the sealing resin 90 is in contact with the end portion, the material constituting the inter-chip wire WA is not limited to gold and can be changed as desired.

[0488] In the second to ninth embodiments, the material of the inter-chip wires WA is not limited to gold and can be changed as desired. In each embodiment, the first terminal wires WB are not limited to copper or aluminum and can be changed as desired. Furthermore, if the first terminal wires WB are copper wires, the palladium coating on the surface of the copper wires may be omitted. Note that the first die pad wires WC, second terminal wires WD, second die pad wires WE, third terminal wires WF, and third die pad wires WG can also be changed in the same manner.

[0489] In each embodiment, the configuration of the second bond portion of each of the first die pad wires WC, the second die pad wires WE, and the third die pad wires WG can be changed as desired. In one example, as shown in FIG. 55 , a security bond WC1 may be formed on each of the second bond portions of the multiple first die pad wires WC. As shown in FIG. 56 , a security bond WE1 may be formed on each of the second bond portions of the multiple second die pad wires WE. A security bond WG1 may be formed on each of the second bond portions of the multiple third die pad wires WG. Note that the configuration of each of the security bonds WC1, WE1, and WG1 is the same as the configuration of the security bond WB1 of the first terminal wire WB (see FIG. 22 ), for example.

[0490] In each embodiment, the number of first die pad wires WC can be changed arbitrarily. The number of second die pad wires WE can be changed arbitrarily. The number of third die pad wires WG can be changed arbitrarily.

[0491] In the first, second, and fourth to ninth embodiments, the configuration of the second bond portion of each of the first terminal wires WB, second terminal wires WD, and third terminal wires WF can be changed as desired. In one example, a security bond may be formed in at least one second bond portion of each of the first terminal wires WB, second terminal wires WD, and third terminal wires WF. The configuration of the security bond is the same as the configuration of the security bond WB1 of the first terminal wire WB (see FIG. 22 ), for example.

[0492] In the third embodiment, among the multiple first terminal wires WB, the first specified wires having the security bond WB1 formed thereon and the second specified wires having no security bond WB1 formed thereon can be arbitrarily changed. For example, the security bond WB1 may be formed on the second bond portion of the first terminal wires WB joined to the first internal terminal portions 12B, 13B, 15B, and 17B, and the security bond WB1 may not be formed on the second bond portion of the first terminal wires WB joined to the first internal terminal portions 14B and 16B. In other words, the first terminal wires WB joined to the first internal terminal portions 12B, 13B, 15B, and 17B may be the first specified wires, and the first terminal wires WB joined to the first internal terminal portions 14B and 16B may be the second specified wires. In this way, in the third embodiment, the multiple first terminal wires WB may include first specified wires on which the security bond WB1 is formed and second specified wires on which the security bond WB1 is not formed.

[0493] In the third embodiment, the plurality of second terminal wires WD may include a third specified wire having a security bond formed at its second bond portion and a fourth specified wire having no security bond formed at its second bond portion. For example, a security bond is formed at the second bond portion of the second terminal wire WD joined to the second internal terminal portion 42B, and no security bond is formed at the second bond portion of the second terminal wire WD joined to the second internal terminal portion 43B.

[0494] In the third embodiment, the plurality of third terminal wires WF may include a fifth specified wire having a security bond formed at the second bond portion and a sixth specified wire having no security bond formed at the second bond portion. In one example, a security bond is formed at the second bond portion of the third terminal wire WF joined to the third internal terminal portion 45B, and no security bond is formed at the second bond portion of the third terminal wire WF joined to the third internal terminal portion 46B.

[0495] In the first, second, and fourth to ninth embodiments, a security bond may be formed on the second bond portion of each of the first terminal wires WB, second terminal wires WD, third terminal wires WF, first die pad wires WC, second die pad wires WE, and third die pad wires WG.

[0496] [Modifications to Sealing Resin] In each embodiment, the surface roughness Rz of each of the sealing front surface 91, sealing rear surface 92, and first to fourth sealing side surfaces 93 to 96 of the sealing resin 90 may be less than 8 μm.

[0497] In each embodiment, it is possible to change the concentration of sulfur added to the sealing resin 90. For example, the concentration of sulfur added to the sealing resin 90 may be greater than 300 μg / g.

[0498] [Application Example of Signal Transmission Device] The signal transmission device 10 of each embodiment can be applied to an insulated gate driver that performs switching operations on power semiconductor elements such as insulated gate bipolar transistors (IGBTs) that control the drive of a motor. Such an insulated gate driver can be applied to an inverter device for an electric vehicle or a hybrid vehicle. In this case, the power supply voltage supplied to the first chip 60 of the signal transmission device 10 is 5 V or 3.3 V relative to the ground potential. Meanwhile, a voltage of, for example, 600 V or more is transiently applied to the second chip 70 compared to the ground potential of the first chip 60. More specifically, a motor driver circuit in an inverter device for a hybrid vehicle or the like typically uses a half-bridge circuit in which a low-side switching element and a high-side switching element are connected in a totem-pole configuration.

[0499] The term "on" used in this disclosure includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Therefore, the expression "A is formed on B" is intended to mean that, although in each of the above embodiments, A may be in contact with B and disposed directly on B, as a modified example, A may be disposed above B without contacting B. In other words, the term "on" does not exclude a structure in which another member is formed between A and B.

[0500] The statement "at least one of A and B" in this specification should be understood to mean "A only, or B only, or both A and B." The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to the present disclosure are not limited to "up" and "down" in the Z direction described in this specification being "up" and "down" in the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0501] <Supplementary Notes> The technical ideas that can be understood from this disclosure are described below. Note that, for the sake of aiding understanding and not intending to be limiting, the corresponding reference numerals in the above embodiment are shown in parentheses for the configurations described in the Supplementary Notes. The reference numerals are shown as examples to aid understanding, and the components described with each reference numeral should not be limited to the components indicated by the reference numerals.

[0502] [Appendix A1] A first chip (60) including an isolation transformer (111, 112); a second chip (70) that receives a signal from the first chip (60) and / or transmits a signal to the first chip (60); a third chip (80) that receives a signal from the first chip (60) and / or transmits a signal to the first chip (60); a first die pad (30) on which the first chip (60) is mounted; a second die pad (50A) that is disposed apart from the first die pad (30) in a first direction (X direction) and on which the second chip (70) is mounted; a third die pad (50B) that is disposed apart from the first die pad (30) in the first direction (X direction) and is disposed apart from the second die pad (50A) in a second direction (Y direction) orthogonal to the first direction (X direction) in a plan view and on which the third chip (80) is mounted; a plurality of first terminals (11-17) arranged on the opposite side of the first chip (60) from the second chip (70) and the third chip (80) in the first direction (X direction) in a plan view, and arranged in the second direction (Y direction) in a plan view; a plurality of second terminals (41-43) arranged on the opposite side of the first chip (60) from the second chip (70) in the first direction (X direction) and arranged in the second direction (Y direction); a plurality of third terminals (44-46) arranged on the opposite side of the first chip (60) from the third chip (80) in the first direction (X direction) and arranged in the second direction (Y direction); inter-chip wires (WA) individually connecting the first chip (60) to the second chip (70) and the third chip (80); and first terminal wires (WB) individually and electrically connecting the first chip (60) to the plurality of first terminals (12-17);the first chip (60), the second chip (70), the third chip (80), the first die pad (30), the second die pad (50A), the third die pad (50B), the inter-chip wires (WA), the first terminal wires (WB), the plurality of first terminals (11-17), the plurality of second terminals (41-43), and the plurality of third terminals (44-46); and a sealing resin (90) that seals the first chip (60), the second chip (70), the third chip (80), the first die pad (30), the second die pad (50A), the third die pad (50B), the inter-chip wires (WA), the first terminal wires (WB), the plurality of first terminals (11-17), the plurality of second terminals (41-43), and the plurality of third terminals (44-46), each of the first terminals (11-17), the second terminals (41-43), and the third terminals (44-46) is exposed from the sealing back surface (92); the inter-chip wires (WA) are formed of a material containing gold; The signal transmission device (10) is configured such that the first terminal wire (WB) is made of a material including copper or aluminum.

[0503] [Appendix A2] The signal transmission device according to Appendix A1, wherein the first terminal wire (WB) is a copper wire whose surface is coated with palladium.

[0504] [Appendix A3] The signal transmission device according to Appendix A1 or A2, further comprising a plurality of second terminal wires (WD) that individually connect the second chip (70) and the plurality of second terminals (41 to 43), wherein the second terminal wires (WD) are formed from a material containing copper or aluminum.

[0505] [Appendix A4] The signal transmission device according to any one of Appendices A1 to A3, further comprising a first die pad wire (WC) connecting the first chip (60) and the first die pad (30), wherein the first die pad wire (WC) is formed of a material containing copper or aluminum.

[0506] [Appendix A5] The signal transmission device according to any one of Appendices A1 to A4, further comprising a second die pad wire (WE) connecting the second chip (70) and the second die pad (50A), wherein the second die pad wire (WE) is formed of a material containing copper or aluminum.

[0507] [Appendix A6] The signal transmission device according to Appendix A4, wherein the first die pad wire (WC) is a bonding wire, and a security bond (WC1) is formed at a joint between the first die pad wire (WC) and the first die pad (30).

[0508] [Appendix A7] The signal transmission device according to Appendix A5, wherein the second die pad wire (WE) is a bonding wire, and a security bond (WE1) is formed at a joint between the second die pad wire (WE) and the second die pad (50A).

[0509] [Appendix A8] The signal transmission device according to any one of Appendices A1 to A7, wherein the first terminals (12 to 17) include first internal terminal portions (12B to 17B) that are arranged apart from the first die pad (30) and to which the first terminal wires (WB) are connected, and the first internal terminal portions (12B to 17B) include side surfaces that intersect with the first terminal wires (WB) that are connected to the first internal terminal portions (12B to 17B) in a planar view, and the side surfaces face the first die pad (30) in a planar view.

[0510] [Appendix A9] The signal transmission device according to any one of Appendices A1 to A8, wherein the shortest distance between the plurality of second terminals (41 to 43) and the plurality of third terminals (44 to 46) is greater than the distance between adjacent second terminals among the plurality of second terminals (41 to 43) in the second direction (Y direction).

[0511] [Appendix A10] The signal transmission device according to any one of Appendices A1 to A7, wherein the plurality of first terminals (12 to 17) include a plurality of first internal terminal portions (12B to 17B) to which the first terminal wires (WB) are connected, and each of the plurality of first internal terminal portions (12B to 17B) is disposed at a distance from the first die pad (30), and the plurality of first terminal wires (WB) include: a first specified wire that does not have a security bond formed at a joint portion with the first internal terminal portion (12B, 17B), and a second specified wire that has a security bond formed at a joint portion with the first internal terminal portion (13B to 16B).

[0512] [Appendix A11] The signal transmission device according to any one of Appendices A1 to A10, wherein the first chip (60) comprises: an element insulating layer (150); a first resin layer (191) provided on the element insulating layer; and a second resin layer (192) provided on the first resin layer, and the isolation transformer (111, 112) comprises: front side coils (111A to 114A) arranged on the first resin layer (191) and covered by the second resin layer (192), and back side coils (111B to 114B) arranged opposite the front side coils (111A to 114A) in the thickness direction (Z direction) of the element insulating layer (150) and embedded in the element insulating layer (150).

[0513] [Appendix A12] The signal transmission device according to any one of Appendices A1 to A10, wherein the first chip (60) comprises: an element insulating layer (150); a passivation film (161) formed on the element insulating layer (150) so as to cover the element insulating layer (150); and a low dielectric layer (193) formed on the surface of the passivation film (161) and having a relative dielectric constant lower than that of the passivation film (161), and the sealing resin (90) covers the low dielectric layer (193).

[0514] [Appendix A13] The signal transmission device according to any one of Appendices A1 to A12, wherein the isolation transformer (111, 112) includes front-side coils (111A to 114A) arranged closer to the chip front surface (61) of the first chip (60), and back-side coils (111B to 114B) arranged opposite the front-side coils (111A to 114A), wherein the front-side coils (111A to 114A) have a coil front surface (171), a coil back surface (172) opposite the coil front surface (171), and a coil side surface (173) connecting the coil front surface (171) and the coil back surface (172), and a curved surface is formed between the coil front surface (171) and the coil side surface (173).

[0515] [Appendix A14] The first chip (60) comprises: a flat substrate (130) mounted on the first die pad (30); and an element insulating layer (150) formed on the substrate (130) and having at least a part of the isolation transformer (111, 112) provided thereon, wherein the substrate (130) comprises: a substrate back surface (132) facing the first die pad (30); a substrate front surface (131) opposite the substrate back surface (132); substrate side surfaces (133-136) connecting the substrate back surface (132) and the substrate front surface (131); a first portion (137) including the substrate back surface (132); and a second portion (138) provided on the first portion (137) and including the substrate front surface (131). A step portion (139) formed so that the second portion (138) is positioned inside the substrate (130) relative to the first portion (137). The signal transmission device according to any one of Appendices A1 to A13.

[0516] [Appendix A15] The first die pad (30) has: a first tip surface (31) facing the second die pad (50A) in the first direction (X direction) in a plan view; a first base end surface (32) opposite the first tip surface (31) in a plan view; a first side surface (33) and a second side surface (34) constituting both side surfaces in the second direction (Y direction); a first tip-side curved surface (35A) formed between the first tip surface (31) and the first side surface (33); a second tip-side curved surface (35B) formed between the first tip surface (31) and the second side surface (34); and a base-side curved surface (36) formed between the first base end surface (32) and the first side surface (33), The signal transmission device according to any one of Appendixes A1 to A14, wherein, in a plan view, the arc lengths of both the first distal curved surface (35A) and the second distal curved surface (35B) are longer than the arc length of the base curved surface (36).

[0517] [Appendix A16] The first terminals (12 to 17) include first internal terminal portions (12B to 17B) that are disposed apart from the first die pad (30) and to which the first terminal wires (WB) are connected, and each of the plurality of first internal terminal portions (12B to 17B) has an internal terminal surface (21) to which the first terminal wires (WB) are joined, an internal terminal back surface (22) facing the opposite side to the internal terminal surface (21), and an internal terminal side surface (23) that connects the internal terminal surface (21) and the internal terminal back surface (22), the internal terminal side surface (23) includes a tip surface (24) that faces the first die pad (30), a plating layer (25) is formed on the internal terminal surface (21), and an end of the internal terminal surface (21) on the tip surface (24) side is not formed with a plating layer (25) and is in contact with the sealing resin (90). A signal transmission device according to any one of appendices A1 to A15.

[0518] [Appendix A17] The signal transmission device according to any one of Appendices A1 to A16, wherein the outer surfaces (91 to 96) of the sealing resin (90) are formed so as to have a surface roughness Rz of 8 μm or more.

[0519] [Appendix A18] The signal transmission device according to Appendix A3, wherein the second terminal wire (WD) is a copper wire having a surface coated with palladium.

[0520] [Appendix A19] The signal transmission device according to Appendix A1 or A2, further comprising a plurality of third terminal wires (WF) that individually connect the third chip (80) and the plurality of third terminals (44 to 46), wherein the third terminal wires (WF) are formed of a material containing copper or aluminum.

[0521] [Appendix A20] The signal transmission device according to Appendix A19, wherein the third terminal wire (WF) is a copper wire hav...

Claims

1. A first chip including an isolation transformer; A second chip configured to receive at least one of signals from the first chip and transmit signals to the first chip; A third chip configured to receive at least one of signals from the first chip and transmit signals to the first chip; A first die pad on which the first chip is mounted; A second die pad spaced apart from the first die pad in a first direction and on which the second chip is mounted; A third die pad spaced apart from the first die pad in the first direction and spaced apart from the second die pad in a second direction orthogonal to the first direction in a plan view, on which the third chip is mounted; A plurality of first terminals arranged in the second direction and disposed on the opposite side of the first chip from the second chip and the third chip in the first direction in a plan view; A plurality of second terminals arranged in the second direction and disposed on the opposite side of the second chip from the first chip in the first direction; A plurality of third terminals arranged in the second direction and disposed on the opposite side of the third chip from the first chip in the first direction; Inter-chip wires individually connecting the first chip to the second chip and the third chip; First terminal wires individually and electrically connecting the first chip to the plurality of first terminals; A sealing resin having a sealing surface and a sealing back surface facing opposite sides of each other in a third direction orthogonal to both the first direction and the second direction, for sealing the first chip, the second chip, the third chip, the first die pad, the second die pad, the third die pad, the inter-chip wires, the first terminal wires, the plurality of first terminals, the plurality of second terminals, and the plurality of third terminals; Each of the first terminals, each of the second terminals, and each of the third terminals is exposed from the sealing back surface; The inter-chip wires are formed of a material containing gold; The first terminal wires are formed of a material containing copper or aluminum. A signal transmission device.

2. The first terminal wires are configured such that the surface of the copper wires is coated with palladium. The signal transmission device according to Claim 1.

3. The signal transmission device further includes a plurality of second terminal wires individually connecting the second chip to the plurality of second terminals. The wire for the second terminal is formed of a material containing copper or aluminum. The signal transmission device according to claim 1.

4. The signal transmission device further includes a wire for the first die pad that connects the first chip and the first die pad. The wire for the first die pad is formed of a material containing copper or aluminum. The signal transmission device according to claim 1.

5. The signal transmission device further includes a wire for the second die pad that connects the second chip and the second die pad. The wire for the second die pad is formed of a material containing copper or aluminum. The signal transmission device according to claim 1.

6. The wire for the first die pad is a bonding wire. A security bond is formed at the joint of the wire for the first die pad with the first die pad. The signal transmission device according to claim 4.

7. The wire for the second die pad is a bonding wire. A security bond is formed at the joint of the wire for the second die pad with the second die pad. The signal transmission device according to claim 5.

8. The first terminal is disposed at a distance from the first die pad and includes a first internal terminal portion to which the wire for the first terminal is connected. The first internal terminal portion includes a side surface that intersects with the wire for the first terminal connected to the first internal terminal portion in a plan view. The side surface faces the first die pad in a plan view. The signal transmission device according to claim 1.

9. The shortest distance between the plurality of second terminals and the plurality of third terminals is greater than the distance between the second terminals adjacent to each other in the second direction among the plurality of second terminals. The signal transmission device according to claim 1.

10. The plurality of first terminals includes first internal terminal portions to which the wires for the first terminals are connected. Each of the plurality of first internal terminal portions is disposed at a distance from the first die pad. The plurality of wires for the first terminals include a first specific wire in which no security bond is formed at the joint with the first internal terminal portion, and a second specific wire in which a security bond is formed at the joint with the first internal terminal portion. The signal transmission device according to claim 1.

11. The first chip includes an element insulating layer, a first resin layer provided on the element insulating layer, and a second resin layer provided on the first resin layer. The first chip is provided with these layers. The insulating transformer A surface-side coil disposed on the first resin layer and covered by the second resin layer, A back-side coil disposed opposite to the surface-side coil in the thickness direction of the element insulating layer and embedded in the element insulating layer, including The signal transmission device according to any one of claims 1 to 10.

12. The first chip includes An element insulating layer, A passivation film formed on the element insulating layer so as to cover the element insulating layer, A low dielectric layer formed on the surface of the passivation film and having a lower relative permittivity than the passivation film, and includes The encapsulating resin covers the low dielectric layer The signal transmission device according to any one of claims 1 to 10.

13. The insulating transformer includes A surface-side coil disposed closer to the chip surface of the first chip, A back-side coil disposed opposite to the surface-side coil, including The surface-side coil has A coil surface, A coil back surface opposite to the coil surface, A coil side surface connecting the coil surface and the coil back surface, and A curved surface is formed between the coil surface and the coil side surface. The signal transmission device according to any one of claims 1 to 10.

14. The first chip includes A flat substrate mounted on the first die pad, An element insulating layer formed on the substrate and provided with at least a part of the insulating transformer, and includes The substrate has A substrate back surface facing the first die pad, A substrate surface opposite to the substrate back surface, A substrate side surface connecting the substrate back surface and the substrate surface, A first portion including the substrate back surface, A second portion provided on the first portion and including the substrate surface, and a step portion formed such that the second portion is located inside the substrate with respect to the first portion. The signal transmission device according to any one of claims 1 to 10.

15. The first die pad has A first front end surface facing the second die pad in a plan view in the first direction, A first base end surface opposite to the first front end surface in a plan view, A first side surface and a second side surface constituting both side surfaces in the second direction, A first front end side curved surface formed between the first front end surface and the first side surface, A second front end side curved surface formed between the first front end surface and the second side surface, A base end side curved surface formed between the first base end surface and the first side surface, and In a plan view, the arc lengths of both the first tip-side curved surface and the second tip-side curved surface are longer than the arc length of the base-end side curved surface. The signal transmission device according to any one of claims 1 to 10.

16. The first terminal is disposed apart from the first die pad and includes a first internal terminal portion to which the first terminal wire is connected. Each of the plurality of first internal terminal portions has an internal terminal surface to which the first terminal wire is joined, an internal terminal back surface facing the side opposite to the internal terminal surface, and an internal terminal side surface connecting the internal terminal surface and the internal terminal back surface, and the internal terminal side surface includes a front end surface facing the first die pad. A plating layer is formed on the internal terminal surface. No plating layer is formed at an end portion on the front end surface side of the internal terminal surface, and it is in contact with the encapsulating resin. The signal transmission device according to any one of claims 1 to 10.

17. The outer surface of the encapsulating resin is formed such that the surface roughness Rz is 8 μm or more. The signal transmission device according to any one of claims 1 to 10.