Wiring board and circuit structure obtained using same

Abstract

A wiring board according to the present disclosure includes a first insulating layer, which has a first surface, a land conductor located on the first surface, a second insulating layer, which covers the first surface and the land conductor and has a second surface on the reverse side from the first insulating layer, a via hole piercing from the second surface of the second insulating layer to the land conductor, and a via-hole conductor which is located inside the via hole and is in contact with the land conductor. The via-hole conductor comprises a base metal layer located on the surface of the land conductor, on the wall surface of the via hole, and at the second surface and an electroplating layer located on the base metal layer. At least some of the base metal layer has a plurality of voids therein.

Description

Wiring board and mounting structure using same

[0001] The present disclosure relates to a wiring board and a mounting structure using the same.

[0002] In wiring boards, as shown in Patent Document 1, vias (via holes) formed in an insulating layer are filled with conductors (via hole conductors) to electrically connect conductor layers located on the top and bottom surfaces of an insulating layer. The via hole conductors are usually connected to via lands at the bottom of the vias. Due to the difference in thermal expansion coefficient between the via hole conductors, such as copper, and the resin forming the insulating layer, stress tends to concentrate at the connection between the via bottom and the via land. Therefore, for example, when exposed to high temperature conditions, the via hole conductors are prone to breakage.

[0003] Japanese Patent Application Laid-Open No. 2007-27341

[0004] The wiring board according to the present disclosure includes a first insulating layer having a first surface, land conductors located on the first surface, a second insulating layer covering the first surface and the land conductors and having a second surface opposite the first insulating layer, via holes penetrating from the second surface of the second insulating layer to the land conductors, and via hole conductors located in the via holes and in contact with the land conductors. The via hole conductors have an underlying metal layer located on the surface of the land conductors, the wall surfaces of the via holes, and the second surface, and an electrolytic plating layer located on the underlying metal layer. A plurality of voids are located in at least a portion of the underlying metal layer.

[0005] Furthermore, a mounting structure according to the present disclosure includes the above-described wiring board and an electronic component located in a mounting area of ​​the wiring board.

[0006] FIG. 1 is an explanatory diagram for explaining a wiring board according to an embodiment of the present disclosure. FIG. 2 is an enlarged cross-sectional view for explaining region X shown in FIG. 1. FIG. 3 is an enlarged cross-sectional view for explaining region Y shown in FIG. 2. FIG. 4 is an explanatory diagram for explaining an example of a method for forming a via-hole conductor in a wiring board according to an embodiment of the present disclosure. FIG. 5 is an explanatory diagram for explaining an example of a method for forming a via-hole conductor in a wiring board according to another embodiment of the present disclosure. FIG. 6 is an explanatory diagram for explaining an example of a method for forming a via-hole conductor in a wiring board according to another embodiment of the present disclosure.

[0007] As described above, stress tends to concentrate at the connection between the via bottom and the via land due to the difference in thermal expansion coefficient between the via-hole conductor and the resin forming the insulating layer. Therefore, for example, when exposed to high temperature conditions, the via-hole conductor is prone to fracture. Therefore, there is a demand for a wiring board with excellent connection reliability of the via-hole conductor and a mounting structure using the same.

[0008] The wiring board and mounting structure according to the present disclosure have the configurations described in the section on means for solving the above problems, and thus have excellent connection reliability of via-hole conductors.

[0009] A wiring board according to an embodiment of the present disclosure will be described with reference to Figures 1 and 2. Figure 1 is an explanatory diagram for describing a wiring board 1 according to an embodiment of the present disclosure. As shown in Figure 1, the wiring board 1 according to the embodiment includes an insulating layer 2, a conductor layer 3, and a solder resist 4.

[0010] The insulating layer 2 includes a core insulating layer 20, a first insulating layer 21, and a second insulating layer 22. The core insulating layer 20 is not particularly limited as long as it is made of an insulating material. Examples of insulating materials include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Two or more of these resins may be mixed together. The thickness of the core insulating layer 20 is not particularly limited, and is, for example, 20 μm or more and 10 mm or less. The core insulating layer 20 is not necessarily required, and is not used in, for example, a substrate known as a coreless substrate or a 2.3D substrate. For example, the thickness of the core insulating layer 20 may exceed 10 mm, as in a motherboard.

[0011] The core insulating layer 20 may contain a reinforcing material. Examples of reinforcing materials include insulating fabric materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more reinforcing materials may be used in combination. Furthermore, the core insulating layer 20 may contain dispersed inorganic insulating fillers such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide.

[0012] A through-hole conductor 20a is located in the core insulating layer 20 to electrically connect the top and bottom surfaces of the core insulating layer 20. The through-hole conductor 20a is located in a through-hole that penetrates from the top surface to the bottom surface of the core insulating layer 20. The through-hole conductor 20a is formed by metal plating such as copper plating. The through-hole conductor 20a is connected to the conductor layers 3 formed on both surfaces of the core insulating layer 20. The through-hole conductor 20a may be located only on the inner wall surface of the through-hole, or may fill the through-hole.

[0013] The conductor layer 3 is not limited as long as it is a conductor such as a metal such as copper, nickel, chromium, or an alloy thereof (e.g., nichrome). Specifically, the conductor layer 3 is formed of a metal foil such as copper foil, a metal plating such as copper plating, or a sputtered metal layer. The thickness of the conductor layer 3 is not particularly limited, and is, for example, 1 μm or more and 30 μm or less. The thickness of the conductor layer 3 tends to become thinner as the wiring becomes finer.

[0014] Build-up layers, in which conductor layers 3 and insulating layers 2 are alternately stacked, are located on both sides of the core insulating layer 20. The build-up layers have a structure in which conductor layers 3 and insulating layers 2 are alternately stacked. In the wiring board 1 according to one embodiment, when focusing on any two contacting insulating layers 2 among the insulating layers 2 constituting the build-up layer, the insulating layer 2 closer to the core insulating layer 20 corresponds to the first insulating layer 21, and the other insulating layer 2 corresponds to the second insulating layer 22.

[0015] Specifically, when the build-up layer has three insulating layers 2, focusing on the insulating layer 2 (first insulating layer 2) located on the surface of the core insulating layer 20 and the insulating layer 2 (second insulating layer 2) located on the surface of the first insulating layer 2, the first insulating layer 2 closer to the core insulating layer 20 corresponds to the first insulating layer 21, and the second insulating layer 2 corresponds to the second insulating layer 22. Focusing on the second insulating layer 2 and the insulating layer 2 (third insulating layer 2) located on the surface of the second insulating layer 2, the second insulating layer 2 closer to the core insulating layer 20 corresponds to the first insulating layer 21, and the third insulating layer 2 corresponds to the second insulating layer 22.

[0016] The insulating layers 2 (first insulating layer 21 and second insulating layer 22) constituting the build-up layers are not particularly limited as long as they are made of an insulating material, similar to the core insulating layer 20. As mentioned above, examples of the insulating layers include epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Two or more of these resins may be mixed together. The insulating layers 2 constituting the build-up layers may be made of the same resin or different resins. The insulating layers 2 constituting the build-up layers and the core insulating layer 20 may be made of the same resin or different resins. The thickness of the insulating layers 2 constituting the build-up layers is not particularly limited, and is, for example, 1 μm or more and 60 μm or less. The insulating layers 2 constituting the build-up layers may have the same thickness or different thicknesses.

[0017] The insulating layer 2 constituting the build-up layer may contain a reinforcing material. Examples of reinforcing materials include insulating fabric materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more reinforcing materials may be used in combination. Furthermore, the insulating layer 2 constituting the build-up layer may contain dispersed inorganic insulating fillers such as silica, alumina, aluminum oxide, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide. Generally, inorganic insulating fillers such as silica and alumina that are chemically resistant to corrosion by neither acid nor alkali are often used for substrates intended for fine wiring. This reduces insulation degradation such as ion migration under high temperature and humidity conditions or under applied voltage.

[0018] 1, a solder resist 4 may be positioned on the surface of the build-up layer. The solder resist 4 is made of a resin, such as an acrylic-modified epoxy resin. The solder resist 4 has openings for electrically connecting the conductor layer 3 to the electrodes of the element via solder 5. Examples of the element include a semiconductor integrated circuit element and an optoelectronic element.

[0019] Via-hole conductors 3b are formed in the insulating layers 2 constituting the build-up layers to electrically connect the upper and lower surfaces of the insulating layers 2 constituting the build-up layers. The via-hole conductors 3b are located in via holes 31 formed to penetrate the insulating layers 2 constituting the build-up layers. That is, as shown in FIG. 2, the via-hole conductors 3b are located in the via holes 31 that penetrate from the second surface 222 of the second insulating layer 22 to the land conductors 3a. FIG. 2 is an enlarged cross-sectional view illustrating region X shown in FIG. 1. The second insulating layer 22 covers the first surface 211 of the first insulating layer 21 and the land conductors 3a located on the first surface 211. The second surface 222 of the second insulating layer 22 is the surface opposite to the first insulating layer 21.

[0020] 2, the via-hole conductor 3b is filled in a via hole 31 formed in the second insulating layer 22, and its bottom (the bottom surface closer to the first surface 211) is in contact with the land conductor 3a. The land conductor 3a and the via-hole conductor 3b are part of the conductor layer 3 and are made of a metal such as copper.

[0021] The via-hole conductor 3b has an underlying metal layer located on the surface of the land conductor 3a, the wall surface of the via hole 31, and the second surface 222, and an electrolytic plating layer 3b2 located on the underlying metal layer. In other words, the underlying metal layer is located between the surface of the land conductor 3a, the wall surface of the via hole 31, the second surface 222, and the electrolytic plating layer 3b2. This allows the electrolytic plating layer 3b2 to firmly adhere to the surface of the land conductor 3a, the wall surface of the via hole 31, and the second surface 222 via the underlying metal layer.

[0022] The base metal layer is formed of a metal such as copper, nickel, chromium, or an alloy thereof (e.g., nichrome). The base metal layer may be an electroless plating layer 3b1 or a sputtered metal layer 8. When the base metal layer is a sputtered metal layer 8, the base metal layer may have a multilayer structure in which a sputtered metal layer 8 made of nichrome is positioned on a sputtered metal layer 8 made of copper, for example.

[0023] FIG. 3 shows an example in which the base metal layer is an electroless plated layer 3b1. As shown in FIG. 3, the via hole conductor 3b has an electroless plated layer 3b1 and an electrolytic plated layer 3b2. FIG. 3 is an enlarged cross-sectional view for illustrating region Y shown in FIG. 2. The electroless plated layer 3b1 is located on the surface of the land conductor 3a, the wall surface of the via hole 31, and the second surface 222. The thickness of the electroless plated layer 3b1 is not particularly limited and is, for example, 100 nm or more and 3 μm or less. The electrolytic plated layer 3b2 is located on the electroless plated layer 3b1. The electroless plated layer 3b1 and the electrolytic plated layer 3b2 are formed of a metal such as copper.

[0024] 3, in the wiring board 1 according to one embodiment, a plurality of voids 32 are located in at least a portion of the electroless plated layer 3b1. Due to the presence of such voids 32, the wiring board 1 according to one embodiment reduces stress applied to the bottom of the via-hole conductor 3b. As a result, breakage of the via-hole conductor 3b is reduced, and the connection reliability of the via-hole conductor 3b is improved.

[0025] It is preferable that the voids 32 are irregularly dispersed rather than regularly arranged. When the voids 32 are irregularly dispersed, stresses applied in various directions to the bottom of the via-hole conductor 3b are more easily alleviated. The size of the voids 32 may be, for example, 1 nm to 300 nm, or 1 nm to 100 nm, at the largest diameter portion.

[0026] 2, the land conductor 3a may have an inclined portion on its periphery that is inclined with respect to the first surface 211 of the first insulating layer 21. The thickness of the inclined portion may increase from the periphery of the land conductor 3a to the side surface of the via-hole conductor 3b in a cross-sectional view. For example, in a cross section including the center of the land conductor 3a in a plan view, the thickness increases from the periphery of the land conductor 3a to the side surface of the via-hole conductor 3b. With this configuration, the stress applied from the insulating layer 2 to the via-hole conductor 3b can be further dispersed.

[0027] 2, the land conductor 3a may have a curved recess 3a1 in cross section. The via-hole conductor 3b may be in contact with the recess 3a1. The recess 3a1 is, for example, recessed from the second surface 222 side toward the first surface 211 side. With this configuration, the stress applied to the via-hole conductor 3b can be further reduced compared to when the via-hole conductor 3b and the land conductor 3a are in contact with each other in a planar manner.

[0028] The via-hole conductor 3b may have a constricted portion 3bK whose width in the horizontal direction along the first surface 211 is the smallest. The plurality of voids 32 may be located closer to the land conductor 3a than the constricted portion 3bK in the direction perpendicular to the first surface 211, at least in the via-hole conductor 3b. The constricted portion 3bK can be defined as, for example, the portion of the via-hole conductor 3b whose length in the horizontal direction along the first surface 211 is the smallest. With this configuration, the point at which the density of the voids 32 changes can be shifted from the boundary between the constricted portion 3bK, where stress is most concentrated, and the insulating layer 2 (second insulating layer 22). As a result, breakage of the via-hole conductor 3b can be further reduced.

[0029] In the electroless plated layer 3b1, the density of the plurality of voids 32 contained in the first region 3b11 may be greater than the density of the plurality of voids 32 contained in the second region 3b12. The first region 3b11 is a region located between the electrolytic plated layer 3b2 and the land conductor 3a. The second region 3b12 is a region located between the electrolytic plated layer 3b2 and the second insulating layer 22. The density of the plurality of voids 32 contained in the first region 3b11 may be greater than 100% and not more than 150% of the density of the plurality of voids 32 contained in the second region 3b12. This configuration can further reduce the stress applied between the via-hole conductor 3b and the land conductor 3a, which are subject to greater stress.

[0030] For example, the first region 3b11 in the base metal layer has a cross section of 1,000,000 nm ２ As shown in FIG. 3, for example, when the base metal layer is an electroless plated layer 3b1, the thickness of the base metal layer may be 1,000,000 nm. ２ When the underlying metal layer is a sputtered metal layer 8, the thickness of the underlying metal layer is 1,000,000 nm. ２ Each of the voids 32 may contain 1 to 10 voids 32 .

[0031] For example, if the base metal layer has a multilayer structure in which a sputtered metal layer 8 made of nichrome is positioned on a sputtered metal layer 8 made of copper, the buffering effect is enhanced and a more effective stress relief effect is likely to be achieved if the number of voids 32 in the sputtered metal layer 8 made of copper, which has a low Young's modulus, is greater than the number of voids 32 in the sputtered metal layer 8 made of nichrome. Furthermore, if a sputtered layer made of nichrome, which has a higher Young's modulus than copper, is positioned at the bottom of a via, where stress tends to concentrate, the placement of voids 32 provides a significant stress relief effect. Because the sputtered layer at the bottom of the via is formed close to the interface between the electroplated layer 3b2 and the land conductor 3a, the placement of voids 32 provides a significant stress relief effect. The number of voids 32 can be confirmed by photographing and observing the voids using an FE-SEM at a magnification of approximately 35,000 times. To reduce cracks when stress is applied to the wiring board 1, the number of voids 32 may be between one and five.

[0032] The space between the electrolytic plating layer 3b2 and the land conductor 3a is defined, for example, as the space between an imaginary line connecting the electrolytic plating layer 3b2 and the land conductor 3a at the shortest distance parallel to the first surface 211. Similarly, the space between the electrolytic plating layer 3b2 and the second insulating layer 22 is defined, for example, as the space between an imaginary line connecting the electrolytic plating layer 3b2 and the second insulating layer 22 at the shortest distance parallel to the first surface 211.

[0033] Next, one embodiment of a method for forming the via-hole conductor 3b in the via hole 31 will be described with reference to Fig. 4. Fig. 4 is an explanatory diagram for describing one example of a method for forming the via-hole conductor 3b in the wiring board 1 according to an embodiment of the present disclosure.

[0034] First, as shown in FIG. 4A , a land conductor 3a is formed on the first surface 211 of the first insulating layer 21. As described above, the land conductor 3a is part of the conductor layer 3 and is made of a metal such as copper. Next, as shown in FIG. 4B , a via hole 31 is formed in the second insulating layer 22. The via hole 31 is formed so as to penetrate from the second surface 222 of the second insulating layer 22 to the land conductor 3a. The via hole 31 is formed, for example, by laser processing or a photolithography method using a photosensitive insulating resin. A carbon dioxide laser, a YAG laser, or an excimer laser is used for the laser processing. Common photosensitive insulating resins are epoxy or polyimide, but other resins may also be used.

[0035] 4C, after the via hole 31 is formed, a curved recess 3a1 is formed in the surface of the land conductor 3a, which is the bottom of the via hole 31. The recess 3a1 is formed by, for example, etching.

[0036] 4D , an electroless plated layer 3b1 is formed on the second surface 222 of the second insulating layer 22, the inner wall surfaces of the via holes 31, and the bottom surfaces of the via holes 31 (recesses 3a1 of the land conductors 3a). As described above, the electroless plated layer 3b1 is made of a metal such as copper. As described above, the thickness of the electroless plated layer 3b1 is, for example, 100 nm or more and 3 μm or less.

[0037] After the electroless plated layer 3b1 is formed, the electroless plated layer 3b1 is subjected to heat treatment. Specifically, the substrate on which the electroless plated layer 3b1 is formed may be heated to a temperature of, for example, 150°C or higher. The upper limit of the heating temperature is approximately 180°C. The heating time is, for example, 30 minutes or more, and at most approximately 120 minutes. By subjecting the electroless plated layer 3b1 to heat treatment, voids 32 are more likely to be formed in the electroless plated layer 3b1.

[0038] Specifically, when heat treatment is performed at a relatively high temperature of 150°C or higher, hydrogen (derived from the plating solution) present in the electroless plated layer 3b1 aggregates. As a result, minute voids 32 with diameters of 100 nm or less are formed. Furthermore, an oxide film is formed on the surface of the electroless plated layer 3b1, and when copper atoms bond with oxygen atoms, the copper atoms migrate, creating voids. As a result, voids 32 with diameters of 50 nm to 200 nm are formed.

[0039] Next, as shown in FIG. 4E, an electrolytic plated layer 3b2 is formed on the surface of the electroless plated layer 3b1, and the via hole 31 is filled with the electrolytic plated layer 3b2. As described above, the electrolytic plated layer 3b2 is formed of a metal such as copper. Next, the electroless plated layer 3b1 exposed from the electrolytic plated layer 3b2 is removed by flash etching, and then a second heat treatment is performed. The second heat treatment may be performed at a temperature of, for example, 190°C or higher. The upper limit of the heating temperature is approximately 250°C. The heating time is, for example, 20 minutes or more, and at most approximately 120 minutes.

[0040] By performing the second heat treatment, the size and position of the voids 32 can be made more random. Specifically, when the electroless plated layer 3b1 is made of copper, metals other than copper contained as impurities diffuse to form the voids 32. Therefore, the formed voids 32 are dispersed, and the voids 32 can be arranged randomly. In this way, in the wiring board 1 according to one embodiment, the via-hole conductors 3b are formed in the via holes 31 as shown in FIG.

[0041] Next, an embodiment in which the base metal layer is a sputtered metal layer 8 will be described with reference to Figures 5 to 7. Figures 5 to 7 are explanatory diagrams for describing an example of a method for forming via-hole conductors 3b in a wiring board according to another embodiment of the present disclosure. In the wiring board according to the other embodiment, the same components as those in the wiring board 1 according to the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

[0042] In the wiring board 1 according to the above-described embodiment, the base metal layer is an electroless plated layer 3b1. On the other hand, in the wiring board according to another embodiment, as shown in Fig. 7C, the base metal layer is a sputtered metal layer 8. In the wiring board according to the other embodiment, the via-hole conductor 3b is formed, for example, as follows.

[0043] As shown in FIG. 5A , a seed layer 6 is formed on the surface of the first insulating layer 21. In FIG. 5A , the seed layer 6 has a two-layer structure consisting of a first seed layer 61 and a second seed layer 62. First, the first seed layer 61 is formed on the surface of the first insulating layer 21. The method for forming the first seed layer 61 is not limited, and it can be formed, for example, by sputtering. The first seed layer 61 is formed, for example, of at least one metal selected from the group consisting of Group 4 elements, Group 5 elements, Group 6 elements, and Group 10 elements. Specific examples of such metals include nickel, chromium, titanium, tantalum, molybdenum, tungsten, palladium, and alloys containing these metals. The first seed layer 61 may be, for example, a nichrome layer formed by sputtering. The first seed layer 61 may have a thickness of, for example, 0.5 nm to 100 nm.

[0044] Next, a second seed layer 62 is formed on the surface of the first seed layer 61. The method for forming the second seed layer 62 is not limited, and it may be formed by sputtering, for example. The second seed layer 62 is made of copper. The second seed layer 62 may have a thickness of, for example, 100 nm or more and 1000 nm or less.

[0045] Next, as shown in FIG. 5B, a resist 7 is formed on the surface of the seed layer 6. The resist 7 has openings, and as shown in FIG. 5B, an electrolytic plating layer 63 is formed in the openings. The electrolytic plating layer 63 is, for example, an electrolytic copper plating layer. After the electrolytic plating layer 63 is formed, the resist 7 and the seed layer 6 covered with the resist 7 are removed, as shown in FIG. 5C. The resist 7 is stripped using a sodium hydroxide aqueous solution or an amine-based resist stripper.

[0046] If the second seed layer 62 of the seed layer 6 is copper, it is etched with a sulfuric acid-hydrogen peroxide solution mixture, and then the first seed layer 61 is etched with an etching solution suitable for etching the metal of the first seed layer 61. For example, if it is nichrome, it is removed by etching with a mixed aqueous solution of sulfuric acid and hydrochloric acid.

[0047] 5D , depressions 631 are formed on the surface of the electroplated layer 63. The depressions 631 are formed by, for example, annealing at a temperature of 150° C. to 250° C. for 20 minutes to 90 minutes. At this time, the depressions 631 have a diameter of 50 nm to 1000 nm and a depth of 50 nm to 300 nm.

[0048] Next, as shown in Fig. 6A, a soft etching process is performed on the surface of the electrolytic plated layer 63, so that the diameter of the depression 631 is, for example, 10 nm to 500 nm and the depth is 5 nm to 50 nm. After the soft etching process, as shown in Fig. 6B, a silane coupling process is performed on the surface of the electrolytic plated layer 63. Specifically, the surface of the electrolytic plated layer 63 is tin-plated, and then treated with nitric acid to perform the silane coupling process. In this manner, the land conductor 3a is formed on the surface of the first insulating layer 21.

[0049] Next, as shown in Fig. 6C, a second insulating layer 22 is formed on the surface of the first insulating layer 21 so as to cover the land conductors 3a. After forming the second insulating layer 22, as shown in Fig. 6D, via holes 31 are formed so as to penetrate from the second surface 222 of the second insulating layer 22 to the land conductors 3a. After forming the via holes 31, curved recesses 3a1 are formed in the surface of the land conductors 3a, which are the bottoms of the via holes 31. The recesses 3a1 are formed by, for example, etching. At this time, the silane coupling layer and tin plating layer formed on the surface of the land conductors 3a are removed. The amount of etching is adjusted so that the recess depth of the recesses 3a1 is smaller than that in electroless plating.

[0050] 7A , a first sputtered metal layer 81 is formed on the second surface 222 of the second insulating layer 22, the inner wall surface of the via hole 31, and the bottom surface of the via hole 31 (the surface of the land conductor 3 a). The first sputtered metal layer 81 is formed of at least one metal selected from the group consisting of Group 4 elements, Group 5 elements, Group 6 elements, and Group 10 elements. Specific examples of such metals include nickel, chromium, titanium, tantalum, molybdenum, tungsten, palladium, and alloys containing these metals. The first sputtered metal layer 81 may be, for example, a nichrome layer formed by sputtering. The first sputtered metal layer 81 may have a thickness of, for example, 0.5 nm to 100 nm.

[0051] When sputtering is performed on the surface of the land conductor 3a having the depression 631, the entrance of the depression 631 is blocked before the depression 631 is filled with metal. As a result, as shown in FIG. 7A, voids 32 are likely to be formed in the depression 631.

[0052] Next, as shown in FIG. 7B , a second sputtered metal layer 82 is formed on the surface of the first sputtered metal layer 81. The second sputtered metal layer 82 is made of, for example, copper. The second sputtered metal layer 82 may be, for example, a copper layer formed by sputtering. The second sputtered metal layer 82 may have a thickness of, for example, 50 nm or more and 1000 nm or less. The sputtered metal layer 8 may have a thickness of, for example, 50 nm or more and 1100 nm or less.

[0053] When forming the second sputtered metal layer 82, for example, by adjusting the settings of the sputtering device, such as by reducing the amount of oscillation of the magnet of the sputtering device, unevenness is likely to occur in the second sputtered metal layer 82. As a result, as shown in FIG. 7B , voids 32 are also likely to be formed in the second sputtered metal layer 82.

[0054] 7C, an electrolytically plated layer 3b2 is formed on the surface of the second sputtered metal layer 82 (sputtered metal layer 8), and the via hole 31 is filled with the electrolytically plated layer 3b2. As described above, the electrolytically plated layer 3b2 is formed of a metal such as copper. By this procedure, the via-hole conductor 3b is formed in the wiring board according to the other embodiment.

[0055] Next, a mounting structure according to the present disclosure will be described. The mounting structure according to one embodiment includes a wiring board 1 according to one embodiment and an element located on the surface of the wiring board 1. A conductor layer 3 in an opening of a solder resist 4 is connected to an electrode of the element via solder 5. As described above, examples of the element include a semiconductor integrated circuit element and an optoelectronic element. The element may be located on both sides of the wiring board 1, or the element may be located on one surface and, for example, a motherboard may be located on the other surface.

[0056] The wiring board according to the present disclosure is not limited to the wiring board 1 according to the embodiment and the wiring boards according to the other embodiments. In the wiring board 1 according to the embodiment, the insulating layer 2 constituting the build-up layer has a two-layer structure. However, the insulating layer constituting the build-up layer in the wiring board according to the present disclosure is not limited to a two-layer structure and may have a stacked structure of three or more layers.

[0057] In the wiring board 1 according to one embodiment and the wiring boards according to other embodiments, the surface of the land conductor 3 a is inclined toward the periphery in cross section. However, in the wiring board according to the present disclosure, the surface of the land conductor may be substantially parallel to the first surface of the first insulating layer.

[0058] In the wiring board 1 according to one embodiment, the land conductor 3 a has a curved recess 3 a 1 in cross section. However, in the wiring board according to the present disclosure, the land conductor does not have to have a recess, and even if it has a recess, it does not have to have a curved recess shape.

[0059] In wiring boards according to other embodiments, sputtered metal layer 8 is formed of two layers: a first sputtered metal layer 81 and a second sputtered metal layer 82. However, in wiring boards according to the present disclosure, sputtered metal layer 8 may have a single-layer structure or a multi-layer structure.

[0060] Furthermore, the invention according to the present disclosure is not limited to the above-described embodiments, and various modifications and improvements are possible within the scope of the present disclosure as shown in (1) and (12) below.

[0061] (1) A wiring board according to the present disclosure includes a first insulating layer having a first surface, land conductors located on the first surface, a second insulating layer covering the first surface and the land conductors and having a second surface opposite the first insulating layer, via holes penetrating from the second surface of the second insulating layer to the land conductors, and via hole conductors located in the via holes and in contact with the land conductors. The via hole conductors include an underlying metal layer located on the surface of the land conductors, the wall surfaces of the via holes, and the second surface, and an electroplated layer located on the underlying metal layer. A plurality of voids are located in at least a portion of the underlying metal layer.

[0062] The present disclosure further discloses the following embodiments (2) to (11).

[0063] (2) In the wiring board described in (1) above, the base metal layer is an electroless plated layer. (3) In the wiring board described in (1) above, the base metal layer is a sputtered metal layer. (4) In the wiring board described in (3) above, the sputtered metal layer has a multilayer structure. (5) In the wiring board described in any one of (1) to (4) above, the land conductor has a sloped portion on the periphery of the land conductor. The thickness of the sloped portion increases from the periphery of the land conductor to the side surface of the via-hole conductor in a cross-sectional view. (6) In the wiring board described in any one of (1) to (5) above, the land conductor has a curved recess in a cross-sectional view. The via-hole conductor is in contact with the recess. (7) In the wiring board described in any one of (1) to (6) above, the via-hole conductor has a constricted portion whose width in the horizontal direction along the first surface is smallest. The multiple voids are located at least in the via-hole conductor closer to the land conductor than the sloped portion in a direction perpendicular to the first surface. (8) In the wiring board according to any one of (1) to (7), the underlying metal layer includes a first region located between the electroplated layer and the land conductor, and a second region located between the electroplated layer and the second insulating layer. The density of the voids included in the first region is greater than the density of the voids included in the second region. (9) In the wiring board according to (8), the first region has a diameter of 1,000,000 nm when viewed in cross section. ２ (10) In the wiring board according to (9), the base metal layer is an electroless plated layer, and the first region has a thickness of 1,000,000 nm when viewed in cross section. ２ (11) In the wiring board according to (9), the base metal layer is a sputtered metal layer, and the first region has a thickness of 1,000,000 nm when viewed in cross section. ２ Each of the plurality of voids contains 1 to 10 of the voids.

[0064] (12) A mounting structure according to the present disclosure includes the wiring board according to any one of (1) to (11) above, and an electronic component located in a mounting area of ​​the wiring board.

[0065] REFERENCE SIGNS LIST 1 wiring board 2 insulating layer 20 core insulating layer 20a through-hole conductor 21 first insulating layer 211 first surface 22 second insulating layer 222 second surface 3 conductor layer 31 via hole 3a land conductor 3a1 recess 3b via hole conductor 3b1 electroless plated layer 3b11 first region 3b12 second region 3b2 electrolytic plated layer 3bK constricted portion 32 void 4 solder resist 5 solder 6 seed layer 61 first seed layer 62 second seed layer 63 electrolytic plated layer 631 recess 7 resist 8 sputtered metal layer 81 first sputtered metal layer 82 second sputtered metal layer

Claims

1. A first insulating layer having a first surface; A land conductor located on the first surface; A second insulating layer covering the first surface and the land conductor and having a second surface on the side opposite to the first insulating layer; A via hole penetrating from the second surface of the second insulating layer to the land conductor; A via hole conductor located in the via hole and in contact with the land conductor; Comprising; The via hole conductor has a base metal layer located on the surface of the land conductor, the wall surface of the via hole, and the second surface, and an electrolytic plating layer located on the base metal layer; A plurality of voids are located in at least a part of the base metal layer; A wiring board.

2. The wiring board according to claim 1, wherein the base metal layer is an electroless plating layer.

3. The wiring board according to claim 1, wherein the base metal layer is a sputtered metal layer.

4. The wiring board according to claim 3, wherein the sputtered metal layer has a multilayer structure.

5. The land conductor has an inclined portion at the periphery thereof; The wiring board according to claim 1, wherein the thickness of the inclined portion is larger from the periphery of the land conductor to the side surface of the via hole conductor when viewed in cross section.

6. The land conductor has a concave portion that is recessed in a curved shape when viewed in cross section; The wiring board according to claim 1, wherein the via hole conductor is in contact with the concave portion.

7. The via hole conductor has a constricted portion with the smallest width in the horizontal direction along the first surface, and the plurality of voids are located at least on the land conductor side of the constricted portion in the vertical direction with respect to the first surface among the via hole conductors. The wiring board according to claim 1.

8. The base metal layer includes a first region located between the electrolytic plating layer and the land conductor, and a second region located between the electrolytic plating layer and the second insulating layer; The wiring board according to claim 1, wherein the density of the plurality of voids included in the first region is larger than the density of the plurality of voids included in the second region.

9. When viewed in cross-section, the first region is 1000000 nm ２ The wiring board according to claim 8, which contains one or more and 40 or less of the plurality of voids per

10. The underlying metal layer is the electroless plating layer, and the first region contains, per 1000000 nm ２ in cross-sectional view, one or more and 40 or less of the plurality of voids, the wiring substrate according to claim 9.

11. The underlying metal layer is the sputtered metal layer, and the first region contains, per 1000000 nm ２ in cross-sectional view, one or more and ten or fewer of the plurality of voids. The wiring substrate according to claim 9

12. A mounting structure including the wiring board according to any one of claims 1 to 11 and an electronic component located in the mounting region of the wiring board.