Drive circuit for power semiconductor element, and power conversion device

Abstract

A power semiconductor element (1a) has: a high-potential-side first main electrode; a low-potential-side second main electrode; a gate, which is a control electrode; and a diode that is inverse-parallel connected between the first main electrode and the second main electrode. A drive circuit (10a) for the power semiconductor element (1a) comprises: a control circuit (11) for selectively applying an on bias voltage and an off bias voltage to a gate of the power semiconductor element (1a) in accordance with a control signal (GSWa) input from the outside; a detection circuit (18) for detecting a gate charge amount of the power semiconductor element (1a); and a determination circuit (19) for determining, on the basis of the gate charge amount detected by the detection circuit (18), whether the diode of the power semiconductor element (1a) is executing a reflux operation.

Description

Power semiconductor device drive circuit and power conversion device

[0001] The present disclosure relates to a drive circuit for a power semiconductor device and a power conversion device.

[0002] A drive circuit for a power semiconductor element (hereinafter simply referred to as "semiconductor element") such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor) is configured to control the current flowing through the semiconductor element by applying a gate bias to the gate to turn the semiconductor element on (conducting) or off (blocking). Such a drive circuit is also called a "gate drive circuit."

[0003] Gate bias includes an on-bias for turning on a semiconductor element and an off-bias for turning off the semiconductor element. The on-bias is a voltage equal to or greater than the gate threshold voltage of the semiconductor element, and the off-bias is a voltage less than the gate threshold voltage. The gate threshold voltage of a typical IGBT or normally-off MOSFET is about 2 to 7 V. Therefore, the on-bias is generally set to about 15 to 20 V, and the off-bias is set to -15 to 0 V.

[0004] A power conversion device uses a bridge circuit in which two semiconductor elements are connected in series. A drive circuit alternately turns on these two semiconductor elements in accordance with a control signal provided by a control device. However, if the on-periods of one semiconductor element being turned off and the other being turned on overlap, there is a risk of both semiconductor elements being turned on simultaneously, causing an excessive current to flow, resulting in a short circuit. To prevent this short circuit, a dead time is set in which both semiconductor elements are turned off.

[0005] However, if the dead time is long, distortion occurs in the waveforms of the voltage and current input and output to the power conversion device, and high frequency operation is hindered, so there is a demand to shorten the dead time as much as possible.

[0006] It is also known that the oxide film of the gate of a semiconductor device has a limited lifespan when subjected to a gate bias. To extend the lifespan of the oxide film, it is necessary to either reduce the electric field applied to the oxide film or shorten the application time of the gate bias.

[0007] As a technology for suppressing the progression of semiconductor element degradation, for example, Japanese Patent Laid-Open Publication No. 2019-68691 (Patent Document 1) discloses a drive circuit for driving an upper arm switch and a lower arm switch. In this drive circuit, of the body diodes of the upper arm switch and the lower arm switch, the diode through which a reflux current flows during dead time is defined as a target diode, the switch having the target diode is defined as a target switch, and the remaining switches are defined as opposing arm switches. The drive circuit is configured to maintain the gate bias of the target switch at a negative voltage during the dead time immediately after the target switch is switched off, from the start of the dead time until partway through the period during which the opposing arm switch is on (hereinafter also referred to as a specified period), and then maintain the gate bias of the target switch at an off voltage until the end of the next dead time. Note that a negative voltage is a voltage less than zero, and an off voltage is a voltage equal to or greater than zero and less than a gate threshold voltage.

[0008] JP 2019-68691 A

[0009] The drive circuit described in Patent Document 1 maintains the gate bias of the target switch at a negative voltage for the specified period described above, thereby preventing self-turn-on of the target switch when the opposing arm switch is switched to the on state.

[0010] However, in Patent Document 1, the gate bias of the target switch must be maintained at a negative voltage from the end of the dead time immediately after the target switch is switched off until the opposing arm switch has finished turning on. Therefore, it is necessary to provide a time leeway between the end of the dead time and the switching of the gate bias from a negative voltage to an off voltage. In this case, the time for which a negative voltage is applied to the gate of the target switch becomes longer, which may affect the lifespan of the oxide film. On the other hand, if a time leeway is not provided for this period, the gate bias of the target switch cannot be maintained at a negative voltage until the opposing arm switch has finished turning on, which may result in self-turn-on of the target switch.

[0011] In other words, to prevent the target switch from self-turning on, it is necessary to apply just the right amount of negative voltage for the period required for the opposing arm switch to turn on, but accurately determining this period was difficult using only the information input to the target switch's drive circuit.One way to solve this difficulty is to prepare a separate isolated signal to detect the timing at which the opposing arm switch turns on, but this method has issues in terms of mounting area and cost.

[0012] In addition, in Patent Document 1, in order to determine whether the upper arm switch or the lower arm switch is the target switch, each arm switch is provided with a sense terminal that outputs a minute current that is correlated with the current flowing between the first terminal and the second terminal, and the direction of current flow is detected based on the minute current output from the sense terminal. This method requires providing a sense terminal for each semiconductor element, which poses a problem in terms of cost.

[0013] The present disclosure has been made to solve such problems, and its main objective is to provide a drive circuit that can determine the freewheeling operation of the diode of a power semiconductor element with a simple configuration.

[0014] A drive circuit according to one aspect of the present disclosure is a drive circuit for driving a power semiconductor element. The power semiconductor element has a first main electrode on a high potential side, a second main electrode on a low potential side, a gate as a control electrode, and a diode connected in anti-parallel between the first main electrode and the second main electrode. The drive circuit includes: a control circuit that selectively applies an on-bias voltage and an off-bias voltage to the gate of the power semiconductor element in accordance with an externally input control signal; a detection circuit that detects the amount of gate charge of the power semiconductor element; and a determination circuit that determines whether the diode of the power semiconductor element is performing a freewheeling operation based on the amount of gate charge detected by the detection circuit.

[0015] According to the present disclosure, it is possible to determine whether a power semiconductor device is in freewheeling operation with a simple configuration, and it is thereby possible to appropriately activate a circuit for suppressing self-turn-on of the power semiconductor device when the power semiconductor device is in freewheeling operation.

[0016] FIG. 5 is a main circuit configuration diagram of a power conversion device according to a first embodiment. FIG. 6 is a block diagram showing an example configuration of a gate drive circuit according to a comparative example. FIG. 7 is a diagram explaining the operation of a semiconductor element. FIG. 8 is a diagram explaining the operation of a semiconductor element. FIG. 9 is a time chart showing the operation of the semiconductor element shown in FIG. 4. FIG. 10 is a diagram explaining self-turn-on of an N-side semiconductor element. FIG. 11 is a block diagram showing an example configuration of a gate drive circuit according to the first embodiment. FIG. 12 is a time chart showing the operation of a semiconductor element. FIG. 13 is a flowchart showing the operation of the gate drive circuit according to the first embodiment. FIG. 14 is a diagram showing an example circuit configuration of a gate drive circuit according to the first embodiment. FIG. 15 is a block diagram showing an example configuration of a gate drive circuit according to a third embodiment. FIG. 16 is a block diagram showing an example configuration of a gate drive circuit according to a fourth embodiment. FIG. 17 is a diagram showing an example circuit configuration of a gate drive circuit according to the fourth embodiment. FIG. 18 is a time chart showing the operation of a semiconductor element. FIG. 19 is a flowchart showing the operation of the gate drive circuit according to the fourth embodiment.

[0017] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings will be denoted by the same reference numerals, and their description will not be repeated in principle.

[0018] First Embodiment <Configuration Example of Power Conversion Device> Fig. 1 is a main circuit configuration diagram of a power conversion device according to a first embodiment of the present disclosure. Power conversion device 100 according to the first embodiment is a three-phase (U, V, W) inverter that performs bidirectional power conversion between a DC power supply 110 and a motor 120, which is a load. Motor 120 is, for example, an induction motor or a synchronous motor. Power conversion device 100 is not limited to an inverter and may be, for example, a non-isolated synchronous rectification converter.

[0019] As shown in Fig. 1, the power conversion device 100 includes three legs 12U, 12V, and 12W and six gate drive circuits 10a to 10f. The three legs 12U, 12V, and 12W are connected in parallel with one another between a DC positive bus PL and a DC negative bus NL. The DC positive bus PL is electrically connected to a positive terminal of a DC power supply 110. The DC negative bus NL is electrically connected to a negative terminal of the DC power supply 110. In this specification, "electrically connected" refers to a direct connection or a connection via another element that allows transmission of electrical energy.

[0020] Leg 12U has two power semiconductor elements (hereinafter also simply referred to as "semiconductor elements") 1a and 1b connected in series. Leg 12V has two semiconductor elements 1c and 1d connected in series. Leg 12W has two semiconductor elements 1e and 1f connected in series. That is, each of legs 12U, 12V, and 12W is configured as a bridge circuit. The connection node of semiconductor elements 1a and 1b, the connection node of semiconductor elements 1c and 1d, and the connection node of semiconductor elements 1e and 1f are connected to motor 120.

[0021] Hereinafter, when semiconductor elements 1a to 1f are not particularly distinguished from one another, they may be collectively referred to as "semiconductor element 1." In addition, in legs 12U, 12V, and 12W, semiconductor elements 1a, 1c, and 1d having a high-potential side main electrode connected to DC positive bus PL and a low-potential side main electrode connected to motor 120 may be referred to as "P-side semiconductor element." Semiconductor elements 1b, 1d, and 1f having a high-potential side main electrode connected to motor 120 and a low-potential side main electrode connected to DC negative bus NL may be referred to as "N-side semiconductor element."

[0022] In FIG. 1, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used as the semiconductor element 1, but any voltage-driven semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) can be used.

[0023] The semiconductor element 1 has a diode connected in anti-parallel. The diode is provided to allow a return current (freewheel current) to flow when the corresponding semiconductor element 1 is turned off. If the semiconductor element 1 is a MOSFET, the freewheel diode may be configured as a parasitic diode (body diode). If the semiconductor element 1 is an IGBT without a built-in diode, the freewheel diode is configured as a diode connected in anti-parallel to the IGBT.

[0024] The control device 130 generates gate command signals GSWa to GSWf, which are control signals for controlling the on / off of the semiconductor elements 1a to 1f. Specifically, the control device 130 generates a gate command signal GSW at an H (logical high) level during a period when the semiconductor element 1 should be on (conductive), and generates a gate command signal GSW at an L (logical low) level during a period when the semiconductor element 1 should be off (cut off). The H-level gate command signal GSW corresponds to an "on command," and the L-level gate command signal GSW corresponds to an "off command."

[0025] Gate drive circuits 10a-10f are provided corresponding to semiconductor elements 1a-1f, respectively. Gate drive circuits 10a-10f control the on-off operation of semiconductor elements 1a-1f by driving corresponding semiconductor elements 1 in accordance with gate command signals GSWa-GSWf provided by control device 130. Specifically, each of gate drive circuits 10a-10f is configured to apply an on-bias voltage to the control electrode (gate) of corresponding semiconductor element 1 in response to an H-level gate command signal GSW (on command), and to apply an off-bias voltage to the gate terminal of corresponding semiconductor element 1 in response to an L-level gate command signal GSW (off command). Hereinafter, when there is no need to distinguish between each of gate drive circuits 10a-10f, they may be collectively referred to as "gate drive circuit 10."

[0026] As a result, the power conversion device 100 can perform an inverse conversion operation in which the DC power supplied from the DC power source 110 is converted into three-phase AC power and supplied to the motor 120, and a forward conversion operation in which the three-phase AC power supplied from the motor 120 is converted into DC power and supplied to the DC power source 110.

[0027] <Configuration of Gate Drive Circuit> Next, the configuration of gate drive circuit 10 according to the first embodiment will be described.

[0028] (Configuration Example of Gate Drive Circuit According to Comparative Example) First, the configuration of a general gate drive circuit will be described as a comparative example to the gate drive circuit according to the first embodiment.

[0029] 2 is a block diagram showing an example of the configuration of a gate drive circuit 10a according to a comparative example. The gate drive circuit 10a drives a P-side semiconductor element 1a. The gate drive circuit 10a that drives the P-side semiconductor element 1a and the gate drive circuit 10b that drives the N-side semiconductor element 1b basically have a common configuration, so the following description will representatively explain the configuration of the gate drive circuit 10a.

[0030] As shown in FIG. 2, the gate drive circuit 10a includes an input terminal T1, output terminals T2 and T3, a control circuit 21, switches 25a and 25b, and a gate resistor .

[0031] The input terminal T1 is connected to the control device 130 (see FIG. 1). The input terminal T1 transfers a gate command signal GSWa provided from the control device 130 to the control circuit 21. The output terminal T2 is connected to the gate, which is the control electrode of the semiconductor element 1a. The output terminal T3 is connected to the source, which is the main electrode on the low potential side of the semiconductor element 1a, and to the reference node 13.

[0032] The control circuit 21 has an on-bias power supply Vp for generating an on-bias voltage Vp to be applied to the gate of the semiconductor element 1a, and an off-bias power supply Vn for generating an off-bias voltage Vn to be applied to the gate of the semiconductor element 1a. The positive terminal of the on-bias power supply Vp is connected to the power supply node 12, and the negative terminal is connected to the reference node 13. The positive terminal of the off-bias power supply Vn is connected to the reference node 13, and the negative terminal is electrically connected to the output node 14.

[0033] The switch 25a is connected between the power supply node 12 and the output node 14. The switch 25b is connected between the output node 14 and the negative terminal of the off-bias power supply Vn. A gate resistor 26 is connected between the output node 14 and the output terminal T2.

[0034] The control circuit 21 selectively turns on and off the switches 25a and 25b in response to the gate command signal GSWa. Specifically, when the gate command signal GSWa is at H level, the control circuit 21 turns on the switch 25a and turns off the switch 25b. As a result, the output node 14 is connected to the power supply node 12, and the on-bias power supply Vp is connected between the output terminals T2 and T3. As a result, the on-bias voltage Vp is applied between the gate and source of the semiconductor element 1a. The on-bias voltage Vp is a voltage higher than the gate threshold voltage Vth of the semiconductor element 1.

[0035] On the other hand, when the gate command signal GSwa is at an L level, the control circuit 21 turns off the switch 25a and turns on the switch 25b. As a result, the output node 14 is connected to the negative terminal of the off-bias power supply Vn, and the off-bias power supply Vn is connected between the output terminals T2 and T3. As a result, the off-bias voltage Vn is applied between the gate and source of the semiconductor element 1a. The off-bias voltage Vn is a voltage less than the gate threshold voltage Vth of the semiconductor element 1.

[0036] In the following explanation, the voltage applied between the gate and source of semiconductor element 1a (hereinafter referred to as the "gate voltage") is Vga, the voltage applied between the drain and source of semiconductor element 1a (hereinafter referred to as the "drain voltage") is Vdsa, and the current flowing through the drain of semiconductor element 1a (hereinafter referred to as the "drain current") is Ida. The gate voltage of semiconductor element 1b is Vgb, the drain voltage of semiconductor element 1b is Vdsb, and the drain current of semiconductor element 1b is Idb.

[0037] (On / Off Operation of Semiconductor Elements 1a, 1b) The semiconductor elements 1a, 1b constituting leg 12U are complementarily turned on and off by gate drive circuits 10a, 10b. While the semiconductor elements 1a, 1b are being turned on and off, a dead time Td is set, which is a period during which both semiconductor elements 1a, 1b are in the off state, so that the on period of the P-side semiconductor element 1a and the on period of the N-side semiconductor element 1b do not overlap each other.

[0038] 3 and 4 are diagrams illustrating the operation of the semiconductor elements 1 a and 1 b. In the following description, the phase current flowing through the windings of the motor 120 is defined as IL, and the direction of the phase current IL from the connection node of the semiconductor elements 1 a and 1 b to the windings is defined as the positive direction, and the direction of the phase current IL from the windings to the connection node of the semiconductor elements 1 a and 1 b is defined as the negative direction.

[0039] 3 shows the on / off operation of the semiconductor elements 1a and 1b when the phase current IL flows in the positive direction. During the on period of the semiconductor element 1a, the semiconductor element 1b is in the off state, as shown in FIG. 3(A). Therefore, current flows from the drain of the semiconductor element 1a through the source to the winding.

[0040] During the dead time Td, the semiconductor elements 1a and 1b are turned off, as shown in Fig. 3B. The windings act to allow a continuous flow of current, so that a return current flows to the windings via the diode of the semiconductor element 1b.

[0041] Next, during the ON period of semiconductor element 1b, semiconductor element 1a is turned OFF, as shown in Fig. 3C. When semiconductor element 1b is turned ON, a return current flows from the source of semiconductor element 1b to the winding via the drain.

[0042] While a return current flows through the diode, a loss occurs due to the forward voltage of the diode. Generally, this loss is greater than the loss caused by the on-resistance of the MOSFET. Therefore, by turning on the semiconductor element 1b during the return period excluding the dead time Td, the return current flows through the semiconductor element 1b (see FIG. 3C).

[0043] 4 shows the on / off operation of the semiconductor elements 1a and 1b when the flow direction of the phase current IL is negative. During the on period of the semiconductor element 1b, the semiconductor element 1a is in the off state, as shown in FIG. 4(A). Therefore, current flows from the winding to the source of the semiconductor element 1a via the drain.

[0044] During the dead time Td, the semiconductor elements 1a and 1b are turned off, as shown in Fig. 4B. The windings act to allow a continuous flow of current, so that a return current flows to the windings via the diode of the semiconductor element 1a.

[0045] Next, during the on-period of the semiconductor element 1a, the semiconductor element 1a is turned off, as shown in Fig. 4(C). When the semiconductor element 1a is turned on, a return current flows from the winding to the drain of the semiconductor element 1a via the source. As described above, in order to reduce loss, the semiconductor element 1a is turned on during the return period excluding the dead time Td, thereby causing the return current to flow through the semiconductor element 1a.

[0046] In this specification, the operation of flowing a current in the forward direction from the drain to the source of the semiconductor element 1 is defined as a "SW (switching) operation." In contrast, the operation of flowing a current (freewheeling current) through the diode of the semiconductor element 1 or from the source to the drain of the semiconductor element 1 is defined as a "freewheeling operation."

[0047] When the phase current IL flows in the positive direction as shown in Fig. 3, the P-side semiconductor element 1a performs a switching operation and the N-side semiconductor element 1b performs a freewheeling operation. When the phase current IL flows in the negative direction as shown in Fig. 4, the N-side semiconductor element 1b performs a switching operation and the P-side semiconductor element 1a performs a freewheeling operation.

[0048] (Operation of the Gate Drive Circuit According to the Comparative Example) Next, the operation of the gate drive circuit according to the comparative example will be described.

[0049] Fig. 5 is a time chart showing the operation of the semiconductor elements 1a and 1b shown in Fig. 4. Fig. 5 shows waveforms of the drain voltage Vds, drain current Id, gate voltage Vg, gate charge Qg, gate current Ig, and gate command signal GSW of the semiconductor elements 1a and 1b. In each waveform, the solid line indicates the waveform of the P-side semiconductor element 1a, and the dashed line indicates the waveform of the N-side semiconductor element 1b.

[0050] The gate charge Qg is the amount of charge stored in the gate parasitic capacitances Cgd (gate-source capacitance) and Cgs (gate-source capacitance) of the semiconductor element 1. The gate charge Qg can be determined by integrating the gate current Ig over time. The gate current Ig is defined as the positive direction in which the gate parasitic capacitances Cgd and Cgs are charged, and the negative direction in which the gate parasitic capacitances Cgd and Cgs are discharged. In the following description, the gate charge Qg of semiconductor element 1a is defined as Qga, and the gate charge Qg of semiconductor element 1b is defined as Qgb.

[0051] As shown in FIG. 5, at time t0, the gate command signal GSWa is at an L level and the gate command signal GSWb is at an H level. In response to the L-level gate command signal GSWa, the gate drive circuit 10a turns on the switch 15b and turns off the switch 15a, thereby applying the off-bias voltage Vn to the gate of the semiconductor element 1a. Therefore, the gate voltage Vga of the semiconductor element 1a becomes the off-bias voltage Vn, and the semiconductor element 1a is in an off-state. Therefore, the drain current Ida is 0, and the drain voltage Vdsa is VDC. VDC corresponds to the voltage between the terminals of the DC power supply 110. Because the gate parasitic capacitances Cgd and Cgs of the semiconductor element 1a are discharged, the gate charge Qga is 0.

[0052] Meanwhile, the gate drive circuit 10b turns on the switch 15a and turns off the switch 15b in response to the H-level gate command signal GSWb, thereby applying the on-bias voltage Vp to the gate of the N-side semiconductor element 1b. Therefore, the gate voltage Vgb of the semiconductor element 1b becomes the on-bias voltage Vp, and the semiconductor element 1b is turned on.

[0053] As shown in Figure 4A, a forward current flows between the drain and source of semiconductor element 1b, and semiconductor element 1b is performing a switching operation. The drain current Idb is equal to the magnitude of phase current IL, and the drain voltage Vdsa is 0. The gate parasitic capacitances Cgs and Cgd of semiconductor element 1b are charged by gate current Igb, so the gate charge Qgb is Qh.

[0054] When the gate command signal GSWb transitions from H level to L level at time t1, the semiconductor element 1b is turned off. Specifically, in response to the L-level gate command signal GSWb, the gate drive circuit 10b turns off the switch 15a and turns on the switch 15b, thereby switching the voltage applied to the gate of the semiconductor element 1b from the on-bias voltage Vp to the off-bias voltage Vn.

[0055] As a result, the charges stored in the gate parasitic capacitances Cgs and Cgd of the semiconductor element 1b are discharged via the gate resistor 26 and the switch 25b, so that the gate charge Qgb gradually decreases from Qh, and the gate voltage Vgb gradually decreases from the on-bias voltage Vp toward the off-bias voltage Vn.

[0056] When the gate voltage Vgb becomes less than the gate threshold voltage Vth, the semiconductor element 1b begins to turn off. When the semiconductor element 1b turns off, the drain current Idb begins to decrease and the drain voltage Vdsb begins to increase. The gate current Igb (discharge current) flows from time t1 until the discharge of the gate parasitic capacitances Cgs and Cgd is completed and the gate charge amount Qgb becomes 0.

[0057] As shown in FIG. 4B, when semiconductor element 1b is turned off, a reflux current flows through the diode of semiconductor element 1a. As the reflux current begins to flow through the diode, the drain voltage Vdsa of semiconductor element 1a begins to decrease, and the drain current Ida begins to increase. If the change in voltage with respect to time during a transient period in which the drain voltage Vdsa changes abruptly is dv / dt, then a displacement current (Cgd × dv / dt) flows through the gate-drain capacitance Cgd of semiconductor element 1a while dv / dt is occurring. This displacement current flows through gate resistor 26, causing the gate voltage Vga to decrease. Furthermore, because the displacement current charges the gate parasitic capacitances Cgd and Cgs, the gate charge Qga increases from 0 to Qa. Qa is greater than 0 and less than Qh.

[0058] The period from time t1 to time t2 corresponds to dead time Td, during which a return current continues to flow through the diode of the semiconductor element 1a.

[0059] At time t2, when the gate command signal GSWa transitions from L level to H level, the semiconductor element 1a is turned on. Specifically, in response to the H level gate command signal GSWa, the gate drive circuit 10a turns on the switch 15a and turns off the switch 15b, thereby switching the voltage applied to the gate of the semiconductor element 1a from the off-bias voltage Vn to the off-bias voltage Vp.

[0060] As a result, a gate current Iga flows from the power supply node 12 to the gate of the semiconductor element 1a via the gate resistor 26, charging the gate parasitic capacitances Cgs and Cgd. The gate charge Qga gradually increases from Qa and reaches Qh. When charging is complete, the gate current Iga stops flowing. After this, the on-bias voltage Vp is continuously applied to the gate of the semiconductor element 1a, so the semiconductor element 1a is maintained in the on state. As shown in FIG. 4C, a reflux current flows between the drain and source of the semiconductor element 1a, and the semiconductor element 1a is performing a reflux operation.

[0061] When the gate command signal GSWa transitions from H level to L level at time t3, the semiconductor element 1a is turned off. Specifically, in response to the L-level gate command signal GSWa, the gate drive circuit 10a turns off the switch 15a and turns on the switch 15b, thereby switching the voltage applied to the gate of the semiconductor element 1a from the on-bias voltage Vp to the off-bias voltage Vn.

[0062] As a result, the charges stored in the gate parasitic capacitances Cgs and Cgd of the semiconductor element 1a are discharged via the gate resistor 26 and the switch 25b. The gate charge Qga gradually decreases from Qh, and the gate voltage Vga gradually decreases from the on-bias voltage Vp toward the off-bias voltage Vn. When the gate voltage Vga becomes less than the gate threshold voltage Vth, the semiconductor element 1a begins to turn off.

[0063] When the semiconductor element 1a is turned off, a reflux current begins to flow through the diode of the semiconductor element 1a, as shown in Fig. 4B. Therefore, the drain voltage Vdsa and the drain current Ida are maintained at constant values ​​without changing even when the semiconductor element 1a is turned off.

[0064] The period from time t3 to t4 corresponds to dead time Td. During dead time Td, the diode of semiconductor element 1a performs reflux operation, so gate charge Qga does not decrease to 0 and maintains Qa. Qa corresponds to the amount of charge stored during dead time Td (the period from time t1 to t2) after semiconductor element 1b is turned off. In other words, it can be seen that gate charge Qgb of semiconductor element 1b during SW operation decreases to 0 after turn-off, while gate charge Qga of semiconductor element 1a during reflux operation does not decrease to 0 after turn-off.

[0065] When the gate command signal GSWb transitions from L level to H level at time t4, the semiconductor element 1b is turned on. Specifically, in response to the H-level gate command signal GSWb, the gate drive circuit 10b turns on the switch 15a and turns off the switch 15b, thereby switching the voltage applied to the gate of the semiconductor element 1b from the off-bias voltage Vn to the on-bias voltage Vp.

[0066] As a result, gate current Igb flows from power supply node 12 to the gate of semiconductor element 1b via gate resistor 26, charging gate parasitic capacitances Cgs and Cgd. Gate charge Qgb gradually increases from 0 and reaches Qh. When charging is complete, gate current Igb stops flowing. After this, on-bias voltage Vp is continuously applied to the gate of semiconductor element 1b, so semiconductor element 1b is maintained in the on state. As shown in FIG. 4A, a forward current flows between the drain and source of semiconductor element 1b, and semiconductor element 1b performs a switching operation.

[0067] In response to the turning on of semiconductor element 1b, drain current Idb begins to flow through semiconductor element 1b. In response to the start of the drain current Idb flowing, drain voltage Vdsb of semiconductor element 1b begins to decrease, and drain current Idb begins to increase. As a result, the reflux current flowing through the diode of semiconductor element 1a decreases, and drain voltage Vdsa begins to increase. Because a reverse voltage is applied to the diode of semiconductor element 1a, a momentary recovery current flows through the diode, and then the diode is turned off.

[0068] After the recovery operation of the diode of the semiconductor element 1a, the drain voltage Vdsa changes abruptly. While the drain voltage Vdsa changes over time (dv / dt), a displacement current (Cgd × dv / dt) flows through the gate-drain capacitance Cgd of the semiconductor element 1a. This displacement current flows through the gate resistor 26, causing the gate voltage Vga to increase. Furthermore, the gate parasitic capacitances Cgd and Cgs are discharged by the displacement current, so the gate charge Qga decreases from Qa to 0.

[0069] The above has described the operating waveforms when the semiconductor element 1b performs a switching operation and the semiconductor element 1a performs a freewheeling operation when the phase current IL<0. When the phase current IL>0, the semiconductor element 1a performs a switching operation and the semiconductor element 1b performs a freewheeling operation, and the operating waveforms can be considered to be similar to those in FIG.

[0070] (Self-Turn-On Phenomenon) As shown in FIG. 5, when the semiconductor element 1b performing the SW operation turns on (time t4 in FIG. 5), a steep voltage change dv / dt is applied between the drain and source of the semiconductor element 1a performing the freewheeling operation. This causes a displacement current (Cgd·dv / dt) to flow through the gate resistor 26, which instantaneously raises the gate voltage Vga. If the gate voltage Vga exceeds the gate threshold voltage Vth, the semiconductor element 1a, which is currently off, may be accidentally turned on. This phenomenon in which the semiconductor element 1a is turned on by itself is called "self-turn-on."

[0071] When the semiconductor element 1a performing the freewheeling operation is turned on (time t2 in FIG. 5), the drain voltage Vdsb of the semiconductor element 1b performing the SW operation does not change, and therefore self-turn-on of the semiconductor element 1b does not occur.

[0072] In leg 12U, which is configured as a bridge circuit, self-turn-on may occur even when semiconductor element 1a performs a switching operation and semiconductor element 1b performs a free-wheeling operation. FIG. 6 is a diagram illustrating self-turn-on of semiconductor element 1b.

[0073] As shown in FIG. 3B, when semiconductor elements 1a and 1b are turned off, a reflux current flows through the diode of semiconductor element 1b. When semiconductor element 1a is turned on in this state, a sudden voltage change dv / dt occurs between the drain and source of semiconductor element 1b after the diode of semiconductor element 1b undergoes recovery operation. During this time, the drain voltage Vdsb rises linearly from 0 to VDC. While dv / dt occurs, a displacement current i (= Cgd × dv / dt) flows through the gate parasitic capacitances Cgd and Cgs of semiconductor element 1a, instantaneously charging the gate-source capacitance Cgs. As a result, the gate voltage Vga rises, and semiconductor element 1b self-turns.

[0074] When self-turn-on of semiconductor element 1b occurs, semiconductor elements 1a and 1b are simultaneously turned on, causing an excessively large short-circuit current to instantaneously flow from DC positive bus line PL to DC negative bus line NL. The loss caused by this short-circuit current may destroy semiconductor elements 1a and 1b.

[0075] (Configuration Example of Gate Drive Circuit According to First Embodiment) As described above, when the semiconductor element 1 performing the SW operation is turned on, self-turn-on of the semiconductor element 1 performing the freewheeling operation can occur. Therefore, if the rise in the gate voltage Vg of the semiconductor element 1 performing the freewheeling operation can be suppressed in accordance with the timing at which the semiconductor element 1 performing the SW operation is turned on, self-turn-on of the semiconductor element 1 can be prevented.

[0076] Here, when we look at the operating waveforms of the semiconductor elements 1a and 1b shown in Figure 5, we can see that the waveforms of the gate current Ig and gate charge Qg are different between the semiconductor element 1b performing SW operation and the semiconductor element 1b performing reflux operation.

[0077] Specifically, in the semiconductor element 1b performing the SW operation, the gate current Igb flows temporarily when the semiconductor element 1b is turned on and off, but the gate current Iga does not flow when the semiconductor element 1a is turned on and off. In contrast, in the semiconductor element 1a performing the freewheeling operation, the gate current Iga flows temporarily not only when the semiconductor element 1a is turned on and off, but also when the semiconductor element 1b is turned on and off.

[0078] Furthermore, in the semiconductor element 1b that performs the SW operation, the gate charge Qgb decreases to 0 when turned off, whereas in the semiconductor element 1a that performs the reflux operation, the gate charge Qga becomes Qa when turned off and does not decrease to 0. The gate charge Qga of the semiconductor element 1a decreases to 0 in response to the turn-on of the semiconductor element 1b.

[0079] Therefore, it is possible to determine whether the semiconductor element 1 is performing a SW operation or a freewheeling operation from the waveform of the gate current Ig or the gate charge Qg. If it can be determined that the semiconductor element 1 is performing a freewheeling operation, it is possible to suppress a momentary rise in the gate voltage Vg at the timing when the other semiconductor element 1 turns on, i.e., at the timing when the diode of that semiconductor element 1 performs a recovery operation. The timing when the diode of that semiconductor element 1 performs a recovery operation can be known from the timing when the gate charge Qg drops from Qa to 0.

[0080] Gate drive circuit 10 according to the first embodiment is configured to determine whether or not the diode of a corresponding semiconductor element 1 is performing a freewheeling operation, based on the waveform of gate charge Qg of that semiconductor element 1. If it is determined that the diode of the corresponding semiconductor element 1 is performing a freewheeling operation, gate drive circuit 10 is configured to detect the timing at which the diode of semiconductor element 1 performs a recovery operation from the waveform of gate charge Qg, and to temporarily reduce off-bias voltage Vn applied to the gate of that semiconductor element 1 in accordance with the detected timing.

[0081] The following describes a detailed configuration of gate drive circuit 10 according to embodiment 1. Since gate drive circuits 10a to 10f basically have a common configuration, the following description will representatively focus on the configuration of gate drive circuit 10a.

[0082] 7 is a block diagram showing an example of the configuration of gate drive circuit 10a according to embodiment 1. As shown in Fig. 7, gate drive circuit 10a includes input terminal T1, output terminals T2 and T3, control circuit 11, switch 15, off-bias switching circuit 16, gate charge detection circuit 18, and freewheel operation determination circuit 19.

[0083] The input terminal T1 is connected to the control device 130 (see FIG. 1). The input terminal T1 transfers a gate command signal GSWa provided from the control device 130 to the control circuit 11. The output terminal T2 is connected to the gate, which is the control electrode of the semiconductor element 1a. The output terminal T3 is connected to the source, which is the main electrode on the low potential side of the semiconductor element 1a, and to a reference node 13.

[0084] The control circuit 11 has an on-bias power supply Vp for generating an on-bias voltage Vp to be applied to the gate of the semiconductor element 1a, an off-bias power supply Vnh for generating an off-bias voltage Vnh to be applied to the gate of the semiconductor element 1a, and an off-bias power supply Vnl for generating an off-bias voltage Vnl. The control circuit 11 differs from the control circuit 21 shown in FIG. 2 in that it has two types of off-bias power supplies Vnh and Vnl.

[0085] The on-bias voltage Vp is a voltage higher than the gate threshold voltage Vth of the semiconductor element 1. The off-bias voltages Vnh and Vnl are voltages lower than the gate threshold voltage Vth of the semiconductor element 1. The off-bias voltage Vnh is higher than the off-bias voltage Vnl. When the gate threshold voltage Vth of a typical normally-off MOSFET or IGBT is approximately 2 to 7 V, the on-bias voltage Vp can be set to, for example, 15 to 20 V. The off-bias voltage Vnh can be set to, for example, 0 to -10 V. The off-bias voltage Vnl can be set to, for example, -2 to -15 V. Note that the magnitude (absolute value) of Vnh is always smaller than the magnitude of Vnl. The off-bias voltage Vnh corresponds to an example of a "first value," and the off-bias voltage Vnl corresponds to an example of a "second value."

[0086] The positive terminal of the on-bias power supply Vp is connected to the power supply node 12, and the negative terminal is connected to the reference node 13. The positive terminal of the off-bias power supply Vnh is connected to the reference node 13, and the negative terminal is electrically connected to the output node 14. The positive terminal of the off-bias power supply Vnl is connected to the reference node 13, and the negative terminal is connected to the output node 14.

[0087] The switch 15 is connected between the power supply node 12 and the output node 14. The off-bias switching circuit 16 has a switch 16h and a switch 16l. The switch 16h is connected between the output node 14 and the negative terminal of the off-bias power supply Vnh. The switch 16l is connected between the output node 14 and the negative terminal of the off-bias power supply Vnl. A gate resistor 17 is connected between the output node 14 and the output terminal T2.

[0088] The gate charge detection circuit 18 detects the gate charge Qg by integrating the gate current Ig flowing through the gate resistor 17 with respect to time. In the example of FIG. 7 , the gate charge detection circuit 18 is configured to calculate the gate current Ig from the voltage across the gate resistor 17, and then integrate it with respect to time to detect the gate charge Qg. There are various methods for integrating the gate current Ig, such as a method using an operational amplifier or a method using a CR filter. Any method may be used to detect the gate current Ig. The gate charge detection circuit 18 outputs the detected value of the gate charge Qga to the freewheel operation determination circuit 19.

[0089] The freewheel operation determination circuit 19 determines whether the diode of the semiconductor element 1a is performing a freewheel operation based on the detected value of the gate charge amount Qg. Specifically, the freewheel operation determination circuit 19 has a predetermined threshold value Qb, and determines whether the diode of the semiconductor element 1a is performing a freewheel operation by comparing the threshold value Qb with the detected value of the gate charge amount Qg.

[0090] Control circuit 11 selectively turns on and off switch 15 and off-bias switching circuit 16 in response to gate command signal GSWa. Specifically, when gate command signal GSWa is at H level, control circuit 11 turns on switch 15 and turns off off-bias switching circuit 16. As a result, output node 14 is connected to power supply node 12, and on-bias power supply Vp is connected between output terminals T2 and T3. As a result, on-bias voltage Vp is applied between the gate and source of semiconductor element 1a.

[0091] On the other hand, when the gate command signal GSwa is at an L level, the control circuit 11 turns off the switch 15 and turns on the off-bias switching circuit 16. The off-bias switching circuit 16 selectively turns on the switches 16h and 16l based on the determination result provided by the freewheel operation determination circuit 19. When the switch 16h is turned on, the output node 14 is connected to the negative terminal of the off-bias power supply Vnh, and the off-bias power supply Vnh is connected between the output terminals T2 and T3. As a result, the off-bias voltage Vnh is applied between the gate and source of the semiconductor element 1a. When the switch 16l is turned on, the output node 14 is connected to the negative terminal of the off-bias power supply Vnl, and the off-bias power supply Vnl is connected between the output terminals T2 and T3. As a result, the off-bias voltage Vnl is applied between the gate and source of the semiconductor element 1a.

[0092] That is, the off-bias switching circuit 16 is configured to be able to switch the gate voltage Vga of the semiconductor element 1 a between the off-bias voltage Vnh and the off-bias voltage Vnl according to the determination result of the freewheel operation determination circuit 19 .

[0093] (Operation of Gate Drive Circuit According to First Embodiment) Next, the operation of gate drive circuit 10a according to the first embodiment will be described.

[0094] 8 is a time chart showing the operation of the semiconductor elements 1a and 1b. The waveforms of the drain voltage Vds, drain current Id, gate voltage Vg, gate charge Qg, gate current Ig, and gate command signal GSW of the semiconductor elements 1a and 1b are shown in FIG. 8. For each waveform, the solid line indicates the waveform of the P-side semiconductor element 1a, and the dashed line indicates the waveform of the N-side semiconductor element 1b.

[0095] The time chart shown in Fig. 8 differs from the time chart shown in Fig. 5 in the waveform of the gate voltage Vga of the semiconductor element 1b. The other waveforms are the same as those shown in Fig. 5, so detailed description will be omitted.

[0096] As shown in Figure 8, at time t0, gate command signal GSWa is at L level and gate command signal GSWb is at H level. In gate drive circuit 10a, control circuit 11 turns off switch 15 and turns on off bias switching circuit 16 in response to the L-level gate command signal GSWa. The gate charge Qga of semiconductor element 1a is 0. Freewheel operation determination circuit 19 compares gate charge Qga with threshold Qb. Threshold Qb is set to a value greater than 0 and equal to or less than gate charge Qa during dead time Td. Since Qga < Qb, freewheel operation determination circuit 19 determines that semiconductor element 1a is not in freewheel operation.

[0097] When it is determined that the semiconductor element 1a is not in freewheeling operation, the off-bias switching circuit 16 turns on switch 16h and turns off switch 16l, thereby applying the off-bias voltage Vnh to the gate of the semiconductor element 1a. The gate voltage Vga of the semiconductor element 1a becomes the off-bias voltage Vnh, and the semiconductor element 1a is in the off-state. Therefore, the drain current Ida is 0 and the drain voltage Vdsa is VDC. VDC corresponds to the voltage between the terminals of the DC power supply 110. Because the gate parasitic capacitances Cgd and Cgs of the semiconductor element 1b are discharged, the gate charge Qga is 0.

[0098] At time t1, when gate command signal GSWb transitions from H level to L level, semiconductor element 1b is turned off. In gate drive circuit 10b, control circuit 11 responds to L-level gate command signal GSWb by turning off switch 15 and turning on off-bias switching circuit 16. Off-bias switching circuit 16 first turns on switch 16h and then turns off switch 16l, thereby applying off-bias voltage Vnh to the gate of semiconductor element 1b. As gate voltage Vgb of semiconductor element 1b becomes off-bias voltage Vnh, charges stored in gate parasitic capacitances Cgs and Cgd of semiconductor element 1b are discharged, and gate charge Qgb gradually decreases from Qh. When discharge of gate parasitic capacitances Cgs and Cgd is complete, gate charge Qgb becomes zero.

[0099] The freewheel operation determination circuit 19 compares the gate charge Qgb with the threshold Qb. Because Qgb<Qb, the freewheel operation determination circuit 19 determines that the diode of the semiconductor element 1b is not in freewheel operation. In response to the determination that the diode of the semiconductor element 1b is not in freewheel operation, the off-bias switching circuit 16 keeps the switch 16h on, thereby continuing to apply the off-bias voltage Vnh to the gate of the semiconductor element 1b.

[0100] In response to the semiconductor element 1b being turned off, a reflux current flows through the diode of the semiconductor element 1a. During a transition period in which the drain voltage Vdsa changes abruptly as the reflux current begins to flow through the diode, a displacement current (Cgd×dv / dt) flows through the gate-drain capacitance Cgd of the semiconductor element 1a. This displacement current flows through the gate resistor 26, causing the gate voltage Vga to decrease. Furthermore, the displacement current charges the gate parasitic capacitances Cgd and Cgs, causing the gate charge Qga to increase from 0 to Qa.

[0101] The period from time t1 to time t2 corresponds to dead time Td, during which a return current continues to flow through the diode of the semiconductor element 1a.

[0102] At time t2, when the gate command signal GSWa transitions from L level to H level, the semiconductor element 1a is turned on. Specifically, in response to the H-level gate command signal GSWa, the gate drive circuit 10a turns on the switch 15 and turns off the off-bias switching circuit 16, thereby switching the voltage applied to the gate of the semiconductor element 1a from the off-bias voltage Vnh to the off-bias voltage Vp. A gate current Iga flows from the power supply node 12 to the gate of the semiconductor element 1a via the gate resistor 17. As the gate parasitic capacitances Cgs and Cgd are charged, the gate charge Qga gradually increases from Qa and reaches Qh. A reflux current flows between the drain and source of the semiconductor element 1a, and the semiconductor element 1a is performing a reflux operation.

[0103] At time t3, when gate command signal GSWa transitions from H level to L level, semiconductor element 1a is turned off. In gate drive circuit 10a, control circuit 11 turns off switch 15 and turns on off bias switching circuit 16 in response to L level gate command signal GSWa. Off bias switching circuit 16 first turns on switch 16h and then turns off switch 16l, thereby applying off bias voltage Vnh to the gate of semiconductor element 1a. When gate voltage Vga of semiconductor element 1a becomes off bias voltage Vnh, charges stored in gate parasitic capacitances Cgs and Cgd of semiconductor element 1a are discharged, and gate charge Qga gradually decreases from Qh.

[0104] The gate voltage Vga gradually decreases from the on-bias voltage Vp toward the off-bias voltage Vn. When the gate voltage Vga becomes less than the gate threshold voltage Vth, the semiconductor element 1a begins to turn off. When the semiconductor element 1a turns off, a reflux current begins to flow through the diode of the semiconductor element 1a. Therefore, the drain voltage Vdsa and the drain current Ida do not change and are maintained at constant values ​​even when the semiconductor element 1a is turned off.

[0105] 5, during the dead time Td from time t3 to t4, the diode of semiconductor element 1a performs a reflux operation, so the gate charge Qga does not decrease to 0 but remains at Qa. Qa corresponds to the charge stored during the dead time Td (the period from time t1 to t2) after semiconductor element 1b is turned off.

[0106] The freewheel operation determination circuit 19 compares the gate charge Qga during the dead time Td with the threshold Qb. Because Qga (=Qa) > Qb, the freewheel operation determination circuit 19 determines that the diode of the semiconductor element 1a is in freewheel operation. In response to the determination that the diode of the semiconductor element 1a is in freewheel operation, the off-bias switching circuit 16 turns off the switch 16h and turns on the switch 16l. As a result, the gate voltage Vga of the semiconductor element 1a is switched from the off-bias voltage Vnh to the off-bias voltage Vnl.

[0107] The timing for switching the gate voltage Vga from the off-bias voltage Vnh to the off-bias voltage Vnl is preferably set to the timing after the gate current Iga has stopped flowing in response to the turn-off of the semiconductor element 1a (time t3). This timing can be determined based on the time constants of the gate parasitic capacitances Cgd and Cgs of the semiconductor element 1a and the gate resistor 17. Alternatively, the timing for switching the gate voltage Vga can be determined based on the fall time Tf of the semiconductor element 1a, which is described in the data sheet or the like. The fall time Tf represents the time it takes for the drain voltage Vdsa to rise from 10% to 90% of the maximum voltage Vdc after the semiconductor element 1a is turned off.

[0108] At time t4, when gate command signal GSWb transitions from L level to H level, semiconductor element 1b is turned on. Specifically, in response to gate command signal GSWb at H level, gate drive circuit 10b turns on switch 15 and turns off off-bias switching circuit 16, thereby switching the voltage applied to the gate of semiconductor element 1b from off-bias voltage Vnh to off-bias voltage Vp.

[0109] When the semiconductor element 1b is turned on, a drain current Idb begins to flow through the semiconductor element 1b, and the drain voltage Vdsa of the semiconductor element 1a changes sharply after the diode of the semiconductor element 1a undergoes recovery operation. While the drain voltage Vdsa changes over time (dv / dt), a displacement current (Cgd × dv / dt) flows through the gate-drain capacitance Cgd of the semiconductor element 1a. As this displacement current flows through the gate resistor 17, the gate voltage Vga increases and the gate charge Qga decreases from Qa to 0.

[0110] However, during the dead time Td from time t3 to t4, the gate voltage Vga of the semiconductor element 1a is switched from the off-bias voltage Vnh to the off-bias voltage Vnl, so even if the gate voltage Vga rises instantaneously after time t4, the gate voltage Vga will not exceed the gate threshold voltage Vth, thereby preventing self-turning of the semiconductor element 1a.

[0111] In the gate drive circuit 10a, the freewheel operation determination circuit 19 compares the gate charge Qga with the threshold Qb. Because Qga (=0)<Qb, the freewheel operation determination circuit 19 determines that the semiconductor element 1a has completed the freewheel operation. In response to the determination that the semiconductor element 1a has completed the freewheel operation, the off-bias switching circuit 16 turns off the switch 16l and turns on the switch 16h. As a result, the gate voltage Vga of the semiconductor element 1a is switched from the off-bias voltage Vnl to the off-bias voltage Vnh.

[0112] That is, the gate drive circuit 10a temporarily reduces the gate voltage Vga of the semiconductor element 1a from the off-bias voltage Vnh to the off-bias voltage Vnl in accordance with the timing when the diode of the semiconductor element 1a performs recovery operation, thereby preventing the gate voltage Vga from momentarily rising in response to the recovery operation of the diode and exceeding the gate threshold voltage Vth.

[0113] Here, the oxide film of the gate of the semiconductor element 1 has a lifespan that corresponds to the magnitude of the voltage applied between the gate and source (i.e., the gate voltage Vg). In particular, if the magnitude of the gate voltage Vg exceeds the maximum voltage that can be applied between the gate and source, the oxide film may be destroyed, or deterioration over time may occur due to an increase in ions inside the oxide film. In order to suppress the progression of deterioration of the oxide film, it is necessary to reduce the magnitude of the gate voltage Vg to ease the electric field applied to the oxide film, or to shorten the application time of the gate voltage Vg.

[0114] Therefore, if the off-bias voltage is fixed at Vnl (e.g., −10 to −20 V), self-turn-on of the semiconductor element 1a can be prevented, but there is a concern that this may accelerate degradation of the oxide film on the gate of the semiconductor element 1a. The gate drive circuit 10a according to the first embodiment temporarily sets the off-bias voltage to Vnl only when the diode of the semiconductor element 1a performs a recovery operation, and otherwise sets the off-bias voltage to Vnh (e.g., 0 to −5 V), which is smaller than Vnl, thereby reducing the magnitude of the gate voltage Vga during the period when the diode of the semiconductor element 1a does not perform a recovery operation. This makes it possible to prevent self-turn-on of the semiconductor element 1a while suppressing the progression of degradation of the oxide film on the gate.

[0115] The above has described the operating waveforms when the semiconductor element 1b performs a switching operation and the semiconductor element 1a performs a freewheeling operation when the phase current IL<0. When the phase current IL>0, the semiconductor element 1a performs a switching operation and the semiconductor element 1b performs a freewheeling operation, and the operating waveforms can be considered to be similar to those in FIG.

[0116] 9 is a flowchart showing the operation of gate drive circuit 10 according to embodiment 1. Fig. 9 shows the operation of gate drive circuit 10 when turning off corresponding semiconductor element 1 in accordance with an L-level gate command signal GSW (OFF command) from control device 130. The determination of whether semiconductor element 1 is performing a reflux operation when receiving an H-level gate command signal GSW (ON command) does not affect the switching of the off bias voltage, so a description thereof will be omitted.

[0117] When the semiconductor element 1 is in the on state, an on-bias voltage Vp is applied to the gate of the semiconductor element 1. In this state, when the gate drive circuit 10 receives an L-level gate command signal GSW (off command) from the control device 130 (step S01), the control circuit 11 turns off the switch 15 and turns on the off-bias switching circuit 16. The off-bias switching circuit 16 turns on the switch 16h and turns off the switch 16l (step S02). As a result, the off-bias voltage Vnh is applied to the gate of the semiconductor element 1. When the gate voltage Vg of the semiconductor element 1 becomes the off-bias voltage Vnh, the charge stored in the gate parasitic capacitances Cgs and Cgd of the semiconductor element 1 is discharged, and the gate charge Qg gradually decreases from Qh. When the gate voltage Vga gradually decreases toward the off-bias voltage Vnh and becomes less than the gate threshold voltage Vth, the semiconductor element 1 begins to turn off.

[0118] The freewheel operation determination circuit 19 compares the gate charge Qg detected by the gate charge detection circuit 18 with the threshold Qb (step S03). If the gate charge Qg is less than the threshold Qb (NO in S03), the freewheel operation determination circuit 19 determines that the diode of the semiconductor element 1 is not in freewheel operation (step S10).

[0119] On the other hand, if the gate charge quantity Qg is equal to or greater than the threshold value Qb (YES in S03), the freewheel operation determination circuit 19 then determines whether the current timing is during the dead time Td after the turn-off period of the semiconductor device 1 (step S04). The turn-off period can be determined based on the gate parasitic capacitances Cgd and Cgs of the semiconductor device 1 and the time constant of the gate resistor 17. Alternatively, it can be determined based on the fall time Tf of the semiconductor device 1a, etc., as described in the data sheet or the like.

[0120] If the current timing is during the turn-off period of the semiconductor element 1, the determination in S04 is NO. In this case, the freewheel operation determination circuit 19 determines that the diode of the semiconductor element 1 is not in freewheel operation (step S10).

[0121] On the other hand, if the current timing is during the dead time Td after the turn-off period of the semiconductor element 1 (YES in S04), the freewheel operation determination circuit 19 determines that the diode of the semiconductor element 1 is in freewheel operation (step S05). In this case, the off-bias switching circuit 16 turns off the switch 16h and turns on the switch 16l (step S06). As a result, the gate voltage Vg of the semiconductor element 1 is switched from the off-bias voltage Vnh to the off-bias voltage Vnl.

[0122] During the dead time Td, when another semiconductor element 1 connected in series to the semiconductor element 1 is turned on, the diode of the semiconductor element 1 performs a recovery operation, causing a steep change in the drain voltage Vds of the semiconductor element 1. While the drain voltage Vds changes over time (dv / dt), a displacement current (Cgd × dv / dt) flows through the gate-drain capacitance Cgd of the semiconductor element 1. As a result, the gate voltage Vg increases and the gate charge Qg decreases from Qa to 0.

[0123] The freewheel operation determination circuit 19 compares the gate charge Qb detected by the gate charge detection circuit 18 with the threshold Qb (step S07). If the gate charge Qg is equal to or greater than the threshold Qb (NO in S07), the freewheel operation determination circuit 19 determines that the diode of the semiconductor element 1 is in freewheel operation (step S05). Therefore, the off-bias switching circuit 16 keeps the switch 16l on (step S06) to maintain the gate voltage Vg of the semiconductor element 1 at the off-bias voltage Vnl.

[0124] On the other hand, if the gate charge Qg is less than the threshold Qb (YES in S07), the freewheel operation determination circuit 19 determines that the semiconductor device 1 has completed the freewheel operation (step S08). In response to the determination that the semiconductor device 1 has completed the freewheel operation, the off-bias switching circuit 16 turns off the switch 16l and turns on the switch 16h (step S09). As a result, the gate voltage Vg of the semiconductor device 1 is switched from the off-bias voltage Vnl to the off-bias voltage Vnh.

[0125] 9, threshold value Qb is used in both the process of determining whether semiconductor element 1 is in freewheeling operation (step S03) and the process of determining whether semiconductor element 1 has finished freewheeling operation (step S07). However, different threshold values ​​may be used for these two processes depending on the characteristics of semiconductor element 1. To reliably prevent self-turn-on of semiconductor element 1, it is desirable to carefully consider and determine the timing of the recovery operation of the diode of semiconductor element 1 and the timing of switching from off-bias voltage Vnl to off-bias voltage Vnh. Therefore, determining the threshold values ​​to be used for each process taking into account the characteristics of semiconductor element 1 is even more effective in preventing self-turn-on.

[0126] Effect of First Embodiment As described above, the gate drive circuit 10 according to the first embodiment is configured to determine whether or not the diode of the corresponding semiconductor element 1 is performing a freewheeling operation based on the detected value of the gate charge Qg of the semiconductor element 1. Therefore, it is possible to determine with a simple configuration whether or not the diode of the semiconductor element is performing a freewheeling operation without needing to install a sense terminal for detecting the direction of current flow in each semiconductor element 1.

[0127] Furthermore, when it is determined that the diode of the semiconductor element 1 is in freewheeling operation, the gate drive circuit 10 can temporarily lower the off-bias voltage based on the detected gate charge Qg, in accordance with the timing at which the diode of the semiconductor element 1 performs recovery operation in response to the turn-on of another semiconductor element 1 connected in series to the semiconductor element 1. This allows the off-bias voltage to be lowered just enough for the time required for the other semiconductor element 1 to turn on. Furthermore, a signal or the like for detecting the turn-on timing of the other semiconductor element 1 is not required. Therefore, with a simple configuration, the off-bias switching circuit 16, which is a circuit for suppressing self-turn-on of the semiconductor element 1, can be activated at an appropriate timing. As a result, it is possible to prevent self-turn-on of the semiconductor element 1 while suppressing the progression of degradation of the gate oxide film.

[0128] Second Embodiment In a second embodiment, an example of the circuit configuration of the gate drive circuit 10 according to the first embodiment will be described.

[0129] 10 is a diagram showing an example of the circuit configuration of the gate drive circuit 10a shown in FIG. 10. As shown in FIG. 10, the switch 15 is composed of an NPN transistor. The collector of the NPN transistor is connected to the power supply node 12, the emitter is connected to the output node 14, and the base is connected to the input terminal T1. The NPN transistor is turned on when it receives an H-level gate command signal GSWa (on command) at its base, and is turned off when it receives an L-level gate command signal GSWa (off command) at its base.

[0130] The gate charge detection circuit 18 includes a differential amplifier 30 and a gate charge calculator 32. The differential amplifier 30 functions as a voltage detector that detects the voltage across the gate resistor 17. The gate charge calculator 32 detects the gate current Ig based on the voltage across the gate resistor 17 and the resistance value of the gate resistor 17, and obtains the gate charge Qg by integrating the detected gate current Ig.

[0131] The freewheel operation determination circuit 19 includes a NOT circuit 40 , a delay circuit 42 , a one-shot circuit 44 , a comparator 46 , and an AND circuit 48 .

[0132] The comparator 46 compares the gate charge Qga calculated by the gate charge calculator 32 with a reference voltage Vref. The reference voltage Vref is a voltage value corresponding to the threshold Qb. When the gate charge Qga is greater than the reference voltage Vref (i.e., the threshold Qb), the comparator 46 outputs an H-level signal. When the gate charge Qga is smaller than the reference voltage Vref (threshold Qb), the comparator 46 outputs an L-level signal.

[0133] The NOT circuit 40 outputs an inverted signal of the gate command signal GSWa input to the input terminal T1.

[0134] The delay circuit 42 receives the output signal of the NOT circuit 40 and delays the output signal by a predetermined delay time to generate a delayed signal. Immediately after the gate command signal GSWa transitions from H level to L level, the gate charge Qga is Qh, which is greater than the threshold Qb, and it is erroneously determined that the diode of the semiconductor element 1a is in freewheeling operation. For this reason, the delay time in the delay circuit 42 is set based on the turn-off time of the semiconductor element 1a. Furthermore, when the semiconductor element 1a is performing a SW operation, the gate charge Qga decreases from Qh to 0 in response to the turn-off of the semiconductor element 1a, so a delay time is also provided to wait for the gate charge Qga to become smaller than the threshold Qb.

[0135] The one-shot circuit 44 generates a one-shot pulse signal in response to the output signal of the NOT circuit 40 transitioning from an L level to an H level. That is, when the one-shot circuit 44 receives an OFF command from the control device 130, it generates a one-shot pulse signal delayed by the turn-off time of the semiconductor element 1. The pulse width of the pulse signal is set based on the dead time Td. The pulse width of the pulse signal can be adjusted by a CR constant within the one-shot circuit 44 so as to be maintained for the dead time Td.

[0136] The AND circuit 48 receives the pulse signal from the one-shot circuit 44 at its first input terminal and the output signal from the comparator 46 at its second input terminal. The AND circuit 48 performs a logical OR operation on the two input signals and outputs the result of the operation. When the gate charge amount Qga is greater than the threshold value Qb, the output signal from the AND circuit 48 becomes H level for a period corresponding to the dead time Td, delayed by the turn-off time of the semiconductor element 1 from the timing of receiving an OFF command from the control device 130. The output signal from the AND circuit 48 is input to the off-bias switching circuit 16 and functions as a signal for switching the gate voltage Vg of the semiconductor element 1 from the off-bias voltage Vh to the off-bias voltage Vnl.

[0137] The off-bias switching circuit 16 includes switches 16l and 16h each made up of a PNP transistor, a NOT circuit 50, and an AND circuit 52.

[0138] The PNP transistor constituting the switch 16 h has an emitter connected to the output node 14 , a collector connected to the negative terminal of the off-bias power supply Vnh, and a base connected to the output terminal of the AND circuit 52 .

[0139] The PNP transistor constituting the switch 16 l has an emitter connected to the output node 14 , a collector connected to the negative terminal of the off-bias power supply Vnl, and a base connected to the output terminal of the NOT circuit 50 .

[0140] The NOT circuit 50 generates an inverted signal of the output signal of the AND circuit 48 included in the freewheel operation determination circuit 19, and inputs the generated inverted signal to the base of the switch 16l.

[0141] The AND circuit 52 receives the output signal of the AND circuit 48 at a first input terminal and the gate command signal GSWa at a second input terminal, calculates the logical AND of these two input signals, and inputs the result of the calculation to the base of the switch 16h.

[0142] The switch 16l is turned on while the output signal of the NOT circuit 50 is at L level, i.e., while the output signal of the AND circuit 48 is at H level. In other words, when the gate charge amount Qga is greater than the threshold value Qb, the switch 16l is turned on for a period corresponding to the dead time Td, which is delayed by the turn-off time of the semiconductor element 1 from the timing when the OFF command is received from the control device 130. In response to the switch 16l being turned on, an off-bias voltage Vnl is applied to the gate of the semiconductor element 1a.

[0143] The switch 16h is turned on when the gate command signal SWa is at L level and the switch 16l is turned off. In response to the switch 16h being turned on, the off-bias voltage Vnh is applied to the gate of the semiconductor element 1a.

[0144] 10 illustrates a configuration in which the switches 16l and 16h are configured as push-pull circuits of bipolar transistors, but the switches 16l and 16h are not limited to this. For example, the switches 16l and 16h may be configured as push-pull circuits of MOSFETs.

[0145] Embodiment 3 In the first embodiment, the gate drive circuit 10 has two types of off-bias power supplies Vnh and Vnl, and the gate voltage Vg of the semiconductor element 1 is switched between the off-bias voltage Vnh and the off-bias voltage Vnl according to the determination result of the freewheel operation determination circuit 19.

[0146] In the third embodiment, a configuration will be described in which one type of off-bias power supply Vn is used to switch the off-bias voltage.

[0147] 11 is a block diagram showing an example of the configuration of a gate drive circuit 10a according to embodiment 3. The gate drive circuit 10a drives a P-side semiconductor element 1a. The gate drive circuit 10a that drives the P-side semiconductor element 1a and the gate drive circuit 10b that drives the N-side semiconductor element 1b basically have a common configuration, so the following description will representatively explain the configuration of the gate drive circuit 10a.

[0148] As shown in FIG. 11 , a gate drive circuit 10 a according to the third embodiment includes an input terminal T1, output terminals T2 and T3, a control circuit 11, a switch 15, an off-bias switching circuit 16, a gate charge amount detection circuit 18, and a free-wheel operation determination circuit 19.

[0149] The gate drive circuit 10a according to the third embodiment differs from the gate drive circuit 10a according to the first embodiment shown in Fig. 7 in the configuration of the control circuit 11. The control circuit 11 has an on-bias power supply Vp for generating an on-bias voltage Vp to be applied to the gate of the semiconductor element 1a, and an off-bias power supply Vn for generating an off-bias voltage Vn to be applied to the gate of the semiconductor element 1a. The control circuit 11 differs from the control circuit 11 shown in Fig. 7 in that it has one type of off-bias power supply Vn.

[0150] The positive terminal of the on-bias power supply Vp is connected to the power supply node 12, and the negative terminal is connected to the reference node 13. The positive terminal of the off-bias power supply Vn is connected to the reference node 13, and the negative terminal is electrically connected to the output node 14.

[0151] The switch 16h of the off-bias switching circuit 16 is connected between the output node 14 and the reference node 13. The switch 16l is connected between the output node 14 and the negative terminal of the off-bias power supply Vn.

[0152] Control circuit 11 selectively turns on and off switch 15 and off-bias switching circuit 16 in response to gate command signal GSWa. Specifically, when gate command signal GSWa is at H level, control circuit 11 turns on switch 15 and turns off off-bias switching circuit 16. As a result, output node 14 is connected to power supply node 12, and on-bias power supply Vp is connected between output terminals T2 and T3. As a result, on-bias voltage Vp is applied between the gate and source of semiconductor element 1a.

[0153] On the other hand, when the gate command signal GSwa is at an L level, the control circuit 11 turns off the switch 15 and turns on the off-bias switching circuit 16. The off-bias switching circuit 16 selectively turns on the switches 16h and 16l based on the determination result provided by the freewheel operation determination circuit 19. When the switch 16h is turned on, the output node 14 is connected to the reference node 13, so that the gate and source of the semiconductor element 1a are at the same potential. In other words, 0 V is applied between the gate and source of the semiconductor element 1a.

[0154] When the switch 16l is turned on, the output node 14 is connected to the negative terminal of the off-bias power supply Vn, and the off-bias power supply Vn is connected between the output terminals T2 and T3. As a result, the off-bias voltage Vn is applied between the gate and source of the semiconductor element 1a. The off-bias voltage Vn is a voltage less than 0 V.

[0155] That is, in the third embodiment, the off-bias switching circuit 16 is configured to be able to switch the gate voltage Vga of the semiconductor element 1a between 0 V and the off-bias voltage Vn in accordance with the determination result of the freewheel operation determination circuit 19. By setting the off-bias voltage Vnh to 0 V in this way, only one type of off-bias power supply is required, thereby enabling the gate drive circuit 10a to be made smaller and less expensive.

[0156] The operation of gate drive circuit 10 according to the third embodiment is the same as that of gate drive circuit 10 according to the first embodiment shown in Figures 8 and 9. That is, the off-bias voltage is temporarily set to a voltage Vn less than 0 V only when the diode of semiconductor element 1 performs a recovery operation, and is set to 0 V otherwise, thereby making it possible to prevent self-turn-on of semiconductor element 1 and suppress the progression of degradation of the gate oxide film. Therefore, the same effects as those of the first embodiment can be obtained in the third embodiment.

[0157] Furthermore, according to the third embodiment, the magnitude of the off-bias voltage can be made smaller than in the first embodiment, and therefore damage to the oxide film of the gate can be reduced.

[0158] Fourth Embodiment In the first embodiment, the off-bias switching circuit 16 switches the gate voltage Vg of the semiconductor element 1 between the off-bias voltage Vnh and the off-bias voltage Vnl in accordance with the determination result of the freewheel operation determination circuit 19.

[0159] In the fourth embodiment, a configuration will be described in which the resistance value of the gate resistor of the semiconductor element 1 is switched in accordance with the determination result of the freewheel operation determination circuit 19. As will be described below, this configuration focuses on the fact that the gate voltage Vg momentarily rises in accordance with the displacement current flowing through the gate resistor during recovery operation of the diode of the semiconductor element 1. The gate drive circuit 10 is configured to suppress this rise in the gate voltage Vg by temporarily lowering the resistance value of the gate resistor in accordance with the timing of the recovery operation.

[0160] 12 is a block diagram showing a configuration example of a gate drive circuit 10a according to embodiment 4. The gate drive circuit 10a drives the P-side semiconductor element 1a. The gate drive circuit 10a that drives the P-side semiconductor element 1a and the gate drive circuit 10b that drives the N-side semiconductor element 1b basically have a common configuration, so the configuration of the gate drive circuit 10a will be representatively described below.

[0161] As shown in FIG. 12, the gate drive circuit 10a includes an input terminal T1, output terminals T2 and T3, a control circuit 11, switches 15a and 15b, a gate resistor 17, a gate charge detection circuit 18, a reflux operation determination circuit 19, and a gate resistor switching circuit 20.

[0162] The gate drive circuit 10a according to the third embodiment differs from the gate drive circuit 10a according to the first embodiment shown in FIG. 7 in that it has switches 15a and 15b and a gate resistance switching circuit 20 instead of the switch 15 and the off-bias switching circuit 16.

[0163] The control circuit 11 has an on-bias power supply Vp for generating an on-bias voltage Vp to be applied to the gate of the semiconductor element 1a, and an off-bias power supply Vn for generating an off-bias voltage Vn to be applied to the gate of the semiconductor element 1a. The positive terminal of the on-bias power supply Vp is connected to a power supply node 12, and the negative terminal is connected to a reference node 13. The positive terminal of the off-bias power supply Vn is connected to the reference node 13, and the negative terminal is electrically connected to an output node 14.

[0164] The switch 15a is connected between the power supply node 12 and the output node 14. The switch 15b is connected between the output node 14 and the negative terminal of the off-bias power supply Vn. The gate resistor 17 and the gate resistor switching circuit 20 are connected between the output node 14 and the output terminal T2.

[0165] The control circuit 11 selectively turns on and off the switches 15a and 15b in response to the gate command signal GSWa. Specifically, when the gate command signal GSWa is at H level, the control circuit 11 turns on the switch 15a and turns off the switch 15b. This connects the output node 14 to the power supply node 12, and therefore the on-bias power supply Vp is connected between the output terminals T2 and T3. As a result, the on-bias voltage Vp is applied between the gate and source of the semiconductor element 1a.

[0166] On the other hand, when gate command signal GSwa is at L level, control circuit 11 turns off switch 15a and turns on switch 15b. As a result, output node 14 is connected to the negative terminal of off-bias power supply Vn, and off-bias power supply Vn is connected between output terminals T2 and T3. As a result, off-bias voltage Vn is applied between the gate and source of semiconductor element 1a.

[0167] A gate charge detection circuit 18 is connected to both ends of the gate resistor 17. The gate charge detection circuit 18 calculates the gate current Iga from the voltage across the gate resistor 17 and integrates it over time to detect the gate charge Qga. To calculate the gate current Iga, the resistance of the gate resistor 17 is set to a fixed value Rg0.

[0168] The freewheel operation determination circuit 19 determines whether the diode of the semiconductor element 1a is performing a freewheel operation based on the detected value of the gate charge amount Qga. As described above, the freewheel operation determination circuit 19 determines whether the diode of the semiconductor element 1a is performing a freewheel operation by comparing the detected value of the gate charge amount Qg with the threshold value Qb.

[0169] The gate resistance switching circuit 20 has a variable resistor and is configured to be able to change the resistance value in accordance with the determination result provided by the freewheel operation determination circuit 19. As will be described later, the gate resistance switching circuit 20 switches the resistance value of the gate resistor Rga of the semiconductor element 1a between two different resistance values ​​in accordance with the determination result of the freewheel operation determination circuit 19.

[0170] Fig. 13 is a diagram showing an example of the circuit configuration of the gate drive circuit 10a shown in Fig. 12. The circuit configurations of the gate charge amount detection circuit 18 and the free-wheel operation determination circuit 19 are the same as the circuit configurations shown in Fig. 10, so their explanation will be omitted.

[0171] The switch 15a is composed of an NPN transistor. The collector of the NPN transistor is connected to the power supply node 12, the emitter is connected to the output node 14, and the base is connected to the input terminal T1. The NPN transistor is turned on when it receives an H-level gate command signal GSWa (on command) at its base, and is turned off when it receives an L-level gate command signal GSWa (off command) at its base.

[0172] The switch 15b is composed of a PNP transistor. The emitter of the PNP transistor is connected to the output node 14, the collector is connected to the negative terminal of the off-bias power supply Vn, and the base is connected to the input terminal T1. The PNP transistor is turned off when it receives an H-level gate command signal GSWa (on command) at its base, and is turned on when it receives an L-level gate command signal GSWa (off command) at its base.

[0173] The gate resistance switching circuit 20 includes a gate resistance Rgon for turning on the semiconductor element 1 a, a gate resistance Rgoff for turning off the semiconductor element 1 a, diodes D 1 and D 2 for preventing backflow, and a switch 60 .

[0174] Diode D1 and gate resistor Rgon are connected in series between output node 14 and gate resistor 17. Diode D1 allows a gate current Ig in the positive direction (the direction that charges gate parasitic capacitances Cgd and Cgs) to flow through gate resistor Rgon, while blocking a gate current Ig in the negative direction (the direction that discharges gate parasitic capacitances Cgd and Cgs) from flowing through gate resistor Rgon.

[0175] Diode D2 and gate resistor Rgoff are connected in series between output node 14 and gate resistor 17. Diode D2 allows negative gate current Ig to flow through gate resistor Rgoff, while blocking positive gate current Ig from flowing through gate resistor Rgoff.

[0176] The switch 60 is connected in parallel with the gate resistor Rgoff. By turning on the switch 60, the gate resistor Rgoff is short-circuited and its resistance value becomes 0. The on / off of the switch 60 is controlled by the freewheel operation determination circuit 19.

[0177] Specifically, when it is determined that the diode of the semiconductor element 1a is in freewheeling operation, the freewheeling operation determination circuit 19 turns on the switch 60. By turning on the switch 60, the gate resistance Rga of the semiconductor element 1a in freewheeling operation becomes the resistance value Rg0 of the gate resistor 17.

[0178] On the other hand, when the diode of semiconductor element 1a is not in freewheeling operation, or when it is determined that the freewheeling operation of the diode of semiconductor element 1a has ended, freewheeling operation determination circuit 19 turns off switch 60. By turning off switch 60, gate resistance Rga of semiconductor element 1a becomes the sum of the resistance value Rg0 of gate resistor 17 and the resistance value of gate resistance Rgon or gate resistance Rgoff.

[0179] That is, when the semiconductor element 1a is turned on, the switch 15a is turned on and an on-bias voltage Vp is applied to the gate of the semiconductor element 1a, causing a gate current Ig to temporarily flow in the forward direction from the power supply node 12 via the switch 15a, the output node 14, the diode D1, the gate resistor Rgon, and the gate resistor 17. The resistance value of the gate resistor Rga of the semiconductor element 1a is Rg0+Rgon.

[0180] On the other hand, when the semiconductor element 1a is turned off, the switch 15b is turned on and the off-bias voltage Vn is applied to the gate of the semiconductor element 1a. As a result, a gate current Ig temporarily flows in the negative direction from the gate of the semiconductor element 1a through the gate resistor 17, the gate resistor Rgoff, the diode D2, the output node 14, and the switch 15b. The resistance value of the gate resistor Rga of the semiconductor element 1a is Rg0+Rgoff.

[0181] As described above, while the semiconductor element 1a is turned off and the diode of the semiconductor element 1a is performing a freewheeling operation, the switch 60 is temporarily turned on. As a result, the gate resistor Rgoff is bypassed, and the resistance value of the gate resistor Rga decreases from Rg0+Rgoff to Rg0.

[0182] While a steep change dv / dt occurs in the drain voltage Vds due to the recovery operation of the diode of the semiconductor element 1a, a displacement current (Cgd × dv / dt) flows through the gate-drain capacitance Cgd of the semiconductor element 1. This displacement current flows through the gate resistance Rga, causing the gate voltage Vga to rise. The increase ΔVga in the gate voltage Vga can be expressed as the product of the displacement current and the resistance value of the gate resistance Rga (ΔVgs = (Cgd × dv / dt) × Rga). In the fourth embodiment, the increase ΔVga can be reduced by temporarily lowering the resistance value of the gate resistance Rga while the displacement current is flowing. This makes it possible to suppress the increase in the gate voltage Vga, thereby preventing self-turn-on of the semiconductor element 1a.

[0183] When the gate charge Qg decreases from Qa to 0 due to the recovery operation of the diode of the semiconductor element 1a, the freewheel operation determination circuit 19 determines that the freewheel operation of the diode of the semiconductor element 1a has ended and turns off the switch 60. As a result, the resistance value of the gate resistor Rga switches from Rg0 to Rg0+Rgoff.

[0184] Here, if the resistance value of the gate resistor Rga is small, the increase in the gate voltage Vga can be suppressed, preventing self-turn-on of the semiconductor element 1a. However, oscillations due to stray inductance components in the gate wiring can occur, potentially causing false gate firing. Furthermore, the semiconductor element 1a is more susceptible to electromagnetic noise, which can similarly trigger false gate firing. The gate drive circuit 10a according to the fourth embodiment temporarily reduces the resistance value of the gate resistor Rga to Rg0 only when the diode of the semiconductor element 1a performs a recovery operation, and otherwise maintains the resistance value of the gate resistor Rga at Rgoff + Rg. This makes it possible to damp gate oscillations while preventing self-turn-on of the semiconductor element 1a. As a result, false firing of the semiconductor element 1a can be prevented.

[0185] (Operation of Gate Drive Circuit According to Fourth Embodiment) Next, the operation of gate drive circuit 10a according to the fourth embodiment will be described.

[0186] 14 is a time chart showing the operation of the semiconductor elements 1a and 1b. The waveforms of the drain voltage Vds, drain current Id, gate voltage Vg, gate charge Qg, switch 60 of gate resistance switching circuit 20, and gate command signal GSW of the semiconductor elements 1a and 1b are shown in FIG. 14. For each waveform, the solid line indicates the waveform of the P-side semiconductor element 1a, and the dashed line indicates the waveform of the N-side semiconductor element 1b.

[0187] The time chart shown in Fig. 14 differs from the time chart shown in Fig. 5 in the waveform of the gate voltage Vga of the semiconductor element 1a. The other waveforms are the same as those shown in Fig. 5, so detailed description will be omitted.

[0188] As shown in Figure 14, at time t0, gate command signal GSWa is at L level and gate command signal GSWb is at H level. In gate drive circuit 10a, control circuit 11 turns off switch 15a and turns on switch 15b in response to the L-level gate command signal GSWa. The gate voltage Vga of semiconductor element 1a becomes off-bias voltage Vn, and semiconductor element 1a is turned off. Therefore, drain current Ida = 0 and drain voltage Vdsa = VDC. Since gate parasitic capacitances Cgd and Cgs of semiconductor element 1b are discharged, gate charge Qga is 0.

[0189] The freewheel operation determination circuit 19 compares the gate charge Qga with the threshold Qb. Because Qga<Qb, the freewheel operation determination circuit 19 determines that the diode of the semiconductor element 1a is not in freewheel operation, and turns off the switch 60 of the gate resistance switching circuit 20. Therefore, the resistance value of the gate resistor Rga of the semiconductor element 1a becomes Rg0+Rgoff.

[0190] At time t1, when gate command signal GSWb transitions from H level to L level, semiconductor element 1b is turned off. In gate drive circuit 10b, control circuit 11 responds to L-level gate command signal GSWb by turning off switch 15a and turning on switch 15b, thereby applying off-bias voltage Vn to the gate of semiconductor element 1b. As gate voltage Vgb of semiconductor element 1b becomes off-bias voltage Vn, gate charge Qgb of semiconductor element 1b gradually decreases from Qh. As discharge of gate parasitic capacitances Cgs and Cgd is completed, gate charge Qgb becomes 0.

[0191] The freewheel operation determination circuit 19 compares the gate charge Qgb with the threshold Qb. Because Qgb<Qb, the freewheel operation determination circuit 19 determines that the diode of the semiconductor element 1b is not in freewheel operation, and keeps the switch 60 of the gate resistance switching circuit 20 in the off state. Therefore, the resistance value of the gate resistor Rgb of the semiconductor element 1b becomes Rg0+Rgoff.

[0192] In response to the semiconductor element 1b being turned off, a reflux current flows through the diode of the semiconductor element 1a. During a transition period in which the drain voltage Vdsa changes abruptly as the reflux current begins to flow through the diode, a displacement current (Cgd×dv / dt) flows through the gate-drain capacitance Cgd of the semiconductor element 1a. This displacement current flows through the gate resistor 17 and the gate resistor Rga of the gate resistance switching circuit 20, causing the gate voltage Vga to decrease. Furthermore, the gate parasitic capacitances Cgd and Cgs are charged by the displacement current, so that the gate charge Qga increases from 0 to Qa.

[0193] The period from time t1 to time t2 corresponds to dead time Td, during which a return current continues to flow through the diode of the semiconductor element 1a.

[0194] At time t2, when the gate command signal GSWa transitions from L level to H level, the semiconductor element 1a is turned on. Specifically, in response to the H-level gate command signal GSWa, the gate drive circuit 10a turns on the switch 15a and turns off the switch 15b, thereby switching the voltage applied to the gate of the semiconductor element 1a from the off-bias voltage Vn to the off-bias voltage Vp. A gate current Iga flows from the power supply node 12 to the gate of the semiconductor element 1a via the gate resistor Rgon and the gate resistor 17 of the gate resistance switching circuit 20. As the gate parasitic capacitances Cgs and Cgd are charged, the gate charge Qga gradually increases from Qa to Qh. A reflux current flows between the drain and source of the semiconductor element 1a, and the semiconductor element 1a is performing a reflux operation.

[0195] When the gate command signal GSWa transitions from H level to L level at time t3, the semiconductor element 1a is turned off. In the gate drive circuit 10a, the control circuit 11 responds to the L-level gate command signal GSWa by turning off the switch 15a and turning on the switch 15b, thereby applying the off-bias voltage Vn to the gate of the semiconductor element 1a.

[0196] As the gate voltage Vga of the semiconductor element 1a becomes the off-bias voltage Vn, the gate charge Qgb gradually decreases from Qh. The gate voltage Vga gradually decreases from the on-bias voltage Vp toward the off-bias voltage Vn. When the gate voltage Vga becomes less than the gate threshold voltage Vth, the semiconductor element 1a begins to turn off. When the semiconductor element 1a turns off, a reflux current begins to flow through the diode of the semiconductor element 1a. Therefore, the drain voltage Vdsa and the drain current Ida do not change and are maintained at constant values ​​even when the semiconductor element 1a is turned off.

[0197] During the dead time Td from time t3 to t4, the diode of the semiconductor element 1a performs freewheeling operation, so the gate charge Qga does not decrease to 0 but remains at Qa. The freewheeling operation determination circuit 19 compares the gate charge Qga during the dead time Td immediately after the semiconductor element 1a is turned off with the threshold Qb. Because Qga (= Qa) > Qb, the freewheeling operation determination circuit 19 determines that the diode of the semiconductor element 1a is performing freewheeling operation. In response to the determination that the diode of the semiconductor element 1a is performing freewheeling operation, the freewheeling operation determination circuit 19 turns on the switch 60 at time t5 after the semiconductor element 1a is turned off. As a result, the resistance value of the gate resistor Rga of the semiconductor element 1a is switched from Rgoff + Rg0 to Rg0.

[0198] The timing for switching the gate resistance Rga from Rgoff+Rg0 to Rg0 is preferably set to the timing after the gate current Iga has finished flowing in response to the turn-off of the semiconductor element 1a (time t3). This timing can be determined based on the gate parasitic capacitances Cgd and Cgs of the semiconductor element 1a and the time constant of the gate resistance 17. Alternatively, the timing for switching the gate voltage Vga can be determined based on the fall time Tf of the semiconductor element 1a, which is described in the data sheet or the like.

[0199] When the gate command signal GSWb transitions from L level to H level at time t4, the semiconductor element 1b is turned on. Specifically, in response to the H-level gate command signal GSWb, the gate drive circuit 10b turns on the switch 15a and turns off the switch 15b, thereby switching the voltage applied to the gate of the semiconductor element 1b from the off-bias voltage Vn to the on-bias voltage Vp.

[0200] When semiconductor element 1b is turned on, drain current Idb begins to flow through semiconductor element 1b, causing the diode of semiconductor element 1a to undergo recovery operation, resulting in a steep change in drain voltage Vdsa of semiconductor element 1a. While the drain voltage Vdsa changes over time (dv / dt), a displacement current (Cgd × dv / dt) flows through gate-drain capacitance Cgd of semiconductor element 1a. This displacement current flows through gate resistor 17 and switch 60, causing gate charge Qga to decrease from Qa to 0.

[0201] However, during the dead time Td from time t3 to t4, the resistance value of the gate resistor Rga of the semiconductor element 1a drops from Rgoff+Rg0 to Rg0. Therefore, even if a displacement current flows through the gate resistor 17 and the gate resistance switching circuit 20 after time t4, the increase amount ΔVga of the gate voltage Vga is suppressed and the gate voltage Vga does not exceed the gate threshold voltage Vth. This prevents the semiconductor element 1a from self-turning. This prevents an excessive short-circuit current from flowing through the semiconductor elements 1a and 1b, which would otherwise lead to destruction of the semiconductor elements 1a and 1b.

[0202] In the gate drive circuit 10a, the freewheel operation determination circuit 19 compares the gate charge Qga with the threshold Qb. Because Qga<Qb, the freewheel operation determination circuit 19 determines that the semiconductor element 1a has completed the freewheel operation. In response to the determination that the semiconductor element 1a has completed the freewheel operation, the freewheel operation determination circuit 19 turns off the switch 60 at time t6. As a result, the resistance value of the gate resistor Rga of the semiconductor element 1a is switched from Rg0 to Rgoff+Rg0.

[0203] That is, the gate drive circuit 10a temporarily reduces the resistance value of the gate resistor Rga of the semiconductor element 1a from Rgoff+Rg0 to Rg0 in accordance with the timing when the diode of the semiconductor element 1a performs recovery operation, thereby preventing the gate voltage Vga from momentarily rising in response to the recovery operation and exceeding the gate threshold voltage Vth.

[0204] Furthermore, the gate drive circuit 10a sets the resistance value of the gate resistor Rga to Rgoff+Rg except when the diode of the semiconductor element 1a performs recovery operation, thereby damping the oscillation of the gate of the semiconductor element 1a and, as a result, making it possible to prevent erroneous firing of the semiconductor element 1a.

[0205] The above has described the operating waveforms when the semiconductor element 1b performs a switching operation and the semiconductor element 1a performs a freewheeling operation when the phase current IL<0. When the phase current IL>0, the semiconductor element 1a performs a switching operation and the semiconductor element 1b performs a freewheeling operation, and the operating waveforms can be considered to be similar to those in FIG.

[0206] 15 is a flowchart showing the operation of gate drive circuit 10 according to embodiment 4. Fig. 15 shows the operation of gate drive circuit 10 when turning off corresponding semiconductor element 1 in accordance with an L-level gate command signal GSW (OFF command) from control device 130. The determination of whether semiconductor element 1 is performing a reflux operation when receiving an H-level gate command signal GSW (ON command) does not affect the switching of gate resistor Rg, so a description thereof will be omitted.

[0207] The flowchart shown in FIG. 15 differs from the flowchart shown in FIG. 9 in that steps S02, S06, and S09 are replaced with steps S11 to S14.

[0208] 15, when the semiconductor element 1 is in the on state, an on-bias voltage Vp is applied to the gate of the semiconductor element 1. In this state, when an L-level gate command signal GSW (off command) is received from the control device 130 (step S01), the control circuit 11 of the gate drive circuit 10 turns off the switch 15a and also turns off the switch 15b (step S11). As a result, the off-bias voltage Vn is applied to the gate of the semiconductor element 1. The gate resistance switching circuit 20 maintains the switch 60 in the off state (step S13). Therefore, the resistance value of the gate resistance Rg of the semiconductor element 1 is Rgoff+Rg.

[0209] As the gate voltage Vg of the semiconductor element 1 becomes the off-bias voltage Vn, the gate charge Qg gradually decreases from Qh. As the gate voltage Vga gradually decreases toward the off-bias voltage Vn and becomes less than the gate threshold voltage Vth, the semiconductor element 1 begins to turn off. The freewheel operation determination circuit 19 compares the gate charge Qg detected by the gate charge detection circuit 18 with a threshold Qb (step S03). If the gate charge Qg is less than the threshold Qb (NO in S03), the freewheel operation determination circuit 19 determines that the diode of the semiconductor element 1 is not in freewheel operation (step S10).

[0210] On the other hand, if the gate charge quantity Qg is equal to or greater than the threshold value Qb (YES in S03), the freewheel operation determination circuit 19 then determines whether the current timing is during the dead time Td after the turn-off period of the semiconductor device 1 (step S04). The turn-off period can be determined based on the gate parasitic capacitances Cgd and Cgs of the semiconductor device 1 and the time constant of the gate resistor 17. Alternatively, it can be determined based on the fall time Tf of the semiconductor device 1a, etc., as described in the data sheet or the like.

[0211] If the current timing is during the turn-off period of the semiconductor element 1, the determination in S04 is NO. In this case, the freewheel operation determination circuit 19 determines that the diode of the semiconductor element 1 is not in freewheel operation (step S10).

[0212] On the other hand, if the current timing is during the dead time Td after the turn-off period of the semiconductor element 1 (YES in S04), the freewheel operation determination circuit 19 determines that the diode of the semiconductor element 1 is in freewheel operation (step S05). In this case, the gate resistance switching circuit 20 turns on the switch 60 (step S13). As a result, the resistance value of the gate resistance Rg of the semiconductor element 1 is switched from Rgoff+Rg to Rg.

[0213] During the dead time Td, when another semiconductor element 1 connected in series to the semiconductor element 1 is turned on, the diode of the semiconductor element 1 performs a recovery operation, causing a steep change in the drain voltage Vds of the semiconductor element 1. While the drain voltage Vds changes over time (dv / dt), a displacement current (Cgd × dv / dt) flows through the gate-drain capacitance Cgd of the semiconductor element 1. As a result, the gate voltage Vg increases and the gate charge Qg decreases from Qa to 0.

[0214] The freewheel operation determination circuit 19 compares the gate charge Qb detected by the gate charge detection circuit 18 with the threshold Qb (step S07). If the gate charge Qg is equal to or greater than the threshold Qb (NO in S07), the freewheel operation determination circuit 19 determines that the semiconductor device 1 is in freewheel operation (step S05). Therefore, the gate resistance switching circuit 20 keeps the switch 60 on (step S13) to maintain the resistance value of the gate resistor Rg of the semiconductor device 1 at Rg.

[0215] On the other hand, if the gate charge quantity Qg is less than the threshold value Qb (YES in S07), the freewheel operation determination circuit 19 determines that the semiconductor device 1 has completed the freewheel operation (step S08). In response to the determination that the semiconductor device 1 has completed the freewheel operation, the gate resistance switching circuit 20 turns off the switch 60 (step S14). As a result, the resistance value of the gate resistance Rg of the semiconductor device 1 is switched from Rg to Rgoff+Rg.

[0216] In the flowchart of Figure 15, as in the flowchart of Figure 9, threshold value Qb is used in both the process of determining whether semiconductor element 1 is in reflux operation (step S03) and the process of determining whether semiconductor element 1 has finished reflux operation (step S07).However, depending on the characteristics of semiconductor element 1, different threshold values ​​may be used in these two processes.

[0217] <Effects of Fourth Embodiment> As described above, the gate drive circuit 10 according to the fourth embodiment is configured to determine whether or not the diode of the corresponding semiconductor element 1 is performing a freewheeling operation based on the detected value of the gate charge Qg of the semiconductor element 1. Therefore, it is not necessary to install a sense terminal for detecting the direction of current flow in each semiconductor element 1, and it is possible to easily determine whether or not the diode of the semiconductor element is performing a freewheeling operation.

[0218] Furthermore, when it is determined that the diode of the semiconductor element 1 is in freewheeling operation, the gate drive circuit 10 can temporarily lower the resistance of the gate resistor of the semiconductor element 1 based on the detected gate charge Qg, in accordance with the timing at which the diode of the semiconductor element 1 performs recovery operation in response to the turn-on of another semiconductor element 1 connected in series to the semiconductor element 1. This allows the resistance of the gate resistor to be lowered just enough for the time required for the other semiconductor element 1 to turn on, thereby suppressing an increase in the gate voltage Vg of the semiconductor element 1 and preventing self-turn-on. Furthermore, a signal or the like for detecting the turn-on timing of the other semiconductor element 1 is not required. Therefore, with a simple configuration, the gate resistance switching circuit 20, which is a circuit for suppressing self-turn-on of the semiconductor element 1, can be activated at an appropriate timing. As a result, it is possible to suppress gate vibration while preventing self-turn-on of the semiconductor element 1.

[0219] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0220] 1, 1a to 1f power semiconductor element, 10, 10a to 10f gate drive circuit, 11, 21 control circuit, 12 power supply node, 12U, 12V, 12W leg, 13 reference node, 14 output node, 15, 15a, 15b, 16l, 16h, 25a, 25b, 60 switch, 16 off bias switching circuit, 17, 26, Rgon, Rgoff gate resistor, 18 gate charge amount detection circuit, 19 freewheel operation determination circuit, 20 gate resistance switching circuit, 30 differential amplifier, 32 gate charge amount calculator, 40, 50 NOT circuit, 42 delay circuit, 44 one-shot circuit, 46 comparator, 48, 52 AND circuit, 100 power conversion device, 110 DC power supply, 120 motor, 130 control device, D1, D2 diode, PL DC positive bus, NL DC negative bus, Vp on-bias power supply (on-bias voltage), Vn, Vnh, Vnl off-bias power supplies (off-bias voltage), T1 input terminal, T2, T3 output terminal.

Claims

1. A drive circuit for driving a power semiconductor device, wherein the power semiconductor device has a first main electrode on the high potential side, a second main electrode on the low potential side, a gate serving as a control electrode, and a diode reversely connected in parallel between the first main electrode and the second main electrode, a control circuit that selectively applies an on-bias voltage and an off-bias voltage to the gate of the power semiconductor device according to a control signal input from the outside, a detection circuit that detects the gate charge amount of the power semiconductor device, and a determination circuit that determines whether or not the diode of the power semiconductor device is performing a freewheeling operation based on the gate charge amount detected by the detection circuit. A drive circuit for a power semiconductor device.

2. The drive circuit further includes an off-bias switching circuit that switches the off-bias voltage applied to the gate between a first voltage and a second voltage lower than the first voltage, when turning off the power semiconductor device according to the control signal, the control circuit applies the off-bias voltage having the first voltage to the gate, when the gate charge amount after turning off the power semiconductor device is greater than a first threshold value, the determination circuit determines that the diode of the power semiconductor device is performing the freewheeling operation, and the off-bias switching circuit switches the off-bias voltage from the first voltage to the second voltage in response to the determination that the diode of the power semiconductor device is performing the freewheeling operation. The drive circuit for a power semiconductor device according to Claim 1.

3. when the gate charge amount after turning off the power semiconductor device is greater than the first threshold value, and when the gate charge amount decreases to less than a second threshold value, the determination circuit determines that the freewheeling operation has ended, and the off-bias switching circuit switches the off-bias voltage from the second voltage to the first voltage in response to the determination that the freewheeling operation has ended. The drive circuit for a power semiconductor device according to Claim 2.

4. when the gate charge amount after turning off the power semiconductor device is less than the first threshold value, the determination circuit determines that the power semiconductor device is not performing the freewheeling operation, The off-bias switching circuit maintains the off-bias voltage at the first voltage in response to a determination that the power semiconductor device is not performing the reflux operation. The drive circuit for a power semiconductor device according to claim 2.

5. The drive circuit for a power semiconductor device according to claim 2, wherein the first voltage is 0V.

6. The power semiconductor device further includes a gate resistance switching circuit that switches between a first resistance value and a second resistance value smaller than the first resistance value. When turning off the power semiconductor device according to the control signal, the control circuit applies the off-bias voltage to the gate through the gate resistance having the first resistance value. When the gate charge amount after turning off the power semiconductor device is greater than a first threshold value, the determination circuit determines that the diode of the power semiconductor device is performing the reflux operation. The gate resistance switching circuit switches the gate resistance from the first resistance value to the second resistance value in response to a determination that the diode of the power semiconductor device is performing the reflux operation. The drive circuit for a power semiconductor device according to claim 1.

7. When the gate charge amount after turning off the power semiconductor device is greater than the first threshold value, and when the gate charge amount drops below a second threshold value, the determination circuit determines that the reflux operation has ended. The gate resistance switching circuit switches the gate resistance from the second resistance value to the first resistance value in response to a determination that the reflux operation has ended. The drive circuit for a power semiconductor device according to claim 6.

8. When the gate charge amount after turning off the power semiconductor device is smaller than the first threshold value, the determination circuit determines that the power semiconductor device is not performing the reflux operation. The gate resistance switching circuit maintains the gate resistance at the first resistance value in response to a determination that the power semiconductor device is not performing the reflux operation. The drive circuit for a power semiconductor device according to claim 6.

9. A DC positive bus and a DC negative bus; A first and a second power semiconductor device connected in series between the DC positive bus and the DC negative bus; A power conversion device comprising the drive circuit according to any one of claims 1 to 8 for driving each of the first and second power semiconductor devices.