Power amplifier

Abstract

The present invention is a power amplifier comprising: a main circuit provided with a first-stage transistor and a next-stage transistor that are cascode-connected, the main circuit amplifying input signals and outputting high-frequency amplified signals; and a bias circuit that applies a bias voltage to the next-stage transistor. The bias circuit is a constant-voltage circuit that generates a bias voltage of a constant voltage on the basis of a power supply that is supplied from outside to a power supply terminal.

Description

Power amplifier

[0001] This application claims priority to Japanese Patent Application No. 2023-019122, filed on February 10, 2023, the contents of which are incorporated herein by reference.

[0002] Patent Document 1 listed below discloses a radio frequency power amplifier that is more efficient and consumes less power than conventional ones. This radio frequency power amplifier includes an input terminal, an output terminal, an input matching circuit, an output matching circuit, a first power supply terminal, a second power supply terminal, a base bias terminal, a base bias resistor, a cascode amplifier in which a first radio frequency amplification transistor and a second radio frequency amplification transistor are stacked in two stages, a load inductor connected between the collector of the second transistor and the first power supply terminal, a first voltage dividing resistor connected between the base of the second radio frequency amplification transistor and the second power supply terminal, a second voltage dividing resistor connected between the base of the second radio frequency amplification transistor and a ground terminal, and a radio frequency grounding capacitor connected between the base of the second radio frequency amplification transistor and the ground terminal.

[0003] In this radio frequency power amplifier, a radio frequency signal is input to the input terminal, appropriate voltages are applied to the base bias terminal, the first power supply terminal, and the second power supply terminal, and an amplified signal can be output from the output terminal by appropriately matching the input matching circuit and the output matching circuit with the base of the first transistor and the collector of the second transistor, respectively, at the frequency of the radio frequency signal. Also, in this radio frequency power amplifier, adjusting the ratio between the values ​​of the first and second voltage dividing resistors makes it easy to control the base voltage (cascode base bias voltage) of the second radio frequency amplifying transistor, allowing the second radio frequency amplifying transistor to be appropriately biased.

[0004] Japanese Patent Application Publication No. 2012-147307

[0005] In a circuit configuration using multiple power supply terminals, if different external power supplies are to be connected to each power supply terminal, the user of the circuit would need to prepare multiple external power supplies, which is uneconomical. One way to eliminate this uneconomical solution is to eliminate the second power supply terminal, connect first and second voltage dividing resistors between the base of the second high frequency amplifier transistor, and adjust the base voltage (cascode base bias voltage) of the second high frequency amplifier transistor by adjusting the ratio of the voltage dividing resistor values.

[0006] However, when such a solution is adopted, the following problem may occur: If there is parasitic resistance (for example, wiring resistance of wiring between the voltage source and the first power terminal) for some reason between the first power terminal and the voltage source that applies voltage to the first power terminal, the collector current of the first high-frequency amplifying transistor and the second high-frequency amplifying transistor will increase as the magnitude of the radio frequency signal increases, resulting in a decrease in the base voltage and collector voltage of the second transistor.

[0007] As a result, the collector voltage of the first high-frequency amplifier transistor decreases in response to the decrease in the cascode base bias voltage, and the Early effect reduces the current gain of the first high-frequency amplifier transistor, resulting in a decrease in output power. Note that when separate external power supplies are connected to the first power supply terminal and the second power supply terminal, the base voltage (cascode base bias voltage) of the second transistor does not decrease even if there is resistance between the first power supply terminal and the external power supply that applies a voltage to the first power supply terminal, or between the second power supply terminal and the external power supply that applies a voltage to the second power supply terminal. Therefore, the collector voltage of the first high-frequency amplifier transistor is maintained, and the output power does not decrease significantly.

[0008] The present invention has been made in view of the above circumstances, and has as its object to provide a power amplifier capable of suppressing a decrease in output power due to a voltage drop in the bias voltage.

[0009] A first aspect of the present invention is a power amplifier comprising: a main circuit including a cascode-connected first-stage transistor and a second-stage transistor, amplifying an input signal and outputting a high-frequency amplified signal; and a bias circuit applying a bias voltage to the second-stage transistor, wherein the bias circuit is a constant voltage circuit that generates a constant bias voltage based on a power supply externally supplied to a power supply terminal.

[0010] A second aspect of the present invention is the power amplifier of the first aspect, wherein the bias circuit generates a reference constant voltage by a base-emitter voltage of one bipolar transistor or a base-emitter voltage of a plurality of bipolar transistors connected in series.

[0011] A third aspect of the present invention is the power amplifier according to the second aspect, wherein the number of the bipolar transistors is two.

[0012] A fourth aspect of the present invention is the power amplifier of any one of the first to third aspects, wherein the main circuit is a differential amplifier circuit including a pair of the first-stage transistor and the next-stage transistor, amplifying a pair of input signals and outputting a pair of amplified signals.

[0013] A fifth aspect of the present invention is the power amplifier according to the fourth aspect, further comprising a pair of bias terminals for individually setting the amplification factor of the first-stage transistor.

[0014] In a sixth aspect of the present invention, the bias circuit includes a first bias NPN bipolar transistor having an emitter terminal connected to a ground line and a base terminal and a collector terminal connected in common, a second bias NPN bipolar transistor having an emitter terminal connected to the base terminal and the collector terminal of the first bias NPN bipolar transistor, a third bias NPN bipolar transistor having a base terminal connected to the collector terminal of the second bias NPN bipolar transistor, a first bias resistor having one end connected to the base terminal and the collector terminal of the first bias NPN bipolar transistor and the other end connected to a power supply line, and a second bias resistor having one end connected to the power supply line and the other end connected to the collector terminal of the second bias NPN bipolar transistor and the collector terminal of the third bias NPN bipolar transistor. a second bias resistor connected to a base terminal of a second bias NPN bipolar transistor; a third bias resistor having one end connected to the base terminal of the second bias NPN bipolar transistor and the other end connected to the emitter terminal of the third bias NPN bipolar transistor; a fourth bias resistor having one end connected to the ground line and the other end connected to the base terminal of the second bias NPN bipolar transistor and one end of the third bias resistor; and a capacitor having one end connected to the ground line and the other end connected to the emitter terminal of the third bias NPN bipolar transistor and the other end of the third bias resistor, wherein the bias voltage is output from the emitter terminal of the third bias NPN bipolar transistor.

[0015] a first-stage NPN bipolar transistor having a base terminal connected to an output terminal of the input matching circuit and an emitter terminal connected to a ground terminal; an amplifying resistor having one end connected to the output terminal of the input matching circuit and the base terminal of the first-stage transistor and the other end connected to a bias terminal; a second-stage NPN bipolar transistor having an emitter terminal connected to the collector terminal of the first-stage NPN bipolar transistor and a base terminal to which the bias voltage is input; an inductor having one end connected to the collector terminal of the second-stage NPN bipolar transistor and the other end connected to a power supply terminal; and an output matching circuit having an input end connected to the collector terminal of the second-stage NPN bipolar transistor and one end of the inductor, and an output end connected to a radio-frequency output terminal.

[0016] In an eighth aspect of the present invention, the main circuit includes an input matching circuit having one input end connected to a first high frequency input terminal and the other input end connected to a second high frequency input terminal; a first initial stage NPN bipolar transistor having a base terminal connected to one output end of the input matching circuit and an emitter terminal connected to a ground terminal; a second initial stage NPN bipolar transistor having a base terminal connected to the other output end of the input matching circuit and an emitter terminal connected to the ground terminal; a first amplifying resistor having one end connected to one output end of the input matching circuit and the base terminal of the first initial stage NPN bipolar transistor and the other end connected to a first bias terminal; a second amplifying resistor having one end connected to the other output end of the input matching circuit and the base terminal of the second initial stage NPN bipolar transistor and the other end connected to a second bias terminal; and a second amplifying resistor having an emitter terminal connected to the collector terminal of the first initial stage NPN bipolar transistor and having a base terminal to which the bias voltage is input. a first next-stage NPN bipolar transistor connected to the collector terminal of the second initial-stage NPN bipolar transistor and having a base terminal to which the bias voltage is input; a first inductor having one end connected to the collector terminal of the first next-stage NPN bipolar transistor and the other end connected to a power supply terminal; a second inductor having one end connected to the collector terminal of the second next-stage NPN bipolar transistor and the other end connected to a power supply terminal; and an output matching circuit having one input end connected to the collector terminal of the first next-stage NPN bipolar transistor and one end of the first inductor, and the other input end connected to the collector terminal of the second next-stage NPN bipolar transistor and one end of the second inductor, one output end connected to the first high-frequency output terminal, and the other output end connected to the second high-frequency output terminal.

[0017] A ninth aspect of the present invention is the power amplifier according to any one of the first to eighth aspects, wherein an emitter length of the second-stage transistor is set to be longer than an emitter length of the first-stage transistor.

[0018] According to the present invention, it is possible to provide a power amplifier that can suppress a decrease in output power caused by a voltage drop in the bias voltage.

[0019] FIG. 1 is a circuit diagram showing the configuration of a radio frequency power amplifier according to a first embodiment of the present invention; FIG. 2 is a first characteristic diagram showing the performance of the radio frequency power amplifier according to the first embodiment of the present invention; FIG. 3 is a second characteristic diagram showing the performance of the radio frequency power amplifier according to the first embodiment of the present invention; FIG. 4 is a circuit diagram showing the configuration of a radio frequency power amplifier according to a second embodiment of the present invention; and FIG. 5 is a characteristic diagram showing the performance of the radio frequency power amplifier according to the second embodiment of the present invention.

[0020] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. First Embodiment First, a first embodiment of the present invention will be described with reference to Figures 1, 2A, and 2B. As shown in FIG. 1 , the radio frequency power amplifier A according to the first embodiment includes a radio frequency input terminal RFin, an input matching circuit Sin, a first transistor Tr1 (first-stage NPN bipolar transistor), a first resistor R1, a bias terminal Vb, a second transistor Tr2 (next-stage NPN bipolar transistor), an inductor L, an output matching circuit Sout, a radio frequency output terminal RFout, a ground terminal GND, a power supply terminal Vcc, a third transistor Tr3 (first bias NPN bipolar transistor), a second resistor R2 (first bias resistor), a fourth transistor Tr4 (second bias NPN bipolar transistor), a third resistor R3 (second bias resistor), a fifth transistor Tr5 (third bias NPN bipolar transistor), a fourth resistor R4 (third bias resistor), a fifth resistor R5 (fourth bias resistor), and a capacitor C.

[0021] Of these components, the input matching circuit Sin, the first transistor Tr1, the second transistor Tr2, the first resistor R1, the inductor L, and the output matching circuit Sout constitute a main circuit M. In addition, the third transistor Tr3, the fourth transistor Tr4, the fifth transistor Tr5, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the capacitor C constitute a bias circuit B as shown in the figure.

[0022] The radio frequency input terminal RFin is an input terminal of the radio frequency power amplifier A (main circuit M) and is connected to the input terminal of the input matching circuit Sin. A radio frequency signal of a predetermined frequency is input to the radio frequency input terminal RFin from an external source. This radio frequency signal is an input signal for the radio frequency power amplifier A and is input to the input terminal of the input matching circuit Sin.

[0023] The input matching circuit Sin has an input terminal connected to the radio frequency input terminal RFin and an output terminal connected to the base terminal of the first transistor Tr1 and one end of the first resistor R1. The input matching circuit Sin is a passive circuit for achieving impedance matching of the radio frequency signal (input signal), suppressing reflection of the radio frequency signal (input signal) and allowing more power to be input to the base terminal of the first transistor Tr1.

[0024] As shown in the figure, the first transistor Tr1 is an NPN bipolar transistor, and its base terminal is connected to the output terminal of the input matching circuit Sin and one end of the first resistor R1. The emitter terminal of the first transistor Tr1 is connected to the ground terminal GND, and its collector terminal is connected to the emitter terminal of the second transistor Tr2. The first transistor Tr1 is cascode-connected to the second transistor Tr2 and corresponds to the initial-stage transistor of the present invention.

[0025] The first resistor R1 has a predetermined first resistance value, one end of which is connected to the output end of the input matching circuit Sin and the base terminal of the first transistor Tr1, and the other end of which is connected to the bias terminal Vb. This first resistor R1 is provided between the bias terminal Vb and the base terminal of the first transistor Tr1 in order to set the base voltage (bias voltage) of the first transistor Tr1.

[0026] The bias terminal Vb is a terminal to which a predetermined bias voltage is supplied from an external bias power supply. This bias terminal Vb is connected to the other end of the first resistor R1. The base voltage (bias voltage) of the first transistor Tr1 is a parameter that sets the gain of the first transistor Tr1. The bias terminal Vb is provided so that the gain of the first transistor Tr1 can be set externally.

[0027] The second transistor Tr2 is an NPN bipolar transistor like the first transistor Tr1, and has a base terminal connected to the output terminal Wo of the bias circuit B. The emitter terminal of the second transistor Tr2 is connected to the collector terminal of the first transistor Tr1, and the collector terminal is connected to one end of the inductor L and the input terminal of the output matching circuit Sout.

[0028] The second transistor Tr2 is cascode-connected to the first transistor Tr1 and corresponds to the next-stage transistor of the present invention. A constant base bias voltage (output voltage Vc) is applied to the second transistor Tr2 from the output terminal Wo of the bias circuit B, causing the second transistor Tr2 to function as an amplifying element together with the first transistor Tr1. That is, an amplified signal (high-frequency signal) obtained by amplifying a high-frequency signal (input signal) in the main circuit M is generated at the collector terminal of the second transistor Tr2.

[0029] The inductor L has a predetermined inductance, and one end of the inductor L is connected to the collector terminal of the second transistor Tr2 and the input terminal of the output matching circuit Sout, and the other end is connected to the power supply terminal Vcc and the power supply line Wd of the bias circuit B. This inductor L is a load of the second transistor Tr2.

[0030] The output matching circuit Sout has an input terminal connected to the collector terminal of the second transistor Tr2 and one end of the inductor L, and an output terminal connected to the radio frequency output terminal RFout. This output matching circuit Sout is a passive circuit for matching the impedance of the amplified signal (radio frequency signal), suppressing reflection of the amplified signal (radio frequency signal) and allowing more power to be input to the next-stage circuit externally connected to the radio frequency output terminal RFout.

[0031] Here, the above-mentioned input matching circuit Sin and output matching circuit Sout are typically configured with a combination of capacitors, inductors, and transmission lines. Furthermore, the input matching circuit Sin and output matching circuit Sout are more typically L-shaped, inverted L-shaped, T-shaped, or π-shaped network circuits configured with capacitors, inductors, and transmission lines. The input matching circuit Sin and output matching circuit Sout may include a capacitor connected in series to block DC current to the radio frequency input terminal RFin or the radio frequency output terminal RFout.

[0032] The radio frequency output terminal RFout is the output terminal of the radio frequency power amplifier A (main circuit M) and is connected to the output terminal of the output matching circuit Sout. This radio frequency output terminal RFout outputs a radio frequency amplified signal (output signal) obtained by amplifying an input signal (radio frequency signal) by the radio frequency power amplifier A (main circuit M) to the next stage circuit.

[0033] As shown in the figure, the ground terminal GND is connected to the emitter terminal of the first transistor Tr1 and the ground line Wg of the bias circuit B. This ground terminal GND is externally grounded, i.e., the ground terminal GND is externally set to a ground potential.

[0034] The power supply terminal Vcc is connected to the other end of the inductor L and the power supply line Wd of the bias circuit B. This power supply terminal Vcc is connected to an external DC voltage power supply, that is, the power supply terminal Vcc is set to a power supply voltage that is a potential higher than the ground potential of the ground terminal GND.

[0035] The main circuit M in the first embodiment includes the above-described input matching circuit Sin, first transistor Tr1, second transistor Tr2, first resistor R1, inductor L, and output matching circuit Sout. Such a main circuit M amplifies an input signal (radio frequency signal) input via a radio frequency input terminal RFin in cooperation with a bias circuit B, and outputs a radio frequency amplified signal (output signal) to a next-stage circuit via a radio frequency output terminal RFout.

[0036] Furthermore, with regard to the first transistor Tr1 (initial stage transistor) and the second transistor Tr2 (next stage transistor) in such a main circuit M, the emitter length of the second transistor Tr2 (next stage transistor) is set to be equal to or greater than the emitter length of the first transistor Tr1 (initial stage transistor). By setting the emitter length of the second transistor Tr2 (next stage transistor) to be greater than the emitter length of the first transistor Tr1 (initial stage transistor), it is possible to reduce phase distortion in the main circuit M.

[0037] Regarding the bias circuit B in the first embodiment, the third transistor Tr3 is an NPN bipolar transistor like the first transistor Tr1 and the second transistor Tr2 described above. The base terminal of the third transistor Tr3 is connected to its own collector terminal, one end of the second resistor R2, and the emitter terminal of the fourth transistor Tr4.

[0038] The third transistor Tr3 has an emitter terminal connected to the ground line Wg of the bias circuit B, i.e., the ground terminal GND, and a collector terminal connected to the base terminal of the third transistor Tr3 itself, one end of the second resistor R2, and the emitter terminal of the fourth transistor Tr4. The base-emitter voltage of the third transistor Tr3 is the same as the emitter-collector voltage.

[0039] That is, the third transistor Tr3 functions as a diode because the base terminal and collector terminal of the third transistor Tr3 are commonly connected (so-called diode connection). In this third transistor Tr3, the base terminal and collector terminal function as the anode terminal of the diode, and the emitter terminal functions as the cathode terminal of the diode. When the third transistor Tr3 is in the ON state (conducting state), the base-emitter voltage (emitter-collector voltage) is set (clamped) to the breakdown voltage of the PN junction of the third transistor Tr3.

[0040] The second resistor R2 has a predetermined second resistance value, and one end of the second resistor R2 is connected to the base terminal and collector terminal of the third transistor Tr3 and the emitter terminal of the fourth transistor Tr4, and the other end is connected to the power supply line Wd of the bias circuit B, i.e., one end of the third resistor R3 and the collector terminal of the fifth transistor Tr5. This second resistor R2 is a current limiting resistor that sets the current (collector current) of the third transistor Tr3.

[0041] The fourth transistor Tr4 is an NPN bipolar transistor like the third transistor Tr3, and has a base terminal connected to one end of the fourth resistor R4 and the other end of the fifth resistor R5, an emitter terminal connected to the base terminal and collector terminal of the third transistor Tr3 and one end of the second resistor R2, and a collector terminal connected to one end of the third resistor R3 and the base terminal of the fifth transistor Tr5.

[0042] That is, the fourth transistor Tr4 is connected in series to the diode-connected third transistor Tr3. Therefore, the base voltage of the fourth transistor Tr4 in the ON state (conducting state) is V ＢＥ１ The base-emitter voltage V in the ON state (conducting state) of the fourth transistor Tr4 is ＢＥ２ The constant voltage is obtained by adding

[0043] Here, the base voltage of the fourth transistor Tr4 in the ON state (conducting state) is the base-emitter voltage V of the two (plural) bipolar transistors (the third transistor Tr3 and the fourth transistor Tr4) connected in series. ＢＥ１ , V ＢＥ２ is a constant reference voltage generated by

[0044] The third resistor R3 has a predetermined third resistance value, and one end of the third resistor R3 is connected to the power supply line Wd of the bias circuit B, i.e., the other end of the second resistor R2, and the collector terminal of the fifth transistor Tr5, and the other end is connected to the collector terminal of the fourth transistor Tr4 and the base terminal of the fifth transistor Tr5. This third resistor R3 is a current-limiting resistor that sets the current (collector current) of the fourth transistor Tr4. In other words, the current (collector current) of the fourth transistor Tr4 is set by the third resistance value.

[0045] The fifth transistor Tr5 is an NPN bipolar transistor like the third transistor Tr3 and the fourth transistor Tr4, and its base terminal is connected to one end of the third resistor R3 and the collector terminal of the fourth transistor Tr4. The fifth transistor Tr5 has its emitter terminal connected to the other end of the fourth resistor R4 and the other end of the capacitor C, and its collector terminal connected to the power supply line Wd of the bias circuit B, i.e., the other end of the second resistor R2, and one end of the third resistor R3. The emitter terminal of the fifth transistor Tr5 is the output terminal Wo of the bias circuit B, and outputs an output voltage Vc to the main circuit M.

[0046] The fourth resistor R4 has a predetermined fourth resistance value, and one end of the fourth resistor R4 is connected to the base terminal of the fourth transistor Tr4 and the other end of the fifth resistor R5, and the other end is connected to the emitter terminal of the fifth transistor Tr5 and the other end of the capacitor C. The other end of the fourth resistor R4, like the emitter terminal of the fifth transistor Tr5, is the output terminal Wo of the bias circuit B. The fourth resistor R4, together with the fifth resistor R5 connected in series with the fourth resistor R4, constitutes a resistive voltage divider circuit.

[0047] The fifth resistor R5 has a predetermined fifth resistance value, and one end of the fifth resistor R5 is connected to the ground line Wg of the bias circuit B, i.e., the emitter terminal of the third transistor Tr3, and one end of the capacitor C, and the other end is connected to the base terminal of the fourth transistor Tr4 and one end of the fourth resistor R4. The fifth resistor R5 constitutes a resistive voltage divider circuit together with the fourth resistor R4 connected in series with the fifth resistor R5.

[0048] One end of the capacitor C is connected to the ground line Wg of the bias circuit B, i.e., the ground terminal GND, the emitter terminal of the third transistor Tr3, and one end of the fifth resistor R5, and the other end is connected to the output terminal Wo of the bias circuit B, i.e., the emitter terminal of the fifth transistor Tr5 and the other end of the fourth resistor R4. This capacitor C is provided to reduce the AC impedance at the output terminal Wo of the bias circuit B.

[0049] Such a bias circuit B is a constant voltage circuit including a third transistor Tr3, a fourth transistor Tr4, a fifth transistor Tr5, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a capacitor C. That is, the bias circuit B supplies a constant output voltage Vc from the output terminal to the base terminal (control terminal) of the second transistor Tr2 in the main circuit M as a base bias voltage, thereby causing the main circuit M to perform an amplification operation.

[0050] Next, the operation and performance of the high-frequency power amplifier A according to the first embodiment will be described in detail with reference to FIGS.

[0051] In this high frequency power amplifier A, the second resistance value of the second resistor R2 is set so that the third transistor Tr3, which functions as a diode, is in the ON state (conducting state). In the ON state (conducting state), the base-emitter voltage (base-collector voltage) V ＢＥ１ is the breakdown voltage of the PN junction that physically constitutes the third transistor Tr3, and is a first constant voltage that is not affected by the power supply voltage applied to the power supply line Wd via the power supply terminal Vcc.

[0052] The fourth transistor Tr4 is set to an ON state (conductive state) by the third resistor R3, the fifth transistor Tr5, the fourth resistor R4, and the fifth resistor R5. That is, the fifth transistor Tr5, the fourth resistor R4, and the fifth resistor R5 set the base voltage of the fourth transistor Tr4 so that the fourth transistor Tr4 is set to an ON state (conductive state). The third resistor R3 sets the ON current (collector current) of the fourth transistor Tr4.

[0053] The base-emitter voltage V of the fourth transistor Tr4 in the ON state (conducting state) ＢＥ２ is the breakdown voltage of the PN junction that physically constitutes the fourth transistor Tr4. In other words, the base-emitter voltage of the fourth transistor Tr4 is a second constant voltage that is not affected by the power supply voltage applied to the power supply line Wd via the power supply terminal Vcc.

[0054] The fourth transistor Tr4 functions as a diode and has a collector voltage equal to the first reference voltage V ＢＥ１ Therefore, the base voltage of the fourth transistor Tr4 is set to the first constant voltage V ＢＥ１ to the second constant voltage V ＢＥ２ The reference constant voltage (V ＢＥ１ +V ＢＥ２ )

[0055] The base voltage of the fifth transistor Tr5 is a voltage obtained by dividing the power supply voltage by the third resistor R3 and the series circuit of the third transistor Tr3 and the fourth transistor Tr4, and the fifth transistor Tr5 is set to the ON state (conducting state). Then, the fourth transistor Tr4 is set to the ON state (conducting state), and the voltage difference between the base terminal of the fourth transistor Tr4 and the ground line Wg (ground potential) becomes equal to the reference constant voltage (V ＢＥ１ +V ＢＥ２ )

[0056] When the fourth resistance value is Ra and the fifth resistance value is Rb, the voltage difference between the emitter terminal of the fifth transistor Tr5 and the ground line Wg (ground potential), that is, the output voltage Vc of the bias circuit B, is determined by the fourth resistance value Ra, the fifth resistance value Rb, and the reference constant voltage (V ＢＥ１ +V ＢＥ２ ) is given by the following equation (1): Vc = (1 + Ra / Rb) (V ＢＥ１ +V ＢＥ２ ) (1)

[0057] That is, the output voltage Vc of the bias circuit B is the base-emitter voltage V of the third transistor Tr3. ＢＥ１ (first constant voltage) and the base-emitter voltage V of the fourth transistor Tr4 ＢＥ２ The output voltage Vc of the bias circuit B is determined only by the second constant voltage (Vcc), the fourth resistance value Ra of the fourth resistor R4, and the fifth resistance value Rb of the fifth resistor R5. The output voltage Vc of the bias circuit B does not depend on the power supply voltage applied to the power supply line Wd via the power supply terminal Vcc.

[0058] Fig. 2A shows the input / output characteristics of the high-frequency power amplifier A. Fig. 2A is an example of the input / output characteristics of the high-frequency power amplifier A obtained by analysis assuming that there is a parasitic resistance of 0, 1, 2, or 5 Ω between the external DC voltage power supply and the power supply terminal Vcc. Fig. 2B shows a reference example in which the base bias voltage of the second transistor Tr2 is generated by resistively dividing the power supply voltage of the power supply terminal Vcc.

[0059] 2A and 2B, the horizontal axis represents the input power (dBm) to the radio frequency power amplifier, and the vertical axis represents the output power (dBm) of the radio frequency power amplifier. The frequency of the input signal to radio frequency power amplifier A is 28 GHz. As shown in FIGS. 2A and 2B, when the parasitic resistance between the external DC voltage power supply and the power supply terminal Vcc is 0 Ω, the input / output characteristics of radio frequency power amplifier A and the input / output characteristics of the reference example are almost the same, but the output power of the reference example becomes smaller than the output power of radio frequency power amplifier A as the value of the parasitic resistance increases.

[0060] FIG. 3 shows the oP1dB characteristics of radio frequency power amplifier A. oP1dB is a general figure of merit used to evaluate the gain linearity of a current amplifier and is defined as the output power when the gain is 1 dB lower than when a small signal is applied. FIG. 3 shows the analysis results of oP1dB for radio frequency power amplifier A, obtained by assuming that there are parasitic resistances of 0, 1, 2, and 5 Ω between the external DC voltage power supply and the power supply terminal Vcc. Note that in FIG. 3, the characteristics of radio frequency power amplifier A are indicated as "A," and a comparative example S is added, showing a case in which the base bias voltage of second transistor Tr2 is generated by resistively dividing the power supply voltage at power supply terminal Vcc.

[0061] 3, the horizontal axis represents the value (Ω) of parasitic resistance, and the vertical axis represents the oP1dB (dBm) of radio frequency power amplifier A. Fig. 3 shows that when the parasitic resistance between the external DC voltage power supply and the power supply terminal Vcc is 0Ω, the oP1dB of radio frequency power amplifier A and the oP1dB of comparative example S are approximately the same, but that as the value of parasitic resistance increases, the oP1dB of radio frequency power amplifier A remains higher than the oP1dB of comparative example S.

[0062] Furthermore, Figure 4 shows the small signal gain characteristics of the high frequency power amplifier A. This Figure 4 shows the analysis results of the small signal gain obtained assuming that there are parasitic resistances of 0, 1, 2, and 5 Ω between the external DC voltage power supply and the power supply terminal Vcc. In this Figure 4, the horizontal axis represents the value of the parasitic resistance (Ω), and the vertical axis represents the small signal gain (dB). Note that in Figure 4, the characteristics of the high frequency power amplifier A are indicated as "A," and a comparative example S is added, showing a case in which the base bias voltage of the second transistor Tr2 is generated by resistively dividing the power supply voltage of the power supply terminal Vcc.

[0063] FIG. 4 shows that when the parasitic resistance between the external DC voltage power supply and the power supply terminal Vcc is 0 Ω, the small signal gain of the high frequency power amplifier A is approximately the same as the small signal gain of the comparative example S, but that as the value of the parasitic resistance increases, the small signal gain of the high frequency power amplifier A is maintained higher than the small signal gain of the comparative example S.

[0064] In the radio frequency power amplifier A according to the first embodiment, the bias circuit B supplies a base bias voltage (output voltage Vc) that is independent of the power supply voltage when current is applied to the power supply line Wd via the power supply terminal Vcc to the second transistor Tr2 of the main circuit M. Therefore, according to the first embodiment, it is possible to provide a radio frequency power amplifier A that can suppress a decrease in output power due to a voltage drop in the base bias voltage of the second transistor Tr2.

[0065] The base terminal of the fifth transistor Tr5 is connected to the wiring between the third resistor R3 and the collector terminal of the fourth transistor Tr4, and when the fifth transistor Tr5 is turned off (non-conductive), the fourth transistor Tr4 is also set to the off state (non-conductive). As a result, the base voltage of the fifth transistor Tr5 rises, and the fifth transistor Tr5 returns to the on state (conductive).

[0066] That is, in the radio frequency power amplifier A according to the first embodiment, the bias circuit B starts up spontaneously, so there is no need to provide a separate starter circuit that forcibly starts the bias circuit B. Therefore, according to the first embodiment, it is possible to simplify the circuit configuration of the radio frequency power amplifier A.

[0067] Second Embodiment Next, a second embodiment of the present invention will be described with reference to Figures 5 and 6. As shown in Figure 5, a radio frequency power amplifier A1 according to the second embodiment includes a main circuit M1 instead of the main circuit M of the radio frequency power amplifier A described above, a first radio frequency input terminal RFin1 and a second radio frequency input terminal RFin2 instead of the radio frequency input terminal RFin, a first bias terminal Vb1 and a second bias terminal Vb2 instead of the bias terminal Vb, and a first radio frequency output terminal RFout1 and a second radio frequency output terminal RFout2 instead of the radio frequency output terminal RFout.

[0068] The main circuit M1 includes a pair of the main circuits M of the first embodiment. That is, as shown in the figure, the main circuit M1 includes an input matching circuit Sin12, an eleventh transistor Tr11 (first initial-stage NPN bipolar transistor), an eleventh resistor R11 (first amplifying resistor), a twenty-first transistor Tr21 (first subsequent-stage NPN bipolar transistor), a first inductor L1, a twelfth transistor Tr12 (second initial-stage NPN bipolar transistor), a twelfth resistor R12 (second amplifying resistor), a twenty-second transistor Tr22 (second subsequent-stage NPN bipolar transistor), a second inductor L2, and an output matching circuit Sout12.

[0069] The eleventh transistor Tr11 and the twelfth transistor Tr12 correspond to the first-stage transistors of the present invention in the radio frequency power amplifier A1 according to the second embodiment, and the twenty-first transistor Tr21 and the twenty-second transistor Tr22 correspond to the next-stage transistors of the present invention in the radio frequency power amplifier A1 according to the second embodiment.

[0070] The first radio frequency input terminal RFin1, together with the second radio frequency input terminal RFin2, is an input terminal of the radio frequency power amplifier A1 (main circuit M1), and is connected to one of a pair of input terminals of the input matching circuit Sin12. A first radio frequency signal of a predetermined frequency is input from the outside to the radio frequency input terminal RFin1. This first radio frequency signal is the first input signal of the radio frequency power amplifier A, and is input to one of the pair of input terminals of the input matching circuit Sin12.

[0071] The second radio frequency input terminal RFin2, together with the first radio frequency input terminal RFin1, is an input terminal of the radio frequency power amplifier A1 (main circuit M1) and is connected to the other of the pair of input terminals of the input matching circuit Sin12. A second radio frequency signal of a predetermined frequency is input from the outside to the second radio frequency input terminal RFin2. This second radio frequency signal is a second input signal of the radio frequency power amplifier A and is input to the other of the pair of input terminals of the input matching circuit Sin12.

[0072] The input matching circuit Sin12 has a pair of input terminals and a pair of output terminals. One of the pair of input terminals of this input matching circuit Sin12 is connected to the first radio frequency input terminal RFin1, and the other input terminal is connected to the second radio frequency input terminal RFin2. Furthermore, one of the pair of output terminals of this input matching circuit Sin12 is connected to the base terminal of the eleventh transistor Tr11 and one end of the eleventh resistor R11, and the other output terminal is connected to the base terminal of the twelfth transistor Tr12 and one end of the twelfth resistor R12.

[0073] Similar to the input matching circuit Sin of the first embodiment, the input matching circuit Sin12 is a passive circuit for achieving impedance matching of the high-frequency signal (input signal). The input matching circuit Sin12 suppresses reflection of the first high-frequency signal (first input signal) and the second high-frequency signal (second input signal), and inputs more power of the first high-frequency signal (first input signal) to the eleventh transistor Tr11 and more power of the second high-frequency signal (second input signal) to the base terminal of the twelfth transistor Tr12.

[0074] The eleventh transistor Tr11 is an NPN bipolar transistor as shown in the figure, and has a base terminal connected to one output terminal of the input matching circuit Sin12 and one end of the eleventh resistor R11. The emitter terminal of the eleventh transistor Tr11 is connected to the ground terminal GND and the emitter terminal of the twelfth transistor Tr12, and the collector terminal is connected to the emitter terminal of the twenty-first transistor Tr21.

[0075] The resistor R11 has a predetermined resistance value, one end of which is connected to one output end of the input matching circuit Sin12 and the base terminal of the transistor Tr11, and the other end of which is connected to the first bias terminal Vb1. The resistor R11 is provided between the first bias terminal Vb1 and the base terminal of the transistor Tr11 in order to set the base voltage (bias voltage) of the transistor Tr11.

[0076] The first bias terminal Vb1 is a terminal to which a predetermined bias voltage is supplied from an external bias power supply. This first bias terminal Vb1 is connected to the other end of the eleventh resistor R11. The base voltage (bias voltage) of the eleventh transistor Tr11 is a parameter that sets the gain of the eleventh transistor Tr11. The first bias terminal Vb1 is provided separately from the second bias terminal Vb2 so that the gain of the eleventh transistor Tr11 can be set externally.

[0077] The twenty-first transistor Tr21 is an NPN bipolar transistor like the eleventh transistor Tr11, and has a base terminal connected to the output terminal Wo of the bias circuit B and the base terminal of the twenty-second transistor Tr22. The twenty-first transistor Tr21 has an emitter terminal connected to the collector terminal of the eleventh transistor Tr11, and a collector terminal connected to one end of the first inductor L1 and one input end of the output matching circuit Sout12.

[0078] The twenty-first transistor Tr21 is cascode-connected to the eleventh transistor Tr11, and performs an amplification function together with the eleventh transistor Tr11 when a predetermined base bias voltage is applied from the output terminal Wo of the bias circuit B. That is, a first amplified signal, which is the first high-frequency signal (first input signal) amplified by the main circuit M1, is generated at the collector terminal of the twenty-first transistor Tr21.

[0079] The first inductor L1 has a predetermined first inductance, and one end of the first inductor L1 is connected to the collector terminal of the transistor Tr21 and one input terminal of the output matching circuit Sout12, and the other end is connected to the power supply terminal Vcc, the power supply line Wd of the bias circuit B, and the other end of the second inductor L2. This first inductor L1 is a load of the transistor Tr21.

[0080] The twelfth transistor Tr12 is an NPN bipolar transistor as shown in the figure, and has a base terminal connected to the other output terminal of the input matching circuit Sin12 and one end of the twelfth resistor R12. The emitter terminal of the twelfth transistor Tr12 is connected to the ground terminal GND and the emitter terminal of the eleventh transistor Tr11, and a collector terminal connected to the emitter terminal of the twenty-second transistor Tr22.

[0081] The twelfth resistor R12 has a predetermined twelfth resistance value, one end of which is connected to the other output end of the input matching circuit Sin12 and the base terminal of the twelfth transistor Tr12, and the other end of which is connected to the bias terminal Vb. The twelfth resistor R12 is provided between the bias terminal Vb and the base terminal of the twelfth transistor Tr12 in order to set the base voltage (bias voltage) of the twelfth transistor Tr12.

[0082] The second bias terminal Vb2 is a terminal to which a predetermined bias voltage is supplied from an external bias power supply. The second bias terminal Vb2 is connected to the other end of the twelfth resistor R12. The base voltage (bias voltage) of the twelfth transistor Tr12 is a parameter that sets the amplification degree of the twelfth transistor Tr12.

[0083] The second bias terminal Vb2 is provided separately from the first bias terminal Vb1 so that the amplification factor of the twelfth transistor Tr12 can be set externally. The first bias terminal Vb1 and the second bias terminal Vb2 correspond to a pair of bias terminals in the present invention.

[0084] The 22nd transistor Tr22 is an NPN bipolar transistor like the 12th transistor Tr12, and has a base terminal connected to the output terminal Wo of the bias circuit B and the base terminal of the 21st transistor 21. The 22nd transistor Tr22 has an emitter terminal connected to the collector terminal of the 12th transistor Tr12, and a collector terminal connected to one end of the second inductor L2 and the other input end of the output matching circuit Sout12.

[0085] The 22nd transistor Tr22 is cascode-connected to the 12th transistor Tr12, and performs an amplification function together with the 12th transistor Tr12 when a predetermined base bias voltage is applied from the output terminal Wo of the bias circuit B. That is, a second amplified signal, which is the second high-frequency signal (second input signal) amplified by the main circuit M1, is generated at the collector terminal of the 22nd transistor Tr22.

[0086] The second inductor L2 has a predetermined second inductance, and one end of the second inductor L2 is connected to the collector terminal of the second transistor Tr22 and the other input terminal of the output matching circuit Sout12, and the other end is connected to the power supply terminal Vcc, the power supply line Wd of the bias circuit B, and the other end of the first inductor L1. This second inductor L2 is a load of the second transistor Tr22.

[0087] The output matching circuit Sout12 has a pair of input terminals and a pair of output terminals. One of the pair of input terminals of this output matching circuit Sout12 is connected to the collector terminal of the twenty-first transistor Tr21 and one end of the first inductor L1, and the other input terminal is connected to the collector terminal of the twenty-second transistor Tr22 and one end of the second inductor L2. Furthermore, one of the pair of output terminals of this output matching circuit Sout12 is connected to the first high-frequency output terminal RFout1, and the other output terminal is connected to the second high-frequency output terminal RFout2.

[0088] The output matching circuit Sout12 is a passive circuit for achieving impedance matching of the first amplified signal and the second amplified signal, which are high-frequency signals. The output matching circuit Sout12 suppresses power reflection of the first amplified signal and the second amplified signal, allowing more power of the first amplified signal to be input to a next-stage circuit externally connected to the first high-frequency output terminal RFout1, and allowing more power of the second amplified signal to be input to a next-stage circuit externally connected to the second high-frequency output terminal RFout2.

[0089] The first radio frequency output terminal RFout1, together with the second radio frequency output terminal RFout2, is an output terminal of the radio frequency power amplifier A1 (main circuit M1), and is connected to one of a pair of output terminals of the output matching circuit Sout12. This first radio frequency output terminal RFout1 outputs a first output signal, which is a first input signal (first radio frequency signal) amplified by the radio frequency power amplifier A1 (main circuit M1), to a next-stage circuit.

[0090] The second high-frequency output terminal RFout2, together with the first high-frequency output terminal RFout1, is an output terminal of the high-frequency power amplifier A1 (main circuit M1), and is connected to the other of the pair of output terminals of the output matching circuit Sout12. This second high-frequency output terminal RFout2 outputs a second output signal, which is a second input signal (second high-frequency signal) amplified by the high-frequency power amplifier A1 (main circuit M1), to the next-stage circuit.

[0091] Here, of the components of the main circuit M1, namely, the input matching circuit Sin12, the eleventh transistor Tr11, the eleventh resistor R11, the twenty-first transistor Tr21, the first inductor L1, the twelfth transistor Tr12, the twelfth resistor R12, the twenty-second transistor Tr22, the second inductor L2, and the output matching circuit Sout12, the input matching circuit Sin12 has the same performance for the first high-frequency signal (first input signal) and the second high-frequency signal (second input signal).

[0092] The output matching circuit Sout12 has the same performance for the first amplified signal and the second amplified signal. The eleventh transistor Tr11 and the twelfth transistor Tr12 are a pair of transistors and have the same characteristics. The twenty-first transistor Tr21 and the twenty-second transistor Tr22 are a pair of transistors, like the eleventh transistor Tr11 and the twelfth transistor Tr12, and have the same characteristics.

[0093] The eleventh resistance value of the eleventh resistor R11 and the twelfth resistance value of the twelfth resistor R12 are set to the same value. The first inductance of the first inductor L1 and the second inductance of the second inductor L2 are set to the same value. Furthermore, the phase of the first high-frequency signal (first input signal) input from the outside to the first high-frequency input terminal RFin1 is inverted with respect to the phase of the second high-frequency signal (second input signal) input from the outside to the second high-frequency input terminal RFin2.

[0094] That is, the main circuit M1 is a differential amplifier circuit that includes a pair of cascode-connected first-stage transistor (eleventh transistor Tr11) and next-stage transistor (twelfth transistor Tr12) and next-stage transistor (twenty-second transistor Tr22), as well as a pair of cascode-connected first-stage transistor (eleventh transistor Tr11) and next-stage transistor (twenty-first transistor Tr21), and that differentially amplifies a pair of input signals (first high-frequency signal and second high-frequency signal) that are in an inverted phase relationship, and outputs a pair of output signals (first output signal and second output signal).

[0095] Furthermore, with regard to the 11th transistor Tr11 and the 12th transistor Tr12 (first-stage transistors) and the 21st transistor Tr21 and the 22nd transistor Tr22 (next-stage transistors) of the main circuit M1, the emitter lengths of the 21st transistor Tr21 and the 22nd transistor Tr22 (next-stage transistors) are set to be equal to or greater than the emitter lengths of the 11th transistor Tr11 and the 12th transistor Tr12 (first-stage transistors).

[0096] By setting the emitter lengths of the 21st transistor Tr21 and the 22nd transistor Tr22 (next-stage transistors) to be greater than the emitter lengths of the 11th transistor Tr11 and the 12th transistor Tr12 (first-stage transistors), it is possible to reduce phase distortion in the main circuit M1.

[0097] The bias circuit B in the second embodiment is similar to the bias circuit B in the first embodiment, but in the main circuit M1 (differential amplifier circuit), the bias circuit B is cascode-connected to the pair of 11th transistor Tr11 and 12th transistor Tr12, and supplies the same base bias voltage to the pair of 21st transistor Tr21 and 22nd transistor Tr22.

[0098] Fig. 6 shows the oP1dB characteristics of the radio frequency power amplifier A1. This Fig. 6 shows the oP1dB characteristics of the radio frequency power amplifier A1 obtained by analyzing oP1dB assuming that there is a parasitic resistance of 0, 1, 2, or 5 Ω between the external DC voltage power supply and the power supply terminal Vcc, and also shows the oP1dB characteristics of the radio frequency power amplifier A according to the first embodiment as a comparative example. In Fig. 6, the horizontal axis represents the value of the parasitic resistance (Ω), the left vertical axis represents the oP1dB (dBm) of the radio frequency power amplifier A1, and the right vertical axis represents the oP1dB (dBm) of the radio frequency power amplifier A.

[0099] 6 shows that when the parasitic resistance between the external DC voltage power supply and the power supply terminal Vcc is 0Ω, the oP1dB value of the radio frequency power amplifier A1 is approximately 3 dB greater than the oP1dB value of the radio frequency power amplifier A, and that as the value of the parasitic resistance increases, the extent to which the oP1dB value decreases becomes smaller than that of the radio frequency power amplifier A. In other words, the radio frequency power amplifier A1 of the second embodiment is able to suppress the decrease in output power more effectively than the radio frequency power amplifier A of the first embodiment.

[0100] In the radio frequency power amplifier A1 according to the second embodiment, the bias circuit B supplies a base bias voltage (output voltage Vc) that is independent of the power supply voltage when current is applied to the power supply line Wd via the power supply terminal Vcc to the first transistor Tr21 and the second transistor Tr22 of the main circuit M1. Therefore, according to the second embodiment, it is possible to provide a radio frequency power amplifier A1 that can further suppress a decrease in output power due to a voltage drop in the base bias voltages of the first transistor Tr21 and the second transistor Tr22.

[0101] The present invention is not limited to the above-described embodiments, and the following modifications are possible, for example. (1) In the first and second embodiments described above, the bias circuit B (constant voltage circuit) having the circuit configuration shown in FIGS. 1 and 5 is employed, but the present invention is not limited to this. That is, the bias circuit (constant voltage circuit) of the present invention is sufficient as long as it can supply a constant voltage as a bias voltage to the next-stage transistor without relying on parasitic resistance between an external DC voltage power supply and the power supply terminal Vcc. The high-frequency power amplifier may also have a circuit configuration other than that of the bias circuit B, for example.

[0102] (2) Although NPN bipolar transistors are used as the transistors, the present invention is not limited to this. PNP bipolar transistors may be used instead of NPN bipolar transistors. Furthermore, N-type or P-type field effect transistors (FETs) may be used for the first transistor Tr1, the second transistor Tr2, the eleventh transistor Tr11, the twelfth transistor Tr12, the twenty-first transistor Tr21, and the twenty-second transistor Tr22, which function as amplifying elements.

[0103] (3) In the first and second embodiments, the base-emitter voltage V ＢＥ１ , V ＢＥ２ However, the present invention is not limited to this. The number of bipolar transistors for generating the reference constant voltage, i.e., the number of bipolar transistors connected in series, may be two or more, or may be one if necessary.

[0104] (4) In the second embodiment, a load inductor pair consisting of the first inductor L1 and the second inductor L2 is used. However, the present invention is not limited to this. Instead of the load inductor pair, a single inductor (transformer) with a center tap may be used.

[0105] (5) In the second embodiment, the first transistor Tr21 and the second transistor Tr22 are connected to the output matching circuit Sout12 using wires. However, the present invention is not limited to this. Instead of using wires, electromagnetic coupling using the load inductor pair described above may be used for this connection.

[0106] (6) In the second embodiment, the second bias terminal Vb2 is provided separately from the first bias terminal Vb1, but the present invention is not limited to this. That is, the first bias terminal Vb1 and the second bias terminal Vb2 may be combined into a single bias terminal.

[0107] A, A1: high frequency power amplifier; B: bias circuit; M, M1: main circuit; Tr1: first transistor (first stage NPN bipolar transistor); Tr2: second transistor (next stage NPN bipolar transistor); Tr3: third transistor (first bias NPN bipolar transistor); Tr4: fourth transistor (second bias NPN bipolar transistor); Tr5: fifth transistor (third bias NPN bipolar transistor); Tr11: eleventh transistor (first first stage NPN bipolar transistor); Tr12: twelfth transistor (second first stage NPN bipolar transistor); Tr21: twenty-first transistor (first next stage NPN bipolar transistor); Tr22: twenty-second transistor (second next stage NPN bipolar transistor); R1: first resistor (amplifying resistor); R2: second resistor (first bias resistor); R3: Third resistor (second bias resistor), R4 fourth resistor (third bias resistor), R5 fifth resistor (fourth bias resistor), R11 eleventh resistor (first amplifying resistor), R12 twelfth resistor (second amplifying resistor), C capacitor, Sin, Sin12 input matching circuit, Sout, Sout12 output matching circuit, L inductor, L1 first inductor, L2 second inductor, RFin high frequency input terminal, RFin1 first high frequency input terminal, RFin2 second high frequency input terminal, RFout high frequency output terminal, RFout1 first high frequency output terminal, RFout2 second high frequency output terminal, Vb bias terminal, Vb1 first bias terminal, Vb2 second bias terminal, GND ground terminal, Vcc power supply terminal, Wd power supply line, Wg ground line, Wo output terminal

Claims

1. a main circuit including a cascode-connected first-stage transistor and a second-stage transistor, amplifying an input signal and outputting a high-frequency amplified signal; a bias circuit that applies a bias voltage to the next-stage transistor; Equipped with The bias circuit is a constant voltage circuit that generates the bias voltage, which is a constant voltage, based on a power supply externally supplied to a power supply terminal.

2. 2. The power amplifier according to claim 1, wherein the bias circuit generates a reference constant voltage by a base-emitter voltage of one bipolar transistor or a base-emitter voltage of a plurality of bipolar transistors connected in series.

3. 3. The power amplifier according to claim 2, wherein the number of said bipolar transistors is two.

4. The power amplifier according to any one of claims 1 to 3, wherein the main circuit is a differential amplifier circuit that includes the first-stage transistor and the second-stage transistor as a pair, amplifies a pair of input signals, and outputs a pair of amplified signals.

5. 5. The power amplifier according to claim 4, further comprising a pair of bias terminals for individually setting the amplification factor of said first-stage transistor.

6. The bias circuit a first bias NPN bipolar transistor having an emitter terminal connected to a ground line and a base terminal and a collector terminal connected in common; a second bias NPN bipolar transistor having an emitter terminal connected to the base terminal and the collector terminal of the first bias NPN bipolar transistor; a third bias NPN bipolar transistor having a base terminal connected to the collector terminal of the second bias NPN bipolar transistor; a first bias resistor having one end connected to the base terminal and the collector terminal of the first bias NPN bipolar transistor and the other end connected to a power supply line; a second bias resistor having one end connected to the power supply line and the other end connected to the collector terminal of the second bias NPN bipolar transistor and the base terminal of the third bias NPN bipolar transistor; a third bias resistor having one end connected to the base terminal of the second bias NPN bipolar transistor and the other end connected to the emitter terminal of the third bias NPN bipolar transistor; a fourth bias resistor having one end connected to the ground line and the other end connected to the base terminal of the second bias NPN bipolar transistor and one end of the third bias resistor; a capacitor having one end connected to the ground line and the other end connected to the emitter terminal of the third bias NPN bipolar transistor and the other end of the third bias resistor; Equipped with 2. The power amplifier according to claim 1, wherein the bias voltage is output from the emitter terminal of the third bias NPN bipolar transistor.

7. The main circuit includes: an input matching circuit whose input end is connected to a high frequency input terminal; a first-stage NPN bipolar transistor having a base terminal connected to the output terminal of the input matching circuit and an emitter terminal connected to a ground terminal; an amplifying resistor having one end connected to the output terminal of the input matching circuit and the base terminal of the first-stage transistor, and the other end connected to a bias terminal; a second-stage NPN bipolar transistor having an emitter terminal connected to the collector terminal of the first-stage NPN bipolar transistor and a base terminal to which the bias voltage is input; an inductor having one end connected to the collector terminal of the next-stage NPN bipolar transistor and the other end connected to a power supply terminal; an output matching circuit having an input terminal connected to the collector terminal of the next-stage NPN bipolar transistor and one end of the inductor, and an output terminal connected to a high-frequency output terminal; 10. The power amplifier of claim 1, further comprising:

8. The main circuit includes: an input matching circuit having one input end connected to the first high frequency input terminal and the other input end connected to the second high frequency input terminal; a first initial-stage NPN bipolar transistor having a base terminal connected to the one output terminal of the input matching circuit and an emitter terminal connected to a ground terminal; a second first-stage NPN bipolar transistor having a base terminal connected to the other output terminal of the input matching circuit and an emitter terminal connected to a ground terminal; a first amplifying resistor having one end connected to the one output end of the input matching circuit and the base terminal of the first initial-stage NPN bipolar transistor, and the other end connected to a first bias terminal; a second amplifying resistor having one end connected to the other output end of the input matching circuit and the base terminal of the second initial-stage NPN bipolar transistor, and the other end connected to a second bias terminal; a first next-stage NPN bipolar transistor having an emitter terminal connected to the collector terminal of the first first-stage NPN bipolar transistor and a base terminal to which the bias voltage is input; a second next-stage NPN bipolar transistor having an emitter terminal connected to the collector terminal of the second first-stage NPN bipolar transistor and a base terminal to which the bias voltage is input; a first inductor having one end connected to the collector terminal of the first next-stage NPN bipolar transistor and the other end connected to a power supply terminal; a second inductor having one end connected to the collector terminal of the second next-stage NPN bipolar transistor and the other end connected to a power supply terminal; an output matching circuit having one input end connected to the collector terminal of the first next-stage NPN bipolar transistor and the one end of the first inductor, the other input end connected to the collector terminal of the second next-stage NPN bipolar transistor and the one end of the second inductor, one output end connected to the first high-frequency output terminal, and the other output end connected to the second high-frequency output terminal; 10. The power amplifier of claim 1, further comprising:

9. 4. The power amplifier according to claim 1, wherein an emitter length of the second-stage transistor is set to be greater than an emitter length of the first-stage transistor.