RC-IGBT and production method for RC-igbt

Abstract

Provided is a RC-IGBT wherein an active region of a semiconductor substrate comprises an IGBT region, a plurality of diode regions, a boundary region, and a lifetime control region. The boundary region is formed between the IGBT region and a diode region adjacent thereto. The lifetime control region overlaps an outer peripheral region, the plurality of diode regions, and the boundary region in plan view. The plurality of diode regions includes a first end diode region. The first end diode region is formed at both ends of the active region in the Y direction in plan view and is continuous with the outer peripheral region. The lifetime control region includes a first end region formed so as to span the first end diode region and the portion of the outer peripheral region that is continuous with the first end diode region.

Description

RC-IGBT and manufacturing method thereof

[0001] The present disclosure relates to a reverse conducting-insulated gate bipolar transistor (RC-IGBT) and a method for manufacturing the RC-IGBT.

[0002] 2. Description of the Related Art As a semiconductor device, an RC-IGBT is known which includes an IGBT region in which an IGBT is formed and a diode region in which a free wheel diode is formed (see, for example, Patent Document 1).

[0003] JP 2018-120990 A

[0004] The RC-IGBT further includes a boundary region formed between the IGBT region and the diode region. Incidentally, a lifetime control region for reducing switching loss may be formed in the diode region of the RC-IGBT.

[0005] In this case, taking into consideration the positional misalignment of the lifetime control region, a lifetime control region is also formed in the boundary region. However, since the boundary region has a different structure from both the IGBT region and the diode region, it is difficult for the boundary region to contribute to both the electrical characteristics of the IGBT and the electrical characteristics of the diode. For this reason, it is preferable to have a small number of boundary regions.

[0006] an RC-IGBT according to one aspect of the present disclosure comprising: a semiconductor substrate; an active region provided in the semiconductor substrate; and a peripheral region provided in the semiconductor substrate and surrounding the active region as viewed in a thickness direction of the semiconductor substrate; the active region including an IGBT region and a plurality of diode regions aligned in a first direction; and a boundary region formed between the IGBT regions adjacent in the first direction and a diode region that is one of the plurality of diode regions; and a lifetime control region provided within the semiconductor substrate and overlapping with the peripheral region, the plurality of diode regions, and the boundary region as viewed in the thickness direction; the plurality of diode regions including first end diode regions that are formed on both ends of the active region in the first direction as viewed in the thickness direction and are continuous with the peripheral region; and the lifetime control region including a first end region formed across the first end diode region and a portion of the peripheral region that is continuous with the first end diode region.

[0007] A method for manufacturing an RC-IGBT according to one aspect of the present disclosure includes the steps of: preparing a wafer having a first wafer main surface and a second wafer main surface opposite the first wafer main surface, the wafer being partitioned into an active region and a peripheral region surrounding the active region; forming, in the active region, an IGBT region and a plurality of diode regions aligned in a first direction, and a boundary region formed between the IGBT region and a diode region that is one of the plurality of diode regions adjacent to each other in the first direction; and providing, within the wafer, a lifetime control region that overlaps with the peripheral region, the plurality of diode regions, and the boundary region when viewed from a thickness direction of the wafer, wherein the plurality of diode regions include first end diode regions that are formed on both ends of the active region in the first direction and are continuous with the peripheral region when viewed from the thickness direction;

[0008] According to the above RC-IGBT and the method for manufacturing the RC-IGBT, the number of boundary regions can be reduced.

[0009] FIG. 1 is a schematic plan view of an RC-IGBT according to a first embodiment. FIG. 2 is a schematic plan view of a semiconductor substrate of the RC-IGBT of FIG. 1. FIG. 3 is a schematic plan view showing a lifetime control region of the semiconductor substrate of FIG. 2. FIG. 4 is a schematic cross-sectional view of the RC-IGBT taken along line F4-F4 in FIG. 2. FIG. 5 is a schematic cross-sectional view of the RC-IGBT taken along line F5-F5 in FIG. 2. FIG. 6 is a schematic cross-sectional view showing an exemplary manufacturing process for the RC-IGBT according to the first embodiment. FIG. 7 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 6. FIG. 8 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 7. FIG. 9 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 8. FIG. 10 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 9. FIG. 11 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 10. FIG. 12 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 11. FIG. 13 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 12. FIG. 14 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 13 . FIG. 15 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 14 . FIG. 16 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 15 . FIG. 17 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 16 . FIG. 18 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 17 . FIG. 19 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 18 . FIG. 20 is a schematic plan view of a semiconductor substrate for an RC-IGBT of a second embodiment. FIG. 21 is a schematic plan view showing a lifetime control region for the semiconductor substrate of FIG. 20 . FIG. 22 is a schematic plan view of an RC-IGBT of a third embodiment. FIG. 23 is a schematic plan view of a semiconductor substrate of the RC-IGBT of FIG. 22 . FIG. 24 is a schematic plan view showing a lifetime control region for the semiconductor substrate of FIG. 23 . FIG. 25 is a schematic plan view of a semiconductor substrate for an RC-IGBT of a modified example. FIG. 26 is a schematic cross-sectional view of an active region of a modified RC-IGBT.

[0010] Hereinafter, several embodiments of an RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor) according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0011] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0012] Furthermore, in the following description, the expressions "the width of part A is equal to the width of part B," "the depth of part A is equal to the depth of part B," "the length of part A is equal to the length of part B," and "the dimensions of part A are equal to the dimensions of part B" mean that the difference between the width (depth, length, dimensions) of part A and the width (depth, length, dimensions) of part B is within 10% of the width (depth, length, dimensions) of part A.

[0013] <First Embodiment> [Overall Structure of RC-IGBT] The overall structure of an RC-IGBT 10 according to a first embodiment will be described with reference to Figures 1 to 3. Figure 1 shows an example of the planar structure of the RC-IGBT 10. Figure 2 shows an example of the planar structure of a semiconductor substrate 12 (described later) of the RC-IGBT 10. Figure 3 shows a lifetime control region 30 (described later) in Figure 2. Note that in Figures 2 and 3, an emitter electrode EM and a gate electrode GT (described later) are indicated by dashed double-dashed lines to facilitate understanding of the drawings.

[0014] 1 corresponds to the thickness direction of the RC-IGBT 10. Note that the term "planar view" used in this specification refers to viewing the RC-IGBT 10 along the Z direction, unless explicitly stated otherwise.

[0015] As shown in FIGS. 1 to 3, the RC-IGBT 10 is a semiconductor device in which an IGBT and a freewheeling diode (FWD) connected in antiparallel to the IGBT are configured on a single chip.

[0016] As shown in FIG. 1, the RC-IGBT 10 includes a rectangular, flat semiconductor substrate 12 whose thickness direction is in the Z direction. The semiconductor substrate 12 may also be referred to as a "chip" or a "semiconductor chip." The semiconductor substrate 12 has a single-layer structure formed, for example, from a silicon single crystal substrate. The semiconductor substrate 12 has a first main surface 14, a second main surface 16 (see FIG. 4) opposite the first main surface 14 in the Z direction, and first to fourth side surfaces 18A to 18D connecting the first main surface 14 and the second main surface 16.

[0017] Both the first main surface 14 and the second main surface 16 are formed in a rectangular shape in a plan view. The first side surface 18A and the second side surface 18B constitute both end surfaces of the semiconductor substrate 12 in the X direction, and the third side surface 18C and the fourth side surface 18D constitute both end surfaces of the semiconductor substrate 12 in the Y direction.

[0018] The RC-IGBT 10 includes an active region 20 provided on a semiconductor substrate 12, and a peripheral region 28 provided on the semiconductor substrate 12 and surrounding the active region 20 in a plan view. In Fig. 1, the active region 20 is indicated by a dashed line to facilitate understanding of the drawing.

[0019] The active region 20 is formed on the first main surface 14. The active region 20 is formed, for example, as a rectangular region that is slightly smaller than the first main surface 14. The peripheral region 28 is a region defined by the active region 20 and the first to fourth side surfaces 18A to 18D in a plan view.

[0020] The RC-IGBT 10 includes an emitter electrode EM, a gate electrode GT, and a collector electrode CL (see FIG. 4). The emitter electrode EM and the gate electrode GT are formed on a first main surface 14. The collector electrode CL is formed on a second main surface 16.

[0021] 1, the emitter electrode EM and the gate electrode GT are formed in, for example, the active region 20. The emitter electrode EM is formed over most of the active region 20. In one example, the gate electrode GT is formed at the end of the active region 20 closer to the fourth side surface 18D in the Y direction and at the center in the X direction. The position of the gate electrode GT can be changed as desired. In one example, the gate electrode GT may be formed in one of the four corner portions of the active region 20.

[0022] The emitter electrode EM and the gate electrode GT have a layered structure of one metal film or multiple metal films. The emitter electrode EM and the gate electrode GT may contain at least one of titanium (Ti), tungsten (W), aluminum (Al), and copper (Cu). In one example, the emitter electrode EM and the gate electrode GT have a layered structure including a Ti-based metal film and an Al-based metal film. While the emitter electrode EM and the gate electrode GT are formed from the same material in the above example, this is not a limitation. The emitter electrode EM and the gate electrode GT may also be formed from different materials.

[0023] The collector electrode CL shown in FIG. 4 covers, for example, the entire second major surface 16. The collector electrode CL has a layered structure of one metal film or multiple metal films. The collector electrode CL includes at least one of Ti, nickel (Ni), palladium (Pd), gold (Au), silver (Ag), and Al. In one example, the collector electrode CL includes a Ti film in contact with the second major surface 16. In one example, the collector electrode CL may have a layered structure including a Ti film, a Ni film, a Pd film, and an Au film stacked in this order from the second major surface 16 side.

[0024] 2 , the active region 20 includes at least one IGBT region 22 (a plurality of IGBT regions in the first embodiment) and a plurality of diode regions 24. In one example, the active region 20 includes a plurality of IGBT regions 22 (two IGBT regions in the first embodiment) and a plurality of diode regions 24 (three IGBT regions in the first embodiment). The IGBT regions 22 and the diode regions 24 are arranged alternately in the Y direction.

[0025] The active region 20 includes at least one boundary region 26 formed between adjacent IGBT regions 22 and diode regions 24. In one example, the active region 20 includes multiple boundary regions 26. In the first embodiment, two IGBT regions 22 and three diode regions 24 are provided, resulting in four boundary regions 26. Here, the Y direction corresponds to the "first direction." The first direction can be said to be the arrangement direction of the IGBT regions 22, diode regions 24, and boundary regions 26.

[0026] Each of the IGBT region 22, the diode region 24, and the boundary region 26 is formed in a strip shape with the X direction as its longitudinal direction and the Y direction as its lateral direction. Therefore, it can also be said that each of the IGBT region 22, the diode region 24, and the boundary region 26 has the X direction as its length direction and the Y direction as its width direction. In the first embodiment, each of the IGBT region 22, the diode region 24, and the boundary region 26 is arranged along its lateral direction (width direction).

[0027] In one example, the length dimensions of the IGBT region 22, the diode region 24, and the boundary region 26 are equal to one another. The IGBT region 22, the diode region 24, and the boundary region 26 are each formed, for example, across the entire X-direction of the active region 20. In other words, the length dimensions of the IGBT region 22, the diode region 24, and the boundary region 26 are equal to the dimension of the active region 20 in the X-direction.

[0028] The width of the boundary region 26 is smaller than the width of both the IGBT region 22 and the diode region 24. In one example, the width of the boundary region 26 is equal to or smaller than half the width of both the IGBT region 22 and the diode region 24. The relationship between the area of ​​the IGBT region 22 and the area of ​​the diode region 24 in the active region 20 is set according to the electrical characteristics of the RC-IGBT 10. In the first embodiment, the total area of ​​the multiple diode regions 24 is larger than the total area of ​​the multiple IGBT regions 22. Furthermore, the width of each diode region 24 is larger than the width of each IGBT region 22. Therefore, the area of ​​each diode region 24 is larger than the area of ​​each IGBT region 22.

[0029] The multiple diode regions 24 include, in a plan view, first end diode regions 24A, 24B formed at both ends of the active region 20 in the Y direction, and a central diode region 24C formed closer to the center of the active region 20 in the Y direction than the first end diode regions 24A, 24B. In the first embodiment, the central diode region 24C is formed in the center of the active region 20 in the Y direction. The first end diode region 24A is formed at one of both ends of the active region 20 in the Y direction, closer to the third side surface 18C. The first end diode region 24B is formed at one of both ends of the active region 20 in the Y direction, closer to the fourth side surface 18D. The first end diode regions 24A, 24B extend along the X direction. Here, the X direction corresponds to the "second direction." In other words, the X direction (second direction) is a direction perpendicular to the Y direction (first direction) in a plan view.

[0030] The peripheral region 28, which is formed outside the active region 20, is formed on the first main surface 14. The peripheral region 28 is a region that does not include the IGBT region 22, the diode region 24, or the boundary region 26. In one example, the peripheral region 28 is formed in the shape of a rectangular frame in a plan view. The peripheral region 28 is a region in which, for example, a termination structure that improves the dielectric strength voltage of the RC-IGBT 10 is provided. The termination structure will be described in detail later.

[0031] Each of the first end diode regions 24A, 24B is a region adjacent to the peripheral region 28 in the Y direction. It can also be said that each of the first end diode regions 24A, 24B is continuous with the peripheral region 28 in the Y direction. In a plan view, the first end diode region 24A is adjacent to a region of the peripheral region 28 between the active region 20 and the third side surface 18C in the Y direction. The first end diode region 24B is adjacent to a region of the peripheral region 28 between the active region 20 and the fourth side surface 18D in the Y direction. In a plan view, it can also be said that the first end diode region 24A is continuous with a region of the peripheral region 28 between the active region 20 and the third side surface 18C in the Y direction. In a plan view, it can also be said that the first end diode region 24B is continuous with a region of the peripheral region 28 between the active region 20 and the fourth side surface 18D in the Y direction.

[0032] Furthermore, each of the first end diode regions 24A, 24B is adjacent to the peripheral region 28 in the X direction. It can also be said that each of the first end diode regions 24A, 24B is continuous with the peripheral region 28 in the X direction. More specifically, of the two ends of each of the first end diode regions 24A, 24B in the X direction, the end closer to the first side surface 18A is adjacent to a region of the peripheral region 28 between the active region 20 and the first side surface 18A in the X direction. Of the two ends of each of the first end diode regions 24A, 24B in the X direction, the end closer to the second side surface 18B is adjacent to a region of the peripheral region 28 between the active region 20 and the second side surface 18B in the X direction. It can also be said that the end closer to the first side surface 18A is continuous with a region of the peripheral region 28 between the active region 20 and the first side surface 18A in the X direction. Of the two ends of each of the first end diode regions 24A, 24B in the X direction, the end closer to the second side surface 18B can also be said to be continuous with the region of the peripheral region 28 between the active region 20 and the second side surface 18B in the X direction.

[0033] Similarly, each of the central diode region 24C, the IGBT region 22, and the boundary region 26 is adjacent to the peripheral region 28 in the X direction. Similarly, each of the central diode region 24C, the IGBT region 22, and the boundary region 26 can also be said to be continuous with the peripheral region 28 in the X direction.

[0034] As shown in Fig. 3, the RC-IGBT 10 includes a lifetime control region 30. The lifetime control region 30 is provided in the semiconductor substrate 12. Note that the lifetime control region 30 is hatched in Fig. 3. Here, lifetime is the average time that excess carriers exist in a semiconductor material before recombining and reaching equilibrium.

[0035] The lifetime control region 30 is a region in which lifetime killers are intentionally formed, for example, by implanting impurities into the semiconductor substrate 12. A lifetime killer is a carrier recombination center that shortens the lifetime. An example of a lifetime killer is a crystal defect. In other words, the lifetime control region 30 can be said to be a region in which crystal defects are formed inside the semiconductor substrate 12. The lifetime control region 30 is formed by implanting, for example, helium (He) into the semiconductor substrate 12.

[0036] The lifetime killer is not limited to a crystal defect, but may also be a vacancy, a divacancy, a complex defect of a vacancy or a divacancy with an element constituting the semiconductor substrate 12, a dislocation, a rare gas element such as helium or neon (Ne), a metal element such as platinum (Pt), or the like.

[0037] The lifetime control region 30 is formed in a region of the active region 20 and the peripheral region 28 other than the IGBT region 22 in a plan view. In other words, the lifetime control region 30 is formed in a region that overlaps with the peripheral region 28, the plurality of diode regions 24, and the plurality of boundary regions 26 in a plan view. Therefore, the lifetime control region 30 includes first end regions 32A and 32B formed across the first end diode regions 24A and 24B and portions of the peripheral region 28 that are continuous with the first end diode regions 24A and 24B, and a central region 32C formed closer to the center of the active region 20 in the Y direction than the first end regions 32A and 32B. In one example, the lifetime control region 30 is formed across the entirety of each of the plurality of diode regions 24, the plurality of boundary regions 26, and the peripheral region 28 in a plan view.

[0038] The first end region 32A includes a region formed across the first end diode region 24A and a portion of the peripheral region 28 that is continuous with the first end diode region 24A in the Y direction. The first end region 32A also includes a region formed across both ends of the first end diode region 24A in the X direction and a portion of the peripheral region 28 that is continuous with the first end diode region 24A in the X direction. The first end region 32A also includes a boundary region 26 that is continuous with the first end diode region 24A on the opposite side of the peripheral region 28 from the peripheral region 28 in the Y direction. In other words, the first end region 32A is formed across the first end diode region 24A, a portion of the peripheral region 28 that is continuous with the first end diode region 24A, and the boundary region 26 that is continuous with the first end diode region 24A.

[0039] In one example, the first end region 32A includes, in a plan view, a first outer periphery region of the outer periphery region 28 between the first end diode region 24A and the third side surface 18C in the Y direction, a second outer periphery region between the first end diode region 24A and the boundary region 26 and the first side surface 18A in the X direction, and a third outer periphery region between the first end diode region 24A and the boundary region 26 and the second side surface 18B in the X direction. The first outer periphery region includes, for example, a corner region defined by the third side surface 18C and the first side surface 18A in a plan view, and a corner region defined by the third side surface 18C and the second side surface 18B. In one example, the first end region 32A is formed over the entire first end diode region 24A, the boundary region 26 adjacent to the first end diode region 24A in the Y direction, the first outer periphery region, the second outer periphery region, and the third outer periphery region in a plan view.

[0040] The first end region 32B includes a region formed across the first end diode region 24B and a portion of the peripheral region 28 that is continuous with the first end diode region 24B in the Y direction. The first end region 32B also includes a region formed across both ends of the first end diode region 24B in the X direction and a portion of the peripheral region 28 that is continuous with the first end diode region 24B in the X direction. The first end region 32B also includes a boundary region 26 that is continuous with the first end diode region 24B on the opposite side of the peripheral region 28 from the peripheral region 28 in the Y direction. In other words, the first end region 32B is formed across the first end diode region 24B, a portion of the peripheral region 28 that is continuous with the first end diode region 24B, and the boundary region 26 that is continuous with the first end diode region 24B.

[0041] In one example, the first end region 32B includes, in a plan view, a fourth outer peripheral region of the outer peripheral region 28 between the first end diode region 24B and the fourth side surface 18D in the Y direction, a fifth outer peripheral region between the first end diode region 24B and the boundary region 26 and the first side surface 18A in the X direction, and a sixth outer peripheral region between the first end diode region 24B and the boundary region 26 and the second side surface 18B in the X direction. The fourth outer peripheral region includes, for example, a corner region defined by the fourth side surface 18D and the first side surface 18A in a plan view, and a corner region defined by the fourth side surface 18D and the second side surface 18B. In one example, the first end region 32B is formed over the entire first end diode region 24B, the boundary region 26 adjacent to the first end diode region 24B in the Y direction, the fourth outer peripheral region, the fifth outer peripheral region, and the sixth outer peripheral region in a plan view.

[0042] The central region 32C includes a region formed across the central diode region 24C and the boundary region 26 that is continuous with both sides of the central diode region 24C in the Y direction. The central region 32C is continuous with a portion of the lifetime control region 30 in the peripheral region 28 that is closer to the first side surface 18A and a portion of the lifetime control region 30 that is closer to the second side surface 18B.

[0043] In one example, central region 32C includes, in plan view, a seventh peripheral region of peripheral region 28 between first side surface 18A and central diode region 24C and boundary regions 26 on both sides of central diode region 24C in the Y direction, and an eighth peripheral region between second side surface 18B and central diode region 24C and boundary regions 26 on both sides of central diode region 24C in the Y direction. In one example, central region 32C is formed across the entire central diode region 24C, the boundary regions 26 on both sides of central diode region 24C in the Y direction, the seventh peripheral region, and the eighth peripheral region.

[0044] The Y-direction dimension LA1 of the first end region 32A is larger than the Y-direction dimension L2 of the central region 32C. The Y-direction dimension LB1 of the first end region 32B is larger than the Y-direction dimension L2 of the central region 32C. The dimension LA1 is equal to the dimension LB1.

[0045] [Cross-sectional structure of active region of RC-IGBT] An example of the cross-sectional structure of the active region 20 of the RC-IGBT 10 will be described with reference to Fig. 4. Fig. 4 shows an example of the cross-sectional structure of the IGBT region 22, the diode region 24, and the boundary region 26.

[0046] As shown in FIG. 4 , the semiconductor substrate 12 includes an n-type semiconductor layer 36. The semiconductor layer 36 is formed throughout the interior of the semiconductor substrate 12. The semiconductor layer 36 includes a first main surface 36A and a second main surface 36B opposite to the first main surface 36A. The second main surface 36B constitutes, for example, the second main surface 16 of the semiconductor substrate 12. The semiconductor layer 36 may also be referred to as, for example, a "drift layer" or a "drift region." The n-type impurity concentration of the semiconductor layer 36 is, for example, 1×10 １３ cm －３ 1x10 or more １５ cm －３ In the first embodiment, n-type corresponds to the "first conductivity type."

[0047] The RC-IGBT 10 includes an n-type buffer region 38 formed in a surface layer portion of the second main surface 36B. The buffer region 38 extends in a layered manner along the second main surface 36B and is exposed from parts of the first to fourth side surfaces 18A to 18D (see FIG. 3). The buffer region 38 has a higher n-type impurity concentration than the semiconductor layer 36. The n-type impurity concentration of the buffer region 38 is, for example, 1×10 １５ cm －３ 1x10 or more １７ cm －３ It may be the following:

[0048] The semiconductor layer 36 includes a first region R1 corresponding to each IGBT region 22, a second region R2 corresponding to each diode region 24, a third region R3 corresponding to the boundary region 26, and a fourth region R4 corresponding to the peripheral region 28 (see Figure 5).

[0049] The IGBT structure in the first region R1 will now be described. Each IGBT region 22 includes a p-type collector region 40 formed in a surface layer portion of the second main surface 36B. The collector region 40 is formed over the entire region of the second main surface 36B corresponding to each IGBT region 22. The p-type impurity concentration of the collector region 40 is 1×10１５ cm －３ 1x10 or more １８ cm －３ In the first embodiment, the p-type corresponds to the "second conductivity type." The collector region 40 exposed from the second major surface 36B is electrically connected to the collector electrode CL.

[0050] Each IGBT region 22 includes a p-type base region 42 formed in a surface layer portion of the first main surface 36A. The base region 42 may also be referred to as a "body region" or a "channel region." The p-type impurity concentration of the base region 42 may be higher than the n-type impurity concentration of the semiconductor layer 36. The p-type impurity concentration of the base region 42 may be, for example, 1×10 １５ cm －３ 1x10 or more １８ cm －３ It may be the following:

[0051] The RC-IGBT 10 includes a first trench electrode structure 44 formed on the first main surface 36A in each IGBT region 22. In one example, each IGBT region 22 may include a plurality of first trench electrode structures 44. The first trench electrode structure 44 may also be referred to as a "gate trench structure." A gate potential is applied to the first trench electrode structure 44.

[0052] The multiple first trench electrode structures 44 are spaced apart from one another in the Y direction in plan view. Each first trench electrode structure 44 is formed in a band shape extending in the X direction in plan view. In this way, the multiple first trench electrode structures 44 are arranged in stripes extending in the X direction. Each first trench electrode structure 44 penetrates the base region 42 so as to reach the semiconductor layer 36 in a cross-sectional view cut along the YZ plane (hereinafter simply referred to as a "cross-sectional view").

[0053] The multiple first trench electrode structures 44 may be arranged at intervals of 1 μm to 10 μm in the Y direction. Each first trench electrode structure 44 may have a width of 0.5 μm to 3 μm inclusive. Each first trench electrode structure 44 may have a depth of 1 μm to 10 μm inclusive. Here, the width of each first trench electrode structure 44 can be defined by the dimension of the first trench electrode structure 44 in the X direction in a plan view.

[0054] The first trench electrode structure 44 includes a first trench 46, a first insulating film 48, and a first buried electrode 50. The first trench 46 extends in the Z direction from the first major surface 36A toward the second major surface 36B. The first trench 46 defines the wall surfaces of the first trench electrode structure 44. In a cross-sectional view, the first trench 46 includes a bottom wall and sidewalls. In FIG. 4 , the sidewalls have a constant opening width from the opening of the first trench 46 toward the bottom wall. The opening width of the bottom wall narrows toward the second major surface 36B. As shown in FIG. 4 , the bottom wall may be curved.

[0055] The cross-sectional shape of the first trench 46 can be arbitrarily changed. For example, the sidewalls may be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall. The bottom wall may be formed, for example, parallel to the first main surface 36A. In this case, the corners between the sidewalls and the bottom wall of the first trench 46 may be formed in a curved shape. Here, the wall surfaces include the side surfaces that constitute the sidewalls and the bottom surface that constitutes the bottom wall.

[0056] The first insulating film 48 covers the wall surface of the first trench 46 in a film form, thereby defining a recess space within the first trench 46. The first insulating film 48 is a silicon oxide film (SiO ２ ), silicon nitride film (SiN), silicon oxynitride film (SiON), and aluminum oxide film (Al ２ O ３ In one example, the first insulating film 48 includes a silicon oxide film formed by oxidizing the semiconductor substrate 12.

[0057] The first buried electrode 50 is buried in the first trench 46 with the first insulating film 48 sandwiched therebetween. A gate potential is applied to the first buried electrode 50. The first buried electrode 50 may include conductive polysilicon. The first buried electrode 50 faces the semiconductor layer 36 and the base region 42 with the first insulating film 48 sandwiched therebetween.

[0058] The RC-IGBT 10 includes two trench connection structures (not shown) electrically connected to the multiple first trench electrode structures 44 in each IGBT region 22. In other words, each IGBT region 22 can be said to include two trench connection structures. More specifically, each first trench electrode structure 44 includes a first end and a second end that form both ends in the X direction. One trench connection structure connects the first ends of the multiple first trench electrode structures 44 to each other. The other trench connection structure connects the second ends of the multiple first trench electrode structures 44 to each other. Each trench connection structure is formed in a strip shape extending in the Y direction in a plan view. The configuration of each trench connection structure is, for example, the same as that of the first trench electrode structure 44.

[0059] The RC-IGBT 10 includes a plurality of second trench electrode structures 52 formed on the first main surface 36A in each IGBT region 22. The second trench electrode structures 52 may also be referred to as "emitter trench structures." A potential (emitter potential in the first embodiment) different from the gate potential is applied to the second trench electrode structures 52. In this manner, the RC-IGBT 10 can be said to include a first trench electrode structure 44 to which a first potential is applied, and a second trench electrode structure 52 to which a second potential different from the first potential is applied. In the first embodiment, the first potential corresponds to the gate potential, and the second potential corresponds to the emitter potential.

[0060] The second trench electrode structures 52 are spaced apart from one another in the Y direction in plan view. Each second trench electrode structure 52 is formed in a band shape extending in the X direction in plan view. In this way, the second trench electrode structures 52 are arranged in stripes extending in the X direction. Each second trench electrode structure 52 penetrates the base region 42 so as to reach the semiconductor layer 36 in cross-sectional view.

[0061] In one example, the multiple first trench electrode structures 44 and the multiple second trench electrode structures 52 are arranged alternately one by one in the Y direction. Each second trench electrode structure 52 is formed, for example, in a mesa region defined by the first trench electrode structures 44 and the trench connection structures on both sides of the second trench electrode structure 52 in the Y direction. The second trench electrode structure 52 is arranged spaced apart in the X direction from the trench connection structures. Therefore, the length of each second trench electrode structure 52 in the X direction is shorter than the length of each first trench electrode structure 44 in the X direction.

[0062] The multiple second trench electrode structures 52 may be arranged at intervals of 1.5 μm to 15 μm in the Y direction. In one example, the width of each second trench electrode structure 52 is equal to the width of each first trench electrode structure 44. The width of the second trench electrode structure 52 can be defined by the dimension of the second trench electrode structure 52 in the X direction in a plan view. In one example, the depth of each second trench electrode structure 52 is equal to the depth of each first trench electrode structure 44.

[0063] Each second trench electrode structure 52 includes a second trench 54, a second insulating film 56, and a second buried electrode 58. The configurations and materials of the second trench 54, the second insulating film 56, and the second buried electrode 58 are the same as the configurations and materials of the first trench 46, the first insulating film 48, and the first buried electrode 50. The cross-sectional shapes of the second trench 54, the second insulating film 56, and the second buried electrode 58 are the same as the cross-sectional shapes of the first trench 46, the first insulating film 48, and the first buried electrode 50. Therefore, detailed description of the second trench 54, the second insulating film 56, and the second buried electrode 58 will be omitted. However, an emitter potential is applied to the second buried electrode 58.

[0064] The RC-IGBT 10 includes a plurality of n-type emitter regions 60 formed in the surface layer portion of the base region 42 in each IGBT region 22. In other words, it can be said that each IGBT region 22 includes an emitter region 60. The emitter regions 60 are respectively arranged between the first trench electrode structure 44 and the second trench electrode structure 52 in the Y direction. Each emitter region 60 is formed in a strip shape extending in the X direction along the first trench electrode structure 44 (second trench electrode structure 52). Each emitter region 60 has a higher n-type impurity concentration than the semiconductor layer 36. The n-type impurity concentration of each emitter region 60 is, for example, 1×10 １９ cm －３ 1x10 or more ２０ cm －３ It may be the following:

[0065] The RC-IGBT 10 includes multiple n-type CS regions 62 (carrier storage regions) formed in the region directly below the base region 42 in each IGBT region 22. That is, each IGBT region 22 includes a CS region 62. The multiple CS regions 62 suppress the discharge of carriers (positive holes) into the base region 42 and promote the accumulation of carriers (positive holes) in the region directly below the multiple first trench electrode structures 44. That is, the multiple CS regions 62 promote low on-resistance and low on-voltage from inside the semiconductor substrate 12. Here, the CS regions 62 may also be referred to as "accumulation regions" that promote carrier accumulation.

[0066] The CS regions 62 are arranged between the first trench electrode structure 44 and the second trench electrode structure 52 in the Y direction. Each CS region 62 is formed in a strip shape extending in the X direction along the first trench electrode structure 44 (second trench electrode structure 52). The multiple CS regions 62 are formed in a region between the bottom of the base region 42 and the bottom wall of the first trench electrode structure 44 (second trench electrode structure 52) in the Z direction. In one example, the multiple CS regions 62 are formed spaced apart from the bottom wall of the first trench electrode structure 44 (second trench electrode structure 52). In one example, the bottoms of the multiple CS regions 62 are located closer to the bottom of the first trench electrode structure 44 (second trench electrode structure 52) than to the middle of the first trench electrode structure 44 (second trench electrode structure 52) in the Z direction.

[0067] In one example, the plurality of CS regions 62 have a lower n-type impurity concentration than the emitter region 60. The n-type impurity concentration of the plurality of CS regions 62 is, for example, 1×10 １５ cm －３ 1x10 or more １７ cm －３ It may be the following:

[0068] Thus, each IGBT region 22 includes a transistor structure including a p-type base region 42 formed in the first main surface 36A, an n-type emitter region 60 formed in the base region 42, and a first buried electrode 50 facing the base region 42 and the emitter region 60 via the first insulating film 48. Here, the first insulating film 48 corresponds to a "gate insulating layer," and the first buried electrode 50 corresponds to a "gate electrode."

[0069] The RC-IGBT 10 includes a plurality of contact holes 64 formed in the first main surface 36A in each IGBT region 22. The contact holes 64 are formed between the first trench electrode structure 44 and the second trench electrode structure 52 in the Y direction. Each contact hole 64 may penetrate the emitter region 60 to reach the base region 42. Each contact hole 64 is formed in a strip shape extending in the X direction, for example, in a plan view.

[0070] The RC-IGBT 10 includes, in each IGBT region 22, a plurality of p-type contact regions 66 formed in a region different from the plurality of emitter regions 60 in a surface layer portion of the base region 42. That is, the IGBT region 22 includes a plurality of contact regions 66. The plurality of contact regions 66 are each formed in a region along the corresponding contact hole 64 in a plan view. The plurality of contact regions 66 are each formed in a strip shape extending along the corresponding contact hole 64 in a plan view.

[0071] The bottom of each contact region 66 is formed in a region between the bottom wall of the contact hole 64 and the bottom of the base region 42 in the Z direction. Each contact region 66 has a higher p-type impurity concentration than the base region 42. The p-type impurity concentration of each contact region 66 is, for example, 1×10 １９ cm －３1x10 or more ２０ cm －３ It may be the following:

[0072] The diode structure in the second region R2 will now be described. In each diode region 24 of the RC-IGBT 10, an n-type cathode region 68 is formed in the surface layer portion of the second main surface 36B. That is, each diode region 24 includes the cathode region 68. The cathode region 68 penetrates the collector region 40 so as to be connected to the buffer region 38. In one example, the cathode region 68 has a higher n-type impurity concentration than the semiconductor layer 36 (buffer region 38). The n-type impurity concentration of the cathode region 68 is, for example, 1×10 １９ cm －３ 1x10 or more ２０ cm －３ It may be the following:

[0073] The RC-IGBT 10 includes a p-type anode region 70 formed in a surface layer portion of the first main surface 36A in each diode region 24. That is, each diode region 24 includes the anode region 70. The anode region 70 faces the cathode region 68 in the Z direction. In one example, the entire anode region 70 faces at least a part of the cathode region 68. In one example, the depth of the anode region 70 is equal to the depth of the base region 42. The p-type impurity concentration of the anode region 70 is, for example, 1×10 １５ cm －３ 1x10 or more １８ cm －３ It may be the following:

[0074] The position, depth, and impurity concentration of the anode region 70 can be changed as desired. In one example, the anode region 70 may face a part of the collector region 40 and a part of the cathode region 68 in the Z direction. In one example, the anode region 70 may be formed deeper than the base region 42 in the Z direction. In one example, the p-type impurity concentration of the anode region 70 may be higher than the p-type impurity concentration of the base region 42. In one example, the p-type impurity concentration of the anode region 70 may be lower than the p-type impurity concentration of the base region 42.

[0075] The anode region 70 forms a pn junction with the semiconductor layer 36. This forms a pn junction diode with the anode region 70 as the anode and the cathode region 68 (semiconductor layer 36) as the cathode.

[0076] The RC-IGBT 10 includes a plurality of third trench electrode structures 72 formed on the first main surface 36A in each diode region 24. The third trench electrode structures 72 may also be referred to as "anode trench structures." A potential different from the gate potential (anode potential in the first embodiment) is applied to the third trench electrode structures 72. In one example, the anode potential may be the same potential as the emitter potential.

[0077] The multiple third trench electrode structures 72 penetrate the anode region 70 so as to reach the semiconductor layer 36 in a cross-sectional view. The multiple third trench electrode structures 72 are arranged spaced apart from one another in the Y direction in a plan view. Each third trench electrode structure 72 is formed in a band shape extending in the X direction in a plan view. That is, the multiple third trench electrode structures 72 are arranged in a stripe shape extending in the X direction. The length in the X direction of each third trench electrode structure 72 is shorter than the length in the X direction of the first trench electrode structure 44. The length in the X direction of each third trench electrode structure 72 is equal to the length in the X direction of the second trench electrode structure 52.

[0078] In one example, the spacing between the multiple third trench electrode structures 72 is equal to the spacing in the Y direction between the first trench electrode structure 44 and the second trench electrode structure 52. In one example, the width of each third trench electrode structure 72 is equal to the width of each first trench electrode structure 44. In one example, the depth of each third trench electrode structure 72 is equal to the depth of each first trench electrode structure 44. Note that the spacing between the multiple third trench electrode structures 72, the width of each third trench electrode structure 72, and the depth of each third trench electrode structure 72 can each be changed as desired.

[0079] Each third trench electrode structure 72 includes a third trench 74, a third insulating film 76, and a third buried electrode 78. The configurations and materials of the third trench 74, the third insulating film 76, and the third buried electrode 78 are the same as, for example, the configurations and materials of the first trench 46, the first insulating film 48, and the first buried electrode 50. The cross-sectional shapes of the third trench 74, the third insulating film 76, and the third buried electrode 78 are the same as, for example, the cross-sectional shapes of the first trench 46, the first insulating film 48, and the first buried electrode 50. Therefore, detailed description of the third trench 74, the third insulating film 76, and the third buried electrode 78 will be omitted. However, an anode potential is applied to the third buried electrode 78.

[0080] The RC-IGBT 10 includes two anode trench connection structures (not shown) formed on the first main surface 36A in each diode region 24 so as to be electrically connected to the multiple third trench electrode structures 72. In other words, each diode region 24 can be said to include two anode trench connection structures. More specifically, each third trench electrode structure 72 includes a first end and a second end that constitute both ends in the X direction. One anode trench connection structure connects the first ends of the multiple third trench electrode structures 72 to each other. The other anode trench connection structure connects the second ends of the multiple third trench electrode structures 72 to each other. Each anode trench connection structure is formed in a strip shape extending in the Y direction in a plan view. The configuration of each anode trench connection structure is, for example, the same as that of the third trench electrode structure 72.

[0081] The RC-IGBT 10 includes a plurality of contact holes 80 formed in the first main surface 36A in each diode region 24. The contact holes 80 are formed between the plurality of third trench electrode structures 72 in the Y direction. Each contact hole 80 is formed to reach the anode region 70. Each contact hole 80 is formed in a strip shape extending in the X direction, for example, in a plan view.

[0082] The RC-IGBT 10 includes, in each diode region 24, a plurality of p-type contact regions 82 formed in a surface layer portion of the anode region 70. That is, the diode region 24 includes a plurality of contact regions 82. The plurality of contact regions 82 are each formed in a region that is aligned with the corresponding contact hole 80 in a plan view. The plurality of contact regions 82 are each formed in a strip shape that extends along the corresponding contact hole 80 in a plan view.

[0083] The bottom of each contact region 82 is formed in a region between the bottom wall of the contact hole 80 and the bottom of the anode region 70 in the Z direction. Each contact region 82 has a higher p-type impurity concentration than the anode region 70. In one example, the p-type impurity concentration of each contact region 82 is equal to the p-type impurity concentration of the contact region 66 of the IGBT region 22. The p-type impurity concentration of each contact region 82 is, for example, 1×10 １９ cm －３ 1x10 or more ２０ cm －３ It may be the following:

[0084] The structure of the region between the IGBT structure and the diode structure in the third region R3 will be described. The RC-IGBT 10 includes a plurality of fourth trench electrode structures 84 formed on the first main surface 36A in each boundary region 26. Each fourth trench electrode structure 84 extends in the Z direction so as to reach the semiconductor layer 36 in a cross-sectional view. The plurality of fourth trench electrode structures 84 are arranged spaced apart from each other in the Y direction in a plan view. Each fourth trench electrode structure 84 is formed in a band shape extending in the X direction in a plan view. In other words, the plurality of fourth trench electrode structures 84 are arranged in a stripe shape extending in the X direction. The length in the X direction of each fourth trench electrode structure 84 is shorter than the length in the X direction of each first trench electrode structure 44.

[0085] Each fourth trench electrode structure 84 is electrically connected to two anode trench connection structures. More specifically, each fourth trench electrode structure 84 includes a first end and a second end that define both ends in the X direction. One anode trench connection structure connects the first ends of the multiple fourth trench electrode structures 84 to each other. The other anode trench connection structure connects the second ends of the multiple fourth trench electrode structures 84 to each other.

[0086] In one example, the spacing between the multiple fourth trench electrode structures 84 is equal to the spacing in the Y direction between the first trench electrode structure 44 and the second trench electrode structure 52. In one example, the width of each fourth trench electrode structure 84 is equal to the width of each first trench electrode structure 44. In one example, the depth of each fourth trench electrode structure 84 is equal to the depth of each first trench electrode structure 44. Note that the spacing between the multiple fourth trench electrode structures 84, the width of each fourth trench electrode structure 84, and the depth of each fourth trench electrode structure 84 can each be changed as desired.

[0087] Each fourth trench electrode structure 84 includes a fourth trench 86, a fourth insulating film 88, and a fourth buried electrode 90. The configurations and materials of the fourth trench 86, the fourth insulating film 88, and the fourth buried electrode 90 are the same as the configurations and materials of the first trench 46, the first insulating film 48, and the first buried electrode 50. The cross-sectional shapes of the fourth trench 86, the fourth insulating film 88, and the fourth buried electrode 90 are the same as the cross-sectional shapes of the first trench 46, the first insulating film 48, and the first buried electrode 50. Therefore, detailed description of the fourth trench 86, the fourth insulating film 88, and the fourth buried electrode 90 will be omitted. However, an anode potential is applied to the fourth buried electrode 90.

[0088] The RC-IGBT 10 includes a plurality of p-type boundary well regions 92 formed in the first main surface 36A in each boundary region 26. That is, the boundary region 26 includes a plurality of boundary well regions 92. The plurality of boundary well regions 92 are formed between the plurality of fourth trench electrode structures 84 in the Y direction. The boundary well regions 92 are formed in mesa regions defined by a pair of fourth trench electrode structures 84 and a pair of anode trench connection structures.

[0089] The boundary well region 92 is formed in a layer shape extending along the first main surface 36A in each boundary region 26. The boundary well region 92 faces the collector region 40 in the Z direction. In one example, the entire area of ​​the boundary well region 92 faces the collector region 40 in the Z direction. In one example, the depth of the boundary well region 92 is equal to the depth of the base region 42. In one example, the boundary well region 92 has a p-type impurity concentration higher than the p-type impurity concentration of the anode region 70. The p-type impurity concentration of the boundary well region 92 is 1×10 １５ cm －３ 1x10 or more １８ cm －３ In one example, the border well region 92 is electrically floating.

[0090] The position, depth, and impurity concentration of the boundary well region 92 can be changed as desired. In one example, the boundary well region 92 may face a part of the collector region 40 and a part of the cathode region 68 in the Z direction. In one example, the boundary well region 92 may be formed deeper than the base region 42 in the Z direction. In one example, the p-type impurity concentration of the boundary well region 92 may be lower than the p-type impurity concentration of the anode region 70. In one example, the p-type impurity concentration of the boundary well region 92 may be equal to the p-type impurity concentration of the anode region 70.

[0091] The boundary well region 92 forms a boundary injection enhanced structure (IE structure) in each boundary region 26. More specifically, the boundary well region 92 forms the boundary IE structure together with the plurality of fourth trench electrode structures 84, and separates the first trench electrode structure 44 adjacent to the boundary well region 92 (third region R3) in the IGBT region 22 (first region R1) from the third trench electrode structure 72 adjacent to the boundary well region 92 (third region R3) in the diode region 24 (second region R2). The boundary IE structure restricts the movement path of holes flowing into the base region 42 in the boundary region 26, thereby promoting the accumulation of holes in the region directly below the base region 42.

[0092] The RC-IGBT 10 includes a plurality of contact holes 94 formed in the first main surface 36A in each boundary region 26. The contact holes 94 are formed between the plurality of fourth trench electrode structures 84 in the Y direction. Each contact hole 94 is formed to reach the boundary well region 92. Each contact hole 94 is formed in a strip shape extending in the X direction, for example, in a plan view.

[0093] The RC-IGBT 10 includes, in each boundary region 26, a plurality of p-type contact regions 96 formed in a surface layer portion of the boundary well region 92. That is, the boundary region 26 includes a plurality of contact regions 96. The plurality of contact regions 96 are each formed in a region that is aligned with the corresponding contact hole 94 in a plan view. The plurality of contact regions 96 are each formed in a strip shape that extends along the corresponding contact hole 94 in a plan view.

[0094] The bottom of each contact region 96 is formed in a region between the bottom wall of the contact hole 94 and the bottom of the boundary well region 92 in the Z direction. Each contact region 96 has a higher p-type impurity concentration than the boundary well region 92. In one example, the p-type impurity concentration of each contact region 96 is equal to the p-type impurity concentration of the contact region 66 of the IGBT region 22. The p-type impurity concentration of each contact region 96 is, for example, 1×10 １９ cm －３ 1x10 or more ２０ cm －３ It may be the following:

[0095] Next, the configuration on the semiconductor layer 36 in the active region 20 will be described. The RC-IGBT 10 includes a main surface insulating film 98 that selectively covers the first main surface 36A. The main surface insulating film 98 is continuous with the insulating films 48, 56, 76, and 88 of the trench electrode structures 44, 52, 72, and 84. The main surface insulating film 98 covers the emitter regions 60 of the IGBT regions 22, the anode regions 70 of the diode regions 24, and the boundary well regions 92 of the boundary regions 26. The thickness of the main surface insulating film 98 is equal to the thickness of the insulating films 48, 56, 76, and 88. The main surface insulating film 98 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. In one example, the main surface insulating film 98 includes a silicon oxide film formed by oxidizing the semiconductor substrate 12. In one example, the main surface insulating film 98 has a single-layer structure composed of a single insulating film.

[0096] The RC-IGBT 10 includes an interlayer insulating film 100 covering the main surface insulating film 98. The interlayer insulating film 100 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. Examples of silicon oxide films that the interlayer insulating film 100 may include include at least one of a non-doped silicate glass (NSG) film, a phosphorus silicate glass (PSG) film, and a boron phosphorus silicate glass (BPSG) film. The interlayer insulating film 100 has a single-layer structure formed by a single insulating film or a layered structure including multiple insulating films. The interlayer insulating film 100 has a thickness greater than that of the main surface insulating film 98. The thickness of the interlayer insulating film 100 may be 0.5 μm or more and 5 μm or less. In one example, the thickness of the interlayer insulating film 100 is 1 μm or more.

[0097] The interlayer insulating film 100 covers each of the trench electrode structures 44, 52, 72, and 84. The interlayer insulating film 100 selectively covers each of the emitter regions 60, each of the anode regions 70, and each of the boundary well regions 92.

[0098] The interlayer insulating film 100 includes a plurality of first openings 102, a plurality of second openings 104, and a plurality of third openings 106. The plurality of first openings 102 expose the plurality of emitter regions 60 individually and communicate with the corresponding contact holes 64. The plurality of second openings 104 expose the plurality of anode regions 70 individually and communicate with the corresponding contact holes 80. The plurality of third openings 106 expose the plurality of boundary well regions 92 individually and communicate with the corresponding contact holes 94. The number, shape, and size of each of the first openings 102, second openings 104, and third openings 106 can be changed as desired.

[0099] The RC-IGBT 10 includes a plurality of first plug electrodes 108 embedded in the plurality of first openings 102, a plurality of second plug electrodes 110 embedded in the plurality of second openings 104, and a plurality of third plug electrodes 112 embedded in the plurality of third openings 106.

[0100] The first plug electrode 108 is embedded in the contact hole 64 through the first opening 102, and is thereby electrically connected to the emitter region 60 and the contact region 66. The second plug electrode 110 is embedded in the contact hole 80 through the second opening 104, and is thereby electrically connected to the anode region 70 and the contact region 82. The third plug electrode 112 is embedded in the contact hole 94 through the third opening 106, and is thereby electrically connected to the boundary well region 92 and the contact region 96.

[0101] Each plug electrode 108, 110, 112 may have a layered structure including a first electrode portion and a second electrode portion. The first electrode portion is formed as a film along the wall surfaces of each opening 102, 104, 106 and each contact hole 64, 80, 94. The second electrode portion is formed to fill the recess space defined by the first electrode portion. The first electrode portion has a layered structure of one metal film or multiple metal films. The first electrode portion may include a titanium-based metal film. The first electrode portion may have a single-layer structure formed of a titanium film or a titanium nitride (TiN) film. The first electrode portion may have a layered structure including a titanium film and a titanium nitride film stacked in any order. The second electrode portion may include at least one of tungsten, molybdenum (Mo), nickel, pure aluminum (aluminum with a purity of 99% or more), pure copper (copper with a purity of 99% or more), an aluminum alloy, and a copper alloy. In one example, the second electrode portion may include at least one of an AlCu alloy, an AlSi alloy, and an AlSiCu alloy, as examples of an aluminum alloy (copper alloy). In one example, the material constituting the second electrode portion is different from the material constituting the first electrode portion. In one example, the second electrode portion is formed of tungsten. An emitter electrode EM is formed on the interlayer insulating film 100 in the active region 20. The emitter electrode EM is in contact with each of the plug electrodes 108, 110, and 112.

[0102] [Cross-sectional Structure of Peripheral Region of RC-IGBT] An example of the cross-sectional structure of the peripheral region 28 of the RC-IGBT 10 will be described with reference to Fig. 5. Fig. 5 shows an example of the cross-sectional structure of the diode region 24 and the peripheral region 28.

[0103] RC-IGBT 10 includes at least one p-type field region 120 formed in a surface layer portion of first main surface 36A as a termination structure that relieves electric field concentration in peripheral region 28. In one example, a portion (inner peripheral end portion) of field region 120 may extend into first end diode region 24A. In other words, a portion of field region 120 may extend into active region 20.

[0104] In the first embodiment, the RC-IGBT 10 includes a plurality of field regions 120. The plurality of field regions 120 are formed in an annular shape surrounding the active region 20 in a plan view. The plurality of field regions 120 may have a higher p-type impurity concentration than the base region 42 (see FIG. 4). The plurality of field regions 120 may have a higher p-type impurity concentration than the anode region 70. The plurality of field regions 120 are in an electrically floating state.

[0105] In one example, the plurality of field regions 120 are formed deeper than the base region 42. In one example, the plurality of field regions 120 are formed deeper than the anode region 70. In one example, the outermost field region 120 of the plurality of field regions 120 is formed wider than the other field regions 120.

[0106] The RC-IGBT 10 includes, as a termination structure, an n-type channel stop region 122 formed in a surface layer portion of the first main surface 36A in the peripheral region 28. The channel stop region 122 is formed away from the multiple field regions 120 on the peripheral edge side of the semiconductor substrate 12. The channel stop region 122 has a higher n-type impurity concentration than the semiconductor layer 36. The channel stop region 122 is formed in an annular shape surrounding the multiple field regions 120 in a plan view. The channel stop region 122 may be exposed from first to fourth side surfaces 18A to 18D (see FIG. 3) of the semiconductor substrate 12.

[0107] The RC-IGBT 10 includes a peripheral insulating film 124 that covers the first main surface 36A in the peripheral region 28. The peripheral insulating film 124 is composed of the main surface insulating film 98 and the interlayer insulating film 100 in the active region 20.

[0108] The peripheral insulating film 124 includes at least one field opening 126 that selectively exposes each field region 120. In one example, one field region 120 is exposed by multiple field openings 126. Each field opening 126 is formed in an annular shape extending along the corresponding field region 120.

[0109] The RC-IGBT 10 includes a field connection electrode 128 electrically connected to the field region 120. A plurality of field connection electrodes 128 are provided corresponding to the plurality of field regions 120. The field connection electrodes 128 are embedded in the field openings 126 and are in contact with the field regions 120. Each field connection electrode 128 is electrically floating. Each field connection electrode 128 has a layered structure of one metal film or multiple metal films. Each field connection electrode 128 may include at least one of titanium, tungsten, aluminum, and copper. In one example, each field connection electrode 128 has a layered structure including a titanium-based metal film and a tungsten-based metal film.

[0110] The RC-IGBT 10 includes, as a termination structure, a plurality of field electrodes 130 formed on the peripheral insulating film 124. The plurality of field electrodes 130 are individually formed corresponding to the plurality of field regions 120. One field electrode 130 is connected to each of the plurality of field connection electrodes 128 connected to one field region 120. As a result, the plurality of field electrodes 130 are individually electrically connected to the plurality of field regions 120. Each field electrode 130 is in an electrically floating state. Each field electrode 130 is formed in an annular shape extending along the corresponding field region 120.

[0111] The outermost field electrode 130 of the plurality of field electrodes 130 includes an extension portion 132 that is extended toward the peripheral edge side of the semiconductor substrate 12. As a result, the outermost field electrode 130 is formed wider than the other field electrodes 130.

[0112] Each field electrode 130 has a layered structure of one metal film or multiple metal films. Each field electrode 130 may include at least one of titanium, tungsten, aluminum, and copper. In one example, each field electrode 130 has a layered structure including a titanium-based metal film and an aluminum-based metal film.

[0113] The peripheral insulating film 124 includes a channel stop opening 134 that exposes the channel stop region 122. In other words, the outer edge of the peripheral insulating film 124 is slightly smaller than the semiconductor substrate 12 in plan view.

[0114] The RC-IGBT 10 includes, as a termination structure, a channel stop electrode 136 formed on the peripheral insulating film 124. The channel stop electrode 136 extends into the channel stop opening 134 and contacts the channel stop region 122. This electrically connects the channel stop electrode 136 to the channel stop region 122. The channel stop electrode 136 is formed in a ring shape extending along the channel stop region 122 in a plan view. The channel stop electrode 136 has a layered structure of one metal film or multiple metal films. The channel stop electrode 136 may contain at least one of titanium, tungsten, aluminum, and copper. In one example, the channel stop electrode 136 may have a layered structure including a titanium-based metal film and an aluminum-based metal film.

[0115] [Cross-sectional Structure of Lifetime Control Region] An example of the cross-sectional structure of the lifetime control region 30 of the RC-IGBT 10 will be described with reference to FIGS. 4 and 5. FIG.

[0116] 4 and 5 , in the lifetime control region 30, crystal defects 138 are formed in the semiconductor layer 36. Since the lifetime control region 30 is formed across the diode region 24, the boundary region 26, and the peripheral region 28, the crystal defects 138 are present in the second region R2, the third region R3, and the fourth region R4 of the semiconductor layer 36.

[0117] 4, the crystal defects 138 are formed across the boundary region 26 and the diode region 24. In other words, the crystal defects 138 are formed across the second region R2 and the third region R3. In one example, the crystal defects 138 are formed across the entire area of ​​each diode region 24 and each boundary region 26 in a planar view. In other words, the crystal defects 138 are formed across the entire area of ​​the second region R2 and the third region R3 in a planar view.

[0118] The crystal defect 138 is formed closer to the second main surface 36B in the Z direction than the third trench electrode structure 72 and the fourth trench electrode structure 84. The crystal defect 138 is separated from the third trench electrode structure 72 and the fourth trench electrode structure 84 in the Z direction.

[0119] As shown in FIG. 5 , the crystal defects 138 are formed across the first end diode region 24A and the peripheral region 28. In other words, the crystal defects 138 are formed across the region of the second region R2 corresponding to the first end diode region 24A and the fourth region R4 adjacent to this region. In one example, the crystal defects 138 are formed across the entire first end diode region 24A and the entire peripheral region 28 in a planar view. In other words, the crystal defects 138 are formed across the region of the second region R2 corresponding to the first end diode region 24A and the entire fourth region R4 in a planar view. It can be said that the crystal defects 138 are formed across the entire lifetime control region 30 in a planar view.

[0120] The crystal defect 138 is formed, for example, in the Z direction closer to the second main surface 36B than the field region 120 and the channel stop region 122. The crystal defect 138 is separated from the field region 120 and the channel stop region 122 in the Z direction.

[0121] 6 to 19, an example of a method for manufacturing the RC-IGBT 10 will be described. An example of a method for manufacturing the active region 20 in the RC-IGBT 10 will be described below. In the following description, components common to the RC-IGBT 10 will be denoted by the same reference numerals.

[0122] As shown in FIG. 6 , the manufacturing method of the RC-IGBT 10 includes a step of preparing an n-type wafer 200, which is the base of the semiconductor substrate 12. The wafer 200 may be an FZ (Floating Zone) substrate formed through an FZ method. The wafer 200 has a first wafer main surface 202 and a second wafer main surface 204. The first wafer main surface 202 and the second wafer main surface 204 correspond to the first main surface 14 and the second main surface 16 of the semiconductor substrate 12, respectively. Next, an active region 20 and a peripheral region 28 (see FIG. 2 ) are defined in the wafer 200. That is, the wafer 200 is partitioned into the active region 20 and the peripheral region 28.

[0123] 7 to 17 , the method for manufacturing the RC-IGBT 10 includes a step of forming, in the active region 20, IGBT regions 22 and a plurality of diode regions 24 aligned in the Y direction, and a boundary region 26 formed between the IGBT regions 22 and diode regions 24 adjacent to each other in the Y direction. Details of this step will be described below.

[0124] As shown in FIG. 7 , a plurality of first trenches 46, a plurality of second trenches 54, a plurality of third trenches 74, and a plurality of fourth trenches 86 are formed in the active region 20. In this process, a hard mask (not shown) having a predetermined pattern is formed on the first wafer main surface 202. The hard mask exposes regions of the first wafer main surface 202 where the first to fourth trenches 46, 54, 74, and 86 are to be formed, and covers the remaining regions. The hard mask may be formed of an inorganic insulating film. Next, unnecessary portions of the wafer 200 are removed by etching using the hard mask. The etching method may be at least one of dry etching and wet etching. After the first to fourth trenches 46, 54, 74, and 86 are formed, the hard mask is removed.

[0125] 8, a base insulating film 206 is formed on the first wafer main surface 202. The base insulating film 206 includes a first insulating film 48, a second insulating film 56, a third insulating film 76, a fourth insulating film 88, and a main surface insulating film 98. The base insulating film 206 may be formed by, for example, at least one of a CVD (Chemical Vapor Deposition) method and an oxidation treatment method (e.g., a thermal oxidation treatment method).

[0126] 9, a base electrode film 208 is formed on the base insulating film 206. The base electrode film 208 is an electrode film that serves as a base for the first buried electrode 50, the second buried electrode 58, the third buried electrode 78, and the fourth buried electrode 90. The base electrode film 208 is embedded in the first to fourth trenches 46, 54, 74, and 86 with the base insulating film 206 interposed therebetween, and covers the first wafer main surface 202 with the base insulating film 206 interposed therebetween. The base electrode film 208 includes conductive polysilicon. The base electrode film 208 may be formed by a CVD method.

[0127] As shown in FIG. 10 , unnecessary portions of the base electrode film 208 (see FIG. 9 ) are removed by, for example, etching. At least one of dry etching and wet etching is used as the etching method. By removing the unnecessary portions of the base electrode film 208, the main surface insulating film 98 is exposed. Then, the first buried electrode 50, the second buried electrode 58, the third buried electrode 78, and the fourth buried electrode 90 are formed.

[0128] 11 , a p-type base region 42, an n-type emitter region 60, an n-type CS region 62, a p-type anode region 70, and a p-type boundary well region 92 are formed in the surface layer portion of the first wafer main surface 202 in the active region 20. The base region 42, the emitter region 60, and the CS region 62 are formed in the surface layer portion of the first wafer main surface 202 in the IGBT region 22, the anode region 70 is formed in the surface layer portion of the first wafer main surface 202 in the diode region 24, and the boundary well region 92 is formed in the surface layer portion of the first wafer main surface 202 in the boundary region 26. The order of the steps for forming these impurity regions is arbitrary. These impurity regions are formed by implanting n-type or p-type impurities through a resist mask (not shown) having a predetermined pattern.

[0129] 12, an interlayer insulating film 100 is formed to cover the first insulating film 48, the second insulating film 56, the third insulating film 76, the fourth insulating film 88, and the main surface insulating film 98. The interlayer insulating film 100 may be formed by, for example, a CVD method.

[0130] 13, a resist mask 210 having a predetermined pattern is formed on the interlayer insulating film 100. The resist mask 210 exposes regions where the first opening 102, the second opening 104, and the third opening 106 are to be formed, and covers the other regions.

[0131] Next, unnecessary portions of the interlayer insulating film 100 are removed by etching using the resist mask 210. At least one of dry etching and wet etching may be used as the etching method. By removing the unnecessary portions of the interlayer insulating film 100, the main surface insulating film 98 is exposed. As a result, a first opening 102, a second opening 104, and a third opening 106 are formed in the interlayer insulating film 100.

[0132] Next, the first wafer main surface 202 exposed from the first opening 102, the second opening 104, and the third opening 106 is removed by etching. At least one of dry etching and wet etching may be used as the etching method. As a result, the contact hole 64 communicating with the first opening 102, the contact hole 80 communicating with the second opening 104, and the contact hole 94 communicating with the third opening 106 are formed.

[0133] Next, p-type impurities are implanted by ion implantation into the portions of the first wafer main surface 202 exposed through the contact holes 64, 80, and 94. This forms p-type contact regions 66, 82, and 96. Thereafter, the resist mask 210 is removed. Note that different resist masks may be used for etching the interlayer insulating film 100 and etching the wafer 200.

[0134] 14, a plug electrode film 212 is formed on the interlayer insulating film 100. The plug electrode film 212 is an electrode film that serves as a base for the first plug electrode 108, the second plug electrode 110, and the third plug electrode 112. The plug electrode film 212 is also embedded in the multiple contact holes 64, 80, and 94. The plug electrode film 212 may be formed by at least one of a sputtering method and a vapor deposition method.

[0135] As shown in FIG. 15 , unnecessary portions of the plug electrode film 212 (see FIG. 14 ) are removed. The unnecessary portions of the plug electrode film 212 may be removed by etching. As the etching method, at least one of dry etching and wet etching is used. As the unnecessary portions of the plug electrode film 212, portions of the plug electrode film 212 located outside the first opening 102, the second opening 104, and the third opening 106 are removed. As a result, the first plug electrode 108, the second plug electrode 110, and the third plug electrode 112 are formed.

[0136] As shown in FIG. 16 , a principal surface electrode film 214 is formed on the interlayer insulating film 100. The principal surface electrode film 214 is an electrode film that serves as a base for the emitter electrode EM and the gate electrode GT (see FIG. 1 ). The principal surface electrode film 214 may be formed by at least one of a sputtering method and a vapor deposition method. Next, unnecessary portions of the principal surface electrode film 214 are removed by patterning using a resist mask (not shown). This forms the emitter electrode EM and the gate electrode GT.

[0137] 17 , an n-type buffer region 38, a p-type collector region 40, and an n-type cathode region 68 are formed in the surface layer portion of the second wafer main surface 204. The order of the steps of forming these impurity regions is arbitrary. The buffer region 38 may be formed by implanting n-type impurities into the entire surface layer portion of the second wafer main surface 204. The collector region 40 may be formed by implanting p-type impurities into the entire IGBT region 22 and boundary region 26 in the surface layer portion of the second wafer main surface 204. The cathode region 68 may be formed by implanting n-type impurities into the entire diode region 24 in the surface layer portion of the second wafer main surface 204.

[0138] Through the above steps, the IGBT regions 22 and multiple diode regions 24 aligned in the Y direction, and the boundary region 26 formed between the IGBT regions 22 and diode regions 24 adjacent in the Y direction, are formed in the active region 20. Here, first end diode regions 24A, 24B (see FIG. 2 ) that are continuous with the peripheral region 28 are formed at both ends of the active region 20 in the X direction.

[0139] As shown in FIG. 18, the manufacturing method of the RC-IGBT 10 includes a step of providing a peripheral region 28 (see FIG. 5), a plurality of diode regions 24, and a lifetime control region 30 that overlaps with the boundary region 26 in a plan view within the wafer 200.

[0140] This process includes forming a metal mask 216 that covers the IGBT region 22 on the second wafer main surface 204 and exposes multiple diode regions 24, the boundary region 26, and the peripheral region 28, and irradiating helium (He) onto the semiconductor layer 36 of the wafer 200 from the second wafer main surface 204 side.

[0141] In one example, a metal mask 216 having a predetermined pattern is first formed on the second wafer main surface 204. The metal mask 216 is in contact with the second wafer main surface 204. The metal mask 216 exposes the diode region 24, boundary region 26, and peripheral region 28 of the second wafer main surface 204 and covers the IGBT region 22. Next, helium is irradiated toward the second wafer main surface 204. As a result, crystal defects 138 are formed in the diode region 24, boundary region 26, and peripheral region 28, which are regions of the semiconductor layer 36 of the wafer 200 that are exposed by the metal mask 216. On the other hand, in the IGBT region 22, which is a region of the wafer 200 covered by the metal mask 216, the metal mask 216 prevents helium from being implanted into the semiconductor layer 36 of the IGBT region 22. As a result, no crystal defects 138 are formed in the IGBT region 22. That is, crystal defects 138 are formed in the second region R2 of the semiconductor layer 36 corresponding to the diode region 24, the third region R3 of the semiconductor layer 36 corresponding to the boundary region 26, and the fourth region R4 of the semiconductor layer 36 corresponding to the peripheral region 28 (see FIG. 5). On the other hand, crystal defects 138 are not formed in the first region R1 of the semiconductor layer 36 corresponding to the IGBT region 22. Through the above steps, the lifetime control region 30 is formed.

[0142] In this way, in the process of providing the lifetime control region 30 within the wafer 200, the lifetime control region 30 is formed so as to span the first end diode regions 24A, 24B (see Figure 3) formed at both ends of the active region 20 in the Y direction and the portion of the peripheral region 28 that is continuous with the first end diode regions 24A, 24B.

[0143] Here, the position of the metal mask 216 is set so as to cover at least the IGBT region 22 and expose the diode region 24. Therefore, it is permissible for the boundary region 26 to be covered by the metal mask 216 due to misalignment of the metal mask 216. It is also permissible for a part of the diode region 24 closer to the boundary region 26 to be covered by the metal mask 216 due to misalignment of the metal mask 216. It is also permissible for a part of the IGBT region 22 closer to the boundary region 26 to be exposed from the metal mask 216 due to misalignment of the metal mask 216.

[0144] 19, the method for manufacturing RC-IGBT 10 includes a step of forming collector electrode CL on second wafer main surface 204. This step is performed after the step of providing lifetime control region 30 in wafer 200 (see FIG. 18).

[0145] In one example, the collector electrode CL is formed on the second wafer main surface 204 by at least one of sputtering and vapor deposition. Thereafter, the wafer 200 is cut in its thickness direction by, for example, dicing, thereby cutting out a plurality of RC-IGBTs 10. Through the above steps, the RC-IGBTs 10 are manufactured.

[0146] [Operation] The operation of the RC-IGBT 10 of the first embodiment will be described. When the IGBT region 22 is formed in the active region 20 closer to the peripheral region 28 in the Y direction than the diode region 24, a boundary region 26 is formed between the outermost IGBT region 22 in the Y direction and the peripheral region 28 aligned with the IGBT region 22 in the Y direction. In other words, a boundary region 26 is formed at each end of the active region 20 in the Y direction to prevent the lifetime control region 30 from being formed in the IGBT region 22. As the number of boundary regions 26 in the active region 20 increases, the area of ​​at least one of the IGBT region 22 and the diode region 24 decreases accordingly. This makes it difficult to improve the electrical characteristics of at least one of the IGBT and the diode. Furthermore, as the number of boundary regions 26 in the active region 20 increases, it becomes difficult to miniaturize the RC-IGBT 10 while maintaining the electrical characteristics of the IGBT and the diode.

[0147] According to the RC-IGBT 10 of the first embodiment, first end diode regions 24A, 24B are formed at both ends of the active region 20 in the Y direction. In other words, no boundary region 26 is formed at both ends of the active region 20 in the Y direction. This allows the number of boundary regions 26 in the active region 20 to be reduced, thereby allowing the area of ​​at least one of the IGBT region 22 and the diode region 24 in the active region 20 to be increased. This makes it possible to improve the electrical characteristics of at least one of the IGBT and the diode. Furthermore, it is possible to reduce the size of the RC-IGBT 10 while maintaining the electrical characteristics of the IGBT and the diode.

[0148] [Effects] The RC-IGBT 10 of the first embodiment has the following effects. (1-1) The RC-IGBT 10 includes a semiconductor substrate 12, an active region 20 provided in the semiconductor substrate 12, and a peripheral region 28 provided in the semiconductor substrate 12 and surrounding the active region 20 in a plan view. The active region 20 includes an IGBT region 22, a plurality of diode regions 24, and a boundary region 26 formed between adjacent IGBT regions 22 and diode regions 24. The RC-IGBT 10 includes a lifetime control region 30 provided in the semiconductor substrate 12 and overlapping the peripheral region 28, the plurality of diode regions 24, and the boundary region 26 in a plan view. The plurality of diode regions 24 include first end diode regions 24A, 24B, which are formed at both ends of the active region 20 in the Y direction in a plan view and are continuous with the peripheral region 28. The lifetime control region 30 includes first end regions 32A, 32B formed across the first end diode regions 24A, 24B and portions of the peripheral region 28 that are continuous with the first end diode regions 24A, 24B.

[0149] With this configuration, the first end diode regions 24A, 24B are formed at both ends of the active region 20 in the Y direction, thereby preventing the formation of the boundary region 26 at both ends of the active region 20 in the Y direction. This makes it possible to improve the electrical characteristics of at least one of the IGBT and the diode. Furthermore, it is possible to reduce the size of the RC-IGBT 10 while maintaining the electrical characteristics of the IGBT and the diode.

[0150] (1-2) The length of the boundary region 26 in the Y direction is shorter than the length of the IGBT region 22 in the Y direction and the length of the diode region 24 in the Y direction. This configuration makes it possible to increase the ratio of the area of ​​at least one of the IGBT region 22 and the diode region 24 to the area of ​​the active region 20. This makes it possible to improve the electrical characteristics of at least one of the IGBT and the diode.

[0151] (1-3) The length of the first end diode regions 24A, 24B in the X direction is equal to the length of the active region 20 in the X direction. With this configuration, the IGBT region 22 is not formed at both ends of the active region 20 in the Y direction, and therefore the boundary region 26 is not formed at both ends of the active region 20 in the Y direction. This makes it possible to improve the electrical characteristics of at least one of the IGBT and the diode. Furthermore, it is possible to reduce the size of the RC-IGBT 10 while maintaining the electrical characteristics of the IGBT and the diode.

[0152] (1-4) A method for manufacturing an RC-IGBT 10 includes the steps of: preparing a wafer 200 having a first wafer main surface 202 and a second wafer main surface 204 opposite to the first wafer main surface 202, the wafer 200 being partitioned into an active region 20 and a peripheral region 28 surrounding the active region 20; forming, in the active region 20, IGBT regions 22 and multiple diode regions 24 aligned in the Y direction, and a boundary region 26 formed between adjacent IGBT regions 22 and diode regions 24 in the X direction; and providing, in the wafer 200, a lifetime control region 30 that overlaps with the peripheral region 28, the multiple diode regions 24, and the boundary region 26 as viewed from the Z direction. The multiple diode regions 24 include first end diode regions 24A, 24B, which are formed at both ends of the active region 20 in the X direction and are continuous with the peripheral region 28 as viewed from the Z direction. In the process of providing the lifetime control region 30 within the wafer 200, the lifetime control region 30 is formed so as to span the first end diode regions 24A, 24B and the portion of the peripheral region 28 that is continuous with the first end diode regions 24A, 24B.

[0153] With this configuration, the first end diode regions 24A, 24B are formed at both ends of the active region 20 in the Y direction, thereby preventing the formation of the boundary region 26 at both ends of the active region 20 in the Y direction. This makes it possible to improve the electrical characteristics of at least one of the IGBT and the diode. Furthermore, it is possible to reduce the size of the RC-IGBT 10 while maintaining the electrical characteristics of the IGBT and the diode.

[0154] Second Embodiment An RC-IGBT 10 of a second embodiment will be described with reference to Figures 20 and 21. The RC-IGBT 10 of the second embodiment differs from the RC-IGBT 10 of the first embodiment in the extent of the diode region 24 and the lifetime control region 30. In the following, components common to the RC-IGBT 10 of the first embodiment are denoted by the same reference numerals, and their description will be omitted. Note that the hatched region in Figure 21 indicates the lifetime control region 30.

[0155] Fig. 20 shows an example of the planar structure of the semiconductor substrate 12 of the RC-IGBT 10. Fig. 21 shows the lifetime control region 30 in Fig. 20. In Fig. 21, the emitter electrode EM and the gate electrode GT are indicated by two-dot chain lines to make the drawing easier to understand.

[0156] 20 , in the active region 20, the IGBT region 22, the diode region 24, and the boundary region 26 are arranged in the Y direction, similar to the first embodiment. Also, similar to the first embodiment, the diode region 24 includes first end diode regions 24A, 24B located at both ends of the active region 20 in the Y direction.

[0157] The diode region 24 of the second embodiment further includes second end diode regions 24D, 24E located at both ends of the active region 20 in the X direction. In a plan view, the second end diode regions 24D, 24E extend in the Y direction.

[0158] The second end diode regions 24D and 24E are continuous with the first end diode regions 24A and 24B and the central diode region 24C. Therefore, in the second embodiment, it can be said that a rectangular frame-shaped diode region 24 is formed on the outer periphery of the active region 20.

[0159] The second end diode regions 24D, 24E include regions overlapping with the IGBT regions 22 when viewed from the X direction. That is, the second end diode regions 24D, 24E include regions aligned with the IGBT regions 22 in the X direction. End boundary regions 26A, 26B are formed in the active region 20 between the second end diode regions 24D, 24E and the IGBT regions 22 in the X direction. The boundary region 26 can be said to include an end boundary region 26A formed between the second end diode region 24D and the IGBT region 22 in the X direction and an end boundary region 26B formed between the second end diode region 24E and the IGBT region 22 in the X direction. The end boundary regions 26A, 26B are continuous with the boundary regions 26 formed on both sides of the IGBT region 22 in the Y direction. Therefore, the boundary region 26 in the second embodiment is formed in the shape of a rectangular frame surrounding the IGBT region 22 in a plan view. As described above, in the second embodiment, the active region 20 includes a region in which the diode region 24, the boundary region 26, and the IGBT region 22 are aligned in the X direction.

[0160] Since the second end diode regions 24D, 24E and the end boundary regions 26A, 26B are formed on both sides of each IGBT region 22 in the X direction, the dimension in the X direction of each IGBT region 22 is smaller than the dimension in the X direction of the active region 20. In other words, the dimension in the X direction of each IGBT region 22 in the second embodiment is smaller than the dimension in the X direction of each IGBT region 22 in the first embodiment.

[0161] Since the second end diode regions 24D, 24E are formed in the active region 20, the ratio of the area of ​​the diode region 24 to the area of ​​the active region 20 in a planar view becomes higher, while the ratio of the area of ​​the IGBT region 22 to the area of ​​the active region 20 becomes lower.

[0162] As shown in FIG. 21 , the lifetime control region 30 includes second end diode regions 24D, 24E and second end regions 32D, 32E formed across portions of the peripheral region 28 that are continuous with the second end diode regions 24D, 24E.

[0163] The second end regions 32D, 32E extend along the Y direction in a plan view and are continuous with the first end regions 32A, 32B and the central region 32C. The second end regions 32D, 32E include the portion of the outer circumferential region 28 between the first end regions 32A, 32B in the Y direction, the second end diode regions 24D, 24E, and the end boundary regions 26A, 26B.

[0164] In this way, the formation of second end regions 32D, 32E makes the dimension in the X direction of the region of lifetime control region 30 adjacent to first side surface 18A and second side surface 18B in plan view larger than in the first embodiment. Note that according to the second embodiment, the same effects as in the first embodiment can be obtained.

[0165] 22 to 24, an RC-IGBT 10 of a third embodiment will be described. The RC-IGBT 10 of the third embodiment differs from the RC-IGBT 10 of the first embodiment in the configurations of the emitter electrode EM and the gate electrode GT, and in the ranges of the IGBT region 22, the diode region 24, and the lifetime control region 30. In the following, components common to the RC-IGBT 10 of the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0166] Fig. 22 shows an example of the planar structure of the RC-IGBT 10. Fig. 23 shows an example of the planar structure of the semiconductor substrate 12 of the RC-IGBT 10. Fig. 24 shows the lifetime control region 30 in Fig. 23. In Figs. 23 and 24, the emitter electrode EM and the gate electrode GT are indicated by two-dot chain lines to make the drawings easier to understand.

[0167] 22, the gate electrode GT includes a gate pad GP and gate fingers GF1 and GF2. In one example, the gate pad GP and the gate fingers GF1 and GF2 are integrally formed.

[0168] The gate finger GF1 includes a first portion extending in the X direction from the end of the gate pad GP closer to the first side surface 18A toward the first side surface 18A, and a second portion extending in the Y direction from the first portion toward the third side surface 18C.

[0169] The gate finger GF2 includes a third portion extending in the X direction from the end of the gate pad GP closer to the second side surface 18B toward the second side surface 18B, and a fourth portion extending in the Y direction from the third portion toward the third side surface 18C.

[0170] The emitter electrode EM includes a first slit SL1 formed so as to avoid the second portion of the gate finger GF1, and a second slit SL2 formed so as to avoid the fourth portion of the gate finger GF2.

[0171] 23 , the active region 20 includes one IGBT region 22, two diode regions 24, and two boundary regions 26. The IGBT region 22, the diode regions 24, and the boundary region 26 are arranged in the X direction. Here, in the third embodiment, the X direction corresponds to the "first direction." Therefore, the Y direction corresponds to the "second direction."

[0172] In the third embodiment, the diode region 24 is composed of first end diode regions 24 A and 24 B. Two boundary regions 26 are formed in a distributed manner between the first end diode region 24 A and the IGBT region 22 in the X direction and between the first end diode region 24 B and the IGBT region 22 in the X direction.

[0173] The second portion of gate finger GF1 and the fourth portion of gate finger GF2 indicated by the two-dot chain lines are arranged in positions that overlap with both ends in the X direction of the IGBT region 22 in a plan view. In other words, the second portion of gate finger GF1 and the fourth portion of gate finger GF2 are arranged in positions in the IGBT region 22 adjacent to the boundary region 26 in the X direction.

[0174] 24 , the lifetime control region 30 is formed in the peripheral region 28, the first end diode regions 24A and 24B, and the boundary region 26. Therefore, the lifetime control region 30 includes a first end region 32A formed across the first end diode region 24A and a portion of the peripheral region 28 that is continuous with the first end diode region 24A in the X direction, and a first end region 32B formed across the first end diode region 24B and a portion of the peripheral region 28 that is continuous with the first end diode region 24B in the X direction. It can also be said that the gate fingers GF1 and GF2 are formed within the lifetime control region 30 in a plan view.

[0175] [Effects] According to the RC-IGBT 10 of the third embodiment, the following effects can be obtained: (3-1) The diode region 24 is made up of the first end diode regions 24A and 24B.

[0176] With this configuration, the diode region 24 and the IGBT region 22 are aligned in only two places, resulting in two boundary regions 26. This minimizes the number of boundary regions 26. Furthermore, since the regions other than the two ends of the active region 20 in the X direction become the IGBT region 22, it is possible to improve electrical characteristics such as reducing the on-resistance of the IGBT in the RC-IGBT 10.

[0177] <Modifications> The above-described embodiments can be modified as follows. The following modifications can be combined with each other as long as no technical contradiction occurs. Furthermore, the first to third embodiments can be combined with each other as long as no technical contradiction occurs.

[0178] In the first and second embodiments, the Y-direction dimension L2 of the central region 32C of the lifetime control region 30 can be changed as desired. In one example, the Y-direction dimension L2 of the central region 32C may be larger than the Y-direction dimensions LA1, LB1 of the first end regions 32A, 32B. In this case, the Y-direction dimension of the central diode region 24C may be larger than the Y-direction dimensions of the first end diode regions 24A, 24B.

[0179] In the first and second embodiments, the central diode region 24C may be omitted. Accordingly, the boundary regions 26 formed on both sides of the central diode region 24C in the Y direction are omitted. In this case, the central region 32C is omitted from the lifetime control region 30.

[0180] In the second embodiment, the extent of the second end regions 32D, 32E of the lifetime control region 30 can be changed as desired. For example, the X-direction dimension of the second end regions 32D, 32E may be smaller than the Y-direction dimension of the first end regions 32A, 32B. Alternatively, the X-direction dimension of the second end regions 32D, 32E may be larger than the Y-direction dimension of the first end regions 32A, 32B.

[0181] In the third embodiment, it is possible to arbitrarily change the arrangement of the diode regions 24. In one example, the diode regions 24 may include a central diode region 24C, similar to the first embodiment.

[0182] In the third embodiment, the shape of the gate electrode GT can be changed as desired. For example, the number of gate fingers GF1, GF2 may be three or more. Furthermore, at least one of the gate fingers GF1, GF2 may be omitted from the gate electrode GT.

[0183] In the third embodiment, the positions of the second portion of the gate finger GF1 and the fourth portion of the gate finger GF2 can be changed as desired. For example, the second portion of the gate finger GF1 and the fourth portion of the gate finger GF2 may be arranged at positions that overlap with the boundary region 26 in a plan view.

[0184] In each embodiment, the IGBT structure in the IGBT region 22 can be changed as desired. For example, in the IGBT structure, the second trench electrode structure 52 may be changed to the first trench electrode structure 44. In addition, in the IGBT structure, the gate electrode structure is not limited to the trench electrode structure and can be changed as desired.

[0185] In each embodiment, the diode structure in the diode region 24 can be changed as desired. The anode electrode structure in the diode structure is not limited to the third trench electrode structure 72 and can be changed as desired.

[0186] The fourth trench electrode structure 84 may be omitted from the boundary region 26 in each embodiment. In each embodiment, the number of IGBT regions 22, diode regions 24, and boundary regions 26 can be changed as desired. In the first and third embodiments, the active region 20 only needs to include the first end diode regions 24A and 24B. In the second embodiment, the active region 20 only needs to include the first end diode regions 24A and 24B and the second end diode regions 24D and 24E.

[0187] In each embodiment, the width of each of the IGBT region 22, the diode region 24, and the boundary region 26 can be changed as desired. For example, the width of the boundary region 26 may be equal to or greater than the width of the diode region 24. For another example, the width of the boundary region 26 may be equal to or greater than the width of the IGBT region 22.

[0188] In each embodiment, the lifetime control region 30 does not have to include the boundary region 26. In other words, the lifetime control region 30 may be configured to include the diode region 24 and the peripheral region 28. Furthermore, the lifetime control region 30 does not have to include the region of the peripheral region 28 that is separated from the diode region 24.

[0189] In each embodiment, as shown in FIG. 25 , the active region 20 may be formed to avoid the gate electrode GT in plan view. In this case, two first end diode regions 24B are formed spaced apart from each other in the X direction. The two first end diode regions 24B can also be said to be formed dispersedly on both sides of the gate electrode GT in the X direction in plan view. Note that, in the active region 20 shown in FIG. 25 , the arrangement of the IGBT region 22, the diode region 24, and the boundary region 26 can be changed as desired. As an example, in the active region 20 shown in FIG. 25 , the arrangement of the IGBT region 22, the diode region 24, and the boundary region 26 may be changed to that of the second or third embodiment.

[0190] In each embodiment, the electrical connection structure between the emitter electrode EM and the anode region 70 in the diode region 24 can be changed as desired. Also, the electrical connection structure between the emitter electrode EM and the boundary well region 92 in the boundary region 26 can be changed as desired.

[0191] 26 , the second plug electrode 110, the interlayer insulating film 100, and the main surface insulating film 98 are omitted in the diode region 24. As a result, the emitter electrode EM is formed so as to contact the first main surface 36A in the diode region 24. The emitter electrode EM is electrically connected to the anode region 70 and the third buried electrode 78 of the third trench electrode structure 72.

[0192] In another example, the third plug electrode 112, the interlayer insulating film 100, and the main surface insulating film 98 (all see FIG. 4 ) are omitted in the boundary region 26. As a result, the emitter electrode EM is formed so as to contact the first main surface 36A in the boundary region 26. The emitter electrode EM is electrically connected to the boundary well region 92 and the fourth buried electrode 90 of the fourth trench electrode structure 84.

[0193] In each embodiment, a structure may be employed in which the conductivity types of the semiconductor layer 36, the buffer region 38, the collector region 40, the base region 42, the emitter region 60, the CS region 62, and the boundary well region 92 are reversed. That is, a p-type region may be an n-type region, and an n-type region may be a p-type region.

[0194] The statement "at least one of A and B" in the present disclosure should be understood to mean "A only, or B only, or both A and B." One or more of the various examples described herein can be combined to the extent that they are not technically inconsistent.

[0195] The term "on" as used in this disclosure includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is mounted on a second element" is intended to mean that in some embodiments, the first element may be placed directly on the second element in contact with the second element, while in other embodiments, the first element may be placed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0196] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z direction described herein being "up" and "down" in the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0197] <Supplementary Notes> The technical ideas that can be understood from the above-described embodiments and modified examples are described below. Note that the reference numerals of the components of the embodiments corresponding to the components described in each supplementary note are shown in parentheses. The reference numerals are shown as examples to aid understanding, and the components described in each supplementary note should not be limited to the components indicated by the reference numerals.

[0198] [Supplementary Note 1] A semiconductor device comprising: a semiconductor substrate (12); an active region (20) provided in the semiconductor substrate (12); and a peripheral region (28) provided in the semiconductor substrate (12) and surrounding the active region (20) when viewed in a thickness direction (Z direction) of the semiconductor substrate (12), wherein the active region (20) includes: an IGBT region (22) and a plurality of diode regions (24) aligned in a first direction (Y direction); and a boundary region (26) formed between the IGBT region (22) and a diode region (24) that is one of the plurality of diode regions (24) adjacent to each other in the first direction (Y direction), and a lifetime control region (30) provided in the semiconductor substrate (12) and overlapping with the peripheral region (28), the plurality of diode regions (24), and the boundary region (26) when viewed in the thickness direction (Z direction), the plurality of diode regions (24) include first end diode regions (24A, 24B), which are formed at both ends of the active region (20) in the first direction (Y direction) when viewed from the thickness direction (Z direction) and are continuous with the peripheral region (28), and the lifetime control region (30) includes first end regions (32A, 32B) formed across the first end diode regions (24A, 24B) and portions of the peripheral region (28) that are continuous with the first end diode regions (24A, 24B).

[0199] [Supplementary Note 2] The RC-IGBT according to Supplementary Note 1, wherein the lifetime control region (30) includes a central region (32C) formed closer to the center of the active region (20) than the first end regions (32A, 32B) in the first direction (Y direction), and dimensions (LA1, LB1) of the first end regions (32A, 32B) in the first direction (Y direction) are greater than a dimension (L2) of the central region (32C) in the first direction (Y direction).

[0200] [Supplementary Note 3] The RC-IGBT according to Supplementary Note 1 or 2, wherein the diode region (24) comprises the first end diode region (24A, 24B).

[0201] [Supplementary Note 4] The RC-IGBT according to Supplementary Note 1 or 2, wherein a direction orthogonal to the first direction (Y direction) when viewed from the thickness direction (Z direction) is defined as a second direction (X direction), and in the second direction (X direction), the diode region (24) includes second end diode regions (24D, 24E) formed on both ends of the active region (20), and the lifetime control region (30) includes second end regions (32D, 32E) formed across the second end diode regions (24D, 24E) and portions of the outer circumferential region (28) that are continuous with the second end diode regions (24D, 24E).

[0202] [Supplementary Note 5] The RC-IGBT according to Supplementary Note 4, wherein the lifetime control region (30) includes a central region (32C) formed closer to the center of the active region (20) than the first end regions (32A, 32B) in the first direction (Y direction), and the second end regions (32D, 32E) are continuous with both the first end regions (32A, 32B) and the central region (32C).

[0203] [Supplementary Note 6] The RC-IGBT according to any one of Supplementary Notes 1 to 5, wherein a direction orthogonal to the first direction (Y direction) when viewed from the thickness direction (Z direction) is defined as a second direction (X direction), and the first end diode regions (24A, 24B) extend along the second direction (X direction).

[0204] [Supplementary Note 7] The RC-IGBT according to any one of Supplementary Notes 1 to 6, wherein a length of the boundary region (26) in the first direction (Y direction) is shorter than both a length of the IGBT region (22) in the first direction (Y direction) and a length of the diode region (24) in the first direction (Y direction).

[0205] [Supplementary Note 8] The RC-IGBT according to any one of Supplementary Notes 1 to 7, comprising: a gate electrode (GT) provided on the semiconductor substrate (20); and gate fingers (GF1, GF2) electrically connected to the gate electrode (GT), wherein, as viewed from the thickness direction (Z direction), the gate fingers (GF1, GF2) are arranged at positions overlapping the IGBT region (22) adjacent to the first end diode region (24A, 24B) with the boundary region (26) interposed therebetween.

[0206] [Supplementary Note 9] The RC-IGBT according to any one of Supplementary Notes 1 to 8, wherein the lifetime control region (30) is a region in which crystal defects (138) are formed inside the semiconductor substrate (12).

[0207] [Supplementary Note 10] The semiconductor substrate (12) includes a semiconductor layer (36) of a first conductivity type (n-type) including a first main surface (36A) and a second main surface (36B) opposite to the first main surface (36A), and the IGBT region (22) includes an IGBT structure including a base region (42) of a second conductivity type (p-type) formed in the first main surface (36A), an emitter region (60) of the first conductivity type (n-type) formed in the base region (42), and a gate electrode (GT) facing the base region (42) and the emitter region (60) via a gate insulating layer (48), and a collector region (40) of the second conductivity type (p-type) formed in the second main surface (36B), the diode region (24) includes an anode region (70) of a second conductivity type (p-type) formed on the first main surface (36A) and a cathode region (68) of a first conductivity type (n-type) formed on the second main surface (36B); the boundary region (26) includes a boundary well region (92) formed in a region overlapping with the collector region (40) and not overlapping with the cathode region (68) when viewed from the thickness direction (Z direction); the semiconductor layer (36) includes a first region (R1) corresponding to the IGBT region (22), a second region (R2) corresponding to the diode region (24), a third region (R3) corresponding to the boundary region (26), and a fourth region (R4) corresponding to the outer periphery region (28); and the crystal defects (138) are present in the second region (R2), the third region (R3), and the fourth region (R4). RC-IGBT as described in Appendix 9.

[0208] [Supplementary Note 11] The method comprises the steps of: preparing a wafer (200) having a first wafer main surface (202) and a second wafer main surface (204) opposite to the first wafer main surface (202), the wafer (200) being partitioned into an active region (20) and a peripheral region (28) surrounding the active region (20); forming, in the active region (20), an IGBT region (22) and a plurality of diode regions (24) aligned in a first direction (Y direction), and a boundary region (26) formed between the IGBT region (22) and a diode region (24) that is one of the plurality of diode regions adjacent in the first direction (Y direction); and providing, in the wafer (200), a lifetime control region (30) that overlaps with the peripheral region (28), the plurality of diode regions (24), and the boundary region (26), as viewed in the thickness direction (Z direction) of the wafer (200), the plurality of diode regions (24) include first end diode regions (24A, 24B), which are formed at both ends of the active region (20) in the first direction (Y direction) when viewed from the thickness direction (Z direction) and are continuous with the peripheral region (28); and in the step of providing the lifetime control region (30) in the wafer (200), the lifetime control region (30) is formed so as to straddle the first end diode regions (24A, 24B) and a portion of the peripheral region (28) that is continuous with the first end diode regions (24A, 24B).

[0209] [Supplementary Note 12] The method for manufacturing an RC-IGBT according to Supplementary Note 11, wherein the step of providing the lifetime control region (30) in the wafer (200) includes the steps of: forming a metal mask (216) that covers the IGBT region (22) on the second wafer main surface (204) and exposes the plurality of diode regions (24), the boundary region (26), and the outer periphery region (28); and irradiating helium onto a semiconductor layer (36) of the wafer (200) from the second wafer main surface (204) side.

[0210] [Supplementary Note 13] The method for manufacturing an RC-IGBT according to Supplementary Note 11 or 12, further comprising the step of forming a collector electrode (CL) on the second wafer main surface (204), wherein the step of forming the collector electrode (CL) on the second wafer main surface (204) is performed after the step of providing the lifetime control region (30) in the wafer (200).

[0211] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0212] 10...RC-IGBT 12...Semiconductor substrate 14...First main surface 16...Second main surface 18A-18D...First to fourth side surfaces 20...Active region 22...IGBT region 24...Diode region 24A, 24B...First end diode region 24C...Central diode region 24D, 24E...Second end diode region 26...Boundary region 26A, 26B...End boundary region 28...Peripheral region 30...Lifetime control region 32A, 32B...First end region 32C...Central region 32D,32E... Second end region 36... Semiconductor layer 36A... First main surface 36B... Second main surface 38... Buffer region 40... Collector region 42... Base region 44... First trench electrode structure 46... First trench 48... First insulating film 50... First buried electrode 52... Second trench electrode structure 54... Second trench 56... Second insulating film 58... Second buried electrode 60... Emitter region 62... CS region 64... Contact hole 66... ​​Contact region 68... Cathode region 70... Anode region 72... Third trench electrode structure 74... Third trench 76... Third insulating film 78... Third buried electrode 80... Contact hole 82... Contact region 84... Fourth trench electrode structure 86... Fourth trench 88... Fourth insulating film 90... Fourth buried electrode 92...Boundary well region 94...Contact hole 96...Contact region 98...Main surface insulating film 100...Interlayer insulating film 102...First opening 104...Second opening 106...Third opening 108...First plug electrode 110...Second plug electrode 112...Third plug electrode 120...Field region 122...Channel stop region 124...Peripheral insulating film 126...Field opening 128...Field connection electrode 130...Field electrode 132...Lead portion 134...Channel stop opening 136...Channel stop electrode 138...Crystal defect 200...Wafer 202...First wafer main surface 204...Second wafer main surface 206...Base insulating film 208...Base electrode film 210...Resist mask 212...Plug electrode film 214...Main surface electrode film 216...Metal mask EM...Emitter electrode SL1...First slit SL2...second slit GT...gate electrode GP...gate pad GF1, GF2...gate finger CL...collector electrode R1 to R4...first to fourth regions LA1, LB1...dimension in the Y direction of the first end region L2...dimension in the Y direction of the central region

Claims

1. a semiconductor substrate; an active region provided on the semiconductor substrate; a peripheral region provided on the semiconductor substrate and surrounding the active region when viewed in a thickness direction of the semiconductor substrate; Equipped with The active area is an IGBT region and a plurality of diode regions aligned in a first direction; a boundary region formed between the IGBT region and a diode region that is one of the plurality of diode regions adjacent to each other in the first direction; Including, a lifetime control region provided in the semiconductor substrate and overlapping with the outer periphery region, the plurality of diode regions, and the boundary region when viewed in the thickness direction; the plurality of diode regions include first end diode regions, the first end diode regions being formed on both ends of the active region in the first direction when viewed from the thickness direction and being continuous with the peripheral region; The lifetime control region includes a first end region formed across the first end diode region and a portion of the outer periphery region that is continuous with the first end diode region. RC-IGBT.

2. the lifetime control region includes a central region formed closer to the center of the active region than the first end region in the first direction, The dimension of the first end region in the first direction is greater than the dimension of the central region in the first direction. The RC-IGBT according to claim 1.

3. The diode region comprises the first end diode region. The RC-IGBT according to claim 1.

4. A direction perpendicular to the first direction when viewed from the thickness direction is defined as a second direction, In the second direction, the diode region includes second end diode regions formed on both ends of the active region; The lifetime control region includes a second end region formed across the second end diode region and a portion of the outer periphery region that is continuous with the second end diode region. The RC-IGBT according to claim 1.

5. the lifetime control region includes a central region formed closer to the center of the active region than the first end region in the first direction, The second end region is continuous with both the first end region and the central region. The RC-IGBT according to claim 4.

6. A direction perpendicular to the first direction when viewed from the thickness direction is defined as a second direction, The first end diode region extends along the second direction. The RC-IGBT according to claim 1.

7. The length of the boundary region in the first direction is shorter than both the length of the IGBT region in the first direction and the length of the diode region in the first direction. The RC-IGBT according to claim 1.

8. a gate electrode provided on the semiconductor substrate; a gate finger electrically connected to the gate electrode; Equipped with When viewed from the thickness direction, the gate finger is disposed at a position overlapping the IGBT region adjacent to the first end diode region with the boundary region interposed therebetween. The RC-IGBT according to claim 1.

9. The lifetime control region is a region in which crystal defects are formed inside the semiconductor substrate. The RC-IGBT according to any one of claims 1 to 8.

10. the semiconductor substrate includes a semiconductor layer of a first conductivity type having a first main surface and a second main surface opposite to the first main surface; the IGBT region includes an IGBT structure including a base region of a second conductivity type formed in the first main surface, an emitter region of a first conductivity type formed in the base region, and a gate electrode facing the base region and the emitter region via a gate insulating layer, and a collector region of the second conductivity type formed in the second main surface; the diode region includes an anode region of a second conductivity type formed in the first main surface and a cathode region of a first conductivity type formed in the second main surface; the boundary region includes a boundary well region formed in a region that overlaps with the collector region but does not overlap with the cathode region when viewed in the thickness direction, the semiconductor layer includes a first region corresponding to the IGBT region, a second region corresponding to the diode region, a third region corresponding to the boundary region, and a fourth region corresponding to the outer periphery region; The crystal defects are present in the second region, the third region, and the fourth region. The RC-IGBT according to claim 9.

11. preparing a wafer having a first wafer main surface and a second wafer main surface opposite to the first wafer main surface, the wafer being partitioned into an active area and a peripheral area surrounding the active area; forming, in the active region, an IGBT region and a plurality of diode regions aligned in a first direction, and a boundary region formed between the IGBT region and a diode region that is one of the plurality of diode regions adjacent to each other in the first direction; providing a lifetime control region in the wafer that overlaps with the outer periphery region, the plurality of diode regions, and the boundary region when viewed in a thickness direction of the wafer; Equipped with the plurality of diode regions include first end diode regions, the first end diode regions being formed on both ends of the active region in the first direction when viewed from the thickness direction and being continuous with the peripheral region; In the step of providing the lifetime control region in the wafer, the lifetime control region is formed so as to extend across the first end diode region and a portion of the outer peripheral region that is continuous with the first end diode region. RC-IGBT manufacturing method.

12. The step of providing the lifetime control region in the wafer includes: forming a metal mask on the second wafer main surface that covers the IGBT region and exposes the plurality of diode regions, the boundary region, and the outer periphery region; irradiating the semiconductor layer of the wafer from the second wafer main surface side with helium; Contains The method for manufacturing the RC-IGBT according to claim 11.

13. further comprising the step of forming a collector electrode on the second wafer main surface, The step of forming the collector electrode on the second wafer main surface is performed after the step of providing the lifetime control region in the wafer. The method for manufacturing an RC-IGBT according to claim 11 or 12.