Semiconductor device

Abstract

This semiconductor device comprises a transistor including: a first gate electrode; a first gate insulating film that is provided above the first gate electrode; an oxide semiconductor layer that is provided above the first gate insulating film, overlaps the first gate electrode, and has a polycrystalline structure; a second gate insulating film that is provided above the oxide semiconductor layer; and a second gate electrode that is provided above the second gate insulating film and overlaps the first gate electrode. When viewed in a plan view, the first gate electrode has a first region that overlaps the oxide semiconductor layer and projects from the second gate electrode in a first direction, and a second region that overlaps the second gate electrode and projects from the oxide semiconductor layer in a second direction intersecting the first direction.

Description

Semiconductor Devices

[0001] An embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In recent years, development of semiconductor devices using oxide semiconductors for the channels has been progressing, instead of amorphous silicon, low-temperature polysilicon, and single-crystal silicon (see, for example, Patent Document 1). The field-effect mobility of conventional thin-film transistors including oxide semiconductor layers is not very high, even when using crystalline oxide semiconductor layers. Therefore, transistors that require high-speed operation are used with crystalline silicon for the channels, and semiconductor devices that use oxide semiconductors for transistors that require low off-current are being researched (see, for example, Patent Documents 2 and 3).

[0003] JP 2021-141338 A JP 2013-008946 A JP 2011-142621 A

[0004] In a top-gate transistor, source and drain regions are formed in an oxide semiconductor layer by ion implantation using the top gate as a mask. Depending on the channel length and back gate width of the transistor, a reliability test may apply a strong electric field not only to the channel region of the transistor but also to the junction between the channel region and the source region and the junction between the channel region and the drain region, which may cause the transistor characteristics to deteriorate. For example, the threshold voltage of the transistor may shift in the negative direction.

[0005] An object of one embodiment of the present invention is to suppress fluctuations in the threshold voltage of a transistor in a semiconductor device and improve reliability.

[0006] A semiconductor device according to one embodiment of the present invention has a transistor including: a first gate electrode; a first gate insulating film provided on the first gate electrode; an oxide semiconductor layer provided on the first gate insulating film, overlapping with the first gate electrode, and having a polycrystalline structure; a second gate insulating film provided on the oxide semiconductor layer; and a second gate electrode provided on the second gate insulating film, overlapping with the first gate electrode. In plan view, the first gate electrode has a first region overlapping with the oxide semiconductor layer and protruding from the second gate electrode in a first direction, and a second region overlapping with the second gate electrode and protruding from the oxide semiconductor layer in a second direction intersecting the first direction.

[0007] 1 is a plan view showing an overview of a semiconductor device according to an embodiment of the present invention; 2 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention; 3 is a sequence diagram showing a manufacturing method of a semiconductor device according to an embodiment of the present invention; 4 is a cross-sectional view showing a manufacturing method of a semiconductor device according to an embodiment of the present invention; 5 is a cross-sectional view showing a manufacturing method of a semiconductor device according to an embodiment of the present invention; 6 is a cross-sectional view showing a manufacturing method of a semiconductor device according to an embodiment of the present invention; 7 is a cross-sectional view showing a manufacturing method of a semiconductor device according to an embodiment of the present invention; 8 is a cross-sectional view showing a manufacturing method of a semiconductor device according to an embodiment of the present invention; 9 is a cross-sectional view showing a manufacturing method of a semiconductor device according to an embodiment of the present invention; 10 is a cross-sectional view showing a manufacturing method of a semiconductor device according to an embodiment of the present invention; 11 is a cross-sectional view showing a manufacturing method of a semiconductor device according to an embodiment of the present invention; 12 is a plan view showing an overview of a semiconductor device according to an embodiment of the present invention; 13 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention; 14 is a sequence diagram showing a manufacturing method of a semiconductor device according to an embodiment of the present invention; 15 is a cross-sectional view showing a manufacturing method of a semiconductor device according to an embodiment of the present invention; 16 is a cross-sectional view showing a manufacturing method of a semiconductor device according to an embodiment of the present invention; 17 is a cross-sectional view showing a manufacturing method of a semiconductor device according to an embodiment of the present invention; 18 is a cross-sectional view showing a manufacturing method of a semiconductor device according to an embodiment of the present invention; 19 is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention; 20 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention; 21 is a cross-sectional view showing an overview of a display device

[0008] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art can easily arrive at by appropriately modifying the configuration of the embodiments while maintaining the gist of the invention are naturally included within the scope of the present invention. For clarity of explanation, the drawings may show the width, film thickness, shape, etc. of each part more schematically than the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements similar to those described above with reference to the previous drawings are given the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0009] The term "semiconductor device" refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one form of a semiconductor device. The semiconductor device of the following embodiments may be, for example, a display device, an integrated circuit (IC) such as a microprocessor (Micro-Processing Unit: MPU), or a transistor used in a memory circuit.

[0010] The term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical components (e.g., a polarizing component, a backlight, a touch panel, etc.) are attached to a display cell. The term "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. Therefore, the embodiments described below will be described using a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer as examples of display devices, but the structure of this embodiment can be applied to display devices including the other electro-optical layers described above.

[0011] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downper." For convenience of explanation, the terms "up" and "downper" are used in the description. However, for example, the hierarchical relationship between the substrate and the oxide semiconductor layer may be reversed from that illustrated. In the following description, for example, the expression "oxide semiconductor layer on a substrate" merely describes the hierarchical relationship between the substrate and the oxide semiconductor layer as described above, and other components may be disposed between the substrate and the oxide semiconductor layer. "Above" or "below" refers to the stacking order in a structure in which multiple layers are stacked. When a pixel electrode is referred to as being above a transistor, the transistor and the pixel electrode may not overlap in a planar view. On the other hand, when a pixel electrode is referred to as being vertically above a transistor, the transistor and the pixel electrode may overlap in a planar view. Note that a "planar view" refers to a view perpendicular to the surface of the substrate.

[0012] In this specification and the like, the terms "film" and "layer" can be interchangeable in some cases. In addition, in this specification and the like, a plurality of oxide semiconductor layers formed from an oxide semiconductor film may be referred to as "-1", "-2", and the like. In addition, a plurality of conductive layers and electrodes formed from a conductive film may be referred to in the same manner.

[0013] In this specification and the like, ordinal numbers are used to distinguish between parts, members, portions, positions, directions, etc., and do not indicate order or priority.

[0014] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0015] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0016] First Embodiment A semiconductor device 100 according to one embodiment of the present invention will be described with reference to FIGS.

[0017] [Configuration of Semiconductor Device 100] Fig. 1 is a plan view showing an outline of a semiconductor device 100 according to an embodiment of the present invention. Fig. 2 is a cross-sectional view showing an outline of the semiconductor device 100 according to an embodiment of the present invention.

[0018] 1 and 2, the semiconductor device 100 includes a transistor 210 provided on a substrate 10. The transistor 210 includes a first gate electrode 12GE, first insulating films 14 and 16, an oxide semiconductor layer 22, a second insulating film 24, and a second gate electrode 26GE. The oxide semiconductor layer 22 includes a channel region 22CH, a source region 22S, and a drain region 22D.

[0019] The first insulating films 14 and 16 function as a first gate insulating film of the transistor 210. The second insulating film 24 functions as a second gate insulating film of the transistor 210. The third insulating films 28 and 32 function as an interlayer insulating film of the transistor 210.

[0020] The transistor 210 further includes a source electrode 44S and a drain electrode 44D. The source electrode 44S and the drain electrode 44D are provided on the third insulating film 32. The source electrode 44S and the drain electrode 44D are connected to the oxide semiconductor layer 22 via contact holes 31-1 and 31-2 provided in the second insulating film 24, the third insulating film 28, and the third insulating film 32.

[0021] The oxide semiconductor layer 22 has a polycrystalline structure including a plurality of crystal grains. Although the details will be described later, the oxide semiconductor layer 22 having a polycrystalline structure can be formed by using a polycrystalline oxide semiconductor (Poly-OS) technique. The structure of the oxide semiconductor layer 22 will be described below, and an oxide semiconductor having a polycrystalline structure may be referred to as Poly-OS.

[0022] The oxide semiconductor layer 22 contains two or more metal elements including indium, and the proportion of indium in the two or more metal elements is 50% or more. Examples of metal elements other than indium include gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), and lanthanoid elements. However, the oxide semiconductor layer 22 may contain a metal element other than the above as long as it contains Poly-OS.

[0023] The crystal grain size of the crystal grains contained in the Poly-OS observed from the top surface of the oxide semiconductor layer 22 (or in the film thickness direction of the oxide semiconductor layer 22) or from a cross section of the oxide semiconductor layer 22 is 0.1 μm or more, preferably 0.3 μm or more, and further preferably 0.5 μm or more. The crystal grain size of the crystal grains can be obtained by, for example, cross-sectional SEM observation, cross-sectional TEM observation, electron backscattered diffraction (EBSD) analysis, or the like.

[0024] The thickness of the oxide semiconductor layer 22 is greater than 10 nm and less than or equal to 50 nm, preferably greater than 10 nm and less than or equal to 30 nm. As described above, since the crystal grain size of the crystal grains contained in the Poly-OS is 0.1 μm or greater, the oxide semiconductor layer 22 includes a region including only one crystal grain in the thickness direction.

[0025] In Poly-OS, a plurality of crystal grains may have one type of crystal structure or a plurality of types of crystal structures. The crystal structure of Poly-OS can be identified by electron beam diffraction, XRD, or the like. That is, the crystal structure of the oxide semiconductor layer 22 can be identified by electron beam diffraction, XRD, or the like.

[0026] The crystal structure of the oxide semiconductor layer 22 is preferably a cubic crystal. A cubic crystal has a highly symmetric crystal structure, and is less likely to undergo structural relaxation and has a stable crystal structure even when oxygen defects are generated in the oxide semiconductor layer 22. As described above, by increasing the proportion of indium, the crystal structure of each of the multiple crystal grains can be controlled, and the oxide semiconductor layer 22 having a cubic crystal structure can be formed.

[0027] The oxide semiconductor layer 22 includes a first crystalline region that overlaps with the second gate electrode 26GE and has a first crystalline structure, and a second crystalline region that does not overlap with the second gate electrode 26GE and has a second crystalline structure. Here, the first crystalline region corresponds to the channel region 22CH. The second crystalline region corresponds to the source region 22S and the drain region 22D. The electrical conductivity of the second crystalline region is greater than the electrical conductivity of the first crystalline region.

[0028] The second crystal structure is identical to the first crystal structure. Here, the two crystal structures being identical means that they have the same crystal system. For example, when the crystal structure of the oxide semiconductor layer 22 is a cubic crystal, the first crystal structure of the first crystal region and the second crystal structure of the second crystal region are both cubic crystals and are identical. The first crystal structure and the second crystal structure can be identified using, for example, a microelectron beam diffraction method.

[0029] In addition, in a predetermined crystal orientation, the d-spacing value of the first crystal structure and the d-spacing value of the second crystal structure are substantially the same. Here, "substantially the same" refers to one d-spacing value being 0.95 to 1.05 times the other d-spacing value. Alternatively, this refers to the two diffraction patterns being nearly identical in a microelectron beam diffraction method.

[0030] There may be no crystal grain boundary between the first and second crystal regions. Furthermore, the first and second crystal regions may be contained within a single crystal grain. In other words, the change from the first crystal region to the second crystal region may be a continuous change in crystal structure.

[0031] The source region 22S and the drain region 22D contain the same impurity element. The source region 22S and the drain region 22D have a lower resistivity than the channel region 22CH due to the addition of the impurity element. In other words, the source region 22S and the drain region 22D have physical properties as a conductor.

[0032] The concentration of impurity elements contained in the source region 22S and the drain region 22D is 1×10 when measured by SIMS (secondary ion mass spectrometry). １８ cm －３ 1x10 or more ２１ cm －３ It is preferable that the impurity element is argon (Ar), phosphorus (P), or boron (B).

[0033] By adding impurity elements to the source region 22S and the drain region 22D, oxygen defects are formed. Hydrogen is trapped in the oxygen defects, so that the resistance of the source region 22S and the drain region 22D can be reduced to be lower than the resistance of the channel region 22CH. Note that even if the source region 22S and the drain region 22D are doped with impurity elements and oxygen defects are formed, the crystal structure is maintained without being destroyed. Therefore, it can be said that the crystal structure of the source region 22S and the drain region 22D is the same as the crystal structure of the channel region 22CH.

[0034] If many oxygen defects are present inside the channel region of an oxide semiconductor layer, hydrogen is trapped in the oxygen defects, which adversely affects the characteristics of a transistor. Therefore, it is necessary to reduce the number of oxygen defects in the oxide semiconductor layer.

[0035] Oxygen defects are less likely to form in crystalline oxide semiconductors than in amorphous oxide semiconductors. It is also known that a crystalline oxide semiconductor can be easily obtained by relatively increasing the indium content of the oxide semiconductor. However, even if a crystalline oxide semiconductor is obtained by relatively increasing the indium content, more oxygen defects than necessary still remain. The oxygen defects can be repaired by supplying oxygen. Therefore, it is necessary to repair the oxygen defects in the oxide semiconductor layer by providing an insulating film capable of releasing oxygen as an insulating film around the oxide semiconductor layer.

[0036] On the other hand, if more oxygen than necessary is supplied to the oxide semiconductor layer, the excess oxygen contained in the oxide semiconductor layer forms defect levels different from oxygen defects, which may cause phenomena such as fluctuations in characteristics due to reliability tests, a decrease in field-effect mobility, or variations in characteristics.

[0037] In this embodiment, the oxide semiconductor layer 22 contains Poly-OS. The oxide semiconductor layer 22 containing Poly-OS has high crystallinity and is a layer in which oxygen defects are sufficiently reduced.

[0038] In this embodiment, the transistor 210 is formed by ion implantation using the second gate electrode 26GE as a mask, thereby forming a source region 22S and a drain region 22D in the oxide semiconductor layer 22. Depending on the channel length of the transistor and the width of the first gate electrode 12GE, a reliability test may apply a strong electric field not only to the channel region of the transistor but also to the junction between the channel region and the source region and the junction between the channel region and the drain region, which may easily degrade the transistor's characteristics. For example, the threshold voltage of the transistor may shift in the negative direction.

[0039] Here, the reliability test refers to, for example, an NBTIS (Negative Bias Temperature Illumination Stress) test. BT stress tests such as NBTIS are a type of accelerated test that can quickly evaluate changes in transistor characteristics (aging) that occur over a long period of use. In particular, the amount of change in the threshold voltage of a transistor before and after the BT stress test is an important index for examining reliability. The smaller the amount of change in threshold voltage before and after the BT stress test, the more reliable the transistor is.

[0040] An object of one embodiment of the present invention is to suppress fluctuations in the threshold voltage of a transistor in a semiconductor device and improve reliability.

[0041] In the transistor 210, when viewed in a plane, the first gate electrode 12GE that functions as a back gate overlaps with the oxide semiconductor layer 22 and has a first region that protrudes in a first direction D1 from the second gate electrode 26GE that functions as a top gate, and a second region that overlaps with the second gate electrode 26GE and protrudes from the oxide semiconductor layer 22 in a second direction D2 that intersects with the first direction D1.

[0042] As a result, the channel region 22CH in the oxide semiconductor layer 22, the junction between the channel region 22CH and the source region 22S, and the junction between the channel region 22CH and the drain region 22D are covered by the first gate electrode 12GE. This makes it possible to suppress deterioration of the junction between the channel region 22CH and the source region 22S, and the junction between the channel region 22CH and the drain region 22D of the transistor 210 due to an electric field applied to the first gate electrode 12GE during the NBTIS test. This makes it possible to suppress a negative shift in the threshold voltage of the transistor 210. This suppresses fluctuations in the threshold voltage of the transistor 210, resulting in a semiconductor device 100 with improved reliability.

[0043] Here, the width of the second gate electrode 26GE (the length in the first direction D1) is referred to as the channel length L1. The length by which the first gate electrode 12GE protrudes from an end of the second gate electrode 26GE in the first direction D1 is referred to as the length L2. The length by which the first gate electrode 12GE protrudes from the oxide semiconductor layer 22 in the second direction D2 is referred to as the length L3. The length from the end of the second gate electrode 26GE to the source electrode 44S (or the center of the contact hole) is referred to as the length L4. As shown in FIG. 1 , in the oxide semiconductor layer 22, the length L4 (also referred to as the first length) from the end of the second gate electrode 26GE in the first direction D1 to the source electrode 44S may be equal to or greater than the length L2 (also referred to as the second length). That is, the first region overlaps with at least a portion of the second crystalline region. In the transistor 210, the first gate electrode 12GE does not need to cover the entire oxide semiconductor layer 22. This allows the area where the first gate electrode 12GE made of metal or the like is arranged to be reduced, and when the transistor 210 is applied to a display device or the like, the area that is shielded from light by the transistor 210 can be reduced, which means that the aperture ratio of the pixels included in the display device can be improved.

[0044] 1 , the first direction D1 is the same direction as the channel length L1 of the transistor, and the second direction D2 is the channel width direction of the transistor. The length L2 may be equal to or greater than the channel length L1. The length L3 (also referred to as the third length) may be smaller than the channel length L1. For example, when the channel length L1 is 3 μm, the length L2 may be equal to or greater than 3 μm, and the length L3 may be 2 μm. By arranging the first gate electrode 12GE in this manner, it is possible to reduce the area occupied by the transistor (particularly, the light-shielding region of the transistor) and reduce the design load by improving layout efficiency, while suppressing the amount of fluctuation in the threshold voltage of the transistor.

[0045] Furthermore, since the oxide semiconductor layer 22 has a crystalline structure not only in the channel region 22CH but also in the source region 22S and the drain region 22D, the resistance of the source region 22S and the drain region 22D can be sufficiently reduced. This reduces the parasitic resistance of the source region 22S and the drain region 22D, and suppresses variations in the on-state current in the electrical characteristics of the transistor 210. Because the transistor 210 has high mobility, when the semiconductor device 100 is used in a display device or the like, variations are suppressed and performance is improved.

[0046] In the semiconductor device 100 according to one embodiment of the present invention, when the channel length L1 of the channel region CH of the transistor 210 is in the range of 2 μm to 4 μm and the channel width W of the channel region CH is in the range of 2 μm to 25 μm, the mobility is 30 cm ２ / Vs or more, 35cm ２ / Vs or more, or 40 cm ２ In this specification and the like, the mobility refers to the field-effect mobility in the saturation region of a transistor, and refers to the maximum value of the field-effect mobility in a region where the potential difference (Vd) between the source electrode and the drain electrode is larger than the value (Vg - Vth) obtained by subtracting the threshold voltage (Vth) of the transistor from the voltage (Vg) supplied to the gate electrode.

[0047] In this embodiment, a configuration is illustrated in which the transistor 210 is a dual-gate transistor that is driven by the first gate electrode 12GE and the second gate electrode 26GE, but the present invention is not limited to this configuration. A top-gate transistor that is driven by the second gate electrode 26GE may also be used as the transistor 210. For example, a bottom-gate transistor that is driven by the first gate electrode 12GE may also be used as the transistor 210. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0048] The first gate electrode 12GE functions as a light-shielding film for the bottom gate of the transistor 210 and the oxide semiconductor layer 22. The first insulating films 14, 16 and the second insulating film 24 function to release oxygen by heat treatment in the manufacturing process. The second insulating film 24, the third insulating films 28, 32 insulate the first gate electrode 12GE from the source electrode 44S and the drain electrode 44D, and reduce parasitic capacitance therebetween. The operation of the transistor 210 is controlled primarily by the voltage supplied to the second gate electrode 26GE. An auxiliary voltage is supplied to the first gate electrode 12GE. Alternatively, the first gate electrode 12GE may simply function as a light-shielding film. In this case, the first gate electrode 12GE may be floating without being supplied with a specific voltage.

[0049] [Method of Manufacturing Semiconductor Device 100] A method of manufacturing the semiconductor device 100 according to one embodiment of the present invention will be described with reference to Figures 3 to 10. Figure 3 is a sequence diagram showing a method of manufacturing the semiconductor device 100 according to one embodiment of the present invention.

[0050] As shown in FIGS. 3 and 4, a first gate electrode 12GE is formed on the substrate 10 ("1st GE formation" in step S1001 shown in FIG. 3).

[0051] The substrate 10 may be a rigid substrate having optical transparency, such as a glass substrate, a quartz substrate, or a sapphire substrate. When the substrate 10 needs to be flexible, a substrate containing a resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, may be used. When a substrate containing a resin is used as the substrate 10, an impurity element may be introduced into the resin to improve the heat resistance of the substrate 10. In particular, when the semiconductor device 100 is a top-emission display, the substrate 10 does not need to be transparent, and therefore an impurity that reduces the transparency of the substrate 10 may be used. When the semiconductor device 100 is used in an integrated circuit other than a display device, a non-optically transparent substrate may be used as the substrate 10, such as a semiconductor substrate, such as a silicon substrate, a silicon carbide substrate, or a compound semiconductor substrate, or a conductive substrate, such as a stainless steel substrate.

[0052] The first gate electrode 12GE is formed by processing a conductive film formed by sputtering. A typical metal material is used for the first gate electrode 12GE. Examples of materials that can be used for the first gate electrode 12GE include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof. The above materials may be used as a single layer or a stacked layer for the first gate electrode 12GE.

[0053] 3 and 4, first insulating films 14 and 16 are formed on the substrate 10 and the first gate electrode 12GE ("1st IF film formation" in step S1002 shown in FIG. 3). The first insulating films 14 and 16 are formed by a chemical vapor deposition (CVD) method or a sputtering method. A general insulating material is used for the first insulating films 14 and 16. For example, silicon oxide (SiO ｘ ), silicon oxynitride (SiO ｘ N ｙ ), silicon nitride (SiN ｘ ), silicon oxynitride (SiN ｘ O ｙ ) and other inorganic insulating materials are used. ｘ N ｙ is a silicon compound containing a smaller ratio (x>y) of nitrogen (N) than oxygen (O). ｘ O ｙ is a silicon compound containing a smaller ratio of oxygen than nitrogen (x>y). In this embodiment, the first insulating films 14 and 16 are formed by stacking a silicon nitride film and a silicon oxide film on the silicon nitride film. The combined thickness of the first insulating films 14 and 16 is, for example, 100 nm to 600 nm, preferably 150 nm to 300 nm.

[0054] The first insulating films 14 and 16 are preferably formed in this order from the substrate 10, with a nitrogen-containing insulating material and an oxygen-containing insulating material. For example, using a nitrogen-containing insulating material as the first insulating film 14 can block impurities diffusing from the substrate 10 toward the oxide semiconductor layer 22. Furthermore, using an oxygen-containing insulating material as the first insulating film 16 can release oxygen by heat treatment. The heat treatment temperature at which the oxygen-containing insulating material releases oxygen is, for example, 500°C or less, 450°C or less, or 400°C or less. That is, the oxygen-containing insulating material releases oxygen at the heat treatment temperature, for example, used in the manufacturing process of the semiconductor device 100 when a glass substrate is used as the substrate 10. In this embodiment, an example is described in which the first insulating films 14 and 16 have a stacked structure of silicon nitride and silicon oxide. However, a single-layer structure of the above-mentioned material may also be used as the first insulating film.

[0055] 3 and 4 , an oxide semiconductor film 17 is formed on the first insulating film 16 (step S1003 “first OS deposition” shown in FIG. 3 ). This step may also be referred to as forming the oxide semiconductor film 17 on the substrate 10. The oxide semiconductor film 17 is formed by sputtering or atomic layer deposition (ALD). The thickness of the oxide semiconductor film 17 is, for example, greater than 10 nm and less than or equal to 30 nm.

[0056] The oxide semiconductor film 17 may be made of a metal oxide having semiconductor properties. The oxide semiconductor film 17 is made of an oxide semiconductor containing two or more metal elements including indium. The ratio of indium to the two or more metal elements is 50% or more. The oxide semiconductor film 17 may be made of a metal element other than indium, such as gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), or a lanthanoid element.

[0057] When the oxide semiconductor film 17 is crystallized by OS annealing, which will be described later, the oxide semiconductor film 17 is preferably amorphous (a state in which the crystalline component of the oxide semiconductor is low) after deposition and before OS annealing. That is, the oxide semiconductor film 17 is preferably formed under conditions that prevent the oxide semiconductor film 17 from crystallizing immediately after deposition as much as possible. For example, when the oxide semiconductor film 17 is formed by a sputtering method, the oxide semiconductor film 17 is formed while controlling the temperature of the object to be formed (the substrate 10 and a structure formed thereon).

[0058] When a film is formed on a target by sputtering, ions generated in the plasma and atoms recoiled from the sputtering target collide with the target, causing the temperature of the target to rise during the film formation process. If the temperature of the target increases during the film formation process, the oxide semiconductor film 17 contains microcrystals immediately after film formation. If the oxide semiconductor film 17 contains microcrystals, the crystal grain size cannot be increased by subsequent OS annealing. To control the temperature of the target as described above, for example, the target can be cooled during film formation. For example, the target can be cooled from the side opposite the target surface so that the temperature of the target surface (hereinafter referred to as the "film formation temperature") is 100°C or less, 70°C or less, 50°C or less, or 30°C or less. In particular, the film formation temperature of the oxide semiconductor film 17 in this embodiment is preferably 50°C or less. By forming the oxide semiconductor film 17 while cooling the substrate, it is possible to obtain the oxide semiconductor film 17 having few crystalline components immediately after the film formation. In this embodiment, the oxide semiconductor film 17 is formed at a film formation temperature of 50° C. or less, and the OS annealing described later is performed at a heating temperature of 400° C. or more. As described above, in this embodiment, the difference between the temperature at which the oxide semiconductor film 17 is formed and the temperature at which the oxide semiconductor film 17 is subjected to the OS annealing is preferably 350° C. or more.

[0059] In the sputtering process, the amorphous oxide semiconductor film 17 is formed under conditions of an oxygen partial pressure of 10% or less. If the oxygen partial pressure is high, the oxide semiconductor film 17 contains excess oxygen, which causes microcrystals to be included in the oxide semiconductor film 17 immediately after film formation. Therefore, it is preferable to form the oxide semiconductor film 17 under conditions of a low oxygen partial pressure. The oxygen partial pressure is, for example, from 3% to 5%, and preferably from 3% to 4%. Note that if the oxide semiconductor film 17 is formed under conditions of an oxygen partial pressure of 2%, the oxide semiconductor film may not be crystallized even if OS annealing is subsequently performed.

[0060] As shown in FIGS. 3 and 5 , a pattern of the oxide semiconductor layer 18 is formed ("OS pattern formation" in step S1004 shown in FIG. 3 ). A resist mask 19 is formed on the oxide semiconductor film 17, and the oxide semiconductor film 17 is etched using the resist mask 19. Wet etching or dry etching may be used to etch the oxide semiconductor film 17. Wet etching can be performed using an acidic etchant. Examples of the etchant that can be used include oxalic acid, PAN, sulfuric acid, hydrogen peroxide solution, and hydrofluoric acid. This allows the formation of a patterned oxide semiconductor layer 18. Then, the resist mask 19 is removed.

[0061] The oxide semiconductor film 17 is preferably patterned before OS annealing. If the oxide semiconductor film 17 is crystallized by OS annealing, it tends to be difficult to etch. In addition, even if the patterned oxide semiconductor layer 18 is damaged by etching, the damage to the oxide semiconductor layer 18 can be repaired by OS annealing, which is preferable.

[0062] 3 and 6 , after the oxide semiconductor layer 18 is patterned, heat treatment (OS annealing) is performed on the oxide semiconductor layer 18 (step S1005 “OS annealing” shown in FIG. 3 ). In the OS annealing, the oxide semiconductor layer 18 is held at a predetermined temperature for a predetermined time. The predetermined temperature is 300° C. or higher and 500° C. or lower, preferably 350° C. or higher and 450° C. or lower. The holding time at the temperature is 15 minutes or higher and 120 minutes or lower, preferably 30 minutes or higher and 60 minutes or lower. By performing the OS annealing, the oxide semiconductor layer 18 is crystallized, and an oxide semiconductor layer 22 having a polycrystalline structure is formed.

[0063] In a thin film transistor, reducing the thickness of the oxide semiconductor layer increases carriers near the interface with the gate insulating film, and the field-effect mobility tends to be higher. That is, in a thin film transistor, the field-effect mobility tends to be higher as the thickness of the region functioning as a channel of the oxide semiconductor layer is reduced. Therefore, the smaller the thickness of the oxide semiconductor layer, the better. However, even if the oxide semiconductor layer is formed to a thickness of 10 nm or less and then subjected to heat treatment, the oxide semiconductor layer may not be sufficiently crystallized.

[0064] Furthermore, in a thin-film transistor, the crystallinity of the oxide semiconductor layer 22 contributes to improving the field-effect mobility. Therefore, it is preferable that the oxide semiconductor layer 22 has a polycrystalline structure. However, if microcrystals are contained in the oxide semiconductor film 17 during its formation, the crystal grain size of the polycrystalline structure cannot be increased even if a heat treatment is subsequently performed. Thus, it is difficult to achieve both a thin oxide semiconductor layer and good crystallization.

[0065] Therefore, when the oxide semiconductor film 17 is formed by a sputtering method, it is formed at a low oxygen partial pressure of 3% or more and 5% or less. By forming the oxide semiconductor film 17 under the condition of a low oxygen partial pressure, it is possible to prevent the oxide semiconductor film 17 from containing excessive oxygen and to prevent the oxide semiconductor film 17 from containing microcrystals immediately after deposition. This makes it possible to prevent crystals from growing from the microcrystals during heat treatment of the oxide semiconductor layer 18. Therefore, even when the oxide semiconductor film 17 is formed to a thin thickness of more than 10 nm and less than or equal to 30 nm, the crystal grain size of the crystal grains in the polycrystalline structure of the oxide semiconductor layer 22 can be increased.

[0066] 3 and 7 , a second insulating film 24 is formed on the oxide semiconductor layer 22 ("2nd IF formation" in step S1006 shown in FIG. 3 ). For the method and insulating material for forming the second insulating film 24, refer to the description of the first insulating films 14 and 16. The thickness of the second insulating film 24 is, for example, 50 nm to 300 nm, 60 nm to 200 nm, or 70 nm to 150 nm.

[0067] It is preferable to use an insulating material containing oxygen as the second insulating film 24. It is also preferable to use an insulating film with few defects as the second insulating film 24. For example, when the oxygen composition ratio in the second insulating film 24 is compared with the oxygen composition ratio in an insulating film having the same composition as the second insulating film 24 (hereinafter referred to as "another insulating film"), the oxygen composition ratio in the second insulating film 24 is closer to the stoichiometric ratio for the insulating film than the oxygen composition ratio in the other insulating film. For example, when the second insulating film 24 and the third insulating film 32 are each made of silicon oxide (SiO ｘ ) is used, the oxygen composition ratio in the silicon oxide used as the second insulating film 24 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio in the silicon oxide used as the third insulating film 32. For example, the second insulating film 24 may be a film in which no defects are observed when evaluated by electron spin resonance (ESR).

[0068] In order to form an insulating film with few defects as the second insulating film 24, the second insulating film 24 may be formed at a film formation temperature of 350° C. or higher. After the second insulating film 24 is formed, a process of implanting oxygen into a part of the second insulating film 24 may be performed. In this embodiment, in order to form an insulating film with few defects as the second insulating film 24, silicon oxide is formed at a film formation temperature of 350° C. or higher.

[0069] 3 and 7, a metal oxide film 25 is formed on the second insulating film 24 ("MO film formation" in step S1007 shown in FIG. 3). The metal oxide film 25 is formed by sputtering. By forming the metal oxide film 25 by the sputtering method, oxygen is implanted into the second insulating film 24.

[0070] The metal oxide film 25 is made of a metal oxide containing aluminum as a main component. For example, the metal oxide film 25 is made of aluminum oxide (AlO ｘ ), aluminum oxynitride (AlO ｘ N ｙ ), aluminum oxide nitride (AlNxOy), aluminum nitride (AlN ｘ An inorganic insulating layer such as aluminum is used. A metal oxide film containing aluminum as a main component means that the ratio of aluminum contained in the metal oxide film is 1% or more of the entire metal oxide film 25. The ratio of aluminum contained in the metal oxide film 25 may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide film 25. The above ratio may be a mass ratio or a weight ratio.

[0071] The thickness of the metal oxide film 25 is, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm. In this embodiment, aluminum oxide is used as the metal oxide film 25. Aluminum oxide has high barrier properties against gases such as oxygen and hydrogen. In this embodiment, the aluminum oxide used as the metal oxide film 25 suppresses outward diffusion of oxygen implanted into the second insulating film 24 during the formation of the metal oxide film 25. In other words, the barrier properties refer to the function of suppressing the permeation of gases such as oxygen and hydrogen through the aluminum oxide. In other words, this means that even if a gas such as oxygen exists from a layer provided below the aluminum oxide film, it is prevented from migrating to a layer provided above the aluminum oxide film. Alternatively, this means that even if a gas such as oxygen exists from a layer provided above the aluminum oxide film, it is prevented from migrating to a layer provided below the aluminum oxide film.

[0072] For example, when the metal oxide film 25 is formed by sputtering, the process gas used in the sputtering remains in the metal oxide film 25. For example, when Ar is used as the process gas for sputtering, Ar may remain in the second insulating film 24. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the second insulating film 24.

[0073] With the second insulating film 24 and the metal oxide film 25 formed on the oxide semiconductor layer 22, a heat treatment (oxidation annealing) is performed to supply oxygen from the second insulating film 24 to the oxide semiconductor layer 22 ("oxidation annealing" in step S1008 shown in FIG. 3). During the process from the formation of the oxide semiconductor film 17 to the formation of the second insulating film 24 on the oxide semiconductor layer 22, many oxygen defects are generated on the top surface and side surfaces of the oxide semiconductor layer 22. Due to the oxidation annealing, oxygen released from the first insulating film 16 and the second insulating film 24 is supplied to the oxide semiconductor layer 22, and the oxygen defects are repaired.

[0074] In the oxidation annealing, the oxygen implanted into the second insulating film 24 is blocked by the metal oxide film 25, and is therefore prevented from being released into the atmosphere. Therefore, the oxidation annealing allows the oxygen to be efficiently supplied to the oxide semiconductor layer 22, and oxygen defects are repaired.

[0075] 3, the metal oxide film 25 is etched (removed) ("MO removal" in step S1009 shown in FIG. 3). Wet etching or dry etching may be used to etch the metal oxide film 25. For example, diluted hydrofluoric acid (DHF) is used for wet etching.

[0076] As shown in FIGS. 3 and 8 , a second gate electrode 26GE is formed on the second insulating film 24 ("2nd GE formation" in step S1010 shown in FIG. 3 ). The second gate electrode 26GE is formed by processing a conductive film formed by sputtering. For materials that can be used for the second gate electrode 26GE, please refer to the description of the material for the first gate electrode 12GE. For the second gate electrode 26GE, the materials listed in the description of the first gate electrode 12GE may be used in a single layer or in a stacked layer. Furthermore, the material for the second gate electrode 26GE may be the same as the material for the first gate electrode 12GE.

[0077] The width of the second gate electrode 26GE (the length in the first direction D1 in FIG. 2 ) corresponds to the channel length L1. In a plan view, the first gate electrode 12GE forms the second gate electrode 26GE so that a first region protruding from the second gate electrode 26GE in the first direction D1 and a second region overlapping the second gate electrode 26GE and protruding from the oxide semiconductor layer 22 in a second direction D2 intersecting the first direction D1 are formed. Furthermore, it is preferable that the length L2 in the first direction D1 in the first region is longer than the length L3 in the second direction D2 in the second region.

[0078] 3 and 9, using the second gate electrode 26GE as a mask, an impurity element is added to the oxide semiconductor layer 22 ("SD region formation" in step S1011 shown in FIG. 3). In this embodiment, a case where the impurity element is added by ion implantation will be described, but it may also be added by ion doping.

[0079] Specifically, the impurity element is doped into the source region 22S and the drain region 22D by ion implantation through the second insulating film 24. In the oxide semiconductor layer 22, the region overlapping with the second gate electrode 26GE is not doped with the impurity element, and functions as the channel region 22CH. For example, argon (Ar), phosphorus (P), or boron (B) may be used as the impurity element. When boron (B) is doped by ion implantation, the acceleration energy is set to 20 keV or more and 40 keV or less, and the implantation amount of boron (B) is set to 1×10 １４ cm －２ 1x10 or more １６ cm －２ The following would suffice.

[0080] By ion implantation, impurity elements are implanted into the source region 22S and the drain region 22D at 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The impurity element can be added at the following concentration. At this time, oxygen defects are formed in the oxide semiconductor in the source region 22S and the drain region 22D by adding the impurity element. Hydrogen is easily trapped in the oxygen defects. This reduces the resistivity of the source region 22S and the drain region 22D, allowing them to function as conductors. Even when the impurity element is added to the oxide semiconductor layer 22 and oxygen defects are formed, the crystal structure is maintained without being broken. Therefore, it can be said that the crystal structure of the source region 22S and the drain region 22D is the same as the crystal structure of the channel region 22CH.

[0081] For example, when an IGZO-based oxide semiconductor layer is used, the resistance of the oxide semiconductor layer is high, and therefore the resistance of the source region and the drain region cannot be sufficiently reduced unless the film thickness is increased. In contrast, in the oxide semiconductor layer 22 having a polycrystalline structure, impurity elements are added to the source region 22S and the drain region 22D, so that the sheet resistance of the source region 22S and the drain region 22D can be reduced to 1000 Ω / sq. or less, preferably 500 Ω / sq. or less, and more preferably 250 Ω / sq. or less.

[0082] 3 and 10 , third insulating films 28 and 32 are formed on the second insulating film 24 and the second gate electrode 26GE ("3rd IF film formation" in step S1012 shown in FIG. 3 ). For the film formation method and insulating material of the third insulating films 28 and 32, refer to the description of the material of the first insulating films 14 and 16. In this embodiment, for example, silicon nitride is formed as the third insulating film 28, and silicon oxide is formed as the third insulating film 32. The third insulating films 28 and 32 function as interlayer insulating films of the transistor 210.

[0083] 3 and 10, contact holes 31-1 and 31-2 are formed in the second insulating film 24 and the third insulating films 28 and 32 (step S1013 "contact opening" shown in FIG. 3). As a result, the source region 22S and the drain region 22D of the oxide semiconductor layer 22 are exposed.

[0084] Finally, as shown in FIG. 3, a source electrode 44S and a drain electrode 44D are formed on the third insulating films 28 and 32 (step S1014 "SD formation" shown in FIG. 3). The source electrode 44S and the drain electrode 44D are formed by processing a conductive film formed by sputtering. This connects the source region 22S and the source electrode 44S, and the drain region 22D and the drain electrode 44D. For materials that can be used for the source electrode 44S and the drain electrode 44D, please refer to the description of the materials for the first gate electrode 12GE.

[0085] Through the above steps, the semiconductor device 100 shown in FIGS. 1 and 2 can be manufactured.

[0086] 11 is a plan view showing a semiconductor device 100A having a structure partially different from that of the semiconductor device 100. As shown in Fig. 11, in a transistor 210A included in the semiconductor device 100A, the shape of a first gate electrode 12GE is different from that of the transistor 210. Note that, in the transistor 210A, a cross-sectional view taken along line A1-A2 is similar to the cross-sectional view shown in Fig. 2, and therefore detailed description thereof will be omitted.

[0087] In a plan view, the first gate electrode 12GE is similar to the transistor 210 in that it has a first region protruding from the second gate electrode 26GE in the first direction D1 and a second region overlapping the second gate electrode 26GE and protruding from the oxide semiconductor layer 22 in the second direction D2. The transistor 210A differs from the transistor 210 in that the length L2 of the first region in the first direction D1 is shorter than the length L3 of the second region in the second direction D2. While the length L2 is preferably equal to or greater than the channel length L1 of the transistor, it is sufficient that the first gate electrode 12GE protrudes from the oxide semiconductor layer 22 in the second direction D2. Even if the length L2 is shorter than the length L3, the threshold voltage of the transistor 210A can be prevented from shifting in the negative direction as long as the first gate electrode 12GE protrudes from the oxide semiconductor layer 22 in the second direction D2. Therefore, fluctuation in the threshold voltage of the transistor 210A can be suppressed, and the reliability of the semiconductor device 100 can be improved.

[0088] Second Embodiment In this embodiment, a semiconductor device 100B having a configuration that is partially different from the semiconductor device 100 described in the first embodiment will be described.

[0089] [Configuration of Semiconductor Device 100B] FIG. 12 is a cross-sectional view showing an outline of a semiconductor device 100B according to one embodiment of the present invention.

[0090] 12, the semiconductor device 100B has a transistor 210B provided on the substrate 10. The configuration of the transistor 210B is generally similar to the configuration of the transistor 210, except that a metal oxide layer 46 is provided between the oxide semiconductor layer 22 and the first insulating film 16. The plan view of the transistor 210B is the same as that of FIG. 2, and therefore is not shown.

[0091] A metal oxide containing aluminum as a main component is used as the metal oxide layer 46. The same material as that of the metal oxide film 25 can be used for the metal oxide layer 46. The thickness of the metal oxide layer 46 is, for example, 1 nm to 100 nm, 1 nm to 50 nm, 1 nm to 30 nm, or 1 nm to 10 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 46. Aluminum oxide has high barrier properties against gases. In this embodiment, the aluminum oxide used as the metal oxide layer 46 blocks hydrogen and oxygen released from the first insulating film 16 and the third insulating film 32, and prevents the released hydrogen and oxygen from reaching the oxide semiconductor layer 22.

[0092] When an excessive amount of oxygen is supplied to the oxide semiconductor layer 22, defect levels different from oxygen defects are formed by the excess oxygen, which may cause phenomena such as fluctuations in characteristics due to reliability tests, a decrease in field-effect mobility, or variations in characteristics.

[0093] By providing the metal oxide layer 46 under the oxide semiconductor layer 22, it is possible to suppress the supply of excess oxygen to the lower surface of the oxide semiconductor layer 22. This makes it possible to suppress the formation of defect states on the lower surface of the oxide semiconductor layer 22. Therefore, it is possible to suppress the characteristic fluctuation, the decrease in field-effect mobility, or the characteristic variation due to the reliability test of the transistor 210B.

[0094] [Manufacturing Method of Semiconductor Device 100B] A manufacturing method of the semiconductor device 100B according to one embodiment of the present invention will be described with reference to Fig. 13. Fig. 13 is a sequence diagram showing a manufacturing method of the semiconductor device 100B according to one embodiment of the present invention. Figs. 14 to 17 are cross-sectional views showing a manufacturing method of the semiconductor device 100B according to one embodiment of the present invention. Furthermore, detailed descriptions of steps similar to those in the first embodiment will be omitted.

[0095] As shown in FIG. 13, steps S1101 and S1102 are similar to steps S1001 and S1002 shown in FIG.

[0096] In this embodiment, as shown in FIGS. 13 and 14 , after the process of step S1102, a metal oxide film 45 containing aluminum as its main component and an oxide semiconductor film 17 are formed on the first insulating film 16 (step S1103 “1st MO, OS film formation” shown in FIG. 13 ).

[0097] The metal oxide film 45 is formed by sputtering or atomic layer deposition. The thickness of the metal oxide film 45 is, for example, 1 nm to 50 nm, 1 nm to 30 nm, 1 nm to 20 nm, or 1 nm to 10 nm. In this embodiment, aluminum oxide is used as the metal oxide film 45. Aluminum oxide has high barrier properties against gases such as oxygen and hydrogen. In this embodiment, the aluminum oxide used as the metal oxide film 45 blocks hydrogen and oxygen released from the first insulating film 16 and prevents the released hydrogen and oxygen from reaching the oxide semiconductor layer 22 to be formed later.

[0098] For the method and material for forming the oxide semiconductor film 17 in this embodiment, the description of the method and material for forming the oxide semiconductor film 17 (Step S1003 “OS film formation” in FIG. 2 ) can be referred to.

[0099] 13 and 15 , a pattern of the oxide semiconductor layer 18 is formed (step S1104 “first OS pattern formation” shown in FIG. 13 ). A resist mask 19 is formed over the oxide semiconductor film 17, and the oxide semiconductor film 17 is etched using the resist mask 19. For the etching method of the oxide semiconductor film 17 in this embodiment, refer to the description of the etching method of the oxide semiconductor film 17 (step S1004 “OS pattern formation” shown in FIG. 2 ).

[0100] 13 and 16 , after the oxide semiconductor layer 18 is patterned, heat treatment (OS annealing) is performed on the oxide semiconductor layer 18 ("OS annealing" in step S1105 shown in FIG. 13 ). For the conditions of the OS annealing, refer to the description of the conditions of the OS annealing on the oxide semiconductor layer 18 ("OS annealing" in step S1005 shown in FIG. 3 ). By performing the OS annealing, the oxide semiconductor layer 18 is crystallized, and an oxide semiconductor layer 22 having a polycrystalline structure is formed.

[0101] As shown in FIGS. 13 and 17 , the metal oxide film 45 is patterned to form a metal oxide layer 46 (step S1106 “MO pattern formation” shown in FIG. 13 ). The oxide semiconductor layer 22 sufficiently crystallized by the heat treatment has etching resistance. Therefore, when the metal oxide film 45 is patterned using the crystallized oxide semiconductor layer 22 as a mask, the oxide semiconductor layer 22 can be prevented from being lost. The metal oxide film 45 is etched using the oxide semiconductor layer 22 patterned in the above process as a mask. The metal oxide film 45 may be etched by wet etching or dry etching. For example, diluted hydrofluoric acid (DHF) is used for wet etching. By etching the metal oxide film 45 using the oxide semiconductor layer 22 as a mask, the photolithography process can be omitted.

[0102] Thereafter, the processes shown in steps S1107 and S1108 in FIG. 13 are the same as the processes shown in steps S1006 and S1007 in FIG. 3, and therefore detailed description thereof will be omitted.

[0103] As shown in FIG. 13 , with the second insulating film 24 and the metal oxide film 25 formed on the oxide semiconductor layer 22, a heat treatment (oxidation annealing) is performed to supply oxygen from the second insulating film 24 to the oxide semiconductor layer 22 ("oxidation annealing" in step S1109 shown in FIG. 13 ).

[0104] In this embodiment, a metal oxide layer 46 is provided below the oxide semiconductor layer 22. When oxidation annealing is performed in this state, oxygen released from the first insulating film 16 is blocked by the metal oxide layer 46, making it difficult for oxygen to be supplied to the lower surface of the oxide semiconductor layer 22. The oxygen released from the first insulating film 16 diffuses from regions where the metal oxide layer 46 is not formed to the second insulating film 24 provided on the first insulating film 16 and reaches the oxide semiconductor layer 22 via the second insulating film 24. As a result, the oxygen released from the first insulating film 16 is difficult to be supplied to the lower surface of the oxide semiconductor layer 22, but is supplied mainly to the side and upper surfaces of the oxide semiconductor layer 22. Furthermore, by oxidation annealing, oxygen released from the second insulating film 24 is supplied to the upper and side surfaces of the oxide semiconductor layer 22. Although hydrogen may be released from the first insulating films 14 and 16 by the oxidation annealing, the hydrogen is blocked by the metal oxide layer 46.

[0105] As described above, the oxidation annealing process can suppress the supply of oxygen to the lower surface of the oxide semiconductor layer 22, which has a small amount of oxygen defects, while supplying oxygen to the upper surface and side surfaces of the oxide semiconductor layer 22, which has a large amount of oxygen defects.

[0106] Thereafter, the processes shown in steps S1110 to S1115 in FIG. 13 are the same as the processes shown in steps S1009 to S1014 in FIG.

[0107] Through the above steps, the semiconductor device 100B shown in FIG. 12 can be manufactured.

[0108] In the semiconductor device 100B manufactured by the above manufacturing method, oxygen defects contained in the oxide semiconductor layer 22 can be further reduced compared to the manufacturing method of the semiconductor device 100 described in the first embodiment. Therefore, in the semiconductor device 100B described in this embodiment, when the channel length L1 of the channel region CH of the transistor 210B is in the range of 2 μm to 4 μm and the channel width W of the channel region CH is in the range of 2 μm to 25 μm, the mobility is 50 cm ２ / Vs or more, 55cm ２ / Vs or more, or 60 cm ２ Electrical characteristics of at least 1000V / Vs can be obtained.

[0109] Furthermore, it is possible to prevent excessive oxygen from being supplied to the underside of the oxide semiconductor layer 22. In particular, by sufficiently reducing oxygen defects contained in the channel region CH, it is possible to prevent hydrogen from being trapped in the oxygen defects. This makes it possible to further reduce the characteristic fluctuations in the reliability test of the transistor 210B, thereby improving the reliability of the semiconductor device 100B.

[0110] 18 to 24, a display device 200 using a semiconductor device 100 according to one embodiment of the present invention will be described. In the embodiment shown below, a configuration in which the semiconductor device 100 described in the first embodiment is applied to the circuitry of a liquid crystal display device will be described.

[0111] [Outline of Display Device 200] Fig. 18 is a plan view showing an outline of a display device 200 according to one embodiment of the present invention. As shown in Fig. 18, the display device 200 has an array substrate 300, a seal portion 310, a counter substrate 320, a flexible printed circuit board (hereinafter also referred to as an FPC 330), and an IC chip 340. The array substrate 300 and the counter substrate 320 are bonded together by the seal portion 310. A plurality of pixel circuits 301 are arranged in a matrix in a liquid crystal region 220 surrounded by the seal portion 310. The liquid crystal region 220 is an area that overlaps with a liquid crystal element 311, which will be described later, in a plan view.

[0112] The sealing region 240 in which the sealing portion 310 is provided is the region surrounding the liquid crystal region 220. The FPC 330 is provided in the terminal region 260. The terminal region 260 is the region in which the array substrate 300 is exposed from the counter substrate 320, and is provided outside the sealing region 240. The outside of the sealing region 240 means the outside of the region in which the sealing portion 310 is provided and the region surrounded by the sealing portion 310. The IC chip 340 is provided on the FPC 330. The IC chip 340 supplies signals for driving each pixel circuit 301.

[0113] [Circuit Configuration of Display Device 200] Fig. 19 is a block diagram showing the circuit configuration of a display device 200 according to one embodiment of the present invention. As shown in Fig. 19, a source driver circuit 302 is provided adjacent to the liquid crystal region 220 in the second direction D2 (column direction) in which the pixel circuits 301 are arranged, and a gate driver circuit 303 is provided adjacent to the liquid crystal region 220 in the first direction D1 (row direction). The source driver circuit 302 and the gate driver circuit 303 are provided in the sealing region 240. However, the region in which the source driver circuit 302 and the gate driver circuit 303 are provided is not limited to the sealing region 240, and may be any region outside the region in which the pixel circuits 301 are provided.

[0114] A source wiring 304 extends from the source driver circuit 302 in the second direction D2 and is connected to the plurality of pixel circuits 301 arranged in the second direction D2. A second gate electrode 26GE extends from the gate driver circuit 303 in the first direction D1 and is connected to the plurality of pixel circuits 301 arranged in the first direction D1.

[0115] A terminal portion 306 is provided in the terminal region 260. The terminal portion 306 and the source driver circuit 302 are connected by a connection wiring 307. Similarly, the terminal portion 306 and the gate driver circuit 303 are connected by a connection wiring 307. When the FPC 330 is connected to the terminal portion 306, an external device to which the FPC 330 is connected is connected to the display device 200, and each pixel circuit 301 provided in the display device 200 is driven by a signal from the external device.

[0116] The transistors 210 , 210 A, and 210 B shown in the first and second embodiments are used as transistors included in the pixel circuit 301 , the source driver circuit 302 , and the gate driver circuit 303 .

[0117] [Pixel Circuit 301 of Display Device 200] Figure 20 is a circuit diagram showing a pixel circuit of a display device 200 according to one embodiment of the present invention. As shown in Figure 20, the pixel circuit 301 includes elements such as a semiconductor device 100, a storage capacitor 350, and a liquid crystal element 311. The semiconductor device 100 has a second gate electrode 26GE, a source electrode 44S, and a drain electrode 44D. The second gate electrode 26GE is connected to the second gate electrode 26GE. The source electrode 44S is connected to a source wiring 304. The drain electrode 44D is connected to the storage capacitor 350 and the liquid crystal element 311. In this embodiment, for convenience of explanation, the electrode indicated by the symbol "44S" is referred to as a source electrode, and the electrode indicated by the symbol "44D" is referred to as a drain electrode. However, the electrode indicated by the symbol "44S" may function as a drain electrode, and the electrode indicated by the symbol "44D" may function as a source electrode.

[0118] [Configuration of Display Device 200] Fig. 20 is a cross-sectional view of a display device 200 according to one embodiment of the present invention. As shown in Fig. 20, the display device 200 is a display device to which the semiconductor device 100 is applied.

[0119] 20 and 22, a first gate electrode 12GE is provided on a substrate 10. An oxide semiconductor layer 22 is provided on the first gate electrode 12GE. A second gate electrode 26GE is provided on the oxide semiconductor layer 22. A source wiring and a drain electrode 44D are provided on the second gate electrode 26GE. The source wiring is connected to a source region 22S via a contact hole 31-1. A region of the source wiring that is connected to the oxide semiconductor layer 22 functions as the source electrode 44S. The drain electrode 44D is connected to the drain region 22D via a contact hole 31-2.

[0120] An insulating film 360 is provided on the source electrode 44S and the drain electrode 44D. A common electrode 370 that is provided in common to a plurality of pixels is provided on the insulating film 360. An insulating film 380 is provided on the common electrode 370. An opening 381 is provided in the insulating films 360 and 380. A pixel electrode 390 is provided on the insulating film 380 and inside the opening 381. The pixel electrode 390 is connected to the drain electrode 44D.

[0121] 22 is a plan view of a pixel electrode 390 and a common electrode 370 of a display device 200 according to one embodiment of the present invention. As shown in FIG. 22 , the common electrode 370 has an overlapping region that overlaps with the pixel electrode 390 in a plan view, and a non-overlapping region that does not overlap with the pixel electrode 390. When a voltage is supplied between the pixel electrode 390 and the common electrode 370, a lateral electric field is formed from the pixel electrode 390 in the overlapping region to the common electrode 370 in the non-overlapping region. This lateral electric field causes liquid crystal molecules contained in the liquid crystal element 311 to operate, thereby determining the grayscale of the pixel.

[0122] In this embodiment, a configuration in which the semiconductor device 100 is used in the pixel circuit 301 is exemplified, but the semiconductor device 100 may also be used in a peripheral circuit including a source driver circuit 302 and a gate driver circuit 303 .

[0123] 23 and 24 , a display device 200 using a semiconductor device 100 according to one embodiment of the present invention will be described. In this embodiment, a configuration in which the semiconductor device 100 described in the first embodiment is applied to the circuit of an organic EL display device will be described. The outline and circuit configuration of the display device 200 are similar to those shown in FIGS. 23 and 24 , and therefore description thereof will be omitted.

[0124] [Pixel Circuit 301 of Display Device 200] Figure 23 is a circuit diagram showing a pixel circuit of a display device 200 according to one embodiment of the present invention. As shown in Figure 23, the pixel circuit 301 includes elements such as a drive transistor 110, a selection transistor 1200, a storage capacitor 215, and a light-emitting element DO. The drive transistor 110 and the selection transistor 120 have the same configuration as the transistor 210 of the semiconductor device 100. The source electrode of the selection transistor 120 is connected to a signal line 211, and the gate electrode of the selection transistor 120 is connected to a gate line 212. The source electrode of the drive transistor 110 is connected to an anode power line 213, and the drain electrode of the drive transistor 110 is connected to one end of the light-emitting element DO. The other end of the light-emitting element DO is connected to a cathode power line 214. The gate electrode of the drive transistor 110 is connected to the drain electrode of the selection transistor 120. The storage capacitor 215 is connected to the gate electrode and drain electrode of the drive transistor 110. A grayscale signal that determines the light-emitting intensity of the light-emitting element DO is supplied to the signal line 211. A signal for selecting a pixel row to which the above-mentioned gray scale signal is to be written is supplied to the gate line 212 .

[0125] [Cross-sectional structure of display device 200] Figure 24 is a cross-sectional view of a display device 200 according to one embodiment of the present invention. The configuration of the display device 200 shown in Figure 24 is similar to that of the display device 200 shown in Figure 20, but the structure above the insulating film 360 of the display device 200 in Figure 24 is different from the structure above the insulating film 360 of the display device 200 in Figure 20. Below, a description of the configuration of the display device 200 shown in Figure 24 that is similar to that of the display device 200 shown in Figure 20 will be omitted, and only differences between the two will be described.

[0126] As shown in FIG. 24 , the display device 200 has a pixel electrode 390, a light-emitting layer 392, and a common electrode 394 (light-emitting element DO) above an insulating film 360. The pixel electrode 390 is provided on the insulating film 360 and inside an opening 381. An insulating film 362 is provided on the pixel electrode 390. An opening 363 is provided in the insulating film 362. The opening 363 corresponds to a light-emitting region. In other words, the insulating film 362 defines a pixel. The light-emitting layer 392 and the common electrode 394 are provided on the pixel electrode 390 exposed by the opening 363. The pixel electrode 390 and the light-emitting layer 392 are provided individually for each pixel. On the other hand, the common electrode 394 is provided in common to a plurality of pixels. Different materials are used for the light-emitting layer 392 depending on the display color of the pixel.

[0127] In the third and fourth embodiments, the semiconductor device 100 described in the first embodiment is applied to a liquid crystal display device and an organic EL display device, but the semiconductor device may also be applied to display devices other than these display devices (for example, a self-luminous display device other than an organic EL display device or an electronic paper display device). Furthermore, the semiconductor device 100 can be applied to a variety of display devices, from small and medium-sized display devices to large display devices, without any particular limitations.

[0128] 25 and 26 , the results of an investigation into whether transistor degradation is due to differences in the shape of the top gate and the bottom gate in an NBTIS test are described. Measurement condition 1 is a case in which the width of the top gate is fixed and the length L2 of the bottom gate in a first region where the bottom gate protrudes from the top gate in a first direction D1 is varied. Measurement condition 2 is a case in which the width of the top gate is fixed and the length L3 of the bottom gate in a second region where the bottom gate protrudes from the oxide semiconductor layer in a second direction D2 is varied.

[0129] (Transistor Configuration Under Measurement Condition 1) The transistor configuration used under measurement condition 1 corresponds to the configuration of the transistor 210 shown in FIGS. 1 and 2. An oxide semiconductor having a polycrystalline structure was used as the oxide semiconductor layer 22. In the following description, the bottom gate corresponds to the first gate electrode, and the top gate corresponds to the second gate electrode. In addition, in FIG. 2, the channel length L1 of the channel region 22CH was set to 3 μm, and the channel width W was set to 4.5 μm. Furthermore, under measurement condition 1, it was confirmed whether the characteristics of the transistor 210 changed depending on the film thicknesses of the first insulating films 14 and 16 and the second insulating film 24. Here, two types of thickness conditions were applied: thickness condition 1, in which a stack of a 200 nm silicon nitride film and a 100 nm silicon oxide film was used as the first insulating films 14, 16, and a 100 nm silicon oxide film was used as the second insulating film 24; and thickness condition 2, in which a stack of a 100 nm silicon nitride film and a 50 nm silicon oxide film was used as the first insulating films 14, 16, and a 75 nm silicon oxide film was used as the second insulating film 24. For each of the two types of thickness conditions, the length L2 of the first gate electrode 12GE protruding in the first direction D1 from the second gate electrode 26GE was varied between ±0 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, and 10 μm. Here, length L2 is a design value.

[0130] (Conditions of NBTIS reliability test) The conditions of the NBTIS reliability test are as follows: Light irradiation conditions: With irradiation (7000 lx) Voltage applied to the first gate electrode: −60 V Voltage applied to the second gate electrode: −20 V Voltage applied to the source electrode and the drain electrode: 0 V Stage temperature during stress application: 85° C., dark room Irradiation time: 1000 sec

[0131] The conditions for measuring the electrical characteristics of the transistor before and after stress application are as follows: Source-drain voltage: 0.1 V, 10 V Voltage applied to the second gate electrode: -15 V to +15 V Measurement environment: 85°C, dark room

[0132] Table 1 shows the relationship between the length L2 of the first gate electrode 12GE protruding from the second gate electrode 26GE in the first direction D1 and the amount of variation ΔVth of the threshold voltage in the case of film thickness condition 1.

[0133]

[0134] Table 2 shows the relationship between the length L2 of the first gate electrode 12GE protruding from the second gate electrode 26GE in the first direction D1 and the amount of variation ΔVth of the threshold voltage in the case of film thickness condition 2.

[0135]

[0136] FIG. 25 shows a graph illustrating the reliability test results of Tables 1 and 2. In FIG. 25, the X-axis represents length L2, and the Y-axis represents the amount of variation in threshold voltage. In FIG. 25, the open squares represent film thickness condition 1, and the black squares represent film thickness condition 2. When the channel length L1 is 3 μm, as shown in FIG. 25, the dependency was confirmed in which the amount of variation in threshold voltage ΔVth decreased as the length L2 increased within the design range of 0 μm to 4 μm (measured value 3 μm). Furthermore, within the design range of 5 μm to 10 μm, the amount of variation in threshold voltage ΔVth did not change significantly even when the length L2 increased.

[0137] Furthermore, under film thickness condition 1, it is preferable that the amount of variation in threshold voltage |ΔVth| is 3 V or less. Therefore, under film thickness condition 1, it is believed that if the length L2 is at least 2 μm or more, it is possible to suppress the variation in threshold voltage of the transistor. Further, under film thickness condition 2, it is preferable that the amount of variation in threshold voltage |ΔVth| is 1 V or less. Therefore, under film thickness condition 2, it is believed that if the length L2 is 3 μm or more, it is possible to suppress the variation in threshold voltage of the transistor. It has also been confirmed that film thickness condition 2 is more effective at suppressing the variation in threshold voltage than film thickness condition 1.

[0138] (Transistor Configuration Under Measurement Condition 2) The transistor configuration used under measurement condition 2 corresponds to the configuration of the transistor 210 shown in FIGS. 1 and 2 . An oxide semiconductor layer having a polycrystalline structure was used as the oxide semiconductor layer 22. In the following description, the bottom gate corresponds to the first gate electrode 12GE, and the top gate corresponds to the second gate electrode 26GE. In addition, in FIG. 2 , the channel length L1 of the channel region 22CH was set to 3 μm, and the channel width W was set to 4.5 μm. As with measurement condition 1, under measurement condition 2, it was confirmed whether the characteristics of the transistor 210 changed depending on the film thicknesses of the first insulating films 14 and 16 and the second insulating film 24. Here, two types of thickness conditions were applied: thickness condition 1, in which a stack of a 200 nm silicon nitride film and a 100 nm silicon oxide film was used as the first insulating films 14, 16, and a 100 nm silicon oxide film was used as the second insulating film 24; and thickness condition 2, in which a stack of a 100 nm silicon nitride film and a 50 nm silicon oxide film was used as the first insulating films 14, 16, and a 75 nm silicon oxide film was used as the second insulating film 24. For each of the two types of thickness conditions, the length L3 of the first gate electrode 12GE protruding in the second direction D2 from the oxide semiconductor layer 22 was varied among ±0 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, and 7 μm. Here, length L3 is a design value.

[0139] (Conditions of NBTIS reliability test) The conditions of the NBTIS reliability test are as follows: Light irradiation conditions: With irradiation (7000 lx) Voltage applied to the first gate electrode: −60 V Voltage applied to the second gate electrode: −20 V Voltage applied to the source electrode and the drain electrode: 0 V Stage temperature during stress application: 85° C., dark room Irradiation time: 1000 sec

[0140] The conditions for measuring the electrical characteristics of the transistor before and after stress application are as follows: Source-drain voltage: 0.1 V, 10 V Voltage applied to the second gate electrode: -15 V to +15 V Measurement environment: 85°C, dark room

[0141] Table 3 shows the relationship between the length L3 of the first gate electrode 12GE protruding from the oxide semiconductor layer 22 in the second direction D2 and the amount of variation ΔVth of the threshold voltage in the case of film thickness condition 1.

[0142]

[0143] Table 4 shows the relationship between the length L3 of the first gate electrode 12GE protruding from the oxide semiconductor layer 22 in the second direction D2 and the amount of variation ΔVth of the threshold voltage in the case of the film thickness condition 2.

[0144]

[0145] FIG. 26 shows a graph illustrating the reliability test results of Tables 3 and 4. In FIG. 26, the X axis represents length L3, and the Y axis represents the threshold voltage variation. In FIG. 26, the open squares represent film thickness condition 1, and the solid squares represent film thickness condition 2. When the channel length L1 is 3 μm, and the length L3 is a design value of 0 μm to 1 μm as shown in FIG. 26, misalignment occurs between the end of the oxide semiconductor layer and the end of the first gate electrode, causing the threshold voltage variation |ΔVth| to exceed 3.0 V. When the length L3 is equal to or greater than the design value of 2 μm (actual measured value 1 μm), the threshold voltage variation ΔVth does not change significantly even when the length L3 is increased.

[0146] Furthermore, under film thickness condition 1, it is preferable that the amount of variation in threshold voltage, |ΔVth|, is 3 V or less. Therefore, under film thickness condition 1, it is considered that if the length L3 is at least greater than 0, taking into account the misalignment between the end of the oxide semiconductor layer and the end of the first gate electrode, the variation in threshold voltage of the transistor can be suppressed. Further, under film thickness condition 2, it is preferable that the amount of variation in threshold voltage, |ΔVth|, is 1 V or less. Therefore, under film thickness condition 2, it is considered that if the length L3 is 2 μm or more, taking into account the misalignment between the end of the oxide semiconductor layer and the end of the first gate electrode, the variation in threshold voltage of the transistor can be suppressed.

[0147] The above-described embodiments and modifications of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Furthermore, those in which a person skilled in the art appropriately adds or deletes components or modifies designs, or adds or omits processes or modifies conditions, based on the semiconductor device and display device of each embodiment or modification, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0148] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention.

[0149] 10: substrate, 12GE: first gate electrode, 14: first insulating film, 16: first insulating film, 17: oxide semiconductor film, 18: oxide semiconductor layer, 19: resist mask, 22: oxide semiconductor layer, 22CH: channel region, 22D: drain region, 22S: source region, 24: second insulating film, 25: metal oxide film, 26GE: second gate electrode, 28: third insulating film, 31-1, 31-2: contact holes, 32: third insulating film, 44D: drain electrode, 44S: source electrode, 45: metal oxide film, 46: metal oxide layer, 100, 100A, 100B: semiconductor device, 110: drive transistor, 120: selection transistor, 200: display device, 203: drain electrode, 210: transistor, 210A: Transistor, 210B: transistor, 211: signal line, 212: gate line, 213: anode power line, 214: cathode power line, 215: storage capacitor, 220: liquid crystal region, 240: sealing region, 260: terminal region, 300: array substrate, 301: pixel circuit, 302: source driver circuit, 303: gate driver circuit, 304: source wiring, 306: terminal portion, 307: connection wiring, 310: sealing portion, 311: liquid crystal element, 320: opposing substrate, 330: flexible printed circuit board, 340: chip, 350: storage capacitor, 360: insulating film, 362: insulating film, 363: opening, 370: common electrode, 380: insulating film, 381: opening, 390: pixel electrode, 392: light-emitting layer, 394: common electrode

Claims

1. a first gate electrode; a first gate insulating film provided on the first gate electrode; an oxide semiconductor layer having a polycrystalline structure, the oxide semiconductor layer being provided on the first gate insulating film and overlapping the first gate electrode; a second gate insulating film provided on the oxide semiconductor layer; a transistor including a second gate electrode provided on the second gate insulating film and overlapping the first gate electrode; In a plan view, the first gate electrode has: a first region overlapping the oxide semiconductor layer and protruding from the second gate electrode in a first direction; and a second region overlapping the second gate electrode and protruding from the oxide semiconductor layer in a second direction intersecting the first direction.

2. the transistor further includes a source electrode and a drain electrode provided on the second gate electrode and connected to the oxide semiconductor layer; 2. The semiconductor device according to claim 1, wherein in the oxide semiconductor layer, a first length in the first direction from the second gate electrode to the source electrode is equal to or greater than a second length in the first direction in the first region.

3. 2. The semiconductor device according to claim 1, wherein the first direction is the same direction as a channel length of the transistor, and the second direction is the same direction as a channel width of the transistor.

4. The semiconductor device according to claim 3 , wherein the second length is 2 μm or more.

5. The semiconductor device according to claim 3 , wherein a third length in the second direction in the second region is greater than zero.

6. the first gate insulating film is a laminate of a silicon nitride film and a silicon oxide film, 2. The semiconductor device according to claim 1, wherein the first gate insulating film has a thickness of 150 nm or more and 300 nm or less.

7. The semiconductor device according to claim 1 , further comprising a first metal oxide layer provided between said first gate insulating film and said oxide semiconductor layer.