Multilevel power conversion system and control device for multilevel power conversion system

Abstract

The present invention provides a means for suppressing overvoltage breakdown of semiconductor elements in a power converter due to lightning surges in a multilevel power conversion system.　This multilevel power conversion system comprises a multilevel power converter (30) and a control device (40) including: an operation control unit (51) that, on the basis of a predetermined condition, transitions the operation mode of the multilevel power converter (30) to a standby mode in which power conversion is not performed between a DC input / output unit (31) and an AC input / output unit (32); and a gate signal generation unit (53) that, in the standby mode, generates and outputs a gate signal to put one and / or both of a third semiconductor switching element (3) and a second semiconductor switching element (2) into a state of continuity or a switching state.

Description

Multilevel power conversion system and control device for multilevel power conversion system

[0001] The present invention relates to a multilevel power conversion system and a control device for the multilevel power conversion system.

[0002] Conventionally, for example, a multilevel power converter has been known that includes a plurality of DC capacitors, two or more of which are connected in series on the DC side, and two semiconductor switching elements connected in anti-series to a series connection point of the plurality of DC capacitors (see, for example, Patent Documents 1 and 2). Note that, hereinafter, in this specification and the like, the DC connection point of the plurality of DC capacitors is also referred to as a "DC neutral point," and the two semiconductor switching elements connected in anti-series to the DC connection point (DC neutral point) of the plurality of DC capacitors are also referred to as a "neutral point element."

[0003] Japanese Patent Publication No. 2013-116020 Japanese Patent Publication No. 2019-024290

[0004] Fig. 22 is a diagram illustrating an example of the configuration of a multilevel power converter 130 according to one aspect. Fig. 22 illustrates a configuration of a three-level NPP (Neutral Point Potential) multilevel power converter 130 for three phases as a first configuration example of the multilevel power converter. As shown in Fig. 22, the multilevel power converter 130 includes two DC capacitors C Ｐ , C Ｎ are connected in series via a DC neutral point C, and two semiconductor switching elements (neutral point elements) 102 and 103 are connected in anti-series to the DC neutral point C for each of the three phases. In the example shown in Fig. 22, the semiconductor switching elements (neutral point elements) 102 and 103 are connected in anti-series with the collector side of an IGBT (Insulated Gate Bipolar Transistor) in common.

[0005] Fig. 23 is a diagram showing an example of the configuration of a multilevel power converter 230 according to another aspect. Fig. 23 shows a configuration of a three-level NPP multilevel power converter 230 for three phases as a second configuration example of the multilevel power converter. As shown in Fig. 23, the multilevel power converter 230 has two DC capacitors C Ｐ , C Ｎ are connected in series via a DC neutral point C, and two semiconductor switching elements (neutral point elements) 202, 203 are connected in anti-series to the DC neutral point C for each of the three phases. In the example shown in Fig. 23, the semiconductor switching elements (neutral point elements) 202, 203 are connected in anti-series with the emitter side of the IGBT in common. The multilevel power converter 130 shown in Fig. 22 and the multilevel power converter 230 shown in Fig. 23 have the same configuration except that the semiconductor switching elements 102, 103 and the semiconductor switching elements 202, 203 are connected in anti-series in the opposite directions.

[0006] Fig. 24 is a diagram showing an example of the configuration of a multilevel power converter 330 according to another aspect. Fig. 24 shows the configuration of a five-level NPP multilevel power converter 330 for one phase as a third example of the configuration of the multilevel power converter. As shown in Fig. 24, the multilevel power converter 330 has four DC capacitors C Ｐ , C Ｎ are connected in series via three DC neutral points C, and two semiconductor switching elements (neutral point elements) 302, 303 are connected in anti-series to each of the DC neutral points C. In the example shown in Fig. 24, the semiconductor switching elements (neutral point elements) 302, 303 are connected in anti-series with the collector side of the IGBT in common. However, although not shown, the semiconductor switching elements (neutral point elements) may also be connected in anti-series with the emitter side in common.

[0007] Here, for example, in a multilevel power conversion system having the multilevel power converters 130, 230, 330, etc. shown in Figures 22 to 24, a surge voltage (lightning surge) caused by a lightning strike has sometimes caused overvoltage breakdown of semiconductor elements. That is, in a multilevel power conversion system, a surge voltage caused by a lightning strike causes large fluctuations in the potentials of the positive and negative poles (P pole and N pole) on the DC side of the power converter, causing part of the surge voltage to charge the parasitic capacitance of the semiconductor elements, resulting in overvoltage breakdown of the semiconductor elements.

[0008] Therefore, an object of the present disclosure is to provide a means for preventing semiconductor elements of a power converter from being destroyed by overvoltage due to a lightning surge in a multilevel power conversion system.

[0009] A multilevel power conversion system according to one aspect includes a DC input / output unit having a positive terminal and a negative terminal connected to a DC power supply or a DC load, a plurality of DC capacitors connected in series between the positive terminal and the negative terminal via a DC neutral point, an AC input / output unit having AC terminals connected to an AC power supply or an AC load, a first semiconductor switching element and a fourth semiconductor switching element connected in series with the same polarity via the AC terminals between the positive terminal and the negative terminal, a first freewheeling diode and a fourth freewheeling diode connected in anti-parallel to the first semiconductor switching element and the fourth semiconductor switching element, respectively, and a third semiconductor switching element connected in series with opposite polarity between the DC neutral point and the AC terminal. a control device including: a multilevel power converter having a first semiconductor switching element and a second semiconductor switching element, and a third freewheeling diode and a second freewheeling diode connected in anti-parallel to the third semiconductor switching element and the second semiconductor switching element, respectively; an operation control unit that transitions an operation mode of the multilevel power converter to a standby mode in which no power conversion is performed between a DC input / output unit and an AC input / output unit based on a predetermined condition; and a gate signal generation unit that generates and outputs a gate signal that puts at least one of the third semiconductor switching element and the second semiconductor switching element into a conducting state or a switching state in the standby mode.

[0010] A control device for a multilevel power conversion system according to one aspect includes a DC input / output unit having a positive terminal and a negative terminal connected to a DC power supply or a DC load, a plurality of DC capacitors connected in series between the positive terminal and the negative terminal via a DC neutral point, an AC input / output unit having AC terminals connected to an AC power supply or an AC load, a first semiconductor switching element and a fourth semiconductor switching element connected in series with the same polarity via the AC terminals between the positive terminal and the negative terminal, a first freewheeling diode and a fourth freewheeling diode connected in anti-parallel to the first semiconductor switching element and the fourth semiconductor switching element, respectively, and a third semiconductor switching element and a second semiconductor switching element connected in series with opposite polarity between the DC neutral point and the AC terminal. a multilevel power converter having a semiconductor switching element, and a third freewheeling diode and a second freewheeling diode connected in anti-parallel to the third and second semiconductor switching elements, respectively, wherein the control device comprises: an operation control unit that transitions an operation mode of the multilevel power converter to a standby mode in which no power conversion is performed between a DC input / output unit and an AC input / output unit based on a predetermined condition; and a gate signal generation unit that generates and outputs a gate signal that places at least one of the third semiconductor switching element and the second semiconductor switching element in a conducting state or a switching state in the standby mode.

[0011] According to the present disclosure, in a multilevel power conversion system, it is possible to prevent semiconductor elements of a power converter from being destroyed by overvoltage due to a lightning surge.

[0012] 1 is a diagram showing an example of the configuration of a multilevel power conversion system according to a first embodiment. FIG. 1 is a diagram showing an example of the configuration of a control device in the multilevel power conversion system shown in FIG. 1. FIG. 2 is a circuit diagram showing an example of the circuit configuration of the multilevel power converter shown in FIG. 1. FIG. 3 is an actual wiring diagram showing an example of the circuit configuration of the multilevel power converter shown in FIG. 1. FIG. 4 is a diagram showing an example of a charging path to parasitic capacitance of each part due to a lightning strike in the circuit configuration of the multilevel power converter shown in FIGS. 3 and 4. FIG. 5 is a diagram showing an equivalent circuit of the charging path shown in FIG. 5. FIG. 6 is a diagram sorting by case whether or not a neutral point element is overvoltage broken down by a lightning surge in the circuit configuration of the multilevel power converter shown in FIGS. 3 and 4. FIG. 7 is a diagram showing an example of a charging path to parasitic capacitance of each part due to a lightning strike when a semiconductor element 2 is turned on in the circuit configuration of the multilevel power converter shown in FIGS. 3 and 4. FIG. 8 is a diagram showing an equivalent circuit of the charging path shown in FIG. 9. FIG. 10 is a diagram showing an example of a charging path to parasitic capacitance of each part due to a lightning strike when a semiconductor element 3 is turned on in the circuit configuration of the multilevel power converter shown in FIGS. 3 and 4. FIG. 11 is a diagram showing an equivalent circuit of the charging path shown in FIG. 10. FIG. 12 is a flowchart showing a state transition sequence between a power generation mode and a standby mode of the multilevel power conversion system shown in FIG. 1. 21 is a diagram showing an example of a control configuration in a voltage command generating unit of the control unit shown in FIG. 2. FIG. 2 is a diagram showing an example of a control configuration in a gate signal ... according to a modified example of the first embodiment. FIG. 2 is a diagram showing an example of a control configuration in a gate signal generating unit of the control unit according to the second embodiment. FIG. 22 is a diagram showing an example of a control configuration in a voltage command generating unit of the control unit according to the third embodiment. FIG. 23 is a diagram showing an example of a control configuration in a gate signal generating unit of the control unit according to the third embodiment. FIG. 24 is a diagram showing an example of a control configuration in a voltage command generating unit of the control unit according to the fourth embodiment. FIG. 25 is a conceptual diagram showing an example of a hardware configuration of a processing circuit included in the control device in the embodiments shown in FIGS. 1 to 20. FIG. 26 is a diagram showing an example of the configuration of a multilevel power converter according to one aspect. FIG. 27 is a diagram showing an example of the configuration of a multilevel power converter according to another aspect.FIG. 10 is a diagram illustrating an example of the configuration of a multilevel power converter according to another embodiment.

[0013] Hereinafter, embodiments of a multilevel power conversion system and a control device for the multilevel power conversion system according to the present disclosure will be described with reference to the drawings.

[0014] <Configuration Example of First Embodiment> FIG. 1 is a diagram showing an example of the configuration of a multilevel power conversion system 20 according to the first embodiment.

[0015] As shown in Fig. 1 , the multilevel power conversion system 20 is connected to a solar cell 11 via a DC cable 12 on the DC side on the left side in Fig. 1 . The multilevel power conversion system 20 is also connected to an AC power grid 15 via an AC cable 13 and a transformer 14 on the AC side on the right side in Fig. 1 . The multilevel power conversion system 20 converts, for example, DC power acquired from the solar cell 11 into AC power and outputs the converted AC power to the AC power grid 15 via the transformer 14. Hereinafter, in this specification and the like, the multilevel power conversion system 20 is also referred to as a "power conversion system 20".

[0016] The solar cell (PV: Photovoltaics) 11 is also called a solar cell panel, and is connected to an input end (DC input / output unit 31 (see FIGS. 3 and 4 )) which is one end of the power conversion system 20 via a DC cable 12. The solar cell 11 generates electricity using sunlight, and the generated DC power is supplied to the power conversion system 20 via the DC cable 12. The solar cell 11 is an example of a "DC power source or DC load," and the "DC power source or DC load" may be, for example, a DC power source such as an "Energy Storage System (ESS)," or another DC load.

[0017] One end of the DC cable 12 is connected to the solar cell 11, and the other end is connected to a DC end (DC input / output unit 31 (see FIGS. 3 and 4 )) of a multilevel power converter 30 (described later) in the power conversion system 20. The DC cable 12 has a positive cable and a negative cable, and supplies DC power from the solar cell 11 to the multilevel power converter 30 (described later).

[0018] One end of the AC cable 13 is connected to an AC end (AC input / output unit 32 (see FIGS. 3 and 4 )) of a multilevel power converter 30 (described later) in the power conversion system 20, and the other end is connected to the AC power grid 15 via a transformer 14. The AC cable 13 is, for example, a three-phase, three-wire, three-phase AC circuit that supplies three-phase AC power, which is a combination of three systems of single-phase AC with mutually shifted phases of current or voltage, using three electric wires, cables, and conductors. The AC cable 13 supplies AC power converted by the multilevel power converter 30 (described later) to the AC power grid 15 side.

[0019] One end of the transformer 14 is connected to the output side, which is the other end of the power conversion system 20, via the AC cable 13, and the other end is connected to the AC power grid 15. The transformer 14 transforms the AC power output from the power conversion system 20 to a predetermined voltage level and outputs it to the AC power grid 15.

[0020] The AC power system (power system) 15 is connected to the transformer 14 and is a system that integrates power generation, power transformation, power transmission, and power distribution for supplying AC power transformed by the transformer 14 to power receiving equipment of consumers, and is connected to, for example, an unspecified load. Hereinafter, in this specification, the AC power system 15 is also simply referred to as the "power system 15." Note that the AC power system (power system) 15 is an example of an "AC power source or an AC load," and the "AC power source or an AC load" may be a power system or, for example, an electric motor, a generator, or other AC load.

[0021] The multilevel power conversion system (power conversion system) 20 is, for example, a power conversion system (PV-PCS: Photovoltaics-Power Conditioning System) for photovoltaic power generation (solar cell). The power conversion system 20 converts DC power supplied from a solar cell 11 into AC power and outputs the converted AC power to a power grid 15 via a transformer 14. Note that the power conversion system 20 is not limited to one for photovoltaic power generation, and may be, for example, a power conversion system for a storage battery (ESS-PCS: Energy Storage System-Power Conditioning System). In other words, the present disclosure is applicable to any power conversion system in which the potential on the DC side fluctuates due to lightning strikes or the like during shutdown.

[0022] The multilevel power conversion system (power conversion system) 20 includes a DC switch 21, an AC reactor 22, an AC capacitor 23, an AC switch 24, a DC voltage sensor 25, an AC current sensor 26, a multilevel power converter 30, and a control device 40. The DC switch 21 and the DC voltage sensor 25 are arranged on the DC cable 12 between the solar cell 11 and the multilevel power converter 30. The AC reactor 22, the AC capacitor 23, the AC switch 24, and the AC current sensor 26 are arranged on the AC cable 13 between the multilevel power converter 30 and the transformer 14. Hereinafter, in this specification and the like, the multilevel power converter 30 will also be referred to as the "power converter 30."

[0023] The DC switch (DC circuit breaker) 21 is provided in series in the DC cable 12 between the solar cell 11 and the power converter 30. The DC switch 21 makes (connects) or opens (disconnects) the DC cable 12 between the solar cell 11 and the power converter 30 in accordance with, for example, an on command or an off command from the control device 40, a higher-level device (not shown), or an operator. The DC switch 21 is, for example, an electrical contactor that can be opened or closed in response to an instruction from the control device 40. Note that the DC switch 21 may also be, for example, a DC circuit breaker that is normally manually opened or closed and automatically shuts off the DC cable 12 when an overcurrent such as a short-circuit current is detected. When the DC switch 21 is opened, the DC power supplied from the solar cell 11 is blocked from flowing into the power converter 30.

[0024] The AC reactor 22 is connected in series to the AC cables 13 of each phase at the output end (AC input / output unit 32 (see FIGS. 3 and 4 )) of the power converter 30. The AC reactor 22 is a smoothing element that has the effect of reducing noise and suppressing surge voltages, for example. The AC reactor 22, together with an AC capacitor 23 connected in an L-shape, constitutes an LC filter circuit (filter circuit) that reduces ripples (vibrations) that occur when switching elements (described later) of the power converter 30 switch on and off.

[0025] The AC capacitors 23 are connected in an L-shape to the AC cables 13 of each phase at the output end of the power converter 30 via branch points. The AC capacitors 23 are electronic components that store or release electricity (charges). For example, the AC capacitors 23, together with the AC reactors 22 connected in an L-shape, constitute an LC filter circuit (filter circuit) that reduces ripples (vibrations) that occur when switching elements (described below) of the power converter 30 switch. The AC capacitors 23, together with the AC reactors 22, constitute a filter circuit, thereby suppressing the outflow of harmonics (harmonic currents) to the power grid 15.

[0026] The AC switch (AC circuit breaker) 24 is provided in series in the AC cable 13 of each phase between the AC reactor 22 (filter circuit) and the transformer 14. The AC switch 24 closes (connects) or opens (disconnects) the AC cable 13 between the power converter 30 and the power grid 15, for example, in accordance with an AC switch operation signal from the control device 40 or an open instruction or close instruction from a higher-level device (not shown) or an operator. When the AC switch 24 is opened, the AC power supplied from the power converter 30 is blocked from flowing out to the power grid 15.

[0027] The DC voltage sensor 25 is, for example, a known DC voltmeter or DC voltage sensor, and is disposed between the solar cell 11 and the power converter 30, and detects a DC voltage value V ｄｃ The position where the DC voltage sensor 25 is disposed is not limited to the position shown in FIG. ｄｃ Any position where the DC voltage value V can be detected is acceptable. ｄｃ is "DC voltage V ｄｃ " or simply "Voltage V ｄｃ The DC voltage V detected by the DC voltage sensor 25 is also referred to as ｄｃ is acquired by the control device 40.

[0028] The AC current sensor 26 is, for example, a known AC ammeter or AC current sensor, and is disposed between the power converter 30 and the transformer 14, and detects a three-phase AC current value I ｕ , I ｖ , I ｗ The position where the AC current sensor 26 is disposed is not limited to the position shown in FIG. ｕ , I ｖ , I ｗ Any position where the AC current value I can be detected is acceptable. ｕ , I ｖ , I ｗ is "AC current I ｕ , I ｖ , I ｗ ", "Current measurement value I ｕ , I ｖ , I ｗ ", or simply "Current I ｕ, I ｖ , I ｗ The AC current I detected by the AC current sensor 26 is also referred to as ｕ , I ｖ , I ｗ is acquired by the control device 40.

[0029] One end of the multilevel power converter (power converter) 30, which is a DC end (DC input / output unit 31 (see FIGS. 3 and 4 )), is connected to a DC switch 21 via a DC cable 12, and the other end, which is an AC end (AC input / output unit 32 (see FIGS. 3 and 4 )), is connected to an AC reactor 22 (filter circuit) via an AC cable 13. The power converter 30 is configured with a plurality of switching elements, such as IGBTs (described below). The power converter 30 is controlled, for example, by a pulse width modulation (PWM) signal, which is a gate drive signal (gate signal) for the switching elements, generated by a control device 40. That is, the power converter 30 is controlled by a gate signal for operating the power converter 30.

[0030] The power converter 30 acquires DC power supplied from the solar cell 11 from one end thereof, and converts the acquired DC power into AC power under control of a pulse width modulation signal (gate signal), and outputs the AC power from the other end, which is the output end, and supplies it to the AC cable 13. In other words, the power converter 30 is operated under control of the gate signal. Details of the power converter 30 will be described later (see FIGS. 3 to 11, etc.).

[0031] The control device 40 is provided, for example, inside or outside the power conversion system 20, and although some wiring and the like are omitted in the figure, it is electrically connected to each component of the power conversion system 20, including the power converter 30, via wired or wireless connections. The control device 40 may be realized as a function of an inverter control circuit (not shown). The control device 40 may also operate, for example, in accordance with instructions from a higher-level device (not shown) or instructions from an operator (not shown) via an operation unit (not shown). The higher-level device (not shown) may, for example, monitor and control multiple power conversion systems 20 in an integrated manner, and may be connected to each power conversion system 20 via wired or wireless connections.

[0032] FIG. 2 is a diagram showing an example of the configuration of the control device 40 in the multilevel power conversion system 20 shown in FIG.

[0033] The control device 40 detects the DC voltage V ｄｃ The control device 40 also acquires the DC voltage V detected by the DC voltage sensor 25 and outputs an AC switch operation signal in accordance with a control method described later (see FIG. 1, etc.). ｄｃ and the AC current I detected by the AC current sensor 26 ｕ , I ｖ , I ｗ and outputs a gate signal in accordance with a control method described later (see FIG. 1 , etc.). The control device 40 has an acquisition unit 41, an output unit 42, a storage unit 43, a system bus 45, and a control unit 50. The acquisition unit 41, the output unit 42, the storage unit 43, and the control unit 50 are connected to each other via the system bus 45.

[0034] The acquisition unit 41 is connected to the DC voltage sensor 25, the AC current sensor 26, and the system bus 45. The acquisition unit 41 may be connected to a higher-level device (not shown). The acquisition unit 41 acquires, for example, the DC voltage V detected by the DC voltage sensor 25. ｄｃ and the AC current I detected by the AC current sensor 26 ｕ , I ｖ , I ｗ The acquisition unit 41 outputs the acquired voltage values ​​and current values ​​to each component of the control device 40 via the system bus 45, for example.

[0035] The output unit 42 is connected to the AC switch 24, the power converter 30, and the system bus 45. The output unit 42 may be connected to a higher-level device (not shown), etc. The output unit 42 outputs an AC switch operation signal to the AC switch 24 or outputs a gate signal to the power converter 30, in accordance with an instruction obtained from the control unit 50 via the system bus 45, for example.

[0036] The storage unit 43 is a volatile or non-volatile storage medium such as a hard disk drive (HDD), a solid state drive (SSD), or other semiconductor memory, and is connected to the system bus 45. The storage unit 43 stores, for example, programs necessary for the operation of each unit of the control device 40, and various pieces of information are written to and read from the storage unit 43 by each unit of the control device 40. The storage unit 43 also stores, for example, values ​​detected by each sensor such as the DC voltage sensor 25 and the AC current sensor 26, various arithmetic expressions and coefficients used in calculations by the control unit 50, predetermined thresholds, predetermined judgment values, and the like.

[0037] The storage unit 43 is connected to each unit of the control device 40 via a system bus 45 or the like so as to enable input and output of various information. The storage unit 43 may be provided outside the control device 40 and connected to the control device 40 by wire or wirelessly. The storage unit 43 may be an external storage medium such as a memory card or a DVD (Digital Versatile Disc), or may be online storage. The storage unit 43 may also be a memory 92 (see FIG. 21 ) described below.

[0038] The system bus (bus) 45 is a data transmission path (bus) that connects each component within the control device 40, and interconnects the acquisition unit 41, output unit 42, memory unit 43, and control unit 50 so that various types of information can be input and output.

[0039] The control unit 50 includes a processor 91 (see FIG. 21 ), which will be described later, such as a CPU (Central Processing Unit) that operates by executing a program. The control unit 50 executes a predetermined program stored in the storage unit 43 or a memory 92 (see FIG. 21 ), which will be described later, to operate the processor 91 and comprehensively control the operation of the power conversion system 20. The control unit 50 may control the operation of the power conversion system 20 in accordance with instructions received from a higher-level device (not shown) or instructions received from an operator (not shown) via an operation unit (not shown).

[0040] The control unit 50 functions as the following units by executing a predetermined program stored in the storage unit 43 or a memory 92 (see FIG. 21 ) described below, for example. The control unit 50 functions as an operation control unit 51, a voltage command generation unit 52, and a gate signal generation unit 53, for example. Note that each of the above functions may be realized by a program executed by a processor 91 (see FIG. 21 ) described below in a processing circuit 90 (see FIG. 21 ) included in the control device 40, or may be realized by hardware 93 (see FIG. 21 ) described below. Note that the operation control unit 51, the voltage command generation unit 52, and the gate signal generation unit 53 execute the predetermined program to perform the following processes.

[0041] The operation control unit 51 detects, for example, the DC voltage V detected by the DC voltage sensor 25 based on a predetermined condition. ｄｃ The operation control unit 51 outputs an AC switch operation signal to the AC switch 24 based on a predetermined condition, for example, based on the open / closed state of the AC switch 24. For example, the operation control unit 51 transitions the operation mode of the power converter 30 to a standby mode in which power conversion is not performed between a DC input / output unit and an AC input / output unit (described later), or to a power generation mode in which power conversion is performed, based on the predetermined condition. The operation control unit 51 also outputs a standby mode signal of 0 (low level) or 1 (high level) and a gate block signal to the gate signal generation unit 53 based on the predetermined condition, for example, based on the open / closed state of the AC switch 24 or the operation mode of the power converter 30.

[0042] The voltage command generating unit 52 generates, for example, a predetermined output power command value P ＿ｒｅｆ and the three-phase AC current I detected by the AC current sensor 26. ｕ , I ｖ , I ｗ Based on this, the three-phase voltage command value V ｕ＿ｒｅｆ , V ｖ＿ｒｅｆ , V ｗ＿ｒｅｆ Then, the voltage command generating unit 52 generates the generated three-phase voltage command values ​​V ｕ＿ｒｅｆ , V ｖ＿ｒｅｆ , V ｗ＿ｒｅｆ to the gate signal generating unit 53.

[0043] The gate signal generator 53 generates the voltage command value V ｕ＿ｒｅｆ , V ｖ＿ｒｅｆ , V ｗ＿ｒｅｆ and the DC voltage V detected by the DC voltage sensor 25. ｄｃ The gate signal generating unit 53 also acquires triangular wave carriers CA1 and CA2 having a predetermined carrier period, and a standby mode signal and a gate block signal output from the operation control unit 51. The gate signal generating unit 53 acquires, for example, a voltage command value V ｕ＿ｒｅｆ , V ｖ＿ｒｅｆ , V ｗ＿ｒｅｆ and DC voltage V ｄｃ The gate signal generator 53 generates gate signals based on the triangular wave carriers CA1 and CA2, the standby mode signal, and the gate block signal. The gate signal generator 53 outputs the generated gate signals to the power converter 30, causing at least one of the semiconductor switching elements 2 and 3 (see FIG. 3, etc.) to be in a conductive state or a switching state when the AC switch 24 is open or the power converter 30 is in standby mode. The gate signal generator 53 also outputs the generated gate signals to the power converter 30, causing both of the semiconductor switching elements 1 and 4 (see FIG. 3, etc.) to be in a non-conductive state when the AC switch 24 is open or the power converter 30 is in standby mode.

[0044] Details of the control configuration or processing (operation) of the operation control unit 51, voltage command generating unit 52, and gate signal generating unit 53 in the control unit 50 (control block) will be described later (see Figures 12 to 20, etc.).

[0045] Fig. 3 is a circuit diagram showing an example of the circuit configuration of the multilevel power converter 30 shown in Fig. 1. For the sake of simplicity, Fig. 3 shows a circuit diagram of one of three phases (e.g., the U-phase) as an example of the circuit configuration of the power converter 30. In practice, the power converter 30 has a three-phase circuit configuration, in which, for example, three circuits shown in Fig. 3 are arranged side by side and the DC sides are connected in parallel (see, for example, Figs. 22 and 23 ). However, in the present disclosure, the number of phases in the circuit configuration of the power converter 30 is not limited to three, and may be a single phase or a multiple phase other than three.

[0046] As shown in Fig. 3, the power converter 30 has a DC input / output unit 31 and an AC input / output unit 32. The power converter 30 also has a positive terminal P, a negative terminal N, and a DC capacitor C Ｐ and DC capacitor C Ｎ , a DC neutral point C, a power semiconductor module A, and a power semiconductor module B. Power semiconductor module A has a power semiconductor element 1, a power semiconductor element 4, and an AC terminal AC, and power semiconductor module B has a power semiconductor element 3, a power semiconductor element 2, and a non-connection terminal NC. In this specification and the like, the AC terminal AC is also referred to as an "AC (Alternating Current) terminal," and the non-connection terminal NC is also referred to as an "NC (No Connection) terminal."

[0047] The DC input / output unit 31 is the DC end of the power converter 30, and has a positive terminal P and a negative terminal N connected to the solar cell 11 (DC power source or DC load).

[0048] The AC input / output unit 32 is an AC end of the power converter 30 and has an AC terminal AC to be connected to the power system 15 (AC power source or AC load).

[0049] The positive terminal P and the negative terminal N are connected to the positive (P pole) side and the negative (N pole) side of a solar cell (DC power source) 11 via a DC cable 12, respectively.

[0050] Between the positive terminal P and the negative terminal N, a DC capacitor C Ｐ and DC capacitor C Ｎand are connected in series via a DC neutral point C. Ｐ and DC capacitor C Ｎ is, for example, a DC smoothing capacitor that smoothes voltage fluctuations (ripples), and is connected in series via a DC neutral point C.

[0051] Furthermore, a power semiconductor module A is connected in series between the positive terminal P and the negative terminal N. In the power semiconductor module A, a power semiconductor element 1 and a power semiconductor element 4 are connected in series with the same polarity via an AC terminal AC (AC terminal). Furthermore, a power semiconductor module B is connected in series between a DC neutral point C and the AC terminal AC. In the power semiconductor module B, a power semiconductor element 3 and a power semiconductor element 2 are connected in series with opposite polarity via a non-connection terminal NC (NC terminal).

[0052] The power semiconductor elements (semiconductor switching elements) 1 to 4 each have a free wheel diode D1 to D4, and the power semiconductor elements 1 to 4 (semiconductor switching elements) and the free wheel diodes D1 to D4 are connected in anti-parallel to each other. The power semiconductor elements 1 to 4 are semiconductor switching elements formed, for example, by IGBTs or the like, and their on / off operations are controlled by gate signals output from the control device 40.

[0053] In the following description and the like, the power semiconductor elements 1 and 4 in the power semiconductor module A are also referred to as "semiconductor switching elements 1 and 4," "semiconductor elements 1 and 4," or simply "elements 1 and 4," respectively. The power semiconductor elements 2 and 3 in the power semiconductor module B are also referred to as "neutral point elements 2 and 3," "semiconductor switching elements 2 and 3," "semiconductor elements 2 and 3," or simply "elements 2 and 3," respectively. The power semiconductor elements (semiconductor switching elements) 1 to 4 are examples of "first semiconductor switching element" to "fourth semiconductor switching element," respectively.

[0054] The free wheel diodes D1 to D4 are connected in anti-parallel to the semiconductor elements 1 to 4, respectively, and are free wheel diodes that free wheel energy when, for example, an IGBT is turned off. Note that hereinafter in this specification, the free wheel diodes D1 to D4 are also referred to as "anti-parallel diodes D1 to D4," or simply as "diodes D1 to D4," respectively. Note that the free wheel diodes D1 to D4 are examples of the "first free wheel diode" to "fourth free wheel diode," respectively.

[0055] Fig. 4 is an actual wiring diagram showing an example of the circuit configuration of the multilevel power converter 30 shown in Fig. 1. In Fig. 4, the same circuit as the circuit diagram shown in Fig. 3 is shown as an actual wiring diagram.

[0056] In the actual wiring diagram shown in FIG. 4 , bus bars are used for each wiring, such as the DC cable 12 and the AC cable 13. Also, in FIG. 4 , power semiconductor module A and power semiconductor module B are disposed on a heat sink 33. The cases (heat sink mounting surfaces) of semiconductor elements 1 to 4 in power semiconductor modules A and B are in electrical contact with the heat sink 33, and the heat sink 33 is grounded, so that the cases of semiconductor elements 1 to 4 may be at ground potential (ground potential GND). That is, since the heat sink 33 is normally grounded, it may be electrically connected to a copper plate or the like attached to the cases (heat sink mounting surfaces) of semiconductor elements 1 to 4, so that the cases of semiconductor elements 1 to 4 may be at ground potential (ground potential GND). Note that the other configurations are the same as those in FIG. 2 , and therefore description thereof will be omitted.

[0057] <Operation Principle of First Embodiment> FIG. 5 is a diagram showing an example of a charging path to the parasitic capacitance of each part due to a lightning strike in the circuit configuration of the multilevel power converter 30 shown in FIGS.

[0058] Hereinafter, the parasitic capacitance C of the semiconductor elements 1 to 4 due to the surge voltage caused by lightning strikes will be １ ~C ４The principle by which the P-pole and N-pole are charged will be explained below. Figure 5 illustrates a case where a lightning strike causes the P-pole and N-pole to be charged to a negative potential relative to the ground. In the following description, the surge voltage caused by a lightning strike will also be referred to as a "lightning surge voltage" or simply as a "surge voltage."

[0059] As described above, the cases of the semiconductor elements 1 to 4 and the heat sink 33 are in electrical contact, the heat sink 33 is grounded, and the cases of the semiconductor elements 1 to 4 may be at ground potential (ground potential GND). In this case, as shown in FIG. 5, a parasitic capacitance C ＡＣ Similarly, there is a parasitic capacitance C between the semiconductor elements 3 and 2 inside the power semiconductor module B and the case (heat sink mounting surface) of the semiconductor elements 3 and 2. ＮＣ exists.

[0060] That is, an insulating substrate (not shown) is disposed between the copper plate attached to the cases (heat sink mounting surface) of the semiconductor elements 1 to 4 and the semiconductor elements 1 to 4. As a result, the insulating substrate (not shown) functions as a capacitor, and a parasitic capacitance C ＡＣ , C ＮＣ exists.

[0061] As shown in FIG. 5, there is also a parasitic capacitance C １ ~C ４ That is, there is a parasitic capacitance C between the collector and emitter of each IGBT of the semiconductor elements 1 to 4. １ ~C ４ exists.

[0062] In this case, for example, when the power conversion system 20 is in a standby state and an OFF signal is applied to the gates of the semiconductor switching elements 1 to 4, if a lightning strike causes the P pole and N pole on the DC side to be charged with a negative potential relative to the ground, the parasitic capacitance of each part is charged along the path shown in Figure 5. Generally, the charging voltage relative to the ground potential due to a lightning strike may differ between the P pole and the N pole, but in Figure 5, for the sake of simplicity, the charging voltage V due to a lightning strike is ＬＳ The figure shows the case where the battery is charged with

[0063] As shown in Fig. 5, when the P-pole and N-pole are charged to a negative potential with respect to the ground by a lightning strike, the voltage rises as shown by the arrows in Fig. 5, and current flows through various paths shown by the broken lines in Fig. 5. At this time, as shown in Fig. 5, the parasitic capacitance C ２ , C ３ This also creates a current route that flows through this path.

[0064] Generally, the parasitic capacitance C of an insulating substrate (not shown) between the copper plate attached to the case (heat sink mounting surface) of the semiconductor elements 2 and 3 and the semiconductor elements 2 and 3 is ＮＣ is the parasitic capacitance C ２ , C ３ is larger than the parasitic capacitance C ２ , C ３ is the parasitic capacitance C ＮＣ Therefore, the parasitic capacitance C ＮＣ and the parasitic capacitance C of the neutral point elements 2 and 3. ２ , C ３ 5, the voltage of the one with the smaller capacitance will rise. As a result, the parasitic capacitance C of the neutral point elements 2 and 3 will rise higher than the potential of the non-connection terminal NC (ground potential). ２ , C ３ The voltage applied to

[0065] FIG. 6 is a diagram showing an equivalent circuit of the charging path shown in FIG.

[0066] Usually, DC capacitor C Ｐ , C Ｎ The capacitance of the DC capacitor C is sufficiently large compared to the parasitic capacitance of each part, andＰ , C Ｎ The voltage charged to the DC capacitor C is small enough to be ignored compared to the voltage charged to the parasitic capacitance of each part. Ｐ , C Ｎ The part can be considered to be in a short-circuit state, and the parasitic capacitance of each part is charged to the voltage shown in the figure.

[0067] As shown in FIG. 6, when the P and N poles are charged to a negative potential relative to the ground by a lightning strike, the charging voltage due to the lightning strike is V ＬＳ Then, the parasitic capacitance C ＮＣ The voltage is expressed by the following equation (1).

[0068]

[0069] On the other hand, in this case, the parasitic capacitance C ２ , C ３ The voltage is expressed by the following equation (2).

[0070]

[0071] As described above, the parasitic capacitance C ＮＣ is relatively large, and the parasitic capacitance C ２ , C ３ Therefore, when the potential of the positive and negative poles on the DC side is charged to the ground by a lightning strike, the parasitic capacitance C ＮＣ The voltage V applied to ＮＣ Therefore, the parasitic capacitance C ２ , C ３ The voltage V applied to ２ =V ３ will be larger.

[0072] As a result, the potentials of the P and N poles on the DC side fluctuate greatly due to the surge voltage caused by lightning, and the parasitic capacitance C ２ , C ３ If a part of the surge voltage is charged to the semiconductor elements 2 and 3, which have a low module withstand voltage, the semiconductor elements 2 and 3 may be destroyed by overvoltage.ＬＳ is much larger than the element breakdown voltage of the neutral point elements 2 and 3, so the voltage V ２ , V ３ When applied, the voltage V ２ , V ３ may exceed the element breakdown voltage of the neutral point elements 2 and 3, resulting in overvoltage breakdown of the neutral point elements 2 and 3.

[0073] FIG. 7 is a diagram showing cases where the neutral elements 2 and 3 are broken down by overvoltage due to a lightning surge in the circuit configuration of the multilevel power converter 30 shown in FIGS.

[0074] In Fig. 7, cases are classified according to whether the P and N poles on the DC side or the AC side are charged with positive or negative polarity by a lightning strike. Also, cases are classified according to whether the connection points of the diodes D2 and D3 of the two neutral point elements 2 and 3 are on the anode side or the cathode side. The results of these case classifications are shown in a matrix in Fig. 7.

[0075] 5 and 6, the case where the P and N poles on the DC side are charged to a negative polarity relative to the ground due to a lightning strike has been described. However, in reality, it is not known whether the P and N poles on the DC side will be charged to a positive polarity or a negative polarity relative to the ground due to a lightning strike, and there are cases where they will be charged to a positive polarity.

[0076] In the circuit configuration shown in FIG. 5, when the P and N poles on the DC side are charged with positive polarity relative to the ground potential, the parasitic capacitance C ＮＣ and parasitic capacitance C ＡＣ Since the charging current of the semiconductor elements 2 and 4 passes through the anti-parallel diodes D2 and D4 of the semiconductor elements 2 and 4, the parasitic capacitance C １ ~C ４ Therefore, in the circuit configuration shown in Figure 5, if the P and N poles on the DC side are charged to a positive potential relative to the ground by a lightning strike, the diodes will bypass the charge and no overvoltage breakdown will occur in the semiconductor elements 1 to 4.

[0077] However, when the cathode sides of the two anti-parallel diodes D2 and D3 of the neutral point elements 2 and 3 are connected as in the circuit configuration shown in FIG. 5, the above is true; however, when the anode sides of the two anti-parallel diodes are connected, the above is not true.

[0078] 23, when the anode sides of two anti-parallel diodes are connected, overvoltage breakdown does not occur in semiconductor elements 2 and 3 when they are charged with negative polarity, but does occur in semiconductor elements 2 and 3 when they are charged with positive polarity. In other words, whether overvoltage breakdown occurs in semiconductor elements 2 and 3 when they are charged with positive polarity or when they are charged with negative polarity depends on the orientation of anti-parallel diodes D2 and D3. This is because when the cathode sides of the two anti-parallel diodes D2 and D3 of neutral point elements 2 and 3 are connected, the circuit becomes equivalent to when the signs of the voltage and current are all reversed when the anode sides are connected.

[0079] 5, when the AC side is charged with positive polarity, the P pole is charged with positive potential to ground through the anti-parallel diode D1 of the semiconductor element 1. Also, the N pole is charged with positive potential to ground through the anti-parallel diode D1 of the semiconductor element 1 and the DC capacitor. Therefore, when "the AC side is charged with positive polarity," the same phenomenon occurs as when "the P pole and N poles on the DC side are charged with positive potential to ground."

[0080] 5, when the AC side is charged with negative polarity, the N pole is charged with negative potential to ground through the anti-parallel diode D4 of the semiconductor element 4. Also, the P pole is charged with negative potential to ground through the anti-parallel diode D4 of the semiconductor element 4 and the DC capacitor. Therefore, when "the AC side is charged with negative polarity," the same phenomenon occurs as when "the P pole and N poles on the DC side are charged with negative potential to ground."

[0081] Therefore, when the AC side is charged by a lightning strike, the current passes through the diode and eventually charges the P and N poles on the DC side as well, so whether the voltage rise caused by a lightning strike is on the DC side or the AC side, the same phenomenon occurs, although the current path is different. Figure 7 summarizes the above explanation.

[0082] As shown in FIG. 7, when the P and N poles on the DC side or the AC side are charged with positive polarity, if the connection points of the diodes D2 and D3 of the two neutral point elements 2 and 3 are on the anode side, the parasitic capacitance C ２ , C ３ On the other hand, when the P and N poles on the DC side or the AC side are charged with positive polarity, if the connection points of the diodes D2 and D3 of the two neutral point elements 2 and 3 are on the cathode side, the parasitic capacitance C ２ , C ３ is not charged, and overvoltage breakdown of the neutral point elements 2 and 3 does not occur.

[0083] In addition, when the P and N poles on the DC side or the AC side are charged with negative polarity, if the connection points of the diodes D2 and D3 of the two neutral point elements 2 and 3 are on the anode side, the parasitic capacitance C ２ , C ３ is not charged, and overvoltage breakdown of the neutral point elements 2 and 3 does not occur. On the other hand, when the P and N poles on the DC side or the AC side are charged with negative polarity, if the connection points of the diodes D2 and D3 of the two neutral point elements 2 and 3 are on the cathode side, the parasitic capacitance C ２ , C ３ may be charged, resulting in overvoltage breakdown.

[0084] Fig. 8 is a diagram showing an example of a charging path to the parasitic capacitance of each part due to a lightning strike when the semiconductor element 2 is turned on in the circuit configuration of the multilevel power converter 30 shown in Fig. 3 and Fig. 4. Fig. 8 shows, similarly to Fig. 5, the charging path to the parasitic capacitance of each part when the semiconductor element 2 is turned on (conductive state) in the case where the P pole and N pole are charged to negative potential relative to ground by a lightning strike.

[0085] 8, when the power converter 30 is in standby mode (standby state), a gate signal is applied to turn on the semiconductor element 2. Therefore, the parasitic capacitance C ２ , C ３ is bypassed by the semiconductor element 2 and is not charged. As a result, it is possible to avoid overvoltage breakdown of the semiconductor elements 2 and 3 due to the application of a charging voltage caused by a lightning strike.

[0086] That is, in the circuit configuration shown in FIG. 5, when the P-pole and N-pole are charged to a negative potential with respect to the ground by a lightning strike, the current flows through the parasitic capacitance C ２ , C ３ On the other hand, in FIG. 8, the current is bypassed by keeping the semiconductor element 2 in the ON state, so the parasitic capacitance C ２ , C ３ will not charge.

[0087] In FIG. 8, since a gate signal that turns on the semiconductor element 2 is given, the parasitic capacitance C ３ There is a possibility that some voltage may be applied to the parasitic capacitance C of the semiconductor element 3. ３ 8, if a gate signal that turns on semiconductor element 2 is given when power converter 30 is in standby mode, neutral elements 2 and 3 can be protected from overvoltage breakdown even if the P and N poles are charged to earth potential by a lightning strike.

[0088] FIG. 9 is a diagram showing an equivalent circuit of the charging path shown in FIG.

[0089] As shown in FIG. 9, when the P and N poles are charged to a negative potential relative to the ground by a lightning strike, the charging voltage due to the lightning strike is V ＬＳ Then, the parasitic capacitance C ＮＣ The voltage is expressed by the following equation (3).

[0090]

[0091] On the other hand, in this case, the parasitic capacitance C ２ , C ３The voltage is expressed by the following equation (4).

[0092]

[0093] That is, according to the formulas (3) and (4), by keeping the semiconductor element 2 in the ON state, the current is bypassed, and the parasitic capacitance C ２ , C ３ It turns out that it is not charging.

[0094] Fig. 10 is a diagram showing an example of a charging path to the parasitic capacitance of each part due to a lightning strike when the semiconductor element 3 is turned on in the circuit configuration of the multilevel power converter 30 shown in Fig. 3 and Fig. 4. Fig. 10 shows, as in Fig. 5, the charging path to the parasitic capacitance of each part when the semiconductor element 3 is turned on (conductive state) in the case where the P pole and N pole are charged to negative potential relative to ground by a lightning strike.

[0095] In the above-described Fig. 8, when the power converter 30 is in standby mode (standby state), a gate signal is applied to turn on the semiconductor element 2. On the other hand, in Fig. 10, a gate signal is applied to turn on the semiconductor element 3. This also reduces the parasitic capacitance C ２ , C ３ is bypassed by the semiconductor element 3 and is not charged. As a result, it is possible to avoid overvoltage breakdown of the semiconductor elements 2 and 3 due to the application of a charging voltage caused by a lightning strike. Note that other configurations and operations in Figure 10 are the same as those in Figure 8, so a description thereof will be omitted.

[0096] Fig. 11 is a diagram showing an equivalent circuit of the charging path shown in Fig. 10. The equivalent circuit shown in Fig. 11 is basically the same as the equivalent circuit shown in Fig. 9.

[0097] That is, as shown in FIG. 11, when the potential of the P pole and the N pole relative to the ground is negatively charged by a lightning strike, the charging voltage due to the lightning strike is V ＬＳ Then, the parasitic capacitance C ＮＣ The voltage is expressed by the formula (3) as in FIG.

[0098]

[0099] In this case, the parasitic capacitance C ２ , C ３ The voltage is expressed by the formula (4) as in FIG.

[0100]

[0101] Therefore, similarly to FIG. 9, according to the formulas (3) and (4), the current is bypassed by keeping the semiconductor element 3 in the ON state, and the parasitic capacitance C ２ , C ３ It turns out that it is not charging.

[0102] As shown in FIGS. 8 to 11, when the power converter 30 is in standby mode (standby state), if a gate signal is applied to turn on one of the semiconductor elements 2 and 3, the parasitic capacitance C ２ , C ３ are bypassed and are not charged. This makes it possible to avoid overvoltage breakdown of the semiconductor elements 2 and 3 due to the application of a charging voltage caused by a lightning strike.

[0103] Here, even if a gate signal that turns on both the semiconductor elements 2 and 3 is applied, the parasitic capacitance C ２ , C ３ By bypassing both of the semiconductor elements 2 and 3, the same effect as described above can be achieved. In other words, when the power converter 30 is in standby mode (standby state), if a gate signal is provided that turns on one or both of the semiconductor elements 2 and 3, it is possible to avoid overvoltage breakdown of the semiconductor elements 2 and 3 due to the application of a charging voltage caused by a lightning strike. In this case, it is sufficient that one or both of the semiconductor elements 2 and 3 are in a conductive state. For example, one or both of the semiconductor elements 2 and 3 may be provided with a gate signal that turns them on continuously, or may be provided with a gate signal that turns them on alternately or irregularly. In other words, it is sufficient that a gate signal that turns at least one of the semiconductor elements 2 and 3 into a conductive state or a switching state is provided.

[0104] 8 to 11, similar to FIGS. 5 and 6, show a case where the P-pole and N-pole are charged to a negative polarity relative to the ground potential by a lightning strike. However, this is not limited to this. As shown in FIG. 7, whether the P-pole and N-pole or the AC side are charged to a positive polarity or a negative polarity by a lightning strike, the same effect as in FIGS. 8 to 11 can be achieved as long as a gate signal that turns on one or both of the semiconductor elements 2 and 3 is applied.

[0105] <Control Example of First Embodiment> Fig. 12 is a flowchart showing a state transition sequence between a power generation mode and a standby mode of the multilevel power conversion system 20 shown in Fig. 1. The flowchart shown in Fig. 12 is started by the control unit 50 (see Fig. 2) of the control device 40, for example, when the power conversion system 20 is started (activated).

[0106] In step S1, the operation control unit 51 of the control unit 50 determines that the AC switch 24 is in the OFF (open) state and transitions the operation mode of the power converter 30 to the standby mode. When the operation control unit 51 transitions the operation mode of the power converter 30 to the standby mode, the operation control unit 51 may output a predetermined standby mode signal and a gate block signal to the gate signal generation unit 53 (see FIGS. 2, 14, etc.). Note that the standby mode is an operation mode in which the AC switch 24 is turned OFF (open) and the power converter 30 does not convert power from the solar cell 11 to the power grid 15, for example, at night or in bad weather. In other words, the standby mode is an operation mode in which power conversion is not performed between the DC input / output unit 31 (see FIGS. 3 and 4) and the AC input / output unit 32 (see FIGS. 3 and 4).

[0107] In conventional power converters, the control device turns off the gate signals of all semiconductor switching elements (providing gate signals that turn all semiconductor switching elements off) when the power converter is in standby mode. Meanwhile, the control unit 50 in the control device 40 disclosed herein provides gate signals that turn on one or both of the anti-series connected neutral point elements 2 and 3, and provides gate signals that turn off the semiconductor elements 1 and 4 other than the neutral point elements 2 and 3, when the power converter is in standby mode. This makes it possible to avoid overvoltage breakdown of the semiconductor elements 1 to 4 due to a lightning surge during standby mode. Details of the control configuration or processing (operation) by the voltage command generation unit 52 and the gate signal generation unit 53 during standby mode will be described later (see FIGS. 13 and 14, etc.).

[0108] In step S2, the operation control unit 51 of the control unit 50 determines whether sunrise has occurred. Specifically, the operation control unit 51 determines whether the DC voltage V detected by the DC voltage sensor 25 has reached the maximum value. ｄｃ is acquired via the acquisition unit 41 (see FIG. 2), and the DC voltage V ｄｃ exceeded 1000V (V ｄｃ Then, the operation control unit 51 determines whether the acquired DC voltage V ｄｃ Whether it is sunrise or not is determined based on whether the voltage exceeds 1000V for two seconds or more.

[0109] The operation control unit 51 controls, for example, a DC voltage V ｄｃ However, if it is determined that the DC voltage V has exceeded 1000V continuously for 2 seconds or more (Yes side), it is determined that sunrise has occurred, and the process proceeds to step S3. ｄｃ However, if it is determined that the voltage does not exceed 1000V for two or more consecutive seconds (No side), it is determined that sunrise has not yet occurred, and the processes of steps S1 and S2 are repeated until it is determined that sunrise has occurred. Note that the values ​​of two seconds, 1000V, etc. are merely examples.

[0110] In step S3, the operation control unit 51 of the control unit 50 outputs an AC switch operation signal to the AC switch 24, for example, via the output unit 42 (see Figure 2), to turn on (close) the AC switch 24.

[0111] In step S4, the operation control unit 51 of the control unit 50 determines that the AC switch 24 is in the ON (closed) state, and transitions the operation mode of the power converter 30 to the power generation mode. When the operation control unit 51 transitions the operation mode of the power converter 30 to the power generation mode, it may output a predetermined standby mode signal and a gate block signal to the gate signal generation unit 53 (see FIGS. 2 , 14 , etc.). Alternatively, when the operation control unit 51 transitions the operation mode of the power converter 30 to the power generation mode, it may output a predetermined operation mode signal (power generation mode signal) to the gate signal generation unit 53. The power generation mode is an operation mode in which power is generated from the solar cell 11, the AC switch 24 is turned ON (closed), and gate signals are applied to the semiconductor elements 1 to 4 of the power converter 30 to switch them, thereby converting the power of the solar cell 11 and transmitting it to the power grid 15. In other words, the power generation mode is an operation mode in which power conversion is performed between the DC input / output unit 31 (see FIGS. 3 and 4) and the AC input / output unit 32 (see FIGS. 3 and 4). Note that the control or processing (operation) by the control unit 50 in the power generation mode is the same as that of a conventional power converter, and therefore a description thereof will be omitted.

[0112] In step S5, the operation control unit 51 of the control unit 50 determines whether or not sunset has occurred. Specifically, the operation control unit 51 determines whether or not the DC voltage V detected by the DC voltage sensor 25 has reached the threshold. ｄｃ is acquired via the acquisition unit 41 (see FIG. 2), and the DC voltage V ｄｃ is less than 900V (V ｄｃ Then, the operation control unit 51 determines whether the obtained DC voltage V ｄｃ Whether sunrise has occurred is determined based on whether the voltage has remained below 900V for 60 seconds or more.

[0113] The operation control unit 51 controls the DC voltage V ｄｃHowever, if it is determined that the DC voltage V has been lower than 900 V for 60 seconds or more (Yes side), it is determined that sunset has occurred, and the process proceeds to step S6. ｄｃ However, if it is determined that the voltage has not been less than 900V for 60 seconds or more (No), it is determined that sunset has not occurred, and the processes of steps S4 and S5 are repeated until it is determined that sunset has occurred. Note that the values ​​such as 60 seconds and 900V are merely examples.

[0114] In step S6, the operation control unit 51 of the control unit 50 outputs an AC switch operation signal to the AC switch 24, for example, via the output unit 42 (see Figure 2), to turn off (open) the AC switch 24.

[0115] In step S7, the control unit 50 determines whether or not the operation of the power conversion system 20 has been completed. The operation of the power conversion system 20 may be completed, for example, in the event of maintenance or a malfunction of the power conversion system 20, or when instructions are received from a higher-level device (not shown) or an operator. When the control unit 50 determines that the operation of the power conversion system 20 has been completed (Yes side), the control unit 50 terminates the processing of this flowchart. On the other hand, when the control unit 50 determines that the operation of the power conversion system 20 has not been completed (No side), the control unit 50 returns the processing to step S1 and repeats the processing of steps S1 to S7.

[0116] Fig. 13 is a diagram showing an example of a control configuration in voltage command generating unit 52 of control unit 50 shown in Fig. 2. Fig. 13 shows examples of control configurations for three phases, namely, U phase, V phase, and W phase, but in the following explanation, control common to each phase will be explained using control of the U phase as an example.

[0117] In step S11, the voltage command generator 52 generates a predetermined output power command value P ＿ｒｅｆ and obtain the output power command value P ＿ｒｅｆ Based on this, the U-phase current command value I ｕ＿ｒｅｆ The predetermined output power command value P ＿ｒｅｆ is obtained based on, for example, a predetermined power demand or a predetermined calculation result, or is obtained from the storage unit 43 or a higher-level device (not shown).

[0118] In step S12, the voltage command generator 52 calculates the U-phase current command value I ｕ＿ｒｅｆ Furthermore, the voltage command generator 52 acquires the U-phase AC current I detected by the AC current sensor (see FIG. 1). ｕ (U-phase current measurement value I ｕ ) via the acquisition unit 41 (see FIG. 2 ). Then, the voltage command generation unit 52 calculates the U-phase current command value I ｕ＿ｒｅｆ The U-phase current measurement value I ｕ Subtracts and outputs the subtracted value.

[0119] In step S13, the voltage command generator 52 performs proportional control based on the value output in the process of step S12 and the proportional control gain Kp, and generates a U-phase voltage command value V ｕ＿ｒｅｆ to the gate signal generating unit 53 (see FIGS. 2 and 14).

[0120] In steps S11 to S13, the voltage command generator 52 generates the V-phase voltage command value V ｖ＿ｒｅｆ and the V-phase voltage command value V ｗ＿ｒｅｆ and the V-phase voltage command value V ｖ＿ｒｅｆ and the V-phase voltage command value V ｗ＿ｒｅｆ and are output to the gate signal generating unit 53.

[0121] The process performed by voltage command generating unit 52 described with reference to FIG. 13 is similar to the process generally performed in the control of a normal power converter.

[0122] Fig. 14 is a diagram showing an example of the control configuration in the gate signal generating unit 53 of the control unit 50 shown in Fig. 2. Fig. 14 shows examples of the control configuration for each of the three phases, U phase, V phase, and W phase, but in the following explanation, the control common to each phase will be explained using the control of the U phase as an example.

[0123] In step S21, the gate signal generator 53 receives the U-phase voltage command value V ｕ＿ｒｅｆ The gate signal generator 53 also acquires the DC voltage V (x) detected by the DC voltage sensor 25. ｄｃThe gate signal generating unit 53 divides the acquired value (x) by the acquired value (y) (x / y) to obtain the U-phase modulated wave D ｕ and the U-phase modulated wave D ｕ The modulated wave D is a voltage command value normalized by half the DC voltage, and the voltage command value V ＿ｒｅｆ DC voltage V ｄｃ is obtained by dividing the result by half after applying a low-pass filter to the

[0124] In step S22a, the gate signal generating unit 53 converts the U-phase modulated wave D output in the process of step S21 into ｕ The comparator compares the triangular wave carrier CA1 generated by the carrier generator with the U-phase modulating wave D. ｕ is larger than the triangular wave carrier CA1, a signal of 1 is output, and the U-phase modulating wave D ｕ is smaller, it outputs a signal of 0. The triangular wave carrier CA1 is a triangular wave signal that changes between 0 and 1 in a fixed carrier period.

[0125] In step S22b, the gate signal generating unit 53 converts the U-phase modulated wave D output in the process of step S21 into ｕ The comparator compares the triangular wave carrier CA2 generated by the carrier generator with the U-phase modulating wave D. Then, the gate signal generating unit 53 determines whether the U-phase modulating wave D is greater than the triangular wave carrier CA2. ｕ is larger than the triangular wave carrier CA2, a signal of 1 is output, and the U-phase modulating wave D ｕ is smaller, it outputs a signal of 0. The triangular wave carrier CA2 is a triangular wave signal that changes between -1 and 0 in a fixed carrier period.

[0126] In step S23a, the gate signal generating unit 53 outputs a signal obtained by delaying the value of the signal output in the process of step S22a using a dead time generator. The dead time generator is for preventing short circuits due to simultaneous conduction of semiconductor switching elements, and outputs a signal by delaying the rise time of the pulse command value.

[0127] In step S23b, the gate signal generating unit 53 outputs a signal obtained by delaying the negative logic (NOT) value of the signal output in the processing of step S22a using a dead time generator. That is, the gate signal generating unit 53 delays and outputs 1 when the signal output in step S22a is 0, and 0 when the signal is 1 using the dead time generator.

[0128] In step S23c, the gate signal generating unit 53 outputs a signal obtained by delaying the signal output in the process of step S22b using a dead time generator.

[0129] In step S23d, the gate signal generating unit 53 outputs a signal obtained by delaying the negative logic (NOT) value of the signal output in the processing of step S22b using a dead time generator. That is, the gate signal generating unit 53 delays and outputs 1 when the signal output in step S22b is 0, and 0 when the signal is 1 using the dead time generator.

[0130] In step S24a, the gate signal generation unit 53 outputs the logical product (AND) of the value of the signal output in step S23a and the negative logic (NOT) value of the standby mode signal. That is, the gate signal generation unit 53 inputs the value of the signal output in step S23a and the negative logic value of the standby mode signal to an AND circuit. In this case, when the standby mode signal is 1, the negative logic of the standby mode signal is 0, so the AND circuit outputs 0 regardless of the value output from the dead time generator. On the other hand, when the standby mode signal is 0, the negative logic of the standby mode signal is 1, so the AND circuit outputs the same value as the value output from the dead time generator. The standby mode signal is acquired, for example, from the operation control unit 51.

[0131] In step S24b, the gate signal generation unit 53 outputs the logical sum (OR) of the value of the signal output in the processing of step S23b and the value of the standby mode signal. That is, the gate signal generation unit 53 inputs the value of the signal output in the processing of step S23b and the value of the standby mode signal to an OR circuit. Then, when at least one of the value of the standby mode signal and the value output from the dead time generator is 1, the OR circuit outputs 1. In this case, when the standby mode signal is 1, the OR circuit outputs 1 regardless of the value output from the dead time generator. On the other hand, when the standby mode signal is 0, the OR circuit outputs the same value as the value output from the dead time generator.

[0132] In step S24c, the gate signal generation unit 53 outputs the logical sum (OR) of the value of the signal output in the processing of step S23c and the value of the standby mode signal. That is, the gate signal generation unit 53 inputs the value of the signal output in the processing of step S23c and the value of the standby mode signal to an OR circuit. Then, when at least one of the value of the standby mode signal and the value output from the dead time generator is 1, the OR circuit outputs 1. In this case, when the standby mode signal is 1, the OR circuit outputs 1 regardless of the value output from the dead time generator. On the other hand, when the standby mode signal is 0, the OR circuit outputs the same value as the value output from the dead time generator.

[0133] In step S24d, the gate signal generation unit 53 outputs the logical product (AND) of the value of the signal output in the processing of step S23d and the negative logic (NOT) value of the standby mode signal. That is, the gate signal generation unit 53 inputs the value of the signal output in the processing of step S23d and the negative logic value of the standby mode signal to an AND circuit. In this case, when the standby mode signal is 1, the negative logic of the standby mode signal is 0, so the AND circuit outputs 0 regardless of the value output from the dead time generator. On the other hand, when the standby mode signal is 0, the negative logic of the standby mode signal is 1, so the AND circuit outputs the same value as the value output from the dead time generator.

[0134] In step S25a, the gate signal generation unit 53 outputs the gate signal gu1 based on the logical product (AND) of the value of the signal output in the process of step S24a and the negative logic (NOT) value of the gate block signal. That is, the gate signal generation unit 53 inputs the value of the signal output in the process of step S24a and the negative logic value of the gate block signal to an AND circuit. When the gate block signal is 1, the negative logic of the gate block signal is 0, and therefore the AND circuit outputs 0 as the gate signal gu1, regardless of the value of the signal output in the process of step S24a. On the other hand, when the gate block signal is 0, the negative logic of the gate block signal is 1, and therefore the AND circuit outputs the same value as the signal output in the process of step S24a. The gate signal gu1 is a gate signal that controls the switching operation of the semiconductor element 1 (see FIGS. 3 to 11, etc.). The gate block signal is acquired, for example, from the operation control unit 51.

[0135] In step S25b, the gate signal generation unit 53 outputs a gate signal gu3 based on the logical product (AND) of the value of the signal output in the processing of step S24b and the negative logic (NOT) value of the gate block signal. That is, the gate signal generation unit 53 inputs the value of the signal output in the processing of step S24b and the negative logic value of the gate block signal to an AND circuit. When the gate block signal is 1, the negative logic of the gate block signal is 0, and therefore the AND circuit outputs 0 as the gate signal gu3, regardless of the value of the signal output in the processing of step S24b. On the other hand, when the gate block signal is 0, the negative logic of the gate block signal is 1, and therefore the AND circuit outputs the same value as the value of the signal output in the processing of step S24b. The gate signal gu3 is a gate signal that controls the switching operation of the semiconductor element (neutral point element) 3 (see Figures 3 to 11, etc.). The gate block signal is acquired, for example, from the operation control unit 51.

[0136] In step S25c, the gate signal generation unit 53 outputs a gate signal gu2 based on the logical product (AND) of the value of the signal output in the process of step S24c and the negative logic (NOT) value of the gate block signal. That is, the gate signal generation unit 53 inputs the value of the signal output in the process of step S24c and the negative logic value of the gate block signal to an AND circuit. When the gate block signal is 1, the negative logic of the gate block signal is 0, and therefore the AND circuit outputs 0 as the gate signal gu2 regardless of the value of the signal output in step S24c. On the other hand, when the gate block signal is 0, the negative logic of the gate block signal is 1, and therefore the AND circuit outputs the same value as the signal output in the process of step S24c. The gate signal gu2 is a gate signal that controls the switching operation of the semiconductor element (neutral point element) 2 (see Figures 3 to 11, etc.). The gate block signal is acquired, for example, from the operation control unit 51.

[0137] In step S25d, the gate signal generation unit 53 outputs a gate signal gu4 based on the logical product (AND) of the value of the signal output in the process of step S24d and the negative logic (NOT) value of the gate block signal. That is, the gate signal generation unit 53 inputs the value of the signal output in the process of step S24d and the negative logic value of the gate block signal to an AND circuit. When the gate block signal is 1, the negative logic of the gate block signal is 0, and therefore the AND circuit outputs 0 as the gate signal gu4 regardless of the value of the signal output in step S24d. On the other hand, when the gate block signal is 0, the negative logic of the gate block signal is 1, and therefore the AND circuit outputs the same value as the value of the signal output in the process of step S24d. The gate signal gu4 is a gate signal that controls the switching operation of the semiconductor element 4 (see Figures 3 to 11, etc.). The gate block signal is acquired, for example, from the operation control unit 51.

[0138] In addition, the gate signal generating unit 53 performs the processing shown in steps S21 to S25d for the V phase and W phase, as with the U phase, and outputs gate signals gv1 to gv4 and gate signals gw1 to gw4 that control the operation of semiconductor elements 1 to 4.

[0139] The processing contents of the gate signal generating unit 53 described above with reference to FIG. 14 also include the contents that are generally performed in the control of a normal three-level power converter. For example, ＿ｒｅｆ The control of comparing the normalized modulated wave D with two carriers, the triangular wave carrier CA1 and the triangular wave carrier CA2, and then inputting the result into a dead time generator and outputting the gate signal g is commonly performed. On the other hand, the processing of the gate signal generator 53 shown in Fig. 14 in this embodiment has the following features.

[0140] That is, in the control configuration shown in Fig. 14, a standby mode signal is used as a countermeasure against lightning surges. In the control configuration shown in Fig. 14, for example, when AC switch 24 is open and there is no need to output power to AC power grid 15 (when power conversion is not performed) (standby mode), the standby mode signal is set to 1.

[0141] In general control of the power converter 30, when the AC switch 24 is open and there is no need to output power to the AC power grid 15, the gate block signal is set to 1 and a gate signal is output to turn all gates off. On the other hand, in the control configuration shown in Fig. 14 of this embodiment, for example, when the AC switch 24 is open and there is no need to output power to the AC power grid 15 (when power conversion is not being performed) (standby mode), the gate block signal is set to 0.

[0142] As a result, when the power converter 30 in this embodiment is in standby mode, the standby mode signal becomes 1 and the gate block signal becomes 0. Therefore, for example, in the U phase, the AND circuits in steps S25a and S25d output 0 as the gate signals gu1 and gu4. On the other hand, the AND circuits in steps S25b and S25c output 1 as the gate signals gu3 and gu2.

[0143] In other words, when the standby mode signal is 1, the AND circuits in steps S24a and S24d output 0 regardless of what signal is received on the other side, and therefore the AND circuits in steps S25a and S25d also output 0 as gate signals gu1 and gu4. On the other hand, when the standby mode signal is 1, the OR circuits in steps S24b and S24c output 1 regardless of what signal is received on the other side, and therefore the AND circuits in steps S25b and S25c also output 1 as gate signals gu3 and gu2.

[0144] As a result, when the power converter 30 is in standby mode, the standby mode signal is 1, so that the semiconductor elements 1 and 4 of each phase are always turned off and the semiconductor elements (neutral elements) 2 and 3 of each phase are always turned on. When the standby mode signal is 0 (power generation mode), the gate block signal is also 0, and the same value as the value output from the dead time generator is output as the gate signals gu1, gu3, gu2, and gu4, respectively.

[0145] 1 to 14 , when the power converter 30 is in standby mode, a gate signal is provided to turn on the semiconductor elements (neutral elements) 2 and 3 of each phase. Therefore, according to this embodiment, when the power converter 30 is in standby mode, even if the ground potential of the P pole and the N pole is charged by a lightning strike, one or both of the neutral elements 2 and 3 are turned on. As a result, according to this embodiment, in the multilevel power conversion system 20, the semiconductor elements 1 to 4 of the power converter 30 are prevented from being destroyed by an overvoltage caused by a lightning surge, and the neutral elements 2 and 3 can be protected from being destroyed by an overvoltage caused by a lightning surge.

[0146] <Modification of First Embodiment> Fig. 15 is a diagram showing an example of a control configuration in a gate signal generating unit 53' of a control unit 50 according to a modification of the first embodiment. In the modification of the first embodiment shown in Fig. 15, the same or similar configurations or processes as those in the first embodiment shown in Figs. 1 to 14 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted or simplified.

[0147] In the modification of the first embodiment, except for the control configuration of the gate signal generating unit 53' shown in Fig. 15, the other configurations and controls are the same as or similar to those of the first embodiment shown in Figs. 1 to 14. In the control shown in Fig. 15, the same or similar processes as those of steps S21 to S22b shown in Fig. 14 are performed, and the processes of steps S26a to S28d are performed instead of the processes of steps S23a to S25d. In the following explanation, as in the explanation of Fig. 14, the control common to each phase will be explained using the control of the U phase as an example.

[0148] The processing in steps S21 to S22b is the same as or similar to the processing shown in FIG. 14, and therefore a description thereof will be omitted.

[0149] In step S26a, the gate signal generating unit 53' outputs the logical product (AND) of the value of the signal output in step S22a and the negative logic (NOT) value of the standby mode signal.

[0150] In step S26b, the gate signal generating unit 53' outputs the logical sum (OR) of the value of the signal output in the process of step S22b and the value of the standby mode signal.

[0151] In step S27a, the gate signal generating unit 53' outputs a signal obtained by delaying the value of the signal output in the process of step S26a using a dead time generator.

[0152] In step S27b, the gate signal generating unit 53' outputs a signal obtained by delaying the negative logic (NOT) value of the signal output in the process of step S26a using a dead time generator.

[0153] In step S27c, the gate signal generating unit 53' outputs a signal obtained by delaying the signal output in the process of step S26b using a dead time generator.

[0154] In step S27d, the gate signal generating unit 53' outputs a signal obtained by delaying the negative logic (NOT) value of the signal output in the processing of step S26b using a dead time generator.

[0155] In steps S28a to S28d, the gate signal generation unit 53′ acquires the values ​​of the signals output in the processing of steps S27a to S27d and the negative logic (NOT) value of the gate block signal, and outputs gate signals gu1, gu3, gu2, and gu4 based on the logical product (AND) of the acquired values ​​of the signals output in the processing of steps S27a to S27d and the negative logic (NOT) value of the gate block signal.

[0156] In addition, the gate signal generating unit 53' performs the processing shown in steps S21 to S22b and S26a to S28d for the V phase and W phase, respectively, in the same manner as for the U phase, and outputs gate signals gv1 to gv4 and gate signals gw1 to gw4 that control the operation of semiconductor elements 1 to 4.

[0157] As described above, in the process of the modified example of the first embodiment shown in Fig. 15, when the power converter 30 is in standby mode, the standby mode signal is 1 and the gate block signal is 0, similar to the process of the first embodiment shown in Fig. 14. Therefore, for example, in the U phase, the AND circuits in steps S28a and S28d output 0 as the gate signals gu1 and gu4. On the other hand, the AND circuits in steps S28b and S28c output 1 as the gate signals gu3 and gu2.

[0158] 14, when the power converter 30 is in standby mode, the standby mode signal is 1, so that the semiconductor elements 1 and 4 of each phase are always turned off and the semiconductor elements (neutral elements) 2 and 3 of each phase are always turned on. When the standby mode signal is 0 (power generation mode), the gate block signal is also 0, and the same values ​​as those output from the dead time generator are output from the AND circuits in steps S28a to S28d as the gate signals gu1, gu3, gu2, and gu4, respectively.

[0159] <Operational Effects of the Modification of the First Embodiment> As described above, the modification of the first embodiment shown in Fig. 15 provides the same operational effects as the first embodiment shown in Fig. 1 to Fig. 14. Therefore, this embodiment also prevents the semiconductor elements 1 to 4 of the power converter 30 in the multilevel power conversion system 20 from being destroyed by an overvoltage caused by a lightning surge, and protects the neutral elements 2 and 3 from being destroyed by an overvoltage caused by a lightning surge.

[0160] Second Embodiment Fig. 16 is a diagram showing an example of a control configuration in a gate signal generating unit 53A of a control unit 50A according to a second embodiment. In the second embodiment shown in Fig. 16, the same or similar configurations or processes as those in the first embodiment and the modified example of the first embodiment shown in Figs. 1 to 15 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted or simplified.

[0161] In the second embodiment, except for the control configuration of the gate signal generating unit 53A of the control unit 50A shown in Fig. 16, the other configurations and controls are the same as or similar to those of the first embodiment shown in Figs. 1 to 14. That is, although not shown, the second embodiment and the third embodiment have a control unit 50A instead of the control unit 50 in the first embodiment shown in Fig. 2. The control unit 50A has a gate signal generating unit 53A instead of the gate signal generating unit 53 of the control unit 50 in the first embodiment shown in Fig. 2. In the following explanation, as with the explanation of Fig. 14, the control common to each phase will be explained using the control of the U phase as an example.

[0162] In the second embodiment, when in standby mode, the control unit 50A outputs to the power converter 30 a gate signal generated based on a voltage command value such that a voltage approximately equal to the DC neutral point C (a voltage that can be considered to be equal) is output to the AC side (AC input / output unit 32 (see FIGS. 3 and 4 )). Note that a voltage approximately equal to the DC neutral point C can be realized by providing a voltage command of 0 (zero) in an output voltage control method that is generally used in three-level power converters.

[0163] In step S31, the gate signal generator 53A calculates the U-phase voltage command value V ｕ＿ｒｅｆThe selector acquires a U-phase voltage command value of 0 (zero) and a standby mode signal. The gate signal generator 53A then selects a U-phase voltage command value V ｕ＿ｒｅｆ and a U-phase voltage command value of 0 (zero) are selected by a selector, and the selected voltage command value is output.

[0164] That is, as shown in step S31 of FIG. 16, when the standby mode signal acquired by the selector is 0, the gate signal generating unit 53A selects the U-phase voltage command value V ｕ＿ｒｅｆ is selected, the U-phase voltage command value V ｕ＿ｒｅｆ On the other hand, when the standby mode signal acquired by the selector is 1, the selector selects a U-phase voltage command value of 0 (zero), and therefore gate signal generation unit 53A outputs a U-phase voltage command value of 0 (zero). Therefore, when power converter 30 is in the standby mode, the standby mode signal is 1, and therefore the selector always selects a voltage command value of 0 (zero), and the selector always outputs a voltage command value of 0 (zero). The selector (multiplexer) is a circuit that selects and outputs one signal (voltage command value) from a plurality of input signals (voltage command values) in accordance with the value of the control signal (standby mode signal).

[0165] In step S32, the gate signal generating unit 53A selects the U-phase voltage command value V ｕ＿ｒｅｆ The gate signal generator 53A also acquires a voltage command value (x) of 0 (zero). ｄｃ The gate signal generating unit 53 then divides the acquired value (x) by the acquired value (y) (x / y) to obtain the U-phase modulated wave D ｕ and the U-phase modulated wave D ｕ Here, when the value (x) output from the selector in the process of step S31 is a voltage command value of 0 (zero), the obtained value (x / y) is also always 0. In this case, in the process of step S32, the U-phase modulated wave D ｕ0 is always output.

[0166] In step S33a, the gate signal generating unit 53A converts the U-phase modulated wave D ｕ The comparator compares the triangular wave carrier CA1 generated by the carrier generator with the U-phase modulating wave D. ｕ is larger than the triangular wave carrier CA1, a signal of 1 is output, and the U-phase modulating wave D ｕ is smaller, a signal of 0 is output.

[0167] Here, when the power converter 30 is in the standby mode and the standby mode signal is 1, the value (x) output from the selector in the process of step S31 is always a voltage command value of 0 (zero), and the U-phase modulated wave D output in the process of step S32 ｕ As described above, the triangular wave carrier CA1 is a triangular wave signal that changes between 0 and 1 in a fixed carrier period, so the value of the U-phase modulating wave D ｕ When the value of is 0, the U-phase modulating wave D is always higher than the triangular wave carrier CA1. ｕ Therefore, when the power converter 30 is in the standby mode and the standby mode signal is 1, the U-phase modulating wave D is always smaller than the triangular wave carrier CA1. ｕ is smaller, in this case, a signal of 0 is always output from the comparator in the process of step S33a.

[0168] In step S33b, the gate signal generating unit 53A converts the U-phase modulated wave D output in the process of step S32 into ｕ The comparator compares the triangular wave carrier CA2 generated by the carrier generator with the U-phase modulating wave D. Then, the gate signal generating unit 53 determines whether the U-phase modulating wave D is greater than the triangular wave carrier CA2. ｕ is larger than the triangular wave carrier CA2, a signal of 1 is output, and the U-phase modulating wave D ｕ is smaller, a signal of 0 is output.

[0169] Here, when the power converter 30 is in the standby mode and the standby mode signal is 1, as described above, the U-phase modulated wave Dｕ As described above, the triangular wave carrier CA2 is a triangular wave signal that changes between -1 and 0 in a fixed carrier period, so the value of the U-phase modulating wave D ｕ When the value of is 0, the U-phase modulating wave D is always higher than the triangular wave carrier CA1. ｕ Therefore, when the power converter 30 is in the standby mode and the standby mode signal is 1, the U-phase modulating wave D is always larger than the triangular wave carrier CA2. ｕ is larger, in this case, a signal of 1 is always output from the comparator in the process of step S33b.

[0170] The processing in steps S34a to S35d is the same as or similar to the processing in steps S27a to S28d shown in FIG. 15, and therefore a description thereof will be omitted.

[0171] As described above, in the process of the second embodiment shown in Fig. 16, similarly to the processes of the first embodiment and its modified example shown in Figs. 14 and 15, when the power converter 30 is in standby mode, the standby mode signal is 1 and the gate block signal is 0. Therefore, for example, in the U phase, the AND circuits in steps S35a and S35d output 0 as the gate signals gu1 and gu4. On the other hand, the AND circuits in steps S35b and S35c output 1 as the gate signals gu3 and gu2.

[0172] 14 and 15, when the power converter 30 is in standby mode, the standby mode signal is 1, so that the semiconductor elements 1 and 4 of each phase are always turned off and the semiconductor elements (neutral elements) 2 and 3 of each phase are always turned on. When the standby mode signal is 0 (power generation mode), the gate block signal is also 0, and the same values ​​as those output from the dead time generator are output from the AND circuits in steps S35a to S35d as the gate signals gu1, gu3, gu2, and gu4, respectively.

[0173] <Operations and Effects of Second Embodiment> As described above, the second embodiment shown in FIG. 16 provides the same operations and effects as the first embodiment and its modified example shown in FIGS.

[0174] 16, when the power converter 30 is in standby mode, a voltage command of 0 (zero) is given, and gate signals gu3 and gu2 are output that are generated based on a voltage command value that outputs to the AC side a voltage approximately equal to that of the DC neutral point C. This also prevents the semiconductor elements 1 to 4 of the power converter 30 from being destroyed by an overvoltage caused by a lightning surge, and protects the neutral point elements 2 and 3 from being destroyed by an overvoltage caused by a lightning surge.

[0175] 17 is a diagram showing an example of a control configuration of a voltage command generating unit 52B of a control unit 50B according to a third embodiment. In the third embodiment shown in FIG. 17 and FIG. 18 described later, the same reference numerals are used to designate the same or similar configurations or processes as those in the first and second embodiments shown in FIGS. 1 to 16, and detailed descriptions thereof will be omitted or simplified.

[0176] In the third embodiment, except for the control configuration of the voltage command generating unit 52B of the control unit 50B shown in FIG. 17 and the gate signal generating unit 53B of the control unit 50B shown in FIG. 18 (described later), the other configurations and controls are the same as or similar to those of the first embodiment shown in FIGS. 1 to 14. That is, although not shown, the third embodiment has a control unit 50B instead of the control unit 50 in the first embodiment shown in FIG. 2. The control unit 50B has a voltage command generating unit 52B instead of the voltage command generating unit 52 of the control unit 50 in the first embodiment shown in FIG. 2, and a gate signal generating unit 53B instead of the gate signal generating unit 53. In the following explanation, as with the explanation of FIG. 13, control common to each phase will be explained using the control of the U phase as an example.

[0177] In step S41, the voltage command generating unit 52B calculates a predetermined output power command value P ＿ｒｅｆ and obtain the output power command value P ＿ｒｅｆ Based on this, the U-phase current command value I ｕ＿ｒｅｆ Output.

[0178] In step S42, the voltage command generating unit 52B calculates the U-phase current command value I ｕ＿ｒｅｆThe selector acquires a U-phase current command value of 0 (zero) and a standby mode signal. The voltage command generator 52B then selects a U-phase current command value I ｕ＿ｒｅｆ and a U-phase current command value of 0 (zero) are selected by a selector, and the selected current command value is output.

[0179] That is, as shown in step S42 of FIG. 17, when the standby mode signal acquired by the selector is 0, the voltage command generating unit 52B selects the U-phase current command value I ｕ＿ｒｅｆ is selected, the U-phase current command value I ｕ＿ｒｅｆ On the other hand, when the standby mode signal acquired by the selector is 1, the selector selects a U-phase current command value of 0 (zero), and therefore voltage command generation unit 52B outputs a U-phase current command value of 0 (zero). Therefore, when power converter 30 is in the standby mode, the standby mode signal is 1, and therefore the selector always selects a current command value of 0 (zero), and the selector always outputs a current command value of 0 (zero).

[0180] In step S43, the voltage command generating unit 52B calculates the U-phase current command value I ｕ＿ｒｅｆ The voltage command generator 52B obtains a U-phase current command value of 0 (zero) or 1 (zero). ｕ (U-phase current measurement value I ｕ ) via the acquisition unit 41 (see FIG. 2 ). Then, the voltage command generation unit 52B acquires the acquired U-phase current command value I ｕ＿ｒｅｆ or 0 (zero) from the U-phase current command value, the acquired U-phase current measurement value I ｕ Subtracts and outputs the subtracted value.

[0181] In step S44, the voltage command generating unit 52B performs proportional control based on the value output in the process of step S43 and the proportional control gain Kp, and generates a U-phase voltage command value V ｕ＿ｒｅｆ to the gate signal generating unit 53B (see FIG. 18).

[0182] In steps S41 to S44, the voltage command generating unit 52B generates the V-phase voltage command value V ｖ＿ｒｅｆ and the V-phase voltage command value V ｗ＿ｒｅｆ and the V-phase voltage command value V ｖ＿ｒｅｆ and the V-phase voltage command value V ｗ＿ｒｅｆ and is output to the gate signal generating unit 53B.

[0183] 18 is a diagram showing an example of a control configuration in a gate signal generating unit 53B of a control unit 50B according to the third embodiment. In the following explanation, as in the explanation of FIG. 14, the control common to each phase will be explained using the control of the U phase as an example.

[0184] The processing of steps S51 to S53d is the same as or similar to the processing of steps S21 to S23d shown in FIG. 14, and therefore a description thereof will be omitted.

[0185] In steps S54a to S54d, the gate signal generation unit 53B acquires the values ​​of the signals output in the processing of steps S53a to S53d and the negative logic (NOT) value of the gate block signal, and outputs gate signals gu1, gu3, gu2, and gu4 based on the logical product (AND) of the acquired values ​​of the signals output in the processing of steps S53a to S53d and the negative logic (NOT) value of the gate block signal.

[0186] In addition, the gate signal generating unit 53 performs the processing shown in steps S51 to S55d for the V phase and W phase, as with the U phase, and outputs gate signals gv1 to gv4 and gate signals gw1 to gw4 that control the operation of semiconductor elements 1 to 4.

[0187] The processing performed by the gate signal generating unit 53B shown in FIG. 18 is similar to the processing generally performed in the control of a normal power converter, except that the gate block signal is 0 even in the standby mode.

[0188] As described above, in the processes shown in FIGS. 17 and 18 , when in standby mode, gate signals generated based on voltage command values ​​that cause the output current of each phase of the AC side (AC input / output unit 32 (see FIGS. 3 and 4 )) of the power converter 30 to be approximately zero (or deemed to be zero) are output to the power converter 30. Note that voltage command values ​​that cause the output current of each phase of the AC side of the power converter 30 to be approximately zero can be achieved by providing a voltage command of 0 (zero) in an output current control method that is commonly used in three-level power converters. That is, to make the current zero when the AC switch 24 is in the off (open) state, the voltage can be set to zero. In other words, to maintain the current at zero, the voltage command value itself is set to approximately 0, and the voltage is set to zero.

[0189] In the process shown in FIG. 17, when the standby mode signal is 1, the U-phase current command value output in the process of step S42 is 0 (zero), and as a result, the U-phase current measurement value I ｕ As a result, the voltage command value V output in the process of step S44 also settles to approximately 0. ｕ＿ｒｅｆ The value of also settles to approximately 0. As a result, when in the standby mode, the gate signal generation unit 53B shown in Fig. 18 outputs to the power converter 30 a gate signal that is generated based on a voltage command value that makes the output current of each phase on the AC side of the power converter 30 approximately 0.

[0190] As described above, in the processing of the third embodiment shown in FIGS. 17 and 18, similarly to the processing of the first and second embodiments shown in FIGS. 13 to 16, when the power converter 30 is in standby mode, the standby mode signal is 1 and the gate block signal is 0. Therefore, for example, in the U phase, the AND circuits in steps S54a and S54d output 0 as gate signals gu1 and gu4. On the other hand, the AND circuits in steps S54b and S54c output 1 as gate signals gu3 and gu2. Note that when the standby mode signal is 0 (power generation mode), the gate block signal is also 0, and the same values ​​as those output from the dead time generator are output as gate signals gu1, gu3, gu2, and gu4 from the AND circuits in steps S54a to S54d, respectively.

[0191] <Operational Effects of the Third Embodiment> As described above, the third embodiment shown in Figures 17 and 18 provides the same operational effects as the first and second embodiments shown in Figures 1 to 16. That is, according to the third embodiment shown in Figures 17 and 18, in the standby mode, a voltage command of 0 (zero) is given, and gate signals gu3, gu2 are output that are generated based on voltage command values ​​that make the output current of each phase on the AC side of power converter 30 zero. This also prevents semiconductor elements 1 to 4 of power converter 30 from being destroyed by an overvoltage caused by a lightning surge, and can protect neutral elements 2 and 3 from being destroyed by an overvoltage caused by a lightning surge.

[0192] 16, the voltage command value itself is directly set to 0, and gate signals gu3 and gu2 are output that are generated based on a voltage command value such that a voltage equal to that of the DC neutral point C is output to the AC side. On the other hand, in the third embodiment shown in FIGS. 17 and 18, the voltage command value itself is not directly manipulated, and the current command value is set to 0, thereby effectively setting the voltage command value to 0 and achieving the same effect as the second embodiment shown in FIG.

[0193] <Fourth embodiment> Fig. 19 is a diagram showing an example of a control configuration in a voltage command generating unit 52C of a control unit 50C according to a fourth embodiment. In the fourth embodiment shown in Fig. 19 and Fig. 20 described later, the same reference numerals are used to designate the same or similar configurations or processes as those in the first to third embodiments shown in Figs. 1 to 18, and detailed descriptions thereof will be omitted or simplified.

[0194] In the fourth embodiment, except for the control configuration of the voltage command generating unit 52C of the control unit 50C shown in FIG. 19 and the gate signal generating unit 53C of the control unit 50C shown in FIG. 20 (described later), the other configurations and controls are the same as or similar to those of the first embodiment shown in FIGS. 1 to 14. That is, although not shown, the fourth embodiment has a control unit 50C instead of the control unit 50 in the first embodiment shown in FIG. 2. The control unit 50C has a voltage command generating unit 52C instead of the voltage command generating unit 52 of the control unit 50 in the first embodiment shown in FIG. 2, and a gate signal generating unit 53C instead of the gate signal generating unit 53. In the following explanation, as with the explanation of FIG. 13, control common to each phase will be explained using the control of the U phase as an example.

[0195] The processing of steps S61 to S63 is the same as or similar to the processing of steps S11 to S13 shown in Fig. 13, and therefore description thereof will be omitted. That is, the processing performed by voltage command generating unit 52C shown in Fig. 19 is similar to the processing generally performed in the control of a normal power converter, as is the processing performed by voltage command generating unit 52 described in Fig. 13.

[0196] 20 is a diagram showing an example of a control configuration in a gate signal generating unit 53C of a control unit 50C according to the fourth embodiment. In the following description, as with the description of FIG. 14, control common to each phase will be described using control of the U phase as an example.

[0197] The processing of steps S71 to S74d is the same as or similar to the processing of steps S51 to S54d shown in Fig. 18, and therefore description thereof will be omitted. That is, the processing performed by gate signal generating unit 53C shown in Fig. 20 is similar to the processing generally performed in the control of a normal power converter, except that the gate block signal is 0 even in the standby mode, similar to the processing performed by gate signal generating unit 53B described in Fig. 18.

[0198] As described above, the process of the fourth embodiment shown in Figures 19 and 20 uses a general control method. However, normally, when the power converter does not need to be operated, the control device stops all gate signals when the AC switch 24 is open or in standby mode. On the other hand, in the process of the fourth embodiment shown in Figures 19 and 20, the control device 40 outputs gate signals generated based on an arbitrary voltage command value or an arbitrary current command value to the power converter 30, just as in the operating state, even when the AC switch 24 is open or in standby mode (standby state).

[0199] <Operational Effects of Fourth Embodiment> As described above, the fourth embodiment shown in Figures 19 and 20 has the same operational effects as the first to third embodiments shown in Figures 1 to 18. That is, the fourth embodiment shown in Figures 19 and 20 also prevents the semiconductor elements 1 to 4 of the power converter 30 from being destroyed by an overvoltage caused by a lightning surge, and can protect the neutral elements 2 and 3 from being destroyed by an overvoltage caused by a lightning surge.

[0200] That is, in a general control method, even when the AC switch 24 is open or in standby mode (standby state), if the power converter 30 is driven in accordance with some voltage command value (current command value), one or both of the neutral point elements 2 and 3 will be turned on. For this reason, in the fourth embodiment shown in Figures 19 and 20, even when the AC switch 24 is open or in standby mode (standby state), the power converter 30 is driven in the same way as in the operating state. As a result, the fourth embodiment shown in Figures 19 and 20 can also achieve the same effects as the first to third embodiments shown in Figures 1 to 18.

[0201] 19 and 20, when the AC switch 24 is in an open standby state and a gate signal is output to the power converter 30, this is a state in which so-called voltage matching operation is being performed. In this case, the neutral point elements 2 and 3 are repeatedly turned on and off, resulting in more power consumption for driving the gate than when the neutral point elements 2 and 3 are not turned on and off. Furthermore, if an AC capacitor 23 (see FIG. 1) is present on the AC side, excess current flows through the AC capacitor, shortening the life of the AC capacitor 23 compared to when no current flows through it.

[0202] On the other hand, according to the second and third embodiments shown in FIGS. 16 to 18 , a voltage command value of 0 (zero) or close to 0 (zero) is output. Therefore, depending on the control method, the neutral point elements 2 and 3 are always on, and the other semiconductor elements 1 and 4 are always off. In this case, because the neutral point elements 2 and 3 are not repeatedly turned on and off, less power is consumed to drive the gates than when the neutral point elements 2 and 3 are repeatedly turned on and off. Furthermore, if an AC capacitor 23 (see FIG. 1 ) is present on the AC side, no current flows through the AC capacitor 23, resulting in a longer life for the AC capacitor 23 than when a voltage that would cause a current to flow through the AC capacitor 23 is applied. Even if the voltage command value becomes a value other than 0 (zero) due to noise in current measurement or the like, and the neutral point element is turned on and off, causing a current to flow, only a small amount of current flows, resulting in a relatively long life for the AC capacitor 23.

[0203] For this reason, from the viewpoints of power consumption and the life of AC capacitor 23, it may appear that the second and third embodiments shown in Figures 16 to 18, which consume less power and have a longer life of AC capacitor 23, are preferable to the fourth embodiment shown in Figures 19 and 20. However, from the viewpoint of protecting semiconductor elements 1 to 4 (neutral point elements 2, 3) from overvoltage breakdown due to lightning surges, the fourth embodiment shown in Figures 19 and 20 and the second and third embodiments shown in Figures 16 to 18 also have similar effects.

[0204] <Hardware Configuration Example> Fig. 21 is a conceptual diagram showing an example of the hardware configuration of the processing circuitry 90 included in the control device 40 in the embodiment shown in Figs. 1 to 20. The functions described above are realized by the processing circuitry 90. In one aspect, the processing circuitry 90 includes at least one processor 91 and at least one memory 92. In another aspect, the processing circuitry 90 includes at least one dedicated hardware 93.

[0205] When the processing circuit 90 includes a processor 91 and a memory 92, each function is realized by software, firmware, or a combination of software and firmware. At least one of the software and firmware is written as a program. At least one of the software and firmware is stored in the memory 92. The processor 91 realizes each function by reading and executing the program stored in the memory 92.

[0206] When the processing circuitry 90 includes dedicated hardware 93, the processing circuitry 90 may be, for example, a single circuit, multiple circuits, a programmed processor, or a combination thereof. Each function is implemented by the processing circuitry 90.

[0207] Each function of the control device 40 may be partially or entirely configured by hardware, or may be configured as a program executed by a processor. That is, the control device 40 can be realized by a computer and a program, and the program can be stored in a storage medium or provided via a network.

[0208] 1 to 21 are divided into the first embodiment and its modified examples shown in FIGS. 1 to 15, the second embodiment shown in FIG. 16, the third embodiment shown in FIGS. 17 and 18, and the fourth embodiment shown in FIGS. 19 and 20. However, any two or more of these embodiments may be combined in series or in parallel. The combined embodiment can also achieve the same effects as the respective effects achieved by the respective embodiments before being combined.

[0209] In the embodiment shown in FIGS. 1 to 21, the control unit 50 controls the DC voltage V ｄｃ The control unit 50 determines whether the power converter 30 is in operation based on the DC voltage V ｄｃ Instead of the above, the state transition of the operation mode of the power converter 30 may be performed based on the value of the DC current, the time, or the hour, etc. In this case, although not shown, the power conversion system 20 may include a DC current sensor, a timer, a clock, etc. In this case, in steps S2 and S5, the control unit 50 may perform the state transition of the operation mode of the power converter 30 based on the value of the DC current, the time, or the hour, etc. acquired from the DC current sensor, the timer, the clock, etc. In this case, the same effects as those of the embodiment shown in FIGS. 1 to 21 can be achieved.

[0210] 1 to 21, when the operation mode of the power converter 30 is the standby mode, the control units 50 to 50C provide gate signals that turn on one or both of the series-connected neutral point elements 2 and 3. When the operation mode of the power converter 30 is the standby mode, the control units 50 to 50C provide gate signals that turn off the semiconductor elements 1 and 4 other than the neutral point elements 2 and 3. However, this is not limited to this. The control units 50 to 50C may provide gate signals as described above simply when they determine that the AC switch 24 is in the off (open) state, regardless of whether the operation mode of the power converter 30 is the standby mode or the power generation mode. This also achieves the same effects as the embodiment shown in FIGS. 1 to 21.

[0211] In addition, in the embodiment shown in FIGS. 1 to 21, the case has been described where the AC side of the power converter 30 (AC input / output unit 32 (see FIGS. 3 and 4)) is connected to the AC power grid 15. However, this is not limiting, and the AC side of the power converter 30 may be connected to an electric motor, a generator, or an AC load. This also achieves the same effects as the embodiment shown in FIGS. 1 to 21.

[0212] Furthermore, according to the embodiment shown in Figures 1 to 21, as described above, the semiconductor elements 1 to 4 of the power converter 30 are prevented from being destroyed by overvoltage due to a lightning surge, and the neutral elements 2 and 3 can be protected from overvoltage breakdown due to a lightning surge. However, this effect is not limited to lightning surges. According to the embodiment shown in Figures 1 to 21, a similar effect is achieved even when the ground potential of the DC side or AC side of the power converter 30 fluctuates significantly due to, for example, a switching surge or an accident in another nearby circuit, in addition to a lightning surge. Therefore, the present disclosure is applicable to cases such as a switching surge and an accident in another nearby circuit, in addition to a lightning surge.

[0213] 1 to 21, the power conversion system 20 and the control device 40 (controllers 50 to 50C) included therein have been described as an example of one aspect of the present disclosure, but the present disclosure is not limited to this. The present disclosure can also be realized as a control method in which processing steps are performed in each part of the control device 40 (controllers 50 to 50C).

[0214] The present disclosure can also be realized as a control program that causes a computer to execute processing steps in each part of the control device 40 (control parts 50 to 50C).

[0215] The present disclosure can also be realized as a storage medium (non-transitory computer-readable storage medium) on which a control program is stored. The control program can be stored and distributed on removable media such as a CD (Compact Disc), a DVD (Digital Versatile Disc), or a USB (Universal Serial Bus) memory. The control program may be uploaded to a network via a network interface (not shown) of the control device 40, or may be downloaded from the network and stored in the storage unit 43, the memory 92, or the like.

[0216] The features and advantages of the embodiments will be apparent from the above detailed description. It is intended that the claims encompass the features and advantages of the above-described embodiments without departing from the spirit and scope of the claims. Furthermore, any improvements and modifications will be readily apparent to those skilled in the art. Therefore, it is not intended that the scope of the inventive embodiments be limited to the above-described embodiments, and appropriate improvements and equivalents within the scope of the disclosed embodiments may be utilized.

[0217] 1... Power semiconductor element (first semiconductor switching element, semiconductor switching element, semiconductor element, element); 2... Power semiconductor element (second semiconductor switching element, neutral point element, semiconductor switching element, semiconductor element, element); 3... Power semiconductor element (third semiconductor switching element, neutral point element, semiconductor switching element, semiconductor element, element); 4... Power semiconductor element (fourth semiconductor switching element, semiconductor switching element, semiconductor element, element); 11... Solar cell (DC power source); 12... DC cable; 13 ...AC cable; 14... transformer; 15... AC power system (power system); 20... multilevel power conversion system (power conversion system); 21... DC switch; 22... AC reactor; 23... AC capacitor; 24... AC switch; 25... DC voltage sensor; 26... AC current sensor; 30... multilevel power converter (power converter); 31... DC input / output unit; 32... AC input / output unit; 33... heat sink; 40... control device; 41... acquisition unit; 42... output unit; 43... memory unit; 45... system bus (bus); 50, 50A, 50B , 50C...control unit; 51...operation control unit; 52, 52B, 52C...voltage command generation unit; 53, 53', 53A, 53B, 53C...gate signal generation unit; 90...processing circuit; 91...processor; 92...memory; 93...hardware; 101...semiconductor switching element; 102...semiconductor switching element (neutral point element); 103...semiconductor switching element (neutral point element); 104...semiconductor switching element; 130...multilevel power converter (power converter); 201...semiconductor switching element; 202...semiconductor switch 203...Semiconductor switching element (neutral point element); 204...Semiconductor switching element; 230...Multilevel power converter (power converter); 301...Semiconductor switching element; 302...Semiconductor switching element (neutral point element); 303...Semiconductor switching element (neutral point element); 304...Semiconductor switching element; 330...Multilevel power converter (power converter); A...Power semiconductor module; AC...AC terminal (AC terminal); B...Power semiconductor module; C...DC neutral point; C １ ~C ４ ...parasitic capacitance; CA1, CA2...triangular wave carrier; C ＡＣ , C ＮＣ ...parasitic capacitance; CＮ , C Ｐ ... DC capacitor; D... Modulation wave; D1 to D4... Freewheeling diodes (anti-parallel diodes, diodes); D ｕ ...U-phase modulated wave; D ｖ ...V phase modulated wave; D ｗ ...W-phase modulating wave; GND...ground potential; g, gu1 to gu4, gv1 to gv4, gw1 to gw4...gate signals; I ｕ ... AC current value (AC current, current, U-phase current measurement value); I ｖ ... AC current value (AC current, current, V-phase current measurement value); I ｗ ... AC current value (AC current, current, W phase current measurement value); I ｕ＿ｒｅｆ ...U-phase current command value (current command value); I ｖ＿ｒｅｆ ...V-phase current command value (current command value); I ｗ＿ｒｅｆ ...W-phase current command value (current command value); Kp...proportional control gain; N...negative terminal (N-pole terminal); NC...non-connection terminal (NC terminal); P...positive terminal (P-pole terminal); P ＿ｒｅｆ ...output power command value; V ＿ｒｅｆ ...Voltage command value; V ２ , V ３ ...Voltage; V ｄｃ ... DC voltage value (DC voltage, voltage); V ＬＳ ... charging voltage; V ＮＣ ...Voltage; V ｕ＿ｒｅｆ ...U-phase voltage command value (voltage command value); V ｖ＿ｒｅｆ ...V-phase voltage command value (voltage command value); V ｗ＿ｒｅｆ ...W-phase voltage command value (voltage command value)

Claims

1. A multilevel power converter comprising: a DC input / output unit having a positive terminal and a negative terminal connected to a DC power supply or a DC load; a plurality of DC capacitors connected in series between the positive terminal and the negative terminal via a DC neutral point; an AC input / output unit having an AC terminal connected to an AC power supply or an AC load; a first semiconductor switching element and a fourth semiconductor switching element connected in series with the same polarity between the positive terminal and the negative terminal via the AC terminal; a first freewheeling diode and a fourth freewheeling diode connected in anti-parallel to the first semiconductor switching element and the fourth semiconductor switching element, respectively; a third semiconductor switching element and a second semiconductor switching element connected in series with anti-polarity between the DC neutral point and the AC terminal; and a third freewheeling diode and a second freewheeling diode connected in anti-parallel to the third semiconductor switching element and the second semiconductor switching element, respectively; and an operation control unit that transitions an operation mode of the multilevel power converter to a standby mode in which power conversion is not performed between the DC input / output unit and the AC input / output unit based on a predetermined condition. a gate signal generating unit configured to generate and output a gate signal that causes at least one of the third semiconductor switching element and the second semiconductor switching element to be in a conductive state or a switching state in the standby mode; and a control device having the gate signal generating unit.

2. A multilevel power conversion system according to claim 1, further comprising an AC switch connected between said AC input / output unit of said multilevel power converter and said AC power source or said AC load, wherein said gate signal generating unit generates and outputs a gate signal for putting at least one of said third semiconductor switching element and said second semiconductor switching element into a conductive state or a switching state when said AC switch is open and said multilevel power converter is in said standby mode.

3. A multilevel power conversion system as claimed in claim 1, characterized in that the gate signal generating unit generates and outputs a gate signal for putting both of the first semiconductor switching element and the fourth semiconductor switching element into a non-conducting state when in the standby mode.

4. A multilevel power conversion system according to claim 1, wherein the gate signal generating unit generates and outputs a gate signal for operating the multilevel power converter based on a zero voltage command value for causing the AC input / output unit to output a voltage approximately equal to the DC neutral point when in the standby mode.

5. A multilevel power conversion system according to claim 1, wherein the control device further comprises a voltage command generating section which generates a voltage command value based on a zero current command value for outputting approximately zero current from the AC input / output section of the multilevel power converter when in the standby mode, and the gate signal generating section generates and outputs a gate signal for operating the multilevel power converter based on the voltage command value generated by the voltage command generating section.

6. A control device for a multilevel power conversion system comprising: a DC input / output unit having a positive terminal and a negative terminal connected to a DC power supply or a DC load; a plurality of DC capacitors connected in series between the positive terminal and the negative terminal via a DC neutral point; an AC input / output unit having AC terminals connected to an AC power supply or an AC load; a first semiconductor switching element and a fourth semiconductor switching element connected in series with the same polarity between the positive terminal and the negative terminal via the AC terminals; a first freewheeling diode and a fourth freewheeling diode connected in anti-parallel to the first semiconductor switching element and the fourth semiconductor switching element, respectively; a third semiconductor switching element and a second semiconductor switching element connected in series with anti-polarity between the DC neutral point and the AC terminal; and a third freewheeling diode and a second freewheeling diode connected in anti-parallel to the third semiconductor switching element and the second semiconductor switching element, respectively, wherein the control device comprises: a gate signal generating unit configured to generate and output a gate signal that causes at least one of the third semiconductor switching element and the second semiconductor switching element to be in a conductive state or a switching state in the standby mode.