Inverter circuit
Patent Information
- Application Number
- JP2025514950
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Filing Date
- 2025-09-22
- Publication Date
- 2026-01-21
AI Technical Summary
Conventional inverter circuits face challenges in accurately controlling the threshold voltage without increasing current consumption, particularly due to manufacturing variations and temperature fluctuations, and often require additional processing steps that can lead to latch-up issues.
The proposed inverter circuit employs a series configuration of a switch element and a load element between different voltages, with a current source adjusting the inversion threshold voltage by controlling the current through the switch element, eliminating the need for additional processing steps and reducing latch-up concerns.
This configuration provides a predetermined threshold value that is stable against manufacturing variations, temperature, and power supply voltage fluctuations, without increasing current consumption and avoiding latch-up issues.
Abstract
Description
Inverter circuit
[0001] The present invention relates to an inverter circuit that inverts a binary input voltage and outputs an inverted binary output voltage.
[0002] Many integrated circuits (hereinafter referred to as "ICs") have a standby mode for the purpose of reducing standby power consumption when electronic devices are not in operation. To operate in this standby mode, a method is used in which the standby mode or active enable mode of the IC is controlled by inputting an IC activation signal voltage from outside the IC.
[0003] When implementing this enable control circuit within an IC chip, it is necessary to configure a circuit that does not increase current consumption during standby mode. By configuring a comparator using the threshold voltage of a single MOS field effect transistor (hereinafter referred to as a "MOS transistor"; a field effect transistor is also referred to as an "FET"), it is possible to configure an enable control circuit for an IC simply and without increasing current consumption.
[0004] On the other hand, as the ICs used in the periphery become smaller and operate at lower voltages, the voltage of this enable control signal is becoming lower, and simply using an FET with a low on-threshold voltage may result in the off-side threshold characteristics becoming too low when temperature characteristics and process variations are taken into account, which may prevent the control signal from shutting off, so that in order to meet market demands, the threshold value must be controlled with high precision, including the temperature characteristics. For this reason, methods such as configuring a comparator with a reference voltage that has good temperature characteristics, or lowering the input transistor threshold value by controlling the back gate of the input transistor are already known (see, for example, Patent Documents 1 and 2).
[0005] Patent No. 4620522 Patent No. 5181893
[0006] However, all enable control circuits implemented using the circuit techniques to date have had trade-off characteristics. A comparator generated using the threshold value of a single FET, which can be easily configured, fluctuates due to process variations in the IC manufacturing process, making it difficult to precisely control the threshold value. Furthermore, methods using a reference voltage with good temperature characteristics consume current to generate the reference voltage, resulting in increased standby current.
[0007] In the method of controlling the back gate of the FET, an additional process step is required to create a device that can separate the back gate potential of the FET from the substrate, which is disadvantageous in terms of cost and delivery, and there is also the problem that a parasitic diode in the direction from the back gate potential to the substrate potential is likely to move, which can lead to latch-up.
[0008] An object of the present invention is to solve the above problems and to provide an inverter circuit having a predetermined threshold voltage, which does not require an additional process for isolating the back gate potential from the substrate during manufacturing and is free from the concern of latch-up.
[0009] An inverter circuit according to one aspect of the present invention includes a series circuit in which a first switch element and a load element are connected in series between two different voltages, and the inverter circuit inverts an input voltage input to an input terminal using the first switch element and outputs the inverted output voltage from an output terminal, and further includes a current source that adjusts a current flowing through the first switch element to adjust an inversion threshold voltage of the inverter circuit.
[0010] Therefore, according to an embodiment of the present invention, an inverter circuit having a predetermined threshold voltage can be provided, which does not require an additional process for isolating the back gate potential from the substrate during manufacturing, is free from concerns about latch-up, and in particular, can suppress fluctuations in the inversion threshold voltage of an inverter circuit that outputs a binary signal due to manufacturing variations, temperature, power supply voltage, etc.
[0011] 1 is a circuit diagram showing a configuration example of an inverter circuit according to a first embodiment. 2 is a circuit diagram showing a configuration example of an inverter circuit according to a second embodiment. 3 is a circuit diagram showing a configuration example of an inverter circuit according to a third embodiment. 4 is a circuit diagram showing a configuration example of an inverter circuit according to a fifth embodiment. 5 is a circuit diagram showing a configuration example of an inverter circuit according to a sixth embodiment. 6 is a circuit diagram showing a configuration example of an inverter circuit according to a seventh embodiment. 7 is a graph showing characteristics of the drain-source current Ids of an NMOS transistor and the threshold voltage Vth of the inverter circuit relative to the input voltage Vin in an inverter circuit according to a conventional example. 8 is a graph showing characteristics of the threshold voltage Vth of the inverter circuit according to an embodiment. FIG. 12 is a circuit diagram showing a configuration example of an inverter circuit according to a 9th embodiment. FIG. 13 is a graph showing characteristics of threshold voltages depending on power supply voltages of inverter circuits according to a conventional example and the 9th embodiment. FIG. 14 is a circuit diagram showing a configuration example of an inverter circuit according to a 10th embodiment. FIG. 15 is a circuit diagram showing a configuration example of an inverter circuit according to a modified example of the 10th embodiment. FIG. 16 is a circuit diagram showing a configuration example of an inverter circuit according to an 11th embodiment. FIG. 17 is a circuit diagram showing a configuration of an inverter circuit according to a 1st comparative example. FIG. 18 is a circuit diagram showing a configuration of an inverter circuit according to a 2nd comparative example.
[0012] Hereinafter, embodiments and modifications of the present invention will be described with reference to the drawings, in which the same or similar components are designated by the same reference numerals.
[0013] First, the inventor's findings will be described below regarding the inverter circuits according to Comparative Examples 1 and 2. In this specification, an N-channel MOS transistor is referred to as an "NMOS transistor" and a P-channel MOS transistor is referred to as a "PMOS transistor."
[0014] (Inventor's Findings) (Comparative Example 1) FIG. 19 is a circuit diagram showing the configuration of an inverter circuit according to Comparative Example 1. As shown in FIG.
[0015] 19, the inverter circuit according to Comparative Example 1 has an input terminal T1, an output terminal T2, a power supply terminal T3, and a ground terminal T4, and is configured with an NMOS transistor Q1 and a load element 10. Here, the load element 10 is configured, for example, with an FET or a resistor. A power supply voltage VDD is connected to the power supply terminal T3, and the ground terminal T4 is grounded and serves as the ground voltage VSS.
[0016] 19, when a low-level input voltage Vin, which is the ground voltage VSS, is input to the input terminal T1, the NMOS transistor Q1 is turned off, and a high-level output voltage Vout, which is the power supply voltage VDD, is output from the output terminal T2. Here, when the input voltage Vin changes from low to high, that is, from the ground voltage VSS to the power supply voltage VDD, the NMOS transistor Q1 is turned on, and a low-level output voltage Vout is output from the output terminal T2.
[0017] In the inverter circuit configured as described above, the operating threshold voltage Vth of the inverter circuit can be set by appropriately setting the resistance values of the NMOS transistor Q1 and the load element 10. The threshold voltage Vth of the NMOS transistor Q1 depends on the manufacturing process, and varies due to manufacturing variations. The threshold voltage Vth also varies depending on the temperature of the NMOS transistor Q1.
[0018] Comparative Example 2 FIG. 20 is a circuit diagram showing the configuration of an inverter circuit according to Comparative Example 2. In FIG.
[0019] 20 is an example of applying the conventional technology described in the Background Art section to an inverter circuit, and has an input terminal T1, an output terminal T2, a power supply terminal T3, and a ground terminal T4, and is configured with an NMOS transistor Q1, a load element 10, a constant current source 24, and an NMOS transistor Q31. Here, a bias voltage generated by flowing a current to a saturation connection node of an NMOS transistor Q31 having the same electrical characteristics as the input transistor is applied to the back gate of the NMOS transistor Q1, which is the input transistor.
[0020] In the inverter circuit configured as described above, NMOS transistor Q1 and NMOS transistor Q31 are the same type of device, and if the threshold voltage Vth of NMOS transistor Q1 varies due to manufacturing, the threshold voltage Vth of NMOS transistor Q31 will fluctuate in the same way. That is, in a wafer manufactured so that the threshold voltage Vth of NMOS transistor Q1 is high, the threshold voltage Vth of NMOS transistor Q31, which generates a backgate bias, will also be high, and the backgate bias voltage generated by NMOS transistor Q31 will also be high, increasing the backgate effect and further lowering the threshold voltage Vth of NMOS transistor Q1. As a result, a backgate bias is generated that suppresses manufacturing variations.
[0021] However, as mentioned in the section on problems to be solved by the invention, this circuit configuration requires an additional manufacturing process to separate the back gate of the input NMOS transistor Q1 from the substrate potential. Also, if the back gate bias voltage generated by the NMOS transistor Q31 and the constant current source 24 is too high, the forward bias device viewed from the back gate to the source will be turned on, raising concerns that latch-up may occur.
[0022] The object of the following embodiments of the present invention is to solve the above problems and provide an inverter circuit having a predetermined threshold voltage, which does not require an additional manufacturing process for isolating the back gate potential from the substrate and is free from concerns about latch-up.
[0023] First Embodiment FIG. 1 is a circuit diagram showing an example of the configuration of an inverter circuit according to a first embodiment.
[0024] 1, the inverter circuit according to the first embodiment has an input terminal T1, an output terminal T2, a power supply terminal T3, and a ground terminal T4, and is configured with an NMOS transistor Q1, a load element 10, and a constant current source 11. Here, the load element 10 is configured, for example, with an FET or a resistor. A power supply voltage VDD is connected to the power supply terminal T3, and the ground terminal T4 is grounded to the ground voltage VSS. In FIG. 1, a series circuit of the NMOS transistor Q1 and the load element 10 is connected between the power supply terminal T3 and the ground terminal T4, and the constant current source 11 is connected in parallel to the load element 10.
[0025] In the inverter circuit configured as described above, when a low-level input voltage Vin, which is the ground voltage VSS, is input to the input terminal T1, the NMOS transistor Q1 is turned off, and a high-level output voltage Vout, which is the input voltage Vin of the power supply voltage VDD, is output from the output terminal T2. Here, when the input voltage Vin changes from low to high, that is, from the ground voltage VSS to the power supply voltage VDD, the NMOS transistor Q1 is turned on, and a low-level output voltage Vout is output from the output terminal T2.
[0026] 1, the constant current source 11 operates to add (supply) the current flowing through the NMOS transistor Q1 by the constant current amount (adjusted current) of the constant current source 11, i.e., to cause a constant current amount to flow in. The amount of current added to the NMOS transistor Q1 increases the input voltage Vin required to determine the polarity of the output terminal T2, and adjusting this current amount controls the inversion threshold voltage Vth of the inverter circuit. Therefore, an inverter circuit having a predetermined threshold value can be provided that does not require an additional process for isolating the backgate potential from the substrate during manufacturing and is free from concerns about latch-up.
[0027] Second Embodiment FIG. 2 is a circuit diagram showing an example of the configuration of an inverter circuit according to a second embodiment.
[0028] 2, the inverter circuit according to the second embodiment differs from the inverter circuit according to the first embodiment in the following respects: (1) A constant current source 12 is provided instead of the constant current source 11. Here, the constant current source 12 is connected in parallel to the source and drain of the NMOS transistor Q1.
[0029] In the inverter circuit configured as described above, when a low-level input voltage Vin, which is the ground voltage VSS, is input to the input terminal T1, the NMOS transistor Q1 is turned off, and a high-level output voltage Vout, which is the power supply voltage VDD, is output from the output terminal T2. Here, when the input voltage Vin changes from low to high, that is, from the ground voltage VSS to the power supply voltage VDD, the NMOS transistor Q1 is turned on, and a low-level output voltage Vout is output from the output terminal T2.
[0030] 2, the constant current source 12 operates to subtract (draw out) the constant current amount (adjusted current) of the constant current source 12 from the current flowing through the NMOS transistor Q1, i.e., to drain a constant current amount, and the input voltage Vin required to determine the polarity of the output terminal T2 changes so as to decrease depending on the current amount subtracted from the NMOS transistor Q1, so that the inversion threshold voltage Vth of the inverter circuit is controlled by adjusting this current amount. Therefore, an inverter circuit having a predetermined threshold can be provided that does not require an additional process for isolating the backgate potential from the substrate during manufacturing and is free from concerns about latch-up.
[0031] Third Embodiment FIG. 3 is a circuit diagram showing an example of the configuration of an inverter circuit according to a third embodiment.
[0032] 3, the inverter circuit according to the third embodiment has an input terminal T1, an output terminal T2, a power supply terminal T3, and a ground terminal T4, and is configured with a PMOS transistor Q2, a load element 10, and a constant current source 12. Here, the load element 10 is configured, for example, with an FET or a resistor. The power supply terminal T3 is connected to a power supply voltage VDD, and the ground terminal T4 is grounded to a ground voltage VSS. In FIG. 3, a series circuit of the PMOS transistor Q2 and the load element 10 is connected between the power supply terminal T3 and the ground terminal T4, and the constant current source 12 is connected in parallel to the source and drain of the PMOS transistor Q2.
[0033] In the inverter circuit configured as described above, when a low-level input voltage Vin, which is the ground voltage VSS, is input to the input terminal T1, the PMOS transistor Q2 is turned on, and a high-level output voltage Vout, which is the power supply voltage VDD, is output from the output terminal T2. Here, when the input voltage Vin changes from low to high, that is, from the ground voltage VSS to the power supply voltage VDD, the PMOS transistor Q2 is turned off, and a low-level output voltage Vout is output from the output terminal T2.
[0034] 3, the constant current source 12 operates to subtract (draw out) the constant current amount (adjusted current) of the constant current source 12 from the current flowing through the PMOS transistor Q2, and the input voltage Vin required to determine the polarity of the output terminal T2 changes so as to increase depending on the amount of current subtracted from the PMOS transistor Q2, so that the inversion threshold voltage Vth of the inverter circuit is controlled by adjusting this current amount. Therefore, an inverter circuit having a predetermined threshold can be provided that does not require an additional process for isolating the backgate potential from the substrate during manufacturing and is free from concerns about latch-up.
[0035] Fourth Embodiment FIG. 4 is a circuit diagram showing an example of the configuration of an inverter circuit according to a fourth embodiment.
[0036] 4, the inverter circuit according to the fourth embodiment differs from the inverter circuit according to the third embodiment shown in FIG. 3 in the following respects: (1) A constant current source 11 is provided instead of the constant current source 12. Here, the constant current source 11 is connected in parallel with the load element 10.
[0037] In the inverter circuit configured as described above, when a low-level input voltage Vin, which is the ground voltage VSS, is input to the input terminal T1, the PMOS transistor Q2 is turned on, and a high-level output voltage Vout, which is the power supply voltage VDD, is output from the output terminal T2. Here, when the input voltage Vin changes from low to high, that is, from the ground voltage VSS to the power supply voltage VDD, the PMOS transistor Q2 is turned off, and a low-level output voltage Vout is output from the output terminal T2.
[0038] 4, the constant current source 11 operates to add (supply) the current flowing through the PMOS transistor Q2 by the constant current (adjusted current) of the constant current source 11, and the amount of current added to the PMOS transistor Q2 changes so as to decrease the input voltage Vin required to determine the polarity of the output terminal T2, so that the inversion threshold voltage Vth of the inverter circuit can be controlled by adjusting this current amount. Therefore, an inverter circuit having a predetermined threshold can be provided that does not require an additional process for isolating the backgate potential from the substrate during manufacturing and is free from concerns about latch-up.
[0039] As described above, in the first to fourth embodiments, the inversion threshold voltage Vth of the inverter circuit can be controlled by adding a predetermined adjustment current to the current flowing through the NMOS transistor Q1 or the PMOS transistor Q2 (first switch element) or by adjusting the current flowing through the NMOS transistor Q1 or the PMOS transistor Q2 so that the predetermined adjustment current is subtracted from the current flowing through the NMOS transistor Q1 or the PMOS transistor Q2. Therefore, an inverter circuit having a predetermined threshold voltage can be provided, which does not require an additional process for isolating the backgate potential from the substrate during manufacturing and is free from concerns about latch-up.
[0040] (Embodiment 5) Fig. 5 is a circuit diagram showing an example of the configuration of an inverter circuit according to embodiment 5. The inverter circuit according to embodiment 5 of Fig. 5 differs from the inverter circuit of Fig. 1 in the following respects: (1) A PMOS transistor Q2 is used as a specific element of the load element 10. Here, the source of the PMOS transistor Q2 is connected to the power supply terminal T3, and the drain of the PMOS transistor Q2 is connected to the output terminal T2. The gate of the PMOS transistor Q3 is connected to the input terminal T1.
[0041] In the inverter circuit configured as described above, when a low-level input voltage Vin, which is the ground voltage VSS, is input to the input terminal T1, the NMOS transistor Q1 is turned off and the PMOS transistor Q2 is turned on, and a high-level output voltage Vout, which is the power supply voltage VDD, is output from the output terminal T2. Here, when the input voltage Vin changes from low to high, that is, from the ground voltage VSS to the power supply voltage VDD, the NMOS transistor Q1 is turned on and the PMOS transistor Q2 is turned off, and a low-level output voltage Vout is output from the output terminal T2. Therefore, the inverter circuit of embodiment 5 has the same functions and effects as embodiment 1.
[0042] (Sixth embodiment) Fig. 6 is a circuit diagram showing an example of the configuration of an inverter circuit according to a sixth embodiment. The inverter circuit according to the sixth embodiment shown in Fig. 6 differs from the inverter circuit shown in Fig. 1 in the following respects: (1) A resistor R1 is used as a specific element of the load element 10. Here, one end of the resistor R1 is connected to a power supply terminal T3, and the other end of the resistor R1 is connected to an output terminal T2.
[0043] In the inverter circuit configured as described above, when a low-level input voltage Vin, which is the ground voltage VSS, is input to the input terminal T1, the NMOS transistor Q1 is turned off, and a high-level output voltage Vout, which is the power supply voltage VDD, is output from the output terminal T2. Here, when the input voltage Vin changes from low to high, that is, from the ground voltage VSS to the power supply voltage VDD, the NMOS transistor Q1 is turned on, and a low-level output voltage Vout is output from the output terminal T2. Therefore, the inverter circuit of embodiment 6 has the same functions and effects as embodiment 1.
[0044] (Seventh embodiment) Fig. 7 is a circuit diagram showing an example of the configuration of an inverter circuit according to a seventh embodiment. The inverter circuit according to the seventh embodiment of Fig. 7 differs from the inverter circuit of Fig. 1 in the following respects: (1) A constant current source 13 is used as a specific element of the load element 10. Here, one end of the constant current source 13 is connected to the power supply terminal T3, and the other end of the constant current source 13 is connected to the output terminal T2.
[0045] In the inverter circuit configured as described above, when a low-level input voltage Vin, which is the ground voltage VSS, is input to the input terminal T1, the NMOS transistor Q1 is turned off, and a high-level output voltage Vout, which is the power supply voltage VDD, is output from the output terminal T2. Here, when the input voltage Vin changes from low to high, that is, from the ground voltage VSS to the power supply voltage VDD, the NMOS transistor Q1 is turned on, and a low-level output voltage Vout is output from the output terminal T2. Therefore, the inverter circuit of embodiment 7 has the same functions and effects as embodiment 1.
[0046] (Modifications) In the inverter circuit according to the second embodiment of Fig. 2, the resistor R1 of Fig. 6 or the constant current source 13 of Fig. 7 may be used as a specific element of the load element 10. In the inverter circuits according to the third or fourth embodiment of Fig. 3 or Fig. 4, the NMOS transistor Q1 instead of the PMOS transistor Q2 of Fig. 5, or the resistor R1 of Fig. 6 or the constant current source 13 of Fig. 7 may be used as a specific element of the load element 10.
[0047] (Variations in Threshold Voltage) Fig. 8 is a graph showing the characteristics of the drain-source current Ids of the NMOS transistor and the inversion threshold voltage Vth of the inverter circuit relative to the input voltage Vin in the inverter circuit according to the conventional example (Fig. 19). Fig. 9 is a graph showing the characteristics of the drain-source current Ids of the NMOS transistor Q1 and the inversion threshold voltage Vth of the inverter circuit relative to the input voltage Vin in the inverter circuit according to this embodiment.
[0048] Here, for the sake of simplicity, if we consider the load element 10 to be the constant current source 13 shown in the seventh embodiment (FIG. 7), the inverter circuit can be realized by using the Ids-Vin characteristic curve of the NMOS transistor in FIG. 8 and the constant current value I ０ The output voltage is inverted at the point where it intersects with the line. The Ids-Vin characteristic curve of this NMOS transistor depends on the threshold voltage Vth of the NMOS transistor, and the input voltage Vin at which current begins to flow as Ids changes. In other words, even if the design is based on the solid line characteristic in Figure 8 as the center value, manufacturing variations and temperature characteristics will cause the characteristic curve to change as shown by the dashed line or dashed line, which will ultimately affect variations in the threshold voltage Vth.
[0049] In contrast to this, in the proposed inverter circuits according to the first to seventh embodiments, as shown in FIG. ０ In addition to this, by adding or subtracting the current amount (adjustment current) of the constant current sources 11 and 12 that reflects the characteristic fluctuation of the threshold voltage Vth of the input transistor, the characteristic curve of the drain-source current Ids-Vin of the NMOS transistor Q1 and the total current value (I ０ +ΔI, I ０ The voltage change at the intersection with the input voltage Vth (-ΔI) can be controlled to be small, resulting in a configuration that reduces variations in the inversion threshold voltage Vth of the inverter circuit. The adjustment current value for addition or subtraction is adjusted to a current that provides electrical characteristics that match the factors (for example, power supply voltage VDD, temperature, or manufacturing variations) whose variations are to be reduced.
[0050] 10 is a graph showing the temperature characteristics of the threshold voltage Vth of a typical FET, and is a diagram illustrating the temperature characteristics of the threshold voltage Vth of an NMOS transistor and manufacturing variations. Generally, as a characteristic of an NMOS transistor, its threshold voltage Vth decreases with temperature, as shown in FIG. 10. Furthermore, in FIG. 10, the threshold voltage fluctuates due to the influence of manufacturing variations, as indicated by the dashed line and the dashed-dotted line.
[0051] Fig. 11 is a graph showing the temperature characteristics of the inversion threshold voltage Vth of the inverter circuit of the conventional example (Fig. 19). As is clear from the temperature characteristics of Fig. 10, the threshold voltage Vth characteristics of, for example, the NMOS transistor Q1 of Fig. 19 are affected by temperature characteristics or manufacturing variations, and therefore the inversion threshold voltage Vth of the inverter circuit of Fig. 19 also changes in accordance with these characteristics.
[0052] Eighth Embodiment Fig. 12 is a circuit diagram showing an example of the configuration of an inverter circuit according to an eighth embodiment. The inverter circuit of Fig. 12 differs from the inverter circuit of Fig. 7 in the following respects: (1) Instead of the constant current source 11, a current mirror circuit 31 configured as a variable current source and made up of PMOS transistors Q11 and Q12, and an NMOS transistor Q13 whose gate and source are connected together, are provided. The differences will be explained below.
[0053] 12, the source and drain of a PMOS transistor Q11 are connected in parallel to a constant current source 13, and the gate of the PMOS transistor Q11 is connected to the gate of a PMOS transistor Q12. The gate and drain of the PMOS transistor Q12 and the drain of an NMOS transistor Q13 are connected to each other. Furthermore, the gate and source of the NMOS transistor Q13 are connected to a terminal T4 and are grounded.
[0054] In the inverter circuit configured as described above, PMOS transistor Q12 and NMOS transistor Q13 form a constant current source that supplies a predetermined current, and a current corresponding to the current supplied by the constant current source is supplied to NMOS transistor Q1. In other words, the leakage current of NMOS transistor Q13 at high temperatures is reflected by PMOS transistors Q11 and Q12 and then supplied to the drain of NMOS transistor Q1. Since the leakage current of NMOS transistor Q13, a semiconductor element, increases sharply only at high temperatures, as shown in FIG. 13, no current flows through NMOS transistor Q13 or PMOS transistors Q11 and Q12 in low temperature regions. As a result, the additive current (adjusting current) is adjusted so that the inversion threshold voltage Vth of the inverter circuit is high only at high temperatures. This offsets the negative temperature-dependent threshold voltage Vth characteristic of the MOS transistors, thereby suppressing the temperature dependence of the inversion threshold voltage of the inverter circuit.
[0055] The advantage of the above circuit configuration is that since correction based on leakage current is performed only at high temperatures, the inversion threshold voltage of the inverter circuit can be controlled without increasing the current consumption of the circuit at room temperature. In this case, NMOS transistor Q1 and NMOS transistor Q13 do not need to be devices with the same size and threshold voltage Vth, and the desired threshold voltage correction can be achieved by changing the leakage current characteristics according to the threshold voltage Vth to be adjusted.
[0056] Furthermore, the gate and source of the NMOS transistor Q13 are connected, and a gate voltage that turns off the NMOS transistor Q13 at room temperature may be applied, and the gate voltage may be adjusted to a value that results in a leakage current occurring at a high temperature that is higher than a predetermined threshold temperature, for example.
[0057] As described above, the eighth embodiment is characterized in that an adjustment current adjusted to exhibit desired threshold voltage characteristics is added to the output terminal T2 of the inverter circuit, and threshold adjustment using the backgate effect is not used.
[0058] 13 is a graph showing the temperature characteristics of leakage current of a typical NMOS transistor, and the dashed and dotted lines indicate that the temperature at which this leakage current characteristic begins to occur varies depending on manufacturing variations in the threshold voltage Vth of the NMOS transistor. That is, an NMOS transistor manufactured to have a high threshold voltage Vth does not generate leakage current until a higher temperature, as shown by the dotted line, while an NMOS transistor manufactured to have a low threshold voltage Vth has leakage current characteristics that generate leakage current at a lower temperature, as shown by the dotted line.
[0059] 14 is a graph showing the temperature characteristics of the inversion threshold voltage Vth of the inverter circuit according to the embodiment. By setting a predetermined optimal design ratio between the NMOS transistor Q13 shown in FIG. 12 , which has the off-state leakage current characteristics shown in FIG. 13 , and the NMOS transistor Q1, which has the threshold voltage Vth characteristics shown in FIG. 13 , it is possible to suppress the decrease in the threshold voltage Vth at high temperatures higher than a predetermined threshold temperature, such as room temperature, and, as shown in FIG. 14 , it is possible to make the lower limit of the threshold voltage Vth higher than in the prior art. Furthermore, this circuit configuration suppresses the fluctuation range of the threshold voltage, including the variations in the manufacturing process and the temperature characteristics, by virtue of the characteristics that the leakage current of the NMOS transistor Q13 occurs at a relatively low temperature for the NMOS transistor Q1 with a low threshold voltage Vth due to manufacturing variations, and that the leakage current begins to occur at a relatively high temperature for the NMOS transistor Q1 with a high threshold voltage due to manufacturing variations.
[0060] By using the inverter circuit according to the eighth embodiment of FIG. 12 , even if an NMOS transistor Q1 whose threshold voltage Vth is tuned low as an absolute value is used at the input terminal T1, it is possible to realize a characteristic that prevents the transistor from being unable to be turned off by a control signal even when temperature characteristics or manufacturing variations are taken into account, and an inverter circuit with a low threshold voltage Vth can be configured.
[0061] 15 is a circuit diagram showing an example of the configuration of an inverter circuit according to a ninth embodiment. The inverter circuit of FIG. 15 differs from the inverter circuit of FIG. 7 in the following respects: (1) Instead of the constant current source 11, a current mirror circuit 32 configured as a variable current source and made up of NMOS transistors Q21 and Q22, and a resistor R2 are provided. The differences will be described below.
[0062] 15, the drain and source of NMOS transistor Q21 are connected in parallel to the drain and source of NMOS transistor Q1, and the gate of NMOS transistor Q21 is connected to the gate of NMOS transistor Q22. The gate and drain of NMOS transistor Q22 are connected to one end of resistor R2, and the other end of resistor R2 is connected to power supply terminal T3. Furthermore, the sources of NMOS transistors Q21 and Q22 are connected to terminal T4 and grounded.
[0063] The inverter circuit configured as described above is an example of a circuit that improves the fluctuation of the threshold voltage Vth depending on the power supply voltage VDD. Here, the current flowing through NMOS transistor Q22 and resistor R2 is a function of the power supply voltage VDD and the resistance value of resistor R2. As the power supply voltage VDD fluctuates, the voltage applied across resistor R2 increases and decreases, and the current also increases proportionally. A current proportional to the power supply voltage VDD flows through NMOS transistor Q22, and a current corresponding to this current flows through NMOS transistor Q21. Therefore, an adjustment current proportional to the power supply voltage VDD is subtracted from the current flowing through NMOS transistor Q1 of the inverter circuit.
[0064] FIG. 16 is a graph showing the characteristics of the threshold voltage depending on the power supply voltage of the inverter circuits according to the conventional example and the ninth embodiment.
[0065] 16 , in the inverter circuit according to the conventional example, when the short channel effect of the NMOS transistor serving as the input transistor becomes apparent and the threshold voltage Vth also increases with respect to the power supply voltage VDD, the fluctuation range can be appropriately adjusted by using the circuit configuration according to the present embodiment 9. On the other hand, when the short channel effect of the NMOS transistor Q1 serving as the input transistor becomes apparent and the threshold voltage Vth decreases with respect to the power supply voltage VDD, the polarities of the NMOS transistors Q21 and Q22 may be switched, and a current mirror circuit 32 may be formed by the NMOS transistors Q21 and Q22 whose sources are connected to the power supply voltage VDD, and a predetermined adjustment current may be added to inject a current into the NMOS transistor Q1 so as to increase the threshold voltage Vth.
[0066] As described above, in the circuit configuration of the conventional example, it is assumed that the threshold voltage Vth has a positive correlation with the power supply voltage, as shown by the dashed line in FIG. 16 , and the solid line in FIG. 16 indicates that the threshold voltage Vth is adjusted to be constant with respect to the power supply voltage VDD by the correction function of the inverter circuit according to the ninth embodiment.
[0067] 17A is a circuit diagram showing an example of the configuration of an inverter circuit according to a tenth embodiment. The inverter circuit of FIG. 17A differs from the inverter circuit according to the seventh embodiment of FIG. 7 in the following respects: (1) Instead of the constant current source 11, a parallel circuit is provided, which is a series circuit of a constant current source 21 and a trimming fuse F1, a series circuit of a constant current source 22 and a trimming fuse F2, and a series circuit of a constant current source 23 and a trimming fuse F3. The differences are explained below.
[0068] In FIG. 17A , the amount of current (adjustment current) added to the constant current source 13 can be adjusted by leaving the trimming fuses F1 to F3 on or by cutting at least one of the trimming fuses F1 to F3 to turn them off. This allows the inversion threshold voltage Vth of the inverter circuit to be adjusted. Note that while FIG. 17A shows three series circuits of constant current sources 21 to 23 and trimming fuses F1 to F3, the present invention is not limited to this configuration and may include one or more such series circuits. Furthermore, as shown in FIG. 17B of a modified example, the current source 13 may be various load elements 10, such as resistors or MOS transistors.
[0069] 18 is a circuit diagram showing an example of the configuration of an inverter circuit according to an eleventh embodiment. The inverter circuit according to the eleventh embodiment of FIG. 18 differs from the inverter circuit of FIG. 1 in the following respects: (1) A PMOS transistor Q2 is inserted between the power supply terminal T3 and the load element 10. That is, a CMOS circuit is configured to include a PMOS transistor Q2 that is complementary to the NMOS transistor Q1, which is an input transistor. The differences are described below.
[0070] 18, a power supply terminal T3 is connected to one end of a constant current source 11 and to the source of a PMOS transistor Q2. The drain of the PMOS transistor Q2 is connected to one end of a load element 10. The gate of the PMOS transistor Q2 is connected to an input terminal T1.
[0071] In the inverter circuit configured as described above, as explained with reference to FIG. 1 , the inversion threshold voltage Vth of the inverter circuit is determined by the on-state characteristics of the NMOS transistor Q1. According to this embodiment, the inversion threshold voltage Vth of the inverter circuit can be adjusted by adding or subtracting an adjusted current from the constant current source 11 or the constant current source 12 to the input voltage Vin near the threshold voltage Vth. Therefore, for input voltages Vin outside the range to be adjusted, specifically, for input voltages Vin sufficiently higher than the threshold voltage Vth in the circuit configurations of FIG. 1 or 18, the output terminal T2 is sufficiently pulled down by the capability of the NMOS transistor Q1, and it is determined that a low-level output voltage Vout having the ground voltage VSS is output, and therefore correction of the threshold voltage according to the effect of the present invention is not required.
[0072] 18, by inserting a PMOS transistor Q2 in series with the NMOS transistor Q1, which cuts off the current flowing through the inverter circuit when the input voltage Vin is close to the power supply voltage VDD within a range of the input voltage Vin that does not affect the characteristics of the adjusted threshold voltage Vth, the through current of the inverter circuit can be reduced. Also, by connecting an adjusted current source to the drain terminal of the PMOS transistor Q2 instead of the source terminal of the PMOS transistor Q2, the current consumption due to the addition of the adjusted current can be reduced.
[0073] 18, in order to reduce current consumption for an input voltage Vin in a range that does not affect the threshold characteristics, a complementary PMOS transistor Q2 may be used to cut off the current flowing through the NMOS transistor Q1, which is the input transistor. Here, if the input transistor is a PMOS transistor, an NMOS transistor may be used for cutting off.
[0074] Furthermore, in the explanation of the inverter circuit according to the eleventh embodiment of FIG. 18 , an inverter circuit having a threshold voltage Vth based on the ground voltage VSS is used, but the present invention is not limited to this. When adjusting the threshold voltage Vth based on the power supply voltage VDD, a PMOS transistor may be configured as the input transistor instead of an NMOS transistor, and a complementary NMOS transistor may be arranged in series with the input transistor to prevent feed-through.
[0075] (Other Modifications) In the above embodiment, the power supply voltage VDD is connected to the terminal T3 and the terminal T4 is grounded, but the present invention is not limited to this, and different voltages may be applied between the terminals T3 and T4. In the example embodiment, the voltage of the terminal T3 is set to a voltage higher than the voltage of the terminal T4.
[0076] In the above embodiment, Q1 is an NMOS transistor, but the present invention is not limited to this, and it may be another switching element that turns on when the input voltage is at a high level and turns off when the input voltage is at a low level.
[0077] In the above embodiment, Q2 is a PMOS transistor, but the present invention is not limited to this, and it may be another switching element that turns off when the input voltage is at a high level and turns on when the input voltage is at a low level.
[0078] As described above in detail, the inverter circuit according to the present invention can provide an inverter circuit having a predetermined threshold voltage, which does not require an additional process for isolating the back gate potential from the substrate during manufacturing, is free from concerns about latch-up, and in particular, can suppress fluctuations in the inversion threshold voltage of an inverter circuit that outputs a binary signal due to manufacturing variations, temperature, power supply voltage, etc.
[0079] 10 Load element 11 to 24 Constant current source 31, 32 Current mirror circuit F1 to F3 Trimming fuse Q1 to Q22 MOS transistor R1, R2 Resistor T1 to T4 Terminal
Claims
1. An inverter circuit includes a series circuit in which a first switch element and a load element are connected in series between two different voltages, and inverts an input voltage input to an input terminal by the first switch element, and outputs an inverted output voltage from an output terminal, a current source connected in parallel to the first switch element or the load element, the current source adjusting a current flowing through the first switch element to adjust an inversion threshold voltage of the inverter circuit; Inverter circuit.
2. the current source adjusts the current flowing through the first switch element by causing a predetermined adjustment current to flow into or out of the first switch element; 2. The inverter circuit according to claim 1.
3. The load element is a resistor or a constant current source.
2. The inverter circuit according to claim 1.
4. The inverter circuit a series circuit connected in parallel to the load element, the series circuit further comprising at least one of a constant current source and a trimming fuse; 2. The inverter circuit according to claim 1.
5. the first switch element is an N-channel MOS transistor or a P-channel MOS transistor; 4. The inverter circuit according to claim 1.
6. the first switch element is an N-channel MOS transistor, the series circuit further includes a second switch element which is a P-channel MOS transistor connected in series to the series circuit of the first switch element and the load element; 4. The inverter circuit according to claim 1.
7. the current source is a current mirror circuit including two semiconductor elements, and includes a current mirror circuit that causes an adjusted current corresponding to a current that changes depending on one of the two different voltages to flow into or out of the first switch element; 2. The inverter circuit according to claim 1.
8. the current source is a current mirror circuit including two semiconductor elements, and includes a current mirror circuit that causes an adjustment current corresponding to a leakage current caused by a transistor at a high temperature higher than a predetermined normal temperature to flow into or out of the first switch element; 2. The inverter circuit according to claim 1.