Display device

Abstract

In the present invention, a complementary metal oxide film semiconductor circuit (C), in which a first TFT (9s) having a first semiconductor layer (12b) formed of polysilicon and a second TFT (9t) having a second semiconductor layer (16b) formed of an oxide semiconductor are combined, is provided, in plan view, with at least one of a first protection pattern (16p) formed of the oxide semiconductor around the first semiconductor layer (12b) of the first TFT (9s) and a second protection pattern (12p) formed of the polysilicon around the second semiconductor layer (16b) of the second TFT (9t).

Description

display device

[0001] The present invention relates to a display device.

[0002] In recent years, self-luminous organic electroluminescence (EL) display devices using organic electroluminescence (EL) elements have been attracting attention as a display device that can replace liquid crystal display devices. In these organic EL display devices, a plurality of thin film transistors (TFTs) are provided for each subpixel, which is the smallest unit of an image. Well-known examples of semiconductor layers that constitute TFTs include a semiconductor layer made of polysilicon, which has high mobility, and a semiconductor layer made of an oxide semiconductor such as In—Ga—Zn—O, which has low leakage current.

[0003] For example, Patent Document 1 discloses a display device having a hybrid structure in which a first TFT using a polysilicon semiconductor and a second TFT using an oxide semiconductor are formed on a substrate.

[0004] Japanese Patent Application Laid-Open No. 2020-17558

[0005] In an organic EL display device having a hybrid structure in which each subpixel is provided with a polysilicon TFT and an oxide semiconductor TFT, it has been proposed to provide a CMOS (complementary metal oxide semiconductor) circuit, which combines a P-channel TFT using a polysilicon semiconductor and an N-channel TFT using an oxide semiconductor, as part of the peripheral circuit. However, the manufacturing process for this hybrid-structure organic EL display device equipped with a CMOS circuit is complicated, and the characteristics of the TFTs constituting the CMOS circuit may be deteriorated due to, for example, destruction of the insulating film caused by electrostatic discharge accumulated during the manufacturing process or penetration of moisture from organic resin materials, making it difficult to ensure a high yield. Therefore, there is room for improvement.

[0006] The present invention has been made in view of the above points, and an object of the present invention is to suppress deterioration of the characteristics of thin film transistors that constitute peripheral circuits in a display device having a hybrid structure.

[0007] In order to achieve the above object, a display device according to the present invention comprises a base substrate, and a thin film transistor layer provided on the base substrate, in which a first thin film transistor having a first semiconductor layer formed of polysilicon and a second thin film transistor having a second semiconductor layer formed of an oxide semiconductor are arranged, the display device having a display area for displaying images and a frame area defined around the display area, a plurality of pixel thin film transistors are provided as the first thin film transistor and the second thin film transistor in each sub-pixel constituting the display area, and a complementary metal oxide semiconductor circuit combining the first thin film transistor and the second thin film transistor is provided in the frame area as a part of a drive circuit, wherein the complementary metal oxide semiconductor circuit is characterized in that, in a plan view, the complementary metal oxide semiconductor circuit is provided with at least one of a first protection pattern formed of the oxide semiconductor around the first semiconductor layer of the first thin film transistor in the complementary metal oxide semiconductor circuit and a second protection pattern formed of the polysilicon around the second semiconductor layer of the second thin film transistor in the complementary metal oxide semiconductor circuit.

[0008] According to the present invention, in a display device having a hybrid structure, it is possible to suppress deterioration of the characteristics of thin film transistors that constitute peripheral circuits.

[0009] FIG. 1 is a plan view showing a schematic configuration of an organic EL display device according to a first embodiment of the present invention. FIG. 2 is a plan view of a display region of the organic EL display device according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view of a display region of the organic EL display device according to the first embodiment of the present invention. FIG. 4 is an equivalent circuit diagram of a TFT layer constituting the organic EL display device according to the first embodiment of the present invention. FIG. 5 is a cross-sectional view of an organic EL layer constituting the organic EL display device according to the first embodiment of the present invention. FIG. 6 is an equivalent circuit diagram showing a drive circuit including a complementary metal oxide semiconductor circuit constituting the organic EL display device according to the first embodiment of the present invention. FIG. 7 is a cross-sectional view of a complementary metal oxide semiconductor circuit constituting the organic EL display device according to the first embodiment of the present invention. FIG. 8 is a plan view of a first TFT constituting the complementary metal oxide semiconductor circuit of the organic EL display device according to the first embodiment of the present invention. FIG. 9 is a plan view of a second TFT constituting the complementary metal oxide semiconductor circuit of the organic EL display device according to the first embodiment of the present invention. FIG. 10 is a plan view of a first modified example of the first TFT constituting the complementary metal oxide semiconductor circuit of the organic EL display device according to the first embodiment of the present invention, and corresponds to FIG. 8 . FIG. 11 is a plan view of a second modified first TFT constituting the complementary metal oxide semiconductor circuit of the organic EL display device according to the first embodiment of the present invention, corresponding to FIG. 8 . FIG. 12 is a plan view of a third modified first TFT constituting the complementary metal oxide semiconductor circuit of the organic EL display device according to the first embodiment of the present invention, corresponding to FIG. 8 . FIG. 13 is a plan view of a fourth modified first TFT constituting the complementary metal oxide semiconductor circuit of the organic EL display device according to the first embodiment of the present invention, corresponding to FIG. 8 . FIG. 14 is a plan view of a first modified second TFT constituting the complementary metal oxide semiconductor circuit of the organic EL display device according to the first embodiment of the present invention, corresponding to FIG. 9 . FIG. 15 is a plan view of a second modified second TFT constituting the complementary metal oxide semiconductor circuit of the organic EL display device according to the first embodiment of the present invention, corresponding to FIG. 9 . FIG. 16 is a plan view of a third modified second TFT constituting the complementary metal oxide semiconductor circuit of the organic EL display device according to the first embodiment of the present invention, corresponding to FIG. 9 .FIG. 17 is a plan view of a fourth modified example of the second TFT constituting the complementary metal oxide semiconductor circuit of the organic EL display device according to the first embodiment of the present invention, and corresponds to FIG.

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments.

[0011] First Embodiment FIGS. 1 to 17 show a first embodiment of a display device according to the present invention. In the following embodiments, an organic EL display device including an organic EL element layer is exemplified as a display device including a light-emitting element layer. FIG. 1 is a plan view showing a schematic configuration of an organic EL display device 50 according to this embodiment. FIGS. 2 and 3 are a plan view and a cross-sectional view of a display region D of the organic EL display device 50. FIG. 4 is an equivalent circuit diagram of a TFT layer 30 constituting the organic EL display device 50. FIG. 5 is a cross-sectional view of an organic EL layer 33 constituting the organic EL display device 50. FIG. 6 is an equivalent circuit diagram showing a gate driver circuit M including a CMOS circuit C constituting the organic EL display device 50. FIG. 7 is a cross-sectional view of the CMOS circuit C. FIGS. 8 and 9 are plan views of a fourth peripheral TFT 9s and a fifth peripheral TFT 9t constituting the CMOS circuit C. 8 and 9, cross-sectional views of the fourth peripheral TFT 9s and the fifth peripheral TFT 9t taken along line A-A form part of the cross-sectional view of Fig. 7. Figs. 10, 11, 12, and 13 are plan views of first, second, third, and fourth modified examples of the fourth peripheral TFT 9s constituting the CMOS circuit C, and correspond to Fig. 8. Figs. 14, 15, 16, and 17 are plan views of first, second, third, and fourth modified examples of the fifth peripheral TFT 9t constituting the CMOS circuit C, and correspond to Fig. 9.

[0012] 1 , the organic EL display device 50 includes, for example, a rectangular display area D for displaying an image, and a frame area F provided in a frame shape around the display area D. Note that, although the present embodiment illustrates a rectangular display area D, this rectangular shape also includes, for example, a substantially rectangular shape with arc-shaped sides, arc-shaped corners, or a shape with a notch in one of the sides.

[0013] In the display region D, a plurality of sub-pixels P are arranged in a matrix as shown in Fig. 2. In the display region D, for example, a sub-pixel P having a red light-emitting region Er for displaying red, a sub-pixel P having a green light-emitting region Eg for displaying green, and a sub-pixel P having a blue light-emitting region Eb for displaying blue are provided adjacent to each other as shown in Fig. 2. In the display region D, one pixel is configured by, for example, three adjacent sub-pixels P having the red light-emitting region Er, the green light-emitting region Eg, and the blue light-emitting region Eb.

[0014] A terminal portion T is provided at the right end of the frame region F in FIG. 1 to extend in one direction (the Y direction in the figure). Between the display region D and the terminal portion T, as shown in FIG. 1, that is, in the frame region F, on the display region D side of the terminal portion T, a folding portion B is provided that can be folded, for example, 180° (in a U-shape) with the Y direction in the figure as the folding axis, to extend in one direction (the Y direction in the figure). A gate driver circuit M is provided at the upper and lower ends of the frame region F in FIG. 1 as a driving circuit. As will be described later, a CMOS circuit C combining a fourth peripheral TFT 9s and a fifth peripheral TFT 9t is provided in the frame region F as part of the gate driver circuit M.

[0015] As shown in FIG. 3, the organic EL display device 50 includes a resin substrate 10 provided as a base substrate, a TFT layer 30 provided on the resin substrate 10, an organic EL element layer 40 provided as a light-emitting element layer on the TFT layer 30, and a sealing film 45 provided on the organic EL element layer 40.

[0016] The resin substrate 10 is made of an organic resin material such as polyimide resin.

[0017] As shown in FIG. 3 , the TFT layer 30 includes, in a display region D, a base coat film 11 provided on a resin substrate 10, four first TFTs 9A, three second TFTs 9B, and one capacitor 9h (see FIG. 4 ) provided on the base coat film 11 for each subpixel P, and a protective insulating film 21 and a planarizing film 22 provided in that order on each of the first TFTs 9A, each of the second TFTs 9B, and each of the capacitors 9h. Here, as shown in FIG. 2 , the display region D of the TFT layer 30 includes a plurality of gate lines 14g extending parallel to one another in the X direction in the drawing. Also, as shown in FIG. 2 , the display region D of the TFT layer 30 includes a plurality of light-emitting control lines 14e extending parallel to one another in the X direction in the drawing. Also, as shown in FIG. 2 , the display region D of the TFT layer 30 includes a plurality of second initialization power lines 18i extending parallel to one another in the X direction in the drawing. As shown in Fig. 2, each light-emitting control line 14e is provided adjacent to each gate line 14g and each second initialization power line 18i. Furthermore, in the display region D of the TFT layer 30, a plurality of source lines 20f are provided so as to extend parallel to each other in the Y direction in the drawing, as shown in Fig. 2. Furthermore, in the display region D of the TFT layer 30, a plurality of power supply lines 20g are provided so as to extend parallel to each other in the Y direction in the drawing, as shown in Fig. 2. Furthermore, each power supply line 20g is provided so as to be adjacent to each source line 20f, as shown in Fig. 2.

[0018] 3, in the TFT layer 30, a base coat film 11, a first semiconductor film, a first gate insulating film 13, a first metal film, a first interlayer insulating film 15, a second semiconductor film, a second gate insulating film 17a (17b, see FIG. 7), a second metal film, a second interlayer insulating film 19, a third metal film, a protective insulating film 21, and a planarizing film 22 are laminated in this order on a resin substrate 10. Here, the gate line 14g and the light-emitting control line 14e are formed from the first metal film. The second initialization power supply line 18i is formed from the second metal film. The source line 20f and the power supply line 20g are formed from the third metal film.

[0019] The base coat film 11, the first gate insulating film 13, the first interlayer insulating film 15, the second gate insulating film 17a (17b), the second interlayer insulating film 19, and the protective insulating film 21 are each composed of a single layer or a stack of inorganic insulating films such as silicon nitride, silicon oxide, or silicon oxynitride. At least the first interlayer insulating film 15 on the side of a second semiconductor layer 16a (16b) (described later) and the second gate insulating film 17a (17b) on the side of the second semiconductor layer 16a (16b) are each composed of a silicon oxide film. The first gate insulating film 13, the first interlayer insulating film 15, the second gate insulating film 17a (17b), and the second interlayer insulating film 19 are provided as a first inorganic insulating film, a second inorganic insulating film, a third inorganic insulating film, and a fourth inorganic insulating film, respectively.

[0020] As shown in Figure 3, the first TFT 9A of the subpixel P includes a first semiconductor layer 12a provided on a base coat film 11, a first gate electrode 14a provided on the first semiconductor layer 12a via a first gate insulating film 13, and a first terminal electrode 20a and a second terminal electrode 20b provided on a second interlayer insulating film 19 so as to be spaced apart from each other.

[0021] The first semiconductor layer 12a is formed of the first semiconductor film made of polysilicon such as LTPS (low temperature polysilicon), and as shown in FIG. 3, includes a first conductor region 12aa and a second conductor region 12ab that are defined to be spaced apart from each other, and a first channel region 12ac that is defined between the first conductor region 12aa and the second conductor region 12ab.

[0022] The first gate electrode 14a is formed from the first metal film and, as shown in FIG. 3, is arranged to overlap the first channel region 12ac of the first semiconductor layer 12a, and is configured to control conduction between the first conductor region 12aa and the second conductor region 12ab of the first semiconductor layer 12a.

[0023] The first terminal electrode 20a and the second terminal electrode 20b are formed from the third metal film, and as shown in FIG. 3, are electrically connected to the first conductor region 12aa and the second conductor region 12ab of the first semiconductor layer 12a, respectively, via a first contact hole Ha and a second contact hole Hb formed in the stacked film of the first gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 19.

[0024] As shown in FIG. 3, the second TFT 9B of the subpixel P includes a second semiconductor layer 16a provided on the first interlayer insulating film 15, a second gate electrode 18a provided on the second semiconductor layer 16a via a second gate insulating film 17a, and a third terminal electrode 20c and a fourth terminal electrode 20d provided spaced apart from each other on the second interlayer insulating film 19.

[0025] The second semiconductor layer 16a is formed from the second semiconductor film made of an oxide semiconductor such as an In—Ga—Zn—O system. As shown in FIG. 3 , the second semiconductor layer 16a includes a third conductor region 16aa and a fourth conductor region 16ab spaced apart from each other, and a second channel region 16ac defined between the third conductor region 16aa and the fourth conductor region 16ab. The In—Ga—Zn—O system oxide semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the proportions (composition ratios) of In, Ga, and Zn are not particularly limited. The In—Ga—Zn—O system oxide semiconductor may be amorphous or crystalline. A crystalline In—Ga—Zn—O system oxide semiconductor preferably has a c-axis oriented generally perpendicular to the layer surface. Instead of the In—Ga—Zn—O system semiconductor, another oxide semiconductor may be included. Other oxide semiconductors include, for example, In—Sn—Zn—O-based semiconductors (e.g., In ２ O ３ -SnO ２In—ZnO; InSnZnO). Here, the In—Sn—Zn—O based semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Other oxide semiconductors include In—Al—Zn—O based semiconductors, In—Al—Sn—Zn—O based semiconductors, Zn—O based semiconductors, In—Zn—O based semiconductors, Zn—Ti—O based semiconductors, Cd—Ge—O based semiconductors, Cd—Pb—O based semiconductors, CdO (cadmium oxide), Mg—Zn—O based semiconductors, In—Ga—Sn—O based semiconductors, In—Ga—O based semiconductors, Zr—In—Zn—O based semiconductors, Hf—In—Zn—O based semiconductors, Al—Ga—Zn—O based semiconductors, Ga—Zn—O based semiconductors, In—Ga—Zn—Sn—O based semiconductors, InGaO ３ (ZnO) ５ , magnesium zinc oxide (Mg ｘ Zn １－ｘ O), cadmium zinc oxide (Cd ｘ Zn １－ｘ The Zn—O-based semiconductor may be ZnO in an amorphous state, a polycrystalline state, a microcrystalline state in which the amorphous state and the polycrystalline state are mixed, or a semiconductor in which no impurity element is added, to which one or more impurity elements selected from the group 1 elements, the group 13 elements, the group 14 elements, the group 15 elements, the group 17 elements, etc. are added.

[0026] The second gate electrode 18a is formed of the second metal film and is provided so as to overlap the second channel region 16ac of the second semiconductor layer 16a, and is configured to control conduction between the third conductor region 16aa and the fourth conductor region 16ab of the second semiconductor layer 16a, as shown in Fig. 3. Here, the second gate insulating film 17a below the second gate electrode 18a is provided in an island shape so as to overlap the second gate electrode 18a, as shown in Fig. 3.

[0027] The third terminal electrode 20c and the fourth terminal electrode 20d are formed from the third metal film and, as shown in FIG. 3, are electrically connected to the third conductor region 16aa and the fourth conductor region 16ab of the second semiconductor layer 16a, respectively, via the third contact hole Hc and the fourth contact hole Hd formed in the second interlayer insulating film 19.

[0028] In this embodiment, four first TFTs 9A each having a first semiconductor layer 12a formed of polysilicon are exemplified by a writing TFT 9c, a driving TFT 9d, a power supply TFT 9e, and a light-emission control TFT 9f (described later), and three second TFTs 9B each having a second semiconductor layer 16a formed of an oxide semiconductor are exemplified by an initialization TFT 9a, a compensation TFT 9b, and anode discharge TFT 9g (described later) (see FIG. 4). In the equivalent circuit diagram of FIG. 4, the first terminal electrodes 20a and the second terminal electrodes 20b of the TFTs 9c, 9d, 9e, and 9f are indicated by circled numbers 1 and 2, and the third terminal electrodes 20c and the fourth terminal electrodes 20d of the TFTs 9a, 9b, and 9g are indicated by circled numbers 3 and 4. 4 shows the pixel circuit of the sub-pixel P in the nth row and the mth column, but also includes a part of the pixel circuit of the sub-pixel P in the (n-1)th row and the mth column. Also, in the equivalent circuit diagram of FIG. 4, the power supply line 20g that supplies the high power supply voltage ELVDD also serves as the first initialization power supply line, but the power supply line 20g and the first initialization power supply line may be provided separately. Also, while the same voltage as the low power supply voltage ELVSS is input to the second initialization power supply line 18i, this is not limiting, and a voltage different from the low power supply voltage ELVSS that turns off the organic EL element 35 (described later) may be input.

[0029] As shown in FIG. 4, in each sub-pixel P, the initialization TFT 9a has a gate electrode electrically connected to the gate line 14g(n-1) of the previous stage (n-1 stage), a third terminal electrode electrically connected to the lower conductive layer of the capacitor 9h described later and the gate electrode of the driving TFT 9d, and a fourth terminal electrode electrically connected to the power supply line 20g.

[0030] As shown in FIG. 4, in each subpixel P, the compensation TFT 9b has its gate electrode electrically connected to the gate line 14g(n) of its own row (nth row), its third terminal electrode electrically connected to the gate electrode of the driving TFT 9d, and its fourth terminal electrode electrically connected to the first terminal electrode of the driving TFT 9d.

[0031] As shown in FIG. 4, in each subpixel P, the writing TFT 9c has a gate electrode electrically connected to the gate line 14g(n) of its own row (nth row), a first terminal electrode electrically connected to the corresponding source line 20f, and a second terminal electrode electrically connected to the second terminal electrode of the driving TFT 9d.

[0032] 4, in each sub-pixel P, the driving TFT 9d has a gate electrode electrically connected to the third terminal electrode of the initialization TFT 9a and the compensation TFT 9b, a first terminal electrode electrically connected to the fourth terminal electrode of the compensation TFT 9b and the second terminal electrode of the power supply TFT 9e, and a second terminal electrode electrically connected to the second terminal electrode of the writing TFT 9c and the first terminal electrode of the light emission control TFT 9f. Here, the driving TFT 9d is configured to control the drive current of the organic EL element 35.

[0033] As shown in FIG. 4, in each subpixel P, the power supply TFT 9e has its gate electrode electrically connected to the light-emitting control line 14e of its own row (nth row), its first terminal electrode electrically connected to the power supply line 20g, and its second terminal electrode electrically connected to the first terminal electrode of the drive TFT 9d.

[0034] As shown in FIG. 4, in each subpixel P, the light emission control TFT 9f has its gate electrode electrically connected to the light emission control line 14e of its own row (nth row), its first terminal electrode electrically connected to the second terminal electrode of the driving TFT 9d, and its second terminal electrode electrically connected to the first electrode 31 (described later) of the organic EL element 35 (described later).

[0035] As shown in FIG. 4, in each subpixel P, the anode discharge TFT 9g has a gate electrode electrically connected to the gate line 14g(n) of the current row (nth row), a third terminal electrode electrically connected to the first electrode 31 of the organic EL element 35, and a fourth terminal electrode electrically connected to the second initialization power line 18i.

[0036] 4, the capacitor 9h includes, for example, a lower conductive layer (not shown) formed of the first metal film, a first interlayer insulating film 15 and a second gate insulating film (not shown) provided so as to cover the lower conductive layer, and an upper conductive layer (not shown) provided on the second gate insulating film so as to overlap the lower conductive layer and formed of the second metal film. Furthermore, in each subpixel P, the lower conductive layer of the capacitor 9h is electrically connected to the gate electrode of the driving TFT 9d and the third terminal electrodes of the initialization TFT 9a and the compensation TFT 9b, and the upper conductive layer is electrically connected to the third terminal electrode of the anode discharge TFT 9g, the second terminal electrode of the emission control TFT 9f, and the first electrode 31 of the organic EL element 35.

[0037] The planarization film 22 has a flat surface in the display region D and is made of an organic resin material such as polyimide resin.

[0038] 3, the organic EL element layer 40 includes a plurality of organic EL elements 35 provided as a plurality of light-emitting elements so as to be arranged in a matrix on the TFT layer 30, corresponding to a plurality of sub-pixels P. Here, as shown in Fig. 3, each organic EL element 35 includes a first electrode 31 provided on the TFT layer 30, an organic EL layer 33 provided on the first electrode 31, and a second electrode 34 provided on the organic EL layer 33 so as to be common to the entire display region D.

[0039] The first electrode 31 is electrically connected to the second terminal electrode of the emission control TFT 9 f of each sub-pixel P through a contact hole formed in the laminated film of the protective insulating film 21 and the planarizing film 22. The first electrode 31 also has a function of injecting holes (positive holes) into the organic EL layer 33. In order to improve the efficiency of hole injection into the organic EL layer 33, the first electrode 31 is preferably formed of a material with a large work function. Examples of materials that can be used for the first electrode 31 include metal materials such as silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), and tin (Sn). The material constituting the first electrode 31 is, for example, astatine (At) / astatine oxide (AtO ２ The first electrode 31 may be made of an alloy such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). The first electrode 31 may be made of a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). The first electrode 31 may be formed by stacking multiple layers of the above materials. Examples of compound materials with a high work function include indium tin oxide (ITO) and indium zinc oxide (IZO). The peripheral edge of the first electrode 31 is covered with an edge cover 22 arranged in a grid pattern over the entire display area D. The edge cover 32 is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based spin-on-glass (SOG) material.

[0040] As shown in FIG. 5, the organic EL layer 33 includes a hole injection layer 1, a hole transport layer 2, a light emitting layer 3, an electron transport layer 4, and an electron injection layer 5, which are stacked in this order on the first electrode 31.

[0041] The hole injection layer 1 is also called an anode buffer layer, and has the function of bringing the energy levels of the first electrode 31 and the organic EL layer 33 closer to each other, thereby improving the efficiency of hole injection from the first electrode 31 to the organic EL layer 33. Examples of materials constituting the hole injection layer 1 include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, and stilbene derivatives.

[0042] The hole transport layer 2 has a function of improving the efficiency of transporting holes from the first electrode 31 to the organic EL layer 33. Examples of materials constituting the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, styrylamine derivatives, polyvinylcarbazole, poly-p-phenylenevinylene, polysilane, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, zinc sulfide, and zinc selenide.

[0043] The light-emitting layer 3 is a region into which holes and electrons are injected from the first electrode 31 and the second electrode 34, respectively, and where the holes and electrons recombine when a voltage is applied between the first electrode 31 and the second electrode 34. The light-emitting layer 3 is made of a material with high luminous efficiency. Examples of materials that can be used for the light-emitting layer 3 include metal oxinoid compounds (8-hydroxyquinoline metal complexes), naphthalene derivatives, anthracene derivatives, diphenylethylene derivatives, vinylacetone derivatives, triphenylamine derivatives, butadiene derivatives, coumarin derivatives, benzoxazole derivatives, oxadiazole derivatives, oxazole derivatives, benzimidazole derivatives, thiadiazole derivatives, benzothiazole derivatives, styryl derivatives, styrylamine derivatives, bisstyrylbenzene derivatives, trisstyrylbenzene derivatives, perylene derivatives, perinone derivatives, aminopyrene derivatives, pyridine derivatives, rhodamine derivatives, aquidin derivatives, phenoxazone, quinacridone derivatives, rubrene, poly-p-phenylenevinylene, and polysilane.

[0044] The electron transport layer 4 has a function of efficiently transferring electrons to the light-emitting layer 3. Examples of materials constituting the electron transport layer 4 include organic compounds such as oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinodimethane derivatives, diphenoquinone derivatives, fluorenone derivatives, silole derivatives, and metal oxinoid compounds.

[0045] The electron injection layer 5 has a function of bringing the energy levels of the second electrode 34 and the organic EL layer 33 closer to each other and improving the efficiency of electron injection from the second electrode 34 to the organic EL layer 33, and this function can reduce the driving voltage of the organic EL element 35. The electron injection layer 5 is also called a cathode buffer layer. Here, examples of materials constituting the electron injection layer 5 include lithium fluoride (LiF), magnesium fluoride (MgF ２ ), calcium fluoride (CaF ２ ), strontium fluoride (SrF ２ ), barium fluoride (BaF ２inorganic alkali compounds such as aluminum oxide (Al ２ O ３ ), strontium oxide (SrO), etc.

[0046] As shown in FIG. 3 , the second electrode 34 is provided to cover each organic EL layer 33 and the edge cover 32. The second electrode 34 has a function of injecting electrons into the organic EL layer 33. To improve the efficiency of electron injection into the organic EL layer 33, the second electrode 34 is preferably made of a material with a small work function. Examples of materials that can be used for the second electrode 34 include silver (Ag), aluminum (Al), vanadium (V), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), and lithium fluoride (LiF). Examples of materials that can be used for the second electrode 34 include magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), and astatine (At) / astatine oxide (AtO). ２ The second electrode 34 may be formed of an alloy such as lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), or lithium fluoride (LiF) / calcium (Ca) / aluminum (Al). The second electrode 34 may be formed of a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). The second electrode 34 may be formed by stacking multiple layers made of the above materials. Examples of materials with a low work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), and lithium fluoride (LiF) / calcium (Ca) / aluminum (Al).

[0047] 3 , the sealing film 45 is provided so as to cover the second electrode 34, and includes a first inorganic sealing film 41, an organic sealing film 42, and a second inorganic sealing film 43 laminated in this order on the second electrode 34, and has the function of protecting the organic EL layer 33 of the organic EL element 35 from moisture, oxygen, etc. Here, the first inorganic sealing film 41 and the second inorganic sealing film 43 are made of inorganic insulating films such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film. Moreover, the organic sealing film 42 is made of an organic resin material such as an acrylic resin, an epoxy resin, a silicone resin, a polyurea resin, a parylene resin, a polyimide resin, or a polyamide resin.

[0048] As shown in FIG. 7, the organic EL display device 50 (TFT layer 30) includes, in the frame region F, a base coat film 11 provided on a resin substrate 10, four first TFTs 9A, one second TFT 9B, and one capacitor 9j (see FIG. 6) provided on the base coat film 11 as a gate driver circuit M, and a protective insulating film 21 and a planarizing film 22 provided in this order on each of the first TFTs 9A, each of the second TFTs 9B, and each of the capacitors 9j.

[0049] As shown in Figures 7 and 8, the first TFT 9A in the frame region F comprises a first semiconductor layer 12b provided on the base coat film 11, a first gate electrode 14b provided on the first semiconductor layer 12b via a first gate insulating film 13, a first source electrode 20h and a first drain electrode 20i provided spaced apart from each other on the second interlayer insulating film 19, and a first protective pattern 16p provided around the first semiconductor layer 12b in a planar view.

[0050] The first semiconductor layer 12b, like the first semiconductor layer 12a, is formed from the first semiconductor film, and as shown in FIG. 7, includes a first source region 12ba and a first drain region 12bb that are defined to be spaced apart from each other, and a first channel region 12bc that is defined between the first source region 12ba and the first drain region 12bb.

[0051] The first gate electrode 14b, like the first gate electrode 14a, is formed from the first metal film and, as shown in FIG. 7, is arranged to overlap the first channel region 12bc of the first semiconductor layer 12b and is configured to control the conduction between the first source region 12ba and the first drain region 12bb of the first semiconductor layer 12b.

[0052] The first source electrode 20h and the first drain electrode 20i are formed from the third metal film, and as shown in FIG. 7, are electrically connected to the first source region 12ba and the first drain region 12bb of the first semiconductor layer 12b, respectively, via a first contact hole Hh and a second contact hole Hi formed in the stacked film of the first gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 19.

[0053] The first protection pattern 16p, like the second semiconductor layer 16a, is formed from the second semiconductor film (conducted), and as shown in Figure 8, is provided in the shape of a rectangular frame ring so as to surround the first semiconductor layer 12b in a planar view.

[0054] In this embodiment, the first TFT 9A (the fourth peripheral TFT 9s described later) is illustrated as having a first protective pattern 16p arranged in a ring shape with the same line width. However, the fourth peripheral TFT 9s may be a fourth peripheral TFT 9sa having a first protective pattern 16pa as shown in FIG. 10, a fourth peripheral TFT 9sb having a first protective pattern 16pb as shown in FIG. 11, a fourth peripheral TFT 9sc having a first protective pattern 16pc as shown in FIG. 12, or a fourth peripheral TFT 9sd having a first protective pattern 16pd as shown in FIG. 13, etc.

[0055] As shown in Figure 10, the fourth peripheral TFT 9sa surrounds the first semiconductor layer 12b in a planar view and has four first protection patterns 16pa arranged in an island shape so as not to overlap with the wiring connected to the first gate electrode 14b, the first source electrode 20h, and the first drain electrode 20i, respectively.

[0056] As shown in Figure 11, the fourth peripheral TFT 9sb surrounds the first semiconductor layer 12b in a planar view and has eight first protection patterns 16pb arranged in an island shape so as not to overlap with the wiring connected to the first gate electrode 14b, the first source electrode 20h, and the first drain electrode 20i, respectively.

[0057] As shown in FIG. 12, the fourth peripheral TFT 9sc is provided with a first protective pattern 16pc that is annularly arranged to surround the first semiconductor layer 12b in a plan view, and whose portions that overlap with the wiring connected to the first gate electrode 14b, the first source electrode 20h, and the first drain electrode 20i are narrower than the portions that do not overlap with the wiring, i.e., which is formed by connecting four first protective patterns 16pa (see FIG. 10).

[0058] As shown in FIG. 13, the fourth peripheral TFT 9sd is provided with a first protective pattern 16pd that is annularly arranged to surround the first semiconductor layer 12b in a planar view, and whose portions that overlap with the wiring connected to the first gate electrode 14b, the first source electrode 20h, and the first drain electrode 20i are narrower than the portions that do not overlap with the wiring, i.e., which is formed by connecting eight first protective patterns 16pb (see FIG. 11).

[0059] As shown in Figures 7 and 9, the second TFT 9B in the frame region F includes a second semiconductor layer 16b provided on the first interlayer insulating film 15, a second gate electrode 18b provided on the second semiconductor layer 16b via a second gate insulating film 17b, a second source electrode 20j and a second drain electrode 20k provided spaced apart from each other on the second interlayer insulating film 19, and a second protection pattern 12p provided around the second semiconductor layer 16b in a planar view.

[0060] The second semiconductor layer 16b, like the second semiconductor layer 16a, is formed from the second semiconductor film, and as shown in FIG. 7, includes a second source region 16ba and a second drain region 16bb that are defined to be spaced apart from each other, and a second channel region 16bc that is defined between the second source region 16ba and the second drain region 16bb.

[0061] The second gate electrode 18b is formed of the second metal film, similar to the second gate electrode 18a, and is provided so as to overlap the second channel region 16bc of the second semiconductor layer 16b, and is configured to control conduction between the second source region 16ba and the second drain region 16bb of the second semiconductor layer 16b, as shown in Fig. 7. Here, the second gate insulating film 17b below the second gate electrode 18b is provided in an island shape so as to overlap the second gate electrode 18b, as shown in Fig. 7.

[0062] The second source electrode 20j and the second drain electrode 20k are formed from the third metal film and are electrically connected to the second source region 16ba and the second drain region 16bb of the second semiconductor layer 16b, respectively, via the third contact hole Hj and the fourth contact hole Hk formed in the second interlayer insulating film 19, as shown in FIG.

[0063] The second protection pattern 12p, like the first semiconductor layer 12a, is formed from the first semiconductor film (conducted), and as shown in FIG. 9, is provided in the shape of a rectangular frame ring so as to surround the second semiconductor layer 16b in a planar view.

[0064] In the present embodiment, the first TFT 9B (a fifth peripheral TFT 9t described later) is illustrated as having a second protective pattern 12p provided in a ring shape with the same line width, but the fifth peripheral TFT 9t may be a fifth peripheral TFT 9ta having a second protective pattern 12pa as shown in Fig. 14, a fifth peripheral TFT 9tb having a second protective pattern 12pb as shown in Fig. 15, a fifth peripheral TFT 9tc having a second protective pattern 12pc as shown in Fig. 16, or a fifth peripheral TFT 9td having a second protective pattern 12pd as shown in Fig. 17. Here, the combination of the first protective pattern 16p (16pa, 16pb, 16pc, 16pd) and the second protective pattern 12p (12pa, 12pb, 12pc, 12pd) described above may be any combination.

[0065] As shown in Figure 14, the fifth peripheral TFT 9ta surrounds the second semiconductor layer 16b in a planar view and has four second protection patterns 12pa arranged in an island shape so as not to overlap with the wiring connected to the second gate electrode 18b, the second source electrode 20j, and the second drain electrode 20k, respectively.

[0066] As shown in Figure 15, the fifth peripheral TFT 9tb surrounds the second semiconductor layer 16b in a planar view and has eight second protection patterns 12pb arranged in an island shape so as not to overlap with the wiring connected to the second gate electrode 18b, the second source electrode 20j, and the second drain electrode 20k, respectively.

[0067] As shown in FIG. 16, the fifth peripheral TFT 9tc is provided with a second protection pattern 12pc that is annularly arranged to surround the second semiconductor layer 16b in a plan view, and whose portions that overlap with the wiring connected to the second gate electrode 18b, the second source electrode 20j, and the second drain electrode 20k are narrower than the portions that do not overlap with the wiring, i.e., which is formed by connecting four second protection patterns 12pa (see FIG. 14).

[0068] As shown in FIG. 17, the fifth peripheral TFT 9td includes a second protection pattern 12pd that is annularly arranged to surround the second semiconductor layer 16b in a plan view, and whose portions that overlap with the wiring connected to the second gate electrode 18b, the second source electrode 20j, and the second drain electrode 20k are narrower than the portions that do not overlap with the wiring, i.e., the second protection pattern 12pd is formed by connecting eight second protection patterns 12pb (see FIG. 15).

[0069] In this embodiment, four first TFTs 9A having a first semiconductor layer 12b formed from polysilicon are exemplified as a first peripheral TFT 9p, a second peripheral TFT 9q, a third peripheral TFT 9r, and a fourth peripheral TFT 9s, which will be described later, and one second TFT 9B having a second semiconductor layer 16b formed from an oxide semiconductor is exemplified as a fifth peripheral TFT 9t, which will be described later (see Figure 6).

[0070] As shown in FIG. 6, the gate driver circuit M includes a flip-flop circuit A and a CMOS circuit C provided for each gate line 14g.

[0071] As shown in FIG. 6, the flip-flop circuit A includes a P-channel first peripheral TFT 9p, a second peripheral TFT 9q, and a third peripheral TFT 9r, and one capacitor 9j, and is configured to input a clock signal CK and an inverted clock signal CKB so that they intersect, thereby outputting a gate signal shifted by half a period from the clock signal CK to a node N1.

[0072] 6, the first peripheral TFT 9p has a first gate electrode 14b to which a clock signal is input, a first source electrode 20h electrically connected to a high-level VDD power supply line, and a first drain electrode 20i electrically connected to the node N1. Note that the first protection pattern 16p (FIG. 7) may be omitted from the first peripheral TFT 9p.

[0073] 6, the second peripheral TFT 9q has its first gate electrode 14b electrically connected to the node N2, its first source electrode 20h receiving the inverted clock signal CKB, and its first drain electrode 20i electrically connected to the node N1. Note that the first protection pattern 16p (FIG. 7) may be omitted from the second peripheral TFT 9q.

[0074] As shown in FIG. 6, the third peripheral TFT 9r has a first gate electrode 14b to which a clock signal is input, a first source electrode 20h to which a start pulse SU is input, and a first drain electrode 20i to which a node N2 is electrically connected. The first protection pattern 16p (FIG. 7) may be omitted from the third peripheral TFT 9r. The start pulse SU is applied when the flip-flop circuit A is in the first stage. When the flip-flop circuit A is in the second stage, the gate signal output in the first stage is input instead of the start pulse SU. Therefore, in subsequent stages, the gate signal of the previous stage is input to the first source electrode 20h of the third peripheral TFT 9r of the flip-flop circuit A.

[0075] As shown in FIG. 6, the capacitor 9j is connected between the nodes N1 and N2 and is configured to maintain a voltage between the first drain electrode 20i and the first gate electrode 14b of the second peripheral TFT 9q.

[0076] 6 and 7, the CMOS circuit C includes a fourth P-channel peripheral TFT 9s and a fifth N-channel peripheral TFT 9t, and is configured such that when a gate signal input from a node N3 has the same potential as the low-level voltage VSS, the fourth peripheral TFT 9s is turned on and the fifth peripheral TFT 9t is turned off, outputting a potential equal to the high-level voltage VDD from a node N4, and when a gate signal input from the node N3 has the same potential as the high-level voltage VDD, the fourth peripheral TFT 9s is turned off and the fifth peripheral TFT 9t is turned on, outputting a potential equal to the low-level voltage VSS from a node N4. The node N3 of the CMOS circuit C is electrically connected to the node N1 of the flip-flop circuit A.

[0077] 6, the fourth peripheral TFT 9s has its first gate electrode 14b electrically connected to the node N3, its first source electrode 20h electrically connected to the power supply line of the high-level voltage VDD, and its first drain electrode 20i electrically connected to the node N4. As described above, the fourth peripheral TFT 9s includes the first semiconductor layer 12b, the first gate electrode 14b, the first source electrode 20h, the first drain electrode 20i, and the first protection pattern 16p (see FIG. 7).

[0078] 6, the fifth peripheral TFT 9t has its second gate electrode 18b electrically connected to the node N3, its second source electrode 20j electrically connected to the power supply line of the low-level voltage VSS, and its second drain electrode 20k electrically connected to the node N4. As described above, the fifth peripheral TFT 9t includes the second semiconductor layer 16b, the second gate electrode 18b, the second source electrode 20j, the second drain electrode 20k, and the second protection pattern 12p (see FIG. 7).

[0079] Here, the operation of the gate driver circuit M (the flip-flop circuit A and the CMOS circuit C) will be described.

[0080] In the flip-flop circuit A, for example, when the clock signal CK is low, the inverted clock signal CKB is high, and the start pulse SU is low, the first peripheral TFT 9p and the third peripheral TFT 9r are turned on. At this time, a low-level start pulse SU is input to the first gate electrode 14b of the second peripheral TFT 9q, turning on the second peripheral TFT 9q. However, because a high-level inverted clock signal CKB is applied to the first source electrode 20h of the second peripheral TFT 9q, no current flows through the second peripheral TFT 9q. Therefore, a high-level gate signal is output to node N1. Subsequently, a high-level gate signal output from node N1 is input to node N3. Since this gate signal has the same potential as the high-level voltage VDD, the fourth peripheral TFT 9s is turned off, the fifth peripheral TFT 9t is turned on, and a gate signal having the same potential as the low-level voltage VSS is output from node N4.

[0081] Next, in the flip-flop circuit A, for example, when the clock signal CK is high, the inverted clock signal CKB is low, and the start pulse SU is high, the first peripheral TFT 9p and the third peripheral TFT 9r are turned off. At this time, a low-level inverted clock signal CKB is input to the first source electrode 20h of the second peripheral TFT 9q, turning on the second peripheral TFT 9q. The high-level voltage stored at node N1 causes current to flow through the second peripheral TFT 9q, and the voltage at node N1 drops by the low-level inverted clock signal CKB. This is because node N2, to which one terminal of capacitor 9j is connected, is floating due to the third peripheral TFT 9r being turned off, and the voltage at node N2 drops by the amount of the drop in the voltage at node N1, enabling full down. Therefore, a low-level gate signal is output to node N1. Next, the low-level gate signal output from node N1 is input to node N3, and when the gate signal has the same potential as the low-level voltage VSS, the fourth peripheral TFT 9s is turned on, the fifth peripheral TFT 9t is turned off, and a gate signal having the same potential as the high-level voltage VDD is output from node N4.

[0082] In the organic EL display device 50 configured as described above, in each subpixel P, when the light-emitting control line 14e is first selected and inactivated, the organic EL element 35 enters a non-light-emitting state. In this non-light-emitting state, the preceding gate line 14g(n-1) is selected, and a gate signal is input to the initialization TFT 9a via that gate line 14g(n-1), turning the initialization TFT 9a on. This applies the high power supply voltage ELVDD of the power supply line 20g to the capacitor 9h, and turns the driving TFT 9d on. As a result, the charge in the capacitor 9h is discharged, and the voltage applied to the gate electrode of the driving TFT 9d is initialized. Next, the gate line 14g(n) in the current row is selected and activated, thereby turning on the compensation TFT 9b and the writing TFT 9c, a predetermined voltage corresponding to a source signal transmitted via the corresponding source line 20f is written to the capacitor 9h via the diode-connected driving TFT 9d, the anode discharge TFT 9g is turned on, an initialization signal is applied to the first electrode 31 of the organic EL element 35 via the second initialization power line 18i, and the charge accumulated in the first electrode 31 is reset. Thereafter, the light-emission control line 14e is selected, turning on the power supply TFT 9e and the light-emission control TFT 9f, and a drive current corresponding to the voltage applied to the gate electrode of the driving TFT 9d is supplied from the power line 20g to the organic EL element 35. In this way, in the organic EL display device 50, the organic EL element 35 emits light at a brightness corresponding to the drive current in each sub-pixel P, thereby displaying an image.

[0083] Next, a method for manufacturing the organic EL display device 50 of this embodiment will be described. The method for manufacturing the organic EL display device 50 of this embodiment includes a TFT layer forming step, an organic EL element layer forming step, and a sealing film forming step.

[0084] <TFT Layer Formation Process> First, a silicon nitride film (thickness: about 50 nm) and a silicon oxide film (thickness: about 250 nm) are sequentially formed on a resin substrate 10 formed on a glass substrate by, for example, a plasma CVD (Chemical Vapor Deposition) method, thereby forming a base coat film 11.

[0085] Next, an amorphous silicon film (about 50 nm thick) is formed on the substrate surface on which the base coat film 11 has been formed, for example, by plasma CVD, and the amorphous silicon film is crystallized by laser annealing or the like to form a first semiconductor film made of polysilicon.The first semiconductor film is then patterned to form first semiconductor layers 12a and 12b, a second protective pattern 12p (before being made into a conductor), and the like.

[0086] Thereafter, a silicon oxide film (about 100 nm thick) is formed by, for example, plasma CVD on the surface of the substrate on which the first semiconductor layers 12a and 12b etc. are formed, thereby forming the first gate insulating film 13.

[0087] Furthermore, a first metal film such as a molybdenum film (about 200 nm thick) is formed on the surface of the substrate on which the first gate insulating film 13 is formed, for example, by sputtering, and then the first metal film is patterned to form the first gate electrodes 14a and 14b, the gate line 14g, the light-emitting control line 14e, etc.

[0088] Next, using the first gate electrodes 14a and 14b as a mask, the first semiconductor layers 12a and 12b are doped with impurity ions (e.g., phosphorus) to make parts of the first semiconductor layers 12a and 12b conductive, thereby forming a first conductor region 12aa, a second conductor region 12ab, and a first channel region 12ac in the first semiconductor layer 12a, and a first source region 12ba, a first drain region 12bb, and a first channel region 12bc in the first semiconductor layer 12b. At this time, a conductive second protection pattern 12p is also formed.

[0089] Thereafter, a silicon nitride film (about 150 nm thick) and a silicon oxide film (about 100 nm thick) are sequentially formed by, for example, plasma CVD on the substrate surface where portions of the first semiconductor layers 12a and 12b have been made conductive, thereby forming a first interlayer insulating film 15.

[0090] Furthermore, on the surface of the substrate on which the first interlayer insulating film 15 is formed, InGaZnO ４After forming a second semiconductor film made of an oxide semiconductor such as a film (thickness: about 30 nm), the second semiconductor film is patterned to form second semiconductor layers 16 a and 16 b, a first protection pattern 16 p (before being made into a conductor), and the like.

[0091] Next, a silicon oxide film (about 100 nm thick) is formed by, for example, plasma CVD on the surface of the substrate on which the second semiconductor layers 16 a and 16 b, etc. are formed, and then a second metal film such as a molybdenum film (about 200 nm thick) is formed by sputtering, and then the second metal film is patterned to form the second gate electrodes 18 a and 18 b, the second initialization power line 18 i, etc.

[0092] Thereafter, the silicon oxide film exposed from the second gate electrodes 18a and 18b and the like is etched to form the second gate insulating films 17a and 17b and the like.

[0093] Furthermore, a silicon oxide film (about 300 nm thick) and a silicon nitride film (about 150 nm thick) are sequentially formed by, for example, plasma CVD on the substrate surface on which the second gate insulating films 17a and 17b etc. are formed, thereby forming a second interlayer insulating film 19. Note that by heat treatment after the formation of the second interlayer insulating film 19, parts of the second semiconductor layers 16a and 16b are made conductive, so that a third conductor region 16aa, a fourth conductor region 16ab, and a second channel region 16ac are formed in the second semiconductor layer 16a, and a second source region 16ba, a second drain region 16bb, and a second channel region 16bc are formed in the second semiconductor layer 16b. At this time, a conductive first protection pattern 16p is also formed.

[0094] Next, on the substrate surface on which the second interlayer insulating film 19 is formed, the first gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 19 are appropriately patterned to form first contact holes Ha and Hh, second contact holes Hb and Hi, third contact holes Hc and Hj, and fourth contact holes Hd and Hk.

[0095] Thereafter, a titanium film (about 50 nm thick), an aluminum film (about 400 nm thick), and a titanium film (about 100 nm thick) are sequentially formed by, for example, sputtering on the surface of the substrate on which the contact holes have been formed to form a third metal film, and then the third metal film is patterned to form a first terminal electrode 20a, a second terminal electrode 20b, a third terminal electrode 20c, a fourth terminal electrode 20d, a first source electrode 20h, a first drain electrode 20i, a second source electrode 20j, a second drain electrode 20k, a source line 20f, a power line 20g, and the like.

[0096] Furthermore, a silicon oxide film (about 250 nm thick) is formed by, for example, plasma CVD on the surface of the substrate on which the first terminal electrodes 20a and the like are formed, thereby forming the protective insulating film 21.

[0097] Next, an acrylic photosensitive resin film (approximately 2 μm thick) is applied to the substrate surface on which the protective insulating film 21 has been formed, for example, by spin coating or slit coating, and then the applied film is pre-baked, exposed to light, developed, and post-baked to form a planarization film 22 having contact holes.

[0098] Finally, the protective insulating film 21 exposed from the contact hole in the planarizing film 22 is removed so that the contact hole reaches the second terminal electrode 20b of the light-emission control TFT 9f.

[0099] In this manner, the TFT layer 30 can be formed.

[0100] <Organic EL element layer forming process> On the planarization film 22 of the TFT layer 30 formed in the TFT layer forming process, a first electrode 31, an edge cover 32, an organic EL layer 33 (hole injection layer 1, hole transport layer 2, light-emitting layer 3, electron transport layer 4, electron injection layer 5), and a second electrode 34 are formed by using a well-known method, thereby forming an organic EL element layer 40.

[0101] <Sealing film forming process> First, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD using a mask on the surface of the substrate on which the organic EL element layer 40 formed in the organic EL element layer forming process is formed, thereby forming a first inorganic sealing film 41.

[0102] Subsequently, an organic resin material such as an acrylic resin is deposited by, for example, an inkjet method on the surface of the substrate on which the first inorganic sealing film 41 has been formed, to form an organic sealing film 42 .

[0103] Furthermore, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed on the substrate on which the organic sealing film 42 has been formed using a mask by plasma CVD to form a second inorganic sealing film 43, thereby forming a sealing film 45.

[0104] Finally, a protective sheet (not shown) is attached to the surface of the substrate on which the sealing film 45 is formed, and then laser light is irradiated from the glass substrate side of the resin substrate 10 to peel the glass substrate from the underside of the resin substrate 10, and further a protective sheet (not shown) is attached to the underside of the resin substrate 10 from which the glass substrate has been peeled.

[0105] In this manner, the organic EL display device 50 of this embodiment can be manufactured.

[0106] As described above, in the organic EL display device 50 of this embodiment, the CMOS circuit C disposed as a peripheral circuit in the frame region F is provided with, in a plan view, the first protective pattern 16 p formed in a ring shape from an oxide semiconductor around the first semiconductor layer 12 b of the fourth peripheral TFT 9 s, and the second protective pattern 12 p formed in a ring shape from polysilicon around the second semiconductor layer 16 b of the fifth peripheral TFT 9 t. As a result, static electricity accumulated during the manufacturing process is easily discharged to the first protective pattern 16 p and the second protective pattern 12 p provided like a lightning rod, but is less likely to be discharged to the first semiconductor layer 12 b and the second semiconductor layer 16 b surrounded by the first protective pattern 16 p and the second protective pattern 12 p, thereby suppressing deterioration of the characteristics of the fourth peripheral TFT 9 s and the fifth peripheral TFT 9 t due to electrostatic discharge. Furthermore, moisture contained in the resin substrate 10 made of an organic resin material, the planarization film 19, and the like is physically blocked by the first protective pattern 16 p and the second protective pattern 12 p, which prevents moisture from penetrating into the first semiconductor layer 12 b and the second semiconductor layer 16 b surrounded by the first protective pattern 16 p and the second protective pattern 12 p, thereby preventing deterioration of the characteristics of the fourth peripheral TFT 9 s and the fifth peripheral TFT 9 t due to moisture penetration. Therefore, in the organic EL display device 50 having a hybrid structure, deterioration of the characteristics of the fourth peripheral TFT 9 s and the fifth peripheral TFT 9 t can be prevented in the CMOS circuit C that constitutes a part of the gate driver M.

[0107] Other Embodiments In the above embodiment, the organic EL display device 50 is illustrated as having both the first protective pattern 16 p and the second protective pattern 12 b in the CMOS circuit C. However, the present invention can also be applied to an organic EL display device that is provided with one of the first protective pattern 16 p and the second protective pattern 12 p in the CMOS circuit C, and a liquid crystal display device that is provided with at least one of the first protective pattern 16 p and the second protective pattern 12 p in the CMOS circuit C.

[0108] In the above embodiment, an organic EL layer having a five-layer stacked structure of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer is exemplified. However, the organic EL layer may have a three-layer stacked structure of, for example, a hole injection layer / hole transport layer, a light-emitting layer, and an electron transport layer / electron injection layer.

[0109] Furthermore, in the above embodiment, an organic EL display device in which the first electrode is an anode and the second electrode is a cathode is exemplified. However, the present invention can also be applied to an organic EL display device in which the layered structure of the organic EL layer is reversed, and the first electrode is a cathode and the second electrode is an anode.

[0110] Furthermore, in the above embodiment, an organic EL display device has been described as an example of a display device. However, the present invention can be applied to a display device including a plurality of light-emitting elements driven by current, and can be applied to, for example, a display device including QLEDs (Quantum-dot light emitting diodes), which are light-emitting elements using a quantum dot-containing layer.

[0111] As described above, the present invention is useful for flexible display devices.

[0112] C CMOS circuit (complementary metal oxide semiconductor circuit) D Display area F Frame area M Gate driver (drive circuit) P Sub-pixel 9A First TFT (first thin film transistor) 9B Second TFT (second thin film transistor) 9a Initialization TFT (pixel thin film transistor, second thin film transistor) 9b Compensation TFT (pixel thin film transistor, second thin film transistor) 9c Writing TFT (pixel thin film transistor, first thin film transistor) 9d Driving TFT (pixel thin film transistor, first thin film transistor) 9e Power supply TFT (pixel thin film transistor, first thin film transistor) 9f Emission control TFT (pixel thin film transistor, first thin film transistor) 9g Anode discharge TFT (pixel thin film transistor, second thin film transistor) 9s Fourth peripheral TFT (first thin film transistor) 9t Fifth peripheral TFT (second thin film transistor) 10 Resin substrate (base substrate) 12a, 12b First semiconductor layer 12p, 12pa, 12pb, 12pc, 12pd Second protective pattern 13 First gate insulating film (first inorganic insulating film) 15 First interlayer insulating film (second inorganic insulating film) 16a, 16b Second semiconductor layer 16p, 16pa, 16pb, 16pc, 16pd First protective pattern 17a, 17b Second gate insulating film (third inorganic insulating film) 19 Second interlayer insulating film (fourth inorganic insulating film) 30 TFT layer (thin film transistor layer) 35 Organic EL element (organic electroluminescence element, light-emitting element) 40 Organic EL element layer (light-emitting element layer) 45 Sealing film 50 Organic EL display device

Claims

1. A base substrate; a thin film transistor layer provided on the base substrate, in which a first thin film transistor having a first semiconductor layer formed of polysilicon and a second thin film transistor having a second semiconductor layer formed of an oxide semiconductor are arranged; a display area for displaying an image and a frame area surrounding the display area are defined; a plurality of pixel thin film transistors are provided as the first thin film transistor and the second thin film transistor in each sub-pixel constituting the display area; a complementary metal oxide semiconductor circuit in which the first thin film transistor and the second thin film transistor are combined is provided in the frame region as a part of a drive circuit, a first protection pattern formed of the oxide semiconductor around the first semiconductor layer of the first thin film transistor in the complementary metal oxide semiconductor circuit, and a second protection pattern formed of the polysilicon around the second semiconductor layer of the second thin film transistor in the complementary metal oxide semiconductor circuit, in a planar view.

2. 2. The display device according to claim 1, The display device, wherein the first protection pattern is provided in a ring shape so as to surround the first semiconductor layer of the first thin film transistor in the complementary metal oxide semiconductor circuit.

3. 3. The display device according to claim 2, A display device characterized in that the first protection pattern is provided with a narrower portion that overlaps with wiring connected to the electrode of the first thin film transistor in the complementary metal oxide semiconductor circuit than the portion that does not overlap with the wiring.

4. 2. The display device according to claim 1, A display device characterized in that the first protection pattern surrounds the first semiconductor layer of the first thin film transistor in the complementary metal oxide semiconductor circuit and is provided in the form of multiple islands so as not to overlap with wiring connected to the electrode of the first thin film transistor.

5. 2. The display device according to claim 1, The display device, wherein the second protection pattern is provided in a ring shape so as to surround the second semiconductor layer of the second thin film transistor in the complementary metal oxide semiconductor circuit.

6. 6. The display device according to claim 5, A display device characterized in that the second protection pattern is provided with a narrower portion that overlaps with wiring connected to the electrode of the second thin film transistor in the complementary metal oxide semiconductor circuit than the portion that does not overlap with the wiring.

7. 2. The display device according to claim 1, A display device characterized in that the second protection pattern surrounds the second semiconductor layer of the second thin film transistor in the complementary metal oxide semiconductor circuit and is provided in the form of multiple islands so as not to overlap with wiring connected to the electrode of the second thin film transistor.

8. The display device according to any one of claims 1 to 7, the thin film transistor layer includes a first semiconductor film made of polysilicon, a first inorganic insulating film, a first metal film, a second inorganic insulating film, a second semiconductor film made of the oxide semiconductor, a third inorganic insulating film, a second metal film, a fourth inorganic insulating film, and a third metal film stacked in this order; the first semiconductor layer is formed by the first semiconductor film, The display device is characterized in that the second semiconductor layer is formed by the second semiconductor film.

9. The display device according to any one of claims 1 to 7, a light emitting element layer provided on the thin film transistor layer, in which a plurality of light emitting elements are arranged corresponding to a plurality of sub-pixels constituting the display area; a sealing film provided on the light-emitting element layer.

10. 10. The display device according to claim 9, The display device is characterized in that each of the light-emitting elements is an organic electroluminescence element.